--- /dev/null	Thu Aug 30 18:39:45 2018
+++ new/usr/src/test/util-tests/tests/dis/risc-v/tst.csr.out	Thu Aug 30 18:39:45 2018
@@ -0,0 +1,129 @@
+    libdis_test:       73 a3 03 00        csrrs t1,ustatus,t2
+    libdis_test+0x4:   73 a3 43 00        csrrs t1,uie,t2
+    libdis_test+0x8:   73 a3 53 00        csrrs t1,utvec,t2
+    libdis_test+0xc:   73 a3 03 04        csrrs t1,uscratch,t2
+    libdis_test+0x10:  73 a3 13 04        csrrs t1,uepc,t2
+    libdis_test+0x14:  73 a3 23 04        csrrs t1,ucause,t2
+    libdis_test+0x18:  73 a3 33 04        csrrs t1,utval,t2
+    libdis_test+0x1c:  73 a3 43 04        csrrs t1,uip,t2
+    libdis_test+0x20:  73 a3 13 00        csrrs t1,fflags,t2
+    libdis_test+0x24:  73 a3 23 00        csrrs t1,frm,t2
+    libdis_test+0x28:  73 a3 33 00        csrrs t1,fcsr,t2
+    libdis_test+0x2c:  73 a3 03 c0        csrrs t1,cycle,t2
+    libdis_test+0x30:  73 a3 13 c0        csrrs t1,time,t2
+    libdis_test+0x34:  73 a3 23 c0        csrrs t1,instret,t2
+    libdis_test+0x38:  73 a3 33 c0        csrrs t1,hpmcounter3,t2
+    libdis_test+0x3c:  73 a3 43 c0        csrrs t1,hpmcounter4,t2
+    libdis_test+0x40:  73 a3 53 c0        csrrs t1,hpmcounter5,t2
+    libdis_test+0x44:  73 a3 63 c0        csrrs t1,hpmcounter6,t2
+    libdis_test+0x48:  73 a3 73 c0        csrrs t1,hpmcounter7,t2
+    libdis_test+0x4c:  73 a3 83 c0        csrrs t1,hpmcounter8,t2
+    libdis_test+0x50:  73 a3 93 c0        csrrs t1,hpmcounter9,t2
+    libdis_test+0x54:  73 a3 a3 c0        csrrs t1,hpmcounter10,t2
+    libdis_test+0x58:  73 a3 b3 c0        csrrs t1,hpmcounter11,t2
+    libdis_test+0x5c:  73 a3 c3 c0        csrrs t1,hpmcounter12,t2
+    libdis_test+0x60:  73 a3 d3 c0        csrrs t1,hpmcounter13,t2
+    libdis_test+0x64:  73 a3 e3 c0        csrrs t1,hpmcounter14,t2
+    libdis_test+0x68:  73 a3 f3 c0        csrrs t1,hpmcounter15,t2
+    libdis_test+0x6c:  73 a3 03 c1        csrrs t1,hpmcounter16,t2
+    libdis_test+0x70:  73 a3 13 c1        csrrs t1,hpmcounter17,t2
+    libdis_test+0x74:  73 a3 23 c1        csrrs t1,hpmcounter18,t2
+    libdis_test+0x78:  73 a3 33 c1        csrrs t1,hpmcounter19,t2
+    libdis_test+0x7c:  73 a3 43 c1        csrrs t1,hpmcounter20,t2
+    libdis_test+0x80:  73 a3 53 c1        csrrs t1,hpmcounter21,t2
+    libdis_test+0x84:  73 a3 63 c1        csrrs t1,hpmcounter22,t2
+    libdis_test+0x88:  73 a3 73 c1        csrrs t1,hpmcounter23,t2
+    libdis_test+0x8c:  73 a3 83 c1        csrrs t1,hpmcounter24,t2
+    libdis_test+0x90:  73 a3 93 c1        csrrs t1,hpmcounter25,t2
+    libdis_test+0x94:  73 a3 a3 c1        csrrs t1,hpmcounter26,t2
+    libdis_test+0x98:  73 a3 b3 c1        csrrs t1,hpmcounter27,t2
+    libdis_test+0x9c:  73 a3 c3 c1        csrrs t1,hpmcounter28,t2
+    libdis_test+0xa0:  73 a3 d3 c1        csrrs t1,hpmcounter29,t2
+    libdis_test+0xa4:  73 a3 e3 c1        csrrs t1,hpmcounter30,t2
+    libdis_test+0xa8:  73 a3 f3 c1        csrrs t1,hpmcounter31,t2
+    libdis_test+0xac:  73 a3 03 c8        csrrs t1,cycleh,t2
+    libdis_test+0xb0:  73 a3 13 c8        csrrs t1,timeh,t2
+    libdis_test+0xb4:  73 a3 23 c8        csrrs t1,instreth,t2
+    libdis_test+0xb8:  73 a3 33 c8        csrrs t1,hpmcounter3h,t2
+    libdis_test+0xbc:  73 a3 43 c8        csrrs t1,hpmcounter4h,t2
+    libdis_test+0xc0:  73 a3 53 c8        csrrs t1,hpmcounter5h,t2
+    libdis_test+0xc4:  73 a3 63 c8        csrrs t1,hpmcounter6h,t2
+    libdis_test+0xc8:  73 a3 73 c8        csrrs t1,hpmcounter7h,t2
+    libdis_test+0xcc:  73 a3 83 c8        csrrs t1,hpmcounter8h,t2
+    libdis_test+0xd0:  73 a3 93 c8        csrrs t1,hpmcounter9h,t2
+    libdis_test+0xd4:  73 a3 a3 c8        csrrs t1,hpmcounter10h,t2
+    libdis_test+0xd8:  73 a3 b3 c8        csrrs t1,hpmcounter11h,t2
+    libdis_test+0xdc:  73 a3 c3 c8        csrrs t1,hpmcounter12h,t2
+    libdis_test+0xe0:  73 a3 d3 c8        csrrs t1,hpmcounter13h,t2
+    libdis_test+0xe4:  73 a3 e3 c8        csrrs t1,hpmcounter14h,t2
+    libdis_test+0xe8:  73 a3 f3 c8        csrrs t1,hpmcounter15h,t2
+    libdis_test+0xec:  73 a3 03 c9        csrrs t1,hpmcounter16h,t2
+    libdis_test+0xf0:  73 a3 13 c9        csrrs t1,hpmcounter17h,t2
+    libdis_test+0xf4:  73 a3 23 c9        csrrs t1,hpmcounter18h,t2
+    libdis_test+0xf8:  73 a3 33 c9        csrrs t1,hpmcounter19h,t2
+    libdis_test+0xfc:  73 a3 43 c9        csrrs t1,hpmcounter20h,t2
+    libdis_test+0x100: 73 a3 53 c9        csrrs t1,hpmcounter21h,t2
+    libdis_test+0x104: 73 a3 63 c9        csrrs t1,hpmcounter22h,t2
+    libdis_test+0x108: 73 a3 73 c9        csrrs t1,hpmcounter23h,t2
+    libdis_test+0x10c: 73 a3 83 c9        csrrs t1,hpmcounter24h,t2
+    libdis_test+0x110: 73 a3 93 c9        csrrs t1,hpmcounter25h,t2
+    libdis_test+0x114: 73 a3 a3 c9        csrrs t1,hpmcounter26h,t2
+    libdis_test+0x118: 73 a3 b3 c9        csrrs t1,hpmcounter27h,t2
+    libdis_test+0x11c: 73 a3 c3 c9        csrrs t1,hpmcounter28h,t2
+    libdis_test+0x120: 73 a3 d3 c9        csrrs t1,hpmcounter29h,t2
+    libdis_test+0x124: 73 a3 e3 c9        csrrs t1,hpmcounter30h,t2
+    libdis_test+0x128: 73 a3 f3 c9        csrrs t1,hpmcounter31h,t2
+    libdis_test+0x12c: 73 a3 03 10        csrrs t1,sstatus,t2
+    libdis_test+0x130: 73 a3 23 10        csrrs t1,sedeleg,t2
+    libdis_test+0x134: 73 a3 33 10        csrrs t1,sideleg,t2
+    libdis_test+0x138: 73 a3 43 10        csrrs t1,sie,t2
+    libdis_test+0x13c: 73 a3 53 10        csrrs t1,stvec,t2
+    libdis_test+0x140: 73 a3 63 10        csrrs t1,scounteren,t2
+    libdis_test+0x144: 73 a3 03 14        csrrs t1,sscratch,t2
+    libdis_test+0x148: 73 a3 13 14        csrrs t1,sepc,t2
+    libdis_test+0x14c: 73 a3 23 14        csrrs t1,scause,t2
+    libdis_test+0x150: 73 a3 33 14        csrrs t1,stval,t2
+    libdis_test+0x154: 73 a3 43 14        csrrs t1,sip,t2
+    libdis_test+0x158: 73 a3 03 18        csrrs t1,satp,t2
+    libdis_test+0x15c: 73 a3 13 f1        csrrs t1,mvendorid,t2
+    libdis_test+0x160: 73 a3 23 f1        csrrs t1,marchid,t2
+    libdis_test+0x164: 73 a3 33 f1        csrrs t1,mimpid,t2
+    libdis_test+0x168: 73 a3 43 f1        csrrs t1,mhartid,t2
+    libdis_test+0x16c: 73 a3 03 30        csrrs t1,mstatus,t2
+    libdis_test+0x170: 73 a3 13 30        csrrs t1,misa,t2
+    libdis_test+0x174: 73 a3 23 30        csrrs t1,medeleg,t2
+    libdis_test+0x178: 73 a3 33 30        csrrs t1,mideleg,t2
+    libdis_test+0x17c: 73 a3 43 30        csrrs t1,mie,t2
+    libdis_test+0x180: 73 a3 53 30        csrrs t1,mtvec,t2
+    libdis_test+0x184: 73 a3 63 30        csrrs t1,mcounteren,t2
+    libdis_test+0x188: 73 a3 03 34        csrrs t1,mscratch,t2
+    libdis_test+0x18c: 73 a3 13 34        csrrs t1,mepc,t2
+    libdis_test+0x190: 73 a3 23 34        csrrs t1,mcause,t2
+    libdis_test+0x194: 73 a3 33 34        csrrs t1,mtval,t2
+    libdis_test+0x198: 73 a3 43 34        csrrs t1,mip,t2
+    libdis_test+0x19c: 73 a3 03 3a        csrrs t1,pmpcfg0,t2
+    libdis_test+0x1a0: 73 a3 13 3a        csrrs t1,pmpcfg1,t2
+    libdis_test+0x1a4: 73 a3 23 3a        csrrs t1,pmpcfg2,t2
+    libdis_test+0x1a8: 73 a3 33 3a        csrrs t1,pmpcfg3,t2
+    libdis_test+0x1ac: 73 a3 03 3b        csrrs t1,pmpaddr0,t2
+    libdis_test+0x1b0: 73 a3 13 3b        csrrs t1,pmpaddr1,t2
+    libdis_test+0x1b4: 73 a3 23 3b        csrrs t1,pmpaddr2,t2
+    libdis_test+0x1b8: 73 a3 33 3b        csrrs t1,pmpaddr3,t2
+    libdis_test+0x1bc: 73 a3 43 3b        csrrs t1,pmpaddr4,t2
+    libdis_test+0x1c0: 73 a3 53 3b        csrrs t1,pmpaddr5,t2
+    libdis_test+0x1c4: 73 a3 63 3b        csrrs t1,pmpaddr6,t2
+    libdis_test+0x1c8: 73 a3 73 3b        csrrs t1,pmpaddr7,t2
+    libdis_test+0x1cc: 73 a3 83 3b        csrrs t1,pmpaddr8,t2
+    libdis_test+0x1d0: 73 a3 93 3b        csrrs t1,pmpaddr9,t2
+    libdis_test+0x1d4: 73 a3 a3 3b        csrrs t1,pmpaddr10,t2
+    libdis_test+0x1d8: 73 a3 b3 3b        csrrs t1,pmpaddr11,t2
+    libdis_test+0x1dc: 73 a3 c3 3b        csrrs t1,pmpaddr12,t2
+    libdis_test+0x1e0: 73 a3 d3 3b        csrrs t1,pmpaddr13,t2
+    libdis_test+0x1e4: 73 a3 e3 3b        csrrs t1,pmpaddr14,t2
+    libdis_test+0x1e8: 73 a3 f3 3b        csrrs t1,pmpaddr15,t2
+    libdis_test+0x1ec: 73 a3 03 00        csrrs t1,ustatus,t2
+    libdis_test+0x1f0: 73 93 43 00        csrrw t1,uie,t2
+    libdis_test+0x1f4: 73 b3 53 00        csrrc t1,utvec,t2
+    libdis_test+0x1f8: 73 d3 0b 04        csrrwi t1,uscratch,0x17
+    libdis_test+0x1fc: 73 63 1b 04        csrrsi t1,uepc,0x16
+    libdis_test+0x200: 73 f3 2a 04        csrrci t1,ucause,0x15
