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--- old/usr/src/uts/common/io/ixgbe/ixgbe_api.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_api.c
1 1 /******************************************************************************
2 2
3 3 Copyright (c) 2001-2012, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 -/*$FreeBSD$*/
33 +/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34 34
35 35 #include "ixgbe_api.h"
36 36 #include "ixgbe_common.h"
37 37
38 -extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
39 -extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
40 -
41 38 /**
42 39 * ixgbe_init_shared_code - Initialize the shared code
43 40 * @hw: pointer to hardware structure
44 41 *
45 42 * This will assign function pointers and assign the MAC type and PHY code.
46 43 * Does not touch the hardware. This function must be called prior to any
47 44 * other function in the shared code. The ixgbe_hw structure should be
48 45 * memset to 0 prior to calling this function. The following fields in
49 46 * hw structure should be filled in prior to calling this function:
50 47 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
51 48 * subsystem_vendor_id, and revision_id
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52 49 **/
53 50 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
54 51 {
55 52 s32 status;
56 53
57 54 DEBUGFUNC("ixgbe_init_shared_code");
58 55
59 56 /*
60 57 * Set the mac type
61 58 */
62 - (void) ixgbe_set_mac_type(hw);
59 + ixgbe_set_mac_type(hw);
63 60
64 61 switch (hw->mac.type) {
65 62 case ixgbe_mac_82598EB:
66 63 status = ixgbe_init_ops_82598(hw);
67 64 break;
68 65 case ixgbe_mac_82599EB:
69 66 status = ixgbe_init_ops_82599(hw);
70 67 break;
68 +#if 0
69 +/* XXX KEBE ASKS - nuke this? */
70 + case ixgbe_mac_82599_vf:
71 + case ixgbe_mac_X540_vf:
72 + status = ixgbe_init_ops_vf(hw);
73 + break;
74 +#endif
75 + case ixgbe_mac_X540:
76 + status = ixgbe_init_ops_X540(hw);
77 + break;
71 78 default:
72 79 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
73 80 break;
74 81 }
75 82
76 83 return status;
77 84 }
78 85
79 86 /**
80 87 * ixgbe_set_mac_type - Sets MAC type
81 88 * @hw: pointer to the HW structure
82 89 *
83 90 * This function sets the mac type of the adapter based on the
84 91 * vendor ID and device ID stored in the hw structure.
85 92 **/
86 93 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
87 94 {
88 95 s32 ret_val = IXGBE_SUCCESS;
89 96
90 97 DEBUGFUNC("ixgbe_set_mac_type\n");
91 98
92 99 if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
93 100 switch (hw->device_id) {
94 101 case IXGBE_DEV_ID_82598:
95 102 case IXGBE_DEV_ID_82598_BX:
96 103 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
97 104 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
98 105 case IXGBE_DEV_ID_82598AT:
99 106 case IXGBE_DEV_ID_82598AT2:
100 107 case IXGBE_DEV_ID_82598EB_CX4:
101 108 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
102 109 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
103 110 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
104 111 case IXGBE_DEV_ID_82598EB_XF_LR:
105 112 case IXGBE_DEV_ID_82598EB_SFP_LOM:
106 113 hw->mac.type = ixgbe_mac_82598EB;
107 114 break;
108 115 case IXGBE_DEV_ID_82599_KX4:
109 116 case IXGBE_DEV_ID_82599_KX4_MEZZ:
110 117 case IXGBE_DEV_ID_82599_XAUI_LOM:
111 118 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
112 119 case IXGBE_DEV_ID_82599_KR:
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113 120 case IXGBE_DEV_ID_82599_SFP:
114 121 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
115 122 case IXGBE_DEV_ID_82599_SFP_FCOE:
116 123 case IXGBE_DEV_ID_82599_SFP_EM:
117 124 case IXGBE_DEV_ID_82599_SFP_SF2:
118 125 case IXGBE_DEV_ID_82599EN_SFP:
119 126 case IXGBE_DEV_ID_82599_CX4:
120 127 case IXGBE_DEV_ID_82599_T3_LOM:
121 128 hw->mac.type = ixgbe_mac_82599EB;
122 129 break;
130 + case IXGBE_DEV_ID_82599_VF:
131 + hw->mac.type = ixgbe_mac_82599_vf;
132 + break;
133 + case IXGBE_DEV_ID_X540_VF:
134 + hw->mac.type = ixgbe_mac_X540_vf;
135 + break;
136 + case IXGBE_DEV_ID_X540T:
137 + case IXGBE_DEV_ID_X540T1:
138 + hw->mac.type = ixgbe_mac_X540;
139 + break;
123 140 default:
124 141 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
125 142 break;
126 143 }
127 144 } else {
128 145 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
129 146 }
130 147
131 148 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
132 - hw->mac.type, ret_val);
149 + hw->mac.type, ret_val);
133 150 return ret_val;
134 151 }
135 152
136 153 /**
137 154 * ixgbe_init_hw - Initialize the hardware
138 155 * @hw: pointer to hardware structure
139 156 *
140 157 * Initialize the hardware by resetting and then starting the hardware
141 158 **/
142 159 s32 ixgbe_init_hw(struct ixgbe_hw *hw)
143 160 {
144 161 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
145 - IXGBE_NOT_IMPLEMENTED);
162 + IXGBE_NOT_IMPLEMENTED);
146 163 }
147 164
148 165 /**
149 166 * ixgbe_reset_hw - Performs a hardware reset
150 167 * @hw: pointer to hardware structure
151 168 *
152 169 * Resets the hardware by resetting the transmit and receive units, masks and
153 170 * clears all interrupts, performs a PHY reset, and performs a MAC reset
154 171 **/
155 172 s32 ixgbe_reset_hw(struct ixgbe_hw *hw)
156 173 {
157 174 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),
158 - IXGBE_NOT_IMPLEMENTED);
175 + IXGBE_NOT_IMPLEMENTED);
159 176 }
160 177
161 178 /**
162 179 * ixgbe_start_hw - Prepares hardware for Rx/Tx
163 180 * @hw: pointer to hardware structure
164 181 *
165 182 * Starts the hardware by filling the bus info structure and media type,
166 183 * clears all on chip counters, initializes receive address registers,
167 184 * multicast table, VLAN filter table, calls routine to setup link and
168 185 * flow control settings, and leaves transmit and receive units disabled
169 186 * and uninitialized.
170 187 **/
171 188 s32 ixgbe_start_hw(struct ixgbe_hw *hw)
172 189 {
173 190 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),
174 - IXGBE_NOT_IMPLEMENTED);
191 + IXGBE_NOT_IMPLEMENTED);
175 192 }
176 193
177 194 /**
178 195 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,
179 196 * which is disabled by default in ixgbe_start_hw();
180 197 *
181 198 * @hw: pointer to hardware structure
182 199 *
183 200 * Enable relaxed ordering;
184 201 **/
185 202 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw)
186 203 {
187 204 if (hw->mac.ops.enable_relaxed_ordering)
188 205 hw->mac.ops.enable_relaxed_ordering(hw);
189 206 }
190 207
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191 208 /**
192 209 * ixgbe_clear_hw_cntrs - Clear hardware counters
193 210 * @hw: pointer to hardware structure
194 211 *
195 212 * Clears all hardware statistics counters by reading them from the hardware
196 213 * Statistics counters are clear on read.
197 214 **/
198 215 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
199 216 {
200 217 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),
201 - IXGBE_NOT_IMPLEMENTED);
218 + IXGBE_NOT_IMPLEMENTED);
202 219 }
203 220
204 221 /**
205 222 * ixgbe_get_media_type - Get media type
206 223 * @hw: pointer to hardware structure
207 224 *
208 225 * Returns the media type (fiber, copper, backplane)
209 226 **/
210 227 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)
211 228 {
212 229 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),
213 - ixgbe_media_type_unknown);
230 + ixgbe_media_type_unknown);
214 231 }
215 232
216 233 /**
217 234 * ixgbe_get_mac_addr - Get MAC address
218 235 * @hw: pointer to hardware structure
219 236 * @mac_addr: Adapter MAC address
220 237 *
221 238 * Reads the adapter's MAC address from the first Receive Address Register
222 239 * (RAR0) A reset of the adapter must have been performed prior to calling
223 240 * this function in order for the MAC address to have been loaded from the
224 241 * EEPROM into RAR0
225 242 **/
226 243 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
227 244 {
228 245 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,
229 - (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
246 + (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
230 247 }
231 248
232 249 /**
233 250 * ixgbe_get_san_mac_addr - Get SAN MAC address
234 251 * @hw: pointer to hardware structure
235 252 * @san_mac_addr: SAN MAC address
236 253 *
237 254 * Reads the SAN MAC address from the EEPROM, if it's available. This is
238 255 * per-port, so set_lan_id() must be called before reading the addresses.
239 256 **/
240 257 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
241 258 {
242 259 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr,
243 - (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
260 + (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
244 261 }
245 262
246 263 /**
247 264 * ixgbe_set_san_mac_addr - Write a SAN MAC address
248 265 * @hw: pointer to hardware structure
249 266 * @san_mac_addr: SAN MAC address
250 267 *
251 268 * Writes A SAN MAC address to the EEPROM.
252 269 **/
253 270 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
254 271 {
255 272 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr,
256 - (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
273 + (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
257 274 }
258 275
259 276 /**
260 277 * ixgbe_get_device_caps - Get additional device capabilities
261 278 * @hw: pointer to hardware structure
262 279 * @device_caps: the EEPROM word for device capabilities
263 280 *
264 281 * Reads the extra device capabilities from the EEPROM
265 282 **/
266 283 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
267 284 {
268 285 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps,
269 - (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
286 + (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
270 287 }
271 288
272 289 /**
273 290 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM
274 291 * @hw: pointer to hardware structure
275 292 * @wwnn_prefix: the alternative WWNN prefix
276 293 * @wwpn_prefix: the alternative WWPN prefix
277 294 *
278 295 * This function will read the EEPROM from the alternative SAN MAC address
279 296 * block to check the support for the alternative WWNN/WWPN prefix support.
280 297 **/
281 298 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
282 - u16 *wwpn_prefix)
299 + u16 *wwpn_prefix)
283 300 {
284 301 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,
285 - (hw, wwnn_prefix, wwpn_prefix),
286 - IXGBE_NOT_IMPLEMENTED);
302 + (hw, wwnn_prefix, wwpn_prefix),
303 + IXGBE_NOT_IMPLEMENTED);
287 304 }
288 305
289 306 /**
290 307 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM
291 308 * @hw: pointer to hardware structure
292 309 * @bs: the fcoe boot status
293 310 *
294 311 * This function will read the FCOE boot status from the iSCSI FCOE block
295 312 **/
296 313 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)
297 314 {
298 315 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status,
299 - (hw, bs),
300 - IXGBE_NOT_IMPLEMENTED);
316 + (hw, bs),
317 + IXGBE_NOT_IMPLEMENTED);
301 318 }
302 319
303 320 /**
304 321 * ixgbe_get_bus_info - Set PCI bus info
305 322 * @hw: pointer to hardware structure
306 323 *
307 324 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
308 325 **/
309 326 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)
310 327 {
311 328 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),
312 - IXGBE_NOT_IMPLEMENTED);
329 + IXGBE_NOT_IMPLEMENTED);
313 330 }
314 331
315 332 /**
316 333 * ixgbe_get_num_of_tx_queues - Get Tx queues
317 334 * @hw: pointer to hardware structure
318 335 *
319 336 * Returns the number of transmit queues for the given adapter.
320 337 **/
321 338 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
322 339 {
323 340 return hw->mac.max_tx_queues;
324 341 }
325 342
326 343 /**
327 344 * ixgbe_get_num_of_rx_queues - Get Rx queues
328 345 * @hw: pointer to hardware structure
329 346 *
330 347 * Returns the number of receive queues for the given adapter.
331 348 **/
332 349 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
333 350 {
334 351 return hw->mac.max_rx_queues;
335 352 }
336 353
337 354 /**
338 355 * ixgbe_stop_adapter - Disable Rx/Tx units
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339 356 * @hw: pointer to hardware structure
340 357 *
341 358 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
342 359 * disables transmit and receive units. The adapter_stopped flag is used by
343 360 * the shared code and drivers to determine if the adapter is in a stopped
344 361 * state and should not touch the hardware.
345 362 **/
346 363 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
347 364 {
348 365 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),
349 - IXGBE_NOT_IMPLEMENTED);
366 + IXGBE_NOT_IMPLEMENTED);
350 367 }
351 368
352 369 /**
353 370 * ixgbe_read_pba_string - Reads part number string from EEPROM
354 371 * @hw: pointer to hardware structure
355 372 * @pba_num: stores the part number string from the EEPROM
356 373 * @pba_num_size: part number string buffer length
357 374 *
358 375 * Reads the part number string from the EEPROM.
359 376 **/
360 377 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)
361 378 {
362 379 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);
363 380 }
364 381
365 382 /**
366 - * ixgbe_read_pba_length - Reads part number string length from EEPROM
367 - * @hw: pointer to hardware structure
368 - * @pba_num_size: part number string buffer length
369 - *
370 - * Reads the part number length from the EEPROM.
371 - * Returns expected buffer size in pba_num_size.
372 - **/
373 -s32 ixgbe_read_pba_length(struct ixgbe_hw *hw, u32 *pba_num_size)
374 -{
375 - return ixgbe_read_pba_length_generic(hw, pba_num_size);
376 -}
377 -
378 -/**
379 383 * ixgbe_read_pba_num - Reads part number from EEPROM
380 384 * @hw: pointer to hardware structure
381 385 * @pba_num: stores the part number from the EEPROM
382 386 *
383 387 * Reads the part number from the EEPROM.
384 388 **/
385 389 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)
386 390 {
387 391 return ixgbe_read_pba_num_generic(hw, pba_num);
388 392 }
389 393
390 394 /**
391 395 * ixgbe_identify_phy - Get PHY type
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392 396 * @hw: pointer to hardware structure
393 397 *
394 398 * Determines the physical layer module found on the current adapter.
395 399 **/
396 400 s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
397 401 {
398 402 s32 status = IXGBE_SUCCESS;
399 403
400 404 if (hw->phy.type == ixgbe_phy_unknown) {
401 405 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),
402 - IXGBE_NOT_IMPLEMENTED);
406 + IXGBE_NOT_IMPLEMENTED);
403 407 }
404 408
405 409 return status;
406 410 }
407 411
408 412 /**
409 413 * ixgbe_reset_phy - Perform a PHY reset
410 414 * @hw: pointer to hardware structure
411 415 **/
412 416 s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
413 417 {
414 418 s32 status = IXGBE_SUCCESS;
415 419
416 420 if (hw->phy.type == ixgbe_phy_unknown) {
417 421 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS)
418 422 status = IXGBE_ERR_PHY;
419 423 }
420 424
421 425 if (status == IXGBE_SUCCESS) {
422 426 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),
423 - IXGBE_NOT_IMPLEMENTED);
427 + IXGBE_NOT_IMPLEMENTED);
424 428 }
425 429 return status;
426 430 }
427 431
428 432 /**
429 433 * ixgbe_get_phy_firmware_version -
430 434 * @hw: pointer to hardware structure
431 435 * @firmware_version: pointer to firmware version
432 436 **/
433 437 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)
434 438 {
435 439 s32 status = IXGBE_SUCCESS;
436 440
437 441 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
438 - (hw, firmware_version),
439 - IXGBE_NOT_IMPLEMENTED);
442 + (hw, firmware_version),
443 + IXGBE_NOT_IMPLEMENTED);
440 444 return status;
441 445 }
442 446
443 447 /**
444 448 * ixgbe_read_phy_reg - Read PHY register
445 449 * @hw: pointer to hardware structure
446 450 * @reg_addr: 32 bit address of PHY register to read
447 451 * @phy_data: Pointer to read data from PHY register
448 452 *
449 453 * Reads a value from a specified PHY register
450 454 **/
451 455 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
452 - u16 *phy_data)
456 + u16 *phy_data)
453 457 {
454 458 if (hw->phy.id == 0)
455 - (void) ixgbe_identify_phy(hw);
459 + ixgbe_identify_phy(hw);
456 460
457 461 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
458 - device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
462 + device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
459 463 }
460 464
461 465 /**
462 466 * ixgbe_write_phy_reg - Write PHY register
463 467 * @hw: pointer to hardware structure
464 468 * @reg_addr: 32 bit PHY register to write
465 469 * @phy_data: Data to write to the PHY register
466 470 *
467 471 * Writes a value to specified PHY register
468 472 **/
469 473 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
470 - u16 phy_data)
474 + u16 phy_data)
471 475 {
472 476 if (hw->phy.id == 0)
473 - (void) ixgbe_identify_phy(hw);
477 + ixgbe_identify_phy(hw);
474 478
475 479 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
476 - device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
480 + device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
477 481 }
478 482
479 483 /**
480 484 * ixgbe_setup_phy_link - Restart PHY autoneg
481 485 * @hw: pointer to hardware structure
482 486 *
483 487 * Restart autonegotiation and PHY and waits for completion.
484 488 **/
485 489 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
486 490 {
487 491 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
488 - IXGBE_NOT_IMPLEMENTED);
492 + IXGBE_NOT_IMPLEMENTED);
489 493 }
490 494
491 495 /**
492 496 * ixgbe_check_phy_link - Determine link and speed status
493 497 * @hw: pointer to hardware structure
494 498 *
495 499 * Reads a PHY register to determine if link is up and the current speed for
496 500 * the PHY.
497 501 **/
498 502 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
499 - bool *link_up)
503 + bool *link_up)
500 504 {
501 505 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
502 - link_up), IXGBE_NOT_IMPLEMENTED);
506 + link_up), IXGBE_NOT_IMPLEMENTED);
503 507 }
504 508
505 509 /**
506 510 * ixgbe_setup_phy_link_speed - Set auto advertise
507 511 * @hw: pointer to hardware structure
508 512 * @speed: new link speed
509 513 * @autoneg: TRUE if autonegotiation enabled
510 514 *
511 515 * Sets the auto advertised capabilities
512 516 **/
513 517 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
514 - bool autoneg,
515 - bool autoneg_wait_to_complete)
518 + bool autoneg,
519 + bool autoneg_wait_to_complete)
516 520 {
517 521 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
518 - autoneg, autoneg_wait_to_complete),
519 - IXGBE_NOT_IMPLEMENTED);
522 + autoneg, autoneg_wait_to_complete),
523 + IXGBE_NOT_IMPLEMENTED);
520 524 }
521 525
522 526 /**
523 527 * ixgbe_check_link - Get link and speed status
524 528 * @hw: pointer to hardware structure
525 529 *
526 530 * Reads the links register to determine if link is up and the current speed
527 531 **/
528 532 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
529 - bool *link_up, bool link_up_wait_to_complete)
533 + bool *link_up, bool link_up_wait_to_complete)
530 534 {
531 535 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
532 - link_up, link_up_wait_to_complete),
533 - IXGBE_NOT_IMPLEMENTED);
536 + link_up, link_up_wait_to_complete),
537 + IXGBE_NOT_IMPLEMENTED);
534 538 }
535 539
536 540 /**
537 541 * ixgbe_disable_tx_laser - Disable Tx laser
538 542 * @hw: pointer to hardware structure
539 543 *
540 544 * If the driver needs to disable the laser on SFI optics.
541 545 **/
542 546 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)
543 547 {
544 548 if (hw->mac.ops.disable_tx_laser)
545 549 hw->mac.ops.disable_tx_laser(hw);
546 550 }
547 551
548 552 /**
549 553 * ixgbe_enable_tx_laser - Enable Tx laser
550 554 * @hw: pointer to hardware structure
551 555 *
552 556 * If the driver needs to enable the laser on SFI optics.
553 557 **/
554 558 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw)
555 559 {
556 560 if (hw->mac.ops.enable_tx_laser)
557 561 hw->mac.ops.enable_tx_laser(hw);
558 562 }
559 563
560 564 /**
561 565 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process
562 566 * @hw: pointer to hardware structure
563 567 *
564 568 * When the driver changes the link speeds that it can support then
565 569 * flap the tx laser to alert the link partner to start autotry
566 570 * process on its end.
567 571 **/
568 572 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
569 573 {
570 574 if (hw->mac.ops.flap_tx_laser)
571 575 hw->mac.ops.flap_tx_laser(hw);
572 576 }
573 577
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574 578 /**
575 579 * ixgbe_setup_link - Set link speed
576 580 * @hw: pointer to hardware structure
577 581 * @speed: new link speed
578 582 * @autoneg: TRUE if autonegotiation enabled
579 583 *
580 584 * Configures link settings. Restarts the link.
581 585 * Performs autonegotiation if needed.
582 586 **/
583 587 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
584 - bool autoneg,
585 - bool autoneg_wait_to_complete)
588 + bool autoneg,
589 + bool autoneg_wait_to_complete)
586 590 {
587 591 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
588 - autoneg, autoneg_wait_to_complete),
589 - IXGBE_NOT_IMPLEMENTED);
592 + autoneg, autoneg_wait_to_complete),
593 + IXGBE_NOT_IMPLEMENTED);
590 594 }
591 595
592 596 /**
593 597 * ixgbe_get_link_capabilities - Returns link capabilities
594 598 * @hw: pointer to hardware structure
595 599 *
596 600 * Determines the link capabilities of the current configuration.
597 601 **/
598 602 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
599 - bool *autoneg)
603 + bool *autoneg)
600 604 {
601 605 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
602 - speed, autoneg), IXGBE_NOT_IMPLEMENTED);
606 + speed, autoneg), IXGBE_NOT_IMPLEMENTED);
603 607 }
604 608
605 609 /**
606 610 * ixgbe_led_on - Turn on LEDs
607 611 * @hw: pointer to hardware structure
608 612 * @index: led number to turn on
609 613 *
610 614 * Turns on the software controllable LEDs.
611 615 **/
612 616 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
613 617 {
614 618 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),
615 - IXGBE_NOT_IMPLEMENTED);
619 + IXGBE_NOT_IMPLEMENTED);
616 620 }
617 621
618 622 /**
619 623 * ixgbe_led_off - Turn off LEDs
620 624 * @hw: pointer to hardware structure
621 625 * @index: led number to turn off
622 626 *
623 627 * Turns off the software controllable LEDs.
624 628 **/
625 629 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
626 630 {
627 631 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),
628 - IXGBE_NOT_IMPLEMENTED);
632 + IXGBE_NOT_IMPLEMENTED);
629 633 }
630 634
631 635 /**
632 636 * ixgbe_blink_led_start - Blink LEDs
633 637 * @hw: pointer to hardware structure
634 638 * @index: led number to blink
635 639 *
636 640 * Blink LED based on index.
637 641 **/
638 642 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
639 643 {
640 644 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),
641 - IXGBE_NOT_IMPLEMENTED);
645 + IXGBE_NOT_IMPLEMENTED);
642 646 }
643 647
644 648 /**
645 649 * ixgbe_blink_led_stop - Stop blinking LEDs
646 650 * @hw: pointer to hardware structure
647 651 *
648 652 * Stop blinking LED based on index.
649 653 **/
650 654 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
651 655 {
652 656 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),
653 - IXGBE_NOT_IMPLEMENTED);
657 + IXGBE_NOT_IMPLEMENTED);
654 658 }
655 659
656 660 /**
657 661 * ixgbe_init_eeprom_params - Initialize EEPROM parameters
658 662 * @hw: pointer to hardware structure
659 663 *
660 664 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
661 665 * ixgbe_hw struct in order to set up EEPROM access.
662 666 **/
663 667 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
664 668 {
665 669 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),
666 - IXGBE_NOT_IMPLEMENTED);
670 + IXGBE_NOT_IMPLEMENTED);
667 671 }
668 672
669 673
670 674 /**
671 675 * ixgbe_write_eeprom - Write word to EEPROM
672 676 * @hw: pointer to hardware structure
673 677 * @offset: offset within the EEPROM to be written to
674 678 * @data: 16 bit word to be written to the EEPROM
675 679 *
676 680 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
677 681 * called after this function, the EEPROM will most likely contain an
678 682 * invalid checksum.
679 683 **/
680 684 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
681 685 {
682 686 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),
683 - IXGBE_NOT_IMPLEMENTED);
687 + IXGBE_NOT_IMPLEMENTED);
684 688 }
685 689
686 690 /**
691 + * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM
692 + * @hw: pointer to hardware structure
693 + * @offset: offset within the EEPROM to be written to
694 + * @data: 16 bit word(s) to be written to the EEPROM
695 + * @words: number of words
696 + *
697 + * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not
698 + * called after this function, the EEPROM will most likely contain an
699 + * invalid checksum.
700 + **/
701 +s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,
702 + u16 *data)
703 +{
704 + return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer,
705 + (hw, offset, words, data),
706 + IXGBE_NOT_IMPLEMENTED);
707 +}
708 +
709 +/**
687 710 * ixgbe_read_eeprom - Read word from EEPROM
688 711 * @hw: pointer to hardware structure
689 712 * @offset: offset within the EEPROM to be read
690 713 * @data: read 16 bit value from EEPROM
691 714 *
692 715 * Reads 16 bit value from EEPROM
693 716 **/
694 717 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
695 718 {
696 719 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),
697 - IXGBE_NOT_IMPLEMENTED);
720 + IXGBE_NOT_IMPLEMENTED);
698 721 }
699 722
700 723 /**
724 + * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM
725 + * @hw: pointer to hardware structure
726 + * @offset: offset within the EEPROM to be read
727 + * @data: read 16 bit word(s) from EEPROM
728 + * @words: number of words
729 + *
730 + * Reads 16 bit word(s) from EEPROM
731 + **/
732 +s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
733 + u16 words, u16 *data)
734 +{
735 + return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer,
736 + (hw, offset, words, data),
737 + IXGBE_NOT_IMPLEMENTED);
738 +}
739 +
740 +/**
701 741 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
702 742 * @hw: pointer to hardware structure
703 743 * @checksum_val: calculated checksum
704 744 *
705 745 * Performs checksum calculation and validates the EEPROM checksum
706 746 **/
707 747 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
708 748 {
709 749 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,
710 - (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
750 + (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
711 751 }
712 752
713 753 /**
714 754 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
715 755 * @hw: pointer to hardware structure
716 756 **/
717 757 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
718 758 {
719 759 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),
720 - IXGBE_NOT_IMPLEMENTED);
760 + IXGBE_NOT_IMPLEMENTED);
721 761 }
722 762
723 763 /**
724 764 * ixgbe_insert_mac_addr - Find a RAR for this mac address
725 765 * @hw: pointer to hardware structure
726 766 * @addr: Address to put into receive address register
727 767 * @vmdq: VMDq pool to assign
728 768 *
729 769 * Puts an ethernet address into a receive address register, or
730 770 * finds the rar that it is aleady in; adds to the pool list
731 771 **/
732 772 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
733 773 {
734 774 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr,
735 - (hw, addr, vmdq),
775 + (hw, addr, vmdq),
736 776 IXGBE_NOT_IMPLEMENTED);
737 777 }
738 778
739 779 /**
740 780 * ixgbe_set_rar - Set Rx address register
741 781 * @hw: pointer to hardware structure
742 782 * @index: Receive address register to write
743 783 * @addr: Address to put into receive address register
744 784 * @vmdq: VMDq "set"
745 785 * @enable_addr: set flag that address is active
746 786 *
747 787 * Puts an ethernet address into a receive address register.
748 788 **/
749 789 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
750 - u32 enable_addr)
790 + u32 enable_addr)
751 791 {
752 792 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,
753 - enable_addr), IXGBE_NOT_IMPLEMENTED);
793 + enable_addr), IXGBE_NOT_IMPLEMENTED);
754 794 }
755 795
756 796 /**
757 797 * ixgbe_clear_rar - Clear Rx address register
758 798 * @hw: pointer to hardware structure
759 799 * @index: Receive address register to write
760 800 *
761 801 * Puts an ethernet address into a receive address register.
762 802 **/
763 803 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
764 804 {
765 805 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),
766 - IXGBE_NOT_IMPLEMENTED);
806 + IXGBE_NOT_IMPLEMENTED);
767 807 }
768 808
769 809 /**
770 810 * ixgbe_set_vmdq - Associate a VMDq index with a receive address
771 811 * @hw: pointer to hardware structure
772 812 * @rar: receive address register index to associate with VMDq index
773 813 * @vmdq: VMDq set or pool index
774 814 **/
775 815 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
776 816 {
777 817 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
778 - IXGBE_NOT_IMPLEMENTED);
818 + IXGBE_NOT_IMPLEMENTED);
819 +
779 820 }
780 821
781 822 /**
823 + * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
824 + * @hw: pointer to hardware structure
825 + * @vmdq: VMDq default pool index
826 + **/
827 +s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)
828 +{
829 + return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,
830 + (hw, vmdq), IXGBE_NOT_IMPLEMENTED);
831 +}
832 +
833 +/**
782 834 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
783 835 * @hw: pointer to hardware structure
784 836 * @rar: receive address register index to disassociate with VMDq index
785 837 * @vmdq: VMDq set or pool index
786 838 **/
787 839 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
788 840 {
789 841 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),
790 - IXGBE_NOT_IMPLEMENTED);
842 + IXGBE_NOT_IMPLEMENTED);
791 843 }
792 844
793 845 /**
794 846 * ixgbe_init_rx_addrs - Initializes receive address filters.
795 847 * @hw: pointer to hardware structure
796 848 *
797 849 * Places the MAC address in receive address register 0 and clears the rest
798 850 * of the receive address registers. Clears the multicast table. Assumes
799 851 * the receiver is in reset when the routine is called.
800 852 **/
801 853 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
802 854 {
803 855 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),
804 - IXGBE_NOT_IMPLEMENTED);
856 + IXGBE_NOT_IMPLEMENTED);
805 857 }
806 858
807 859 /**
808 860 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
809 861 * @hw: pointer to hardware structure
810 862 **/
811 863 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)
812 864 {
813 865 return hw->mac.num_rar_entries;
814 866 }
815 867
816 868 /**
817 869 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses
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818 870 * @hw: pointer to hardware structure
819 871 * @addr_list: the list of new multicast addresses
820 872 * @addr_count: number of addresses
821 873 * @func: iterator function to walk the multicast address list
822 874 *
823 875 * The given list replaces any existing list. Clears the secondary addrs from
824 876 * receive address registers. Uses unused receive address registers for the
825 877 * first secondary addresses, and falls back to promiscuous mode as needed.
826 878 **/
827 879 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
828 - u32 addr_count, ixgbe_mc_addr_itr func)
880 + u32 addr_count, ixgbe_mc_addr_itr func)
829 881 {
830 882 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,
831 - addr_list, addr_count, func),
832 - IXGBE_NOT_IMPLEMENTED);
883 + addr_list, addr_count, func),
884 + IXGBE_NOT_IMPLEMENTED);
833 885 }
834 886
835 887 /**
836 888 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
837 889 * @hw: pointer to hardware structure
838 890 * @mc_addr_list: the list of new multicast addresses
839 891 * @mc_addr_count: number of addresses
840 892 * @func: iterator function to walk the multicast address list
841 893 *
842 894 * The given list replaces any existing list. Clears the MC addrs from receive
843 895 * address registers and the multicast table. Uses unused receive address
844 896 * registers for the first multicast addresses, and hashes the rest into the
845 897 * multicast table.
846 898 **/
847 899 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
848 - u32 mc_addr_count, ixgbe_mc_addr_itr func)
900 + u32 mc_addr_count, ixgbe_mc_addr_itr func,
901 + bool clear)
849 902 {
850 903 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
851 - mc_addr_list, mc_addr_count, func),
852 - IXGBE_NOT_IMPLEMENTED);
904 + mc_addr_list, mc_addr_count, func, clear),
905 + IXGBE_NOT_IMPLEMENTED);
853 906 }
854 907
855 908 /**
856 909 * ixgbe_enable_mc - Enable multicast address in RAR
857 910 * @hw: pointer to hardware structure
858 911 *
859 912 * Enables multicast address in RAR and the use of the multicast hash table.
860 913 **/
861 914 s32 ixgbe_enable_mc(struct ixgbe_hw *hw)
862 915 {
863 916 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),
864 - IXGBE_NOT_IMPLEMENTED);
917 + IXGBE_NOT_IMPLEMENTED);
865 918 }
866 919
867 920 /**
868 921 * ixgbe_disable_mc - Disable multicast address in RAR
869 922 * @hw: pointer to hardware structure
870 923 *
871 924 * Disables multicast address in RAR and the use of the multicast hash table.
872 925 **/
873 926 s32 ixgbe_disable_mc(struct ixgbe_hw *hw)
874 927 {
875 928 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),
876 - IXGBE_NOT_IMPLEMENTED);
929 + IXGBE_NOT_IMPLEMENTED);
877 930 }
878 931
879 932 /**
880 933 * ixgbe_clear_vfta - Clear VLAN filter table
881 934 * @hw: pointer to hardware structure
882 935 *
883 936 * Clears the VLAN filer table, and the VMDq index associated with the filter
884 937 **/
885 938 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
886 939 {
887 940 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
888 - IXGBE_NOT_IMPLEMENTED);
941 + IXGBE_NOT_IMPLEMENTED);
889 942 }
890 943
891 944 /**
892 945 * ixgbe_set_vfta - Set VLAN filter table
893 946 * @hw: pointer to hardware structure
894 947 * @vlan: VLAN id to write to VLAN filter
895 948 * @vind: VMDq output index that maps queue to VLAN id in VFTA
896 949 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
897 950 *
898 951 * Turn on/off specified VLAN in the VLAN filter table.
899 952 **/
900 953 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
901 954 {
902 955 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
903 - vlan_on), IXGBE_NOT_IMPLEMENTED);
956 + vlan_on), IXGBE_NOT_IMPLEMENTED);
904 957 }
905 958
906 959 /**
960 + * ixgbe_set_vlvf - Set VLAN Pool Filter
961 + * @hw: pointer to hardware structure
962 + * @vlan: VLAN id to write to VLAN filter
963 + * @vind: VMDq output index that maps queue to VLAN id in VFVFB
964 + * @vlan_on: boolean flag to turn on/off VLAN in VFVF
965 + * @vfta_changed: pointer to boolean flag which indicates whether VFTA
966 + * should be changed
967 + *
968 + * Turn on/off specified bit in VLVF table.
969 + **/
970 +s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
971 + bool *vfta_changed)
972 +{
973 + return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
974 + vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);
975 +}
976 +
977 +/**
907 978 * ixgbe_fc_enable - Enable flow control
908 979 * @hw: pointer to hardware structure
909 - * @packetbuf_num: packet buffer number (0-7)
910 980 *
911 981 * Configures the flow control settings based on SW configuration.
912 982 **/
913 -s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
983 +s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
914 984 {
915 - return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num),
916 - IXGBE_NOT_IMPLEMENTED);
985 + return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
986 + IXGBE_NOT_IMPLEMENTED);
917 987 }
918 988
919 989 /**
990 + * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
991 + * @hw: pointer to hardware structure
992 + * @maj: driver major number to be sent to firmware
993 + * @min: driver minor number to be sent to firmware
994 + * @build: driver build number to be sent to firmware
995 + * @ver: driver version number to be sent to firmware
996 + **/
997 +s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
998 + u8 ver)
999 +{
1000 + return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
1001 + build, ver), IXGBE_NOT_IMPLEMENTED);
1002 +}
1003 +
1004 +
1005 +/**
920 1006 * ixgbe_read_analog_reg8 - Reads 8 bit analog register
921 1007 * @hw: pointer to hardware structure
922 1008 * @reg: analog register to read
923 1009 * @val: read value
924 1010 *
925 1011 * Performs write operation to analog register specified.
926 1012 **/
927 1013 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
928 1014 {
929 1015 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
930 - val), IXGBE_NOT_IMPLEMENTED);
1016 + val), IXGBE_NOT_IMPLEMENTED);
931 1017 }
932 1018
933 1019 /**
934 1020 * ixgbe_write_analog_reg8 - Writes 8 bit analog register
935 1021 * @hw: pointer to hardware structure
936 1022 * @reg: analog register to write
937 1023 * @val: value to write
938 1024 *
939 1025 * Performs write operation to Atlas analog register specified.
940 1026 **/
941 1027 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
942 1028 {
943 1029 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,
944 - val), IXGBE_NOT_IMPLEMENTED);
1030 + val), IXGBE_NOT_IMPLEMENTED);
945 1031 }
946 1032
947 1033 /**
948 1034 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
949 1035 * @hw: pointer to hardware structure
950 1036 *
951 1037 * Initializes the Unicast Table Arrays to zero on device load. This
952 1038 * is part of the Rx init addr execution path.
953 1039 **/
954 1040 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
955 1041 {
956 1042 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
957 - IXGBE_NOT_IMPLEMENTED);
1043 + IXGBE_NOT_IMPLEMENTED);
958 1044 }
959 1045
960 1046 /**
961 1047 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
962 1048 * @hw: pointer to hardware structure
963 1049 * @byte_offset: byte offset to read
964 1050 * @data: value read
965 1051 *
966 1052 * Performs byte read operation to SFP module's EEPROM over I2C interface.
967 1053 **/
968 1054 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
969 - u8 *data)
1055 + u8 *data)
970 1056 {
971 1057 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,
972 - dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1058 + dev_addr, data), IXGBE_NOT_IMPLEMENTED);
973 1059 }
974 1060
975 1061 /**
976 1062 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
977 1063 * @hw: pointer to hardware structure
978 1064 * @byte_offset: byte offset to write
979 1065 * @data: value to write
980 1066 *
981 1067 * Performs byte write operation to SFP module's EEPROM over I2C interface
982 1068 * at a specified device address.
983 1069 **/
984 1070 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
985 - u8 data)
1071 + u8 data)
986 1072 {
987 1073 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,
988 - dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1074 + dev_addr, data), IXGBE_NOT_IMPLEMENTED);
989 1075 }
990 1076
991 1077 /**
992 1078 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
993 1079 * @hw: pointer to hardware structure
994 1080 * @byte_offset: EEPROM byte offset to write
995 1081 * @eeprom_data: value to write
996 1082 *
997 1083 * Performs byte write operation to SFP module's EEPROM over I2C interface.
998 1084 **/
999 1085 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,
1000 - u8 byte_offset, u8 eeprom_data)
1086 + u8 byte_offset, u8 eeprom_data)
1001 1087 {
1002 1088 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,
1003 - (hw, byte_offset, eeprom_data),
1004 - IXGBE_NOT_IMPLEMENTED);
1089 + (hw, byte_offset, eeprom_data),
1090 + IXGBE_NOT_IMPLEMENTED);
1005 1091 }
1006 1092
1007 1093 /**
1008 1094 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1009 1095 * @hw: pointer to hardware structure
1010 1096 * @byte_offset: EEPROM byte offset to read
1011 1097 * @eeprom_data: value read
1012 1098 *
1013 1099 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1014 1100 **/
1015 1101 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
1016 1102 {
1017 1103 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,
1018 - (hw, byte_offset, eeprom_data),
1019 - IXGBE_NOT_IMPLEMENTED);
1104 + (hw, byte_offset, eeprom_data),
1105 + IXGBE_NOT_IMPLEMENTED);
1020 1106 }
1021 1107
1022 1108 /**
1023 1109 * ixgbe_get_supported_physical_layer - Returns physical layer type
1024 1110 * @hw: pointer to hardware structure
1025 1111 *
1026 1112 * Determines physical layer capabilities of the current configuration.
1027 1113 **/
1028 1114 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
1029 1115 {
1030 1116 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
1031 - (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
1117 + (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
1032 1118 }
1033 1119
1034 1120 /**
1035 - * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics
1121 + * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
1036 1122 * @hw: pointer to hardware structure
1037 1123 * @regval: bitfield to write to the Rx DMA register
1038 1124 *
1039 1125 * Enables the Rx DMA unit of the device.
1040 1126 **/
1041 1127 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)
1042 1128 {
1043 1129 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
1044 - (hw, regval), IXGBE_NOT_IMPLEMENTED);
1130 + (hw, regval), IXGBE_NOT_IMPLEMENTED);
1045 1131 }
1046 1132
1047 1133 /**
1134 + * ixgbe_disable_sec_rx_path - Stops the receive data path
1135 + * @hw: pointer to hardware structure
1136 + *
1137 + * Stops the receive data path.
1138 + **/
1139 +s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)
1140 +{
1141 + return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path,
1142 + (hw), IXGBE_NOT_IMPLEMENTED);
1143 +}
1144 +
1145 +/**
1146 + * ixgbe_enable_sec_rx_path - Enables the receive data path
1147 + * @hw: pointer to hardware structure
1148 + *
1149 + * Enables the receive data path.
1150 + **/
1151 +s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)
1152 +{
1153 + return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,
1154 + (hw), IXGBE_NOT_IMPLEMENTED);
1155 +}
1156 +
1157 +/**
1048 1158 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
1049 1159 * @hw: pointer to hardware structure
1050 1160 * @mask: Mask to specify which semaphore to acquire
1051 1161 *
1052 1162 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
1053 1163 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1054 1164 **/
1055 1165 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
1056 1166 {
1057 1167 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
1058 - (hw, mask), IXGBE_NOT_IMPLEMENTED);
1168 + (hw, mask), IXGBE_NOT_IMPLEMENTED);
1059 1169 }
1060 1170
1061 1171 /**
1062 1172 * ixgbe_release_swfw_semaphore - Release SWFW semaphore
1063 1173 * @hw: pointer to hardware structure
1064 1174 * @mask: Mask to specify which semaphore to release
1065 1175 *
1066 1176 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified
1067 1177 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1068 1178 **/
1069 1179 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
1070 1180 {
1071 1181 if (hw->mac.ops.release_swfw_sync)
1072 1182 hw->mac.ops.release_swfw_sync(hw, mask);
1073 1183 }
1074 1184
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