Print this page
3178 Support for LSI 2208 chipset in mr_sas
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/io/mr_sas/mr_sas.h
+++ new/usr/src/uts/common/io/mr_sas/mr_sas.h
1 1 /*
2 2 * mr_sas.h: header for mr_sas
3 3 *
4 4 * Solaris MegaRAID driver for SAS2.0 controllers
5 - * Copyright (c) 2008-2009, LSI Logic Corporation.
5 + * Copyright (c) 2008-2012, LSI Logic Corporation.
6 6 * All rights reserved.
7 7 *
8 + * Version:
9 + * Author:
10 + * Swaminathan K S
11 + * Arun Chandrashekhar
12 + * Manju R
13 + * Rasheed
14 + * Shakeel Bukhari
15 + *
8 16 * Redistribution and use in source and binary forms, with or without
9 17 * modification, are permitted provided that the following conditions are met:
10 18 *
11 19 * 1. Redistributions of source code must retain the above copyright notice,
12 20 * this list of conditions and the following disclaimer.
13 21 *
14 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
15 23 * this list of conditions and the following disclaimer in the documentation
16 24 * and/or other materials provided with the distribution.
17 25 *
18 26 * 3. Neither the name of the author nor the names of its contributors may be
19 27 * used to endorse or promote products derived from this software without
20 28 * specific prior written permission.
21 29 *
22 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
↓ open down ↓ |
11 lines elided |
↑ open up ↑ |
29 37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 41 * DAMAGE.
34 42 */
35 43
36 44 /*
37 45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
38 46 */
47 +
39 48 #ifndef _MR_SAS_H_
40 49 #define _MR_SAS_H_
41 50
42 51 #ifdef __cplusplus
43 52 extern "C" {
44 53 #endif
45 54
46 55 #include <sys/scsi/scsi.h>
47 56 #include "mr_sas_list.h"
57 +#include "ld_pd_map.h"
48 58
49 59 /*
50 60 * MegaRAID SAS2.0 Driver meta data
51 61 */
52 -#define MRSAS_VERSION "LSIv2.7"
53 -#define MRSAS_RELDATE "Apr 21, 2010"
62 +#define MRSAS_VERSION "6.503.00.00ILLUMOS"
63 +#define MRSAS_RELDATE "July 30, 2012"
54 64
55 65 #define MRSAS_TRUE 1
56 66 #define MRSAS_FALSE 0
57 67
58 68 #define ADAPTER_RESET_NOT_REQUIRED 0
59 69 #define ADAPTER_RESET_REQUIRED 1
60 70
71 +#define PDSUPPORT 1
72 +
61 73 /*
62 74 * MegaRAID SAS2.0 device id conversion definitions.
63 75 */
64 76 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT)
77 +#define MRSAS_GET_BOUNDARY_ALIGNED_LEN(len, new_len, boundary_len) { \
78 + int rem; \
79 + rem = (len / boundary_len); \
80 + if ((rem * boundary_len) != len) { \
81 + new_len = len + ((rem + 1) * boundary_len - len); \
82 + } else { \
83 + new_len = len; \
84 + } \
85 +}
65 86
87 +
66 88 /*
67 89 * MegaRAID SAS2.0 supported controllers
68 90 */
69 91 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078
70 92 #define PCI_DEVICE_ID_LSI_2108V 0x0079
93 +#define PCI_DEVICE_ID_LSI_TBOLT 0x005b
94 +#define PCI_DEVICE_ID_LSI_INVADER 0x005d
71 95
72 96 /*
73 97 * Register Index for 2108 Controllers.
74 98 */
75 99 #define REGISTER_SET_IO_2108 (2)
76 100
77 101 #define MRSAS_MAX_SGE_CNT 0x50
102 +#define MRSAS_APP_RESERVED_CMDS 32
78 103
79 104 #define MRSAS_IOCTL_DRIVER 0x12341234
80 105 #define MRSAS_IOCTL_FIRMWARE 0x12345678
81 106 #define MRSAS_IOCTL_AEN 0x87654321
82 107
83 108 #define MRSAS_1_SECOND 1000000
84 109
110 +#ifdef PDSUPPORT
111 +
112 +#define UNCONFIGURED_GOOD 0x0
113 +#define PD_SYSTEM 0x40
114 +#define MR_EVT_PD_STATE_CHANGE 0x0072
115 +#define MR_EVT_PD_REMOVED_EXT 0x00f8
116 +#define MR_EVT_PD_INSERTED_EXT 0x00f7
117 +#define MR_DCMD_PD_GET_INFO 0x02020000
118 +#define MRSAS_TBOLT_PD_LUN 1
119 +#define MRSAS_TBOLT_PD_TGT_MAX 255
120 +#define MRSAS_TBOLT_GET_PD_MAX(s) ((s)->mr_tbolt_pd_max)
121 +
122 +#endif
123 +
124 +/* Raid Context Flags */
125 +#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
126 +#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
127 +typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
128 + MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
129 + MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1
130 +} MR_RAID_FLAGS_IO_SUB_TYPE;
131 +
85 132 /* Dynamic Enumeration Flags */
86 -#define MRSAS_PD_LUN 1
87 133 #define MRSAS_LD_LUN 0
88 -#define MRSAS_PD_TGT_MAX 255
89 -#define MRSAS_GET_PD_MAX(s) ((s)->mr_pd_max)
90 134 #define WWN_STRLEN 17
91 -#define APP_RESERVE_CMDS 32
135 +#define LD_SYNC_BIT 1
136 +#define LD_SYNC_SHIFT 14
137 +/* ThunderBolt (TB) specific */
138 +#define MRSAS_THUNDERBOLT_MSG_SIZE 256
139 +#define MRSAS_THUNDERBOLT_MAX_COMMANDS 1024
140 +#define MRSAS_THUNDERBOLT_MAX_REPLY_COUNT 1024
141 +#define MRSAS_THUNDERBOLT_REPLY_SIZE 8
142 +#define MRSAS_THUNDERBOLT_MAX_CHAIN_COUNT 1
143 +
144 +#define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
145 +#define MPI2_FUNCTION_LD_IO_REQUEST 0xF1
146 +
147 +#define MR_EVT_LD_FAST_PATH_IO_STATUS_CHANGED (0xFFFF)
148 +
149 +#define MR_INTERNAL_MFI_FRAMES_SMID 1
150 +#define MR_CTRL_EVENT_WAIT_SMID 2
151 +#define MR_INTERNAL_DRIVER_RESET_SMID 3
152 +
153 +
92 154 /*
93 155 * =====================================
94 156 * MegaRAID SAS2.0 MFI firmware definitions
95 157 * =====================================
96 158 */
97 159 /*
98 160 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for
99 161 * protocol between the software and firmware. Commands are issued using
100 162 * "message frames"
101 163 */
102 164
103 165 /*
104 166 * FW posts its state in upper 4 bits of outbound_msg_0 register
105 167 */
106 -#define MFI_STATE_SHIFT 28
107 -#define MFI_STATE_MASK ((uint32_t)0xF<<MFI_STATE_SHIFT)
108 -#define MFI_STATE_UNDEFINED ((uint32_t)0x0<<MFI_STATE_SHIFT)
109 -#define MFI_STATE_BB_INIT ((uint32_t)0x1<<MFI_STATE_SHIFT)
110 -#define MFI_STATE_FW_INIT ((uint32_t)0x4<<MFI_STATE_SHIFT)
111 -#define MFI_STATE_WAIT_HANDSHAKE ((uint32_t)0x6<<MFI_STATE_SHIFT)
112 -#define MFI_STATE_FW_INIT_2 ((uint32_t)0x7<<MFI_STATE_SHIFT)
113 -#define MFI_STATE_DEVICE_SCAN ((uint32_t)0x8<<MFI_STATE_SHIFT)
114 -#define MFI_STATE_BOOT_MESSAGE_PENDING ((uint32_t)0x9<<MFI_STATE_SHIFT)
115 -#define MFI_STATE_FLUSH_CACHE ((uint32_t)0xA<<MFI_STATE_SHIFT)
116 -#define MFI_STATE_READY ((uint32_t)0xB<<MFI_STATE_SHIFT)
117 -#define MFI_STATE_OPERATIONAL ((uint32_t)0xC<<MFI_STATE_SHIFT)
118 -#define MFI_STATE_FAULT ((uint32_t)0xF<<MFI_STATE_SHIFT)
168 +#define MFI_STATE_MASK 0xF0000000
169 +#define MFI_STATE_UNDEFINED 0x00000000
170 +#define MFI_STATE_BB_INIT 0x10000000
171 +#define MFI_STATE_FW_INIT 0x40000000
172 +#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
173 +#define MFI_STATE_FW_INIT_2 0x70000000
174 +#define MFI_STATE_DEVICE_SCAN 0x80000000
175 +#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
176 +#define MFI_STATE_FLUSH_CACHE 0xA0000000
177 +#define MFI_STATE_READY 0xB0000000
178 +#define MFI_STATE_OPERATIONAL 0xC0000000
179 +#define MFI_STATE_FAULT 0xF0000000
119 180
120 181 #define MRMFI_FRAME_SIZE 64
121 182
122 183 /*
123 184 * During FW init, clear pending cmds & reset state using inbound_msg_0
124 185 *
125 186 * ABORT : Abort all pending cmds
126 187 * READY : Move from OPERATIONAL to READY state; discard queue info
127 188 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
128 189 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
129 190 */
130 191 #define MFI_INIT_ABORT 0x00000001
131 192 #define MFI_INIT_READY 0x00000002
132 193 #define MFI_INIT_MFIMODE 0x00000004
133 194 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
134 195 #define MFI_INIT_HOTPLUG 0x00000010
135 196 #define MFI_STOP_ADP 0x00000020
136 197 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
137 198
138 199 /*
139 200 * MFI frame flags
140 201 */
|
↓ open down ↓ |
12 lines elided |
↑ open up ↑ |
141 202 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
142 203 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
143 204 #define MFI_FRAME_SGL32 0x0000
144 205 #define MFI_FRAME_SGL64 0x0002
145 206 #define MFI_FRAME_SENSE32 0x0000
146 207 #define MFI_FRAME_SENSE64 0x0004
147 208 #define MFI_FRAME_DIR_NONE 0x0000
148 209 #define MFI_FRAME_DIR_WRITE 0x0008
149 210 #define MFI_FRAME_DIR_READ 0x0010
150 211 #define MFI_FRAME_DIR_BOTH 0x0018
151 -#define MFI_FRAME_IEEE 0x0020
212 +#define MFI_FRAME_IEEE 0x0020
152 213
153 214 /*
154 215 * Definition for cmd_status
155 216 */
156 217 #define MFI_CMD_STATUS_POLL_MODE 0xFF
157 218 #define MFI_CMD_STATUS_SYNC_MODE 0xFF
158 219
159 220 /*
160 221 * MFI command opcodes
161 222 */
162 223 #define MFI_CMD_OP_INIT 0x00
163 224 #define MFI_CMD_OP_LD_READ 0x01
164 225 #define MFI_CMD_OP_LD_WRITE 0x02
165 226 #define MFI_CMD_OP_LD_SCSI 0x03
166 227 #define MFI_CMD_OP_PD_SCSI 0x04
167 228 #define MFI_CMD_OP_DCMD 0x05
168 229 #define MFI_CMD_OP_ABORT 0x06
169 230 #define MFI_CMD_OP_SMP 0x07
170 231 #define MFI_CMD_OP_STP 0x08
171 232
172 233 #define MR_DCMD_CTRL_GET_INFO 0x01010000
173 234
174 235 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
|
↓ open down ↓ |
13 lines elided |
↑ open up ↑ |
175 236 #define MR_FLUSH_CTRL_CACHE 0x01
176 237 #define MR_FLUSH_DISK_CACHE 0x02
177 238
178 239 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
179 240 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01
180 241
181 242 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
182 243 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
183 244 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
184 245 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
185 -#define MR_DCMD_PD_GET_INFO 0x02020000
186 246
187 247 /*
188 248 * Solaris Specific MAX values
189 249 */
190 250 #define MAX_SGL 24
251 +
191 252 /*
192 253 * MFI command completion codes
193 254 */
194 255 enum MFI_STAT {
195 256 MFI_STAT_OK = 0x00,
196 257 MFI_STAT_INVALID_CMD = 0x01,
197 258 MFI_STAT_INVALID_DCMD = 0x02,
198 259 MFI_STAT_INVALID_PARAMETER = 0x03,
199 260 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
200 261 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
201 262 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
202 263 MFI_STAT_APP_IN_USE = 0x07,
203 264 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
204 265 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
205 266 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
206 267 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
207 268 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
208 269 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
209 270 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
210 271 MFI_STAT_FLASH_BUSY = 0x0f,
211 272 MFI_STAT_FLASH_ERROR = 0x10,
212 273 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
213 274 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
214 275 MFI_STAT_FLASH_NOT_OPEN = 0x13,
215 276 MFI_STAT_FLASH_NOT_STARTED = 0x14,
216 277 MFI_STAT_FLUSH_FAILED = 0x15,
217 278 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
218 279 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
219 280 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
220 281 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
221 282 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
222 283 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
223 284 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
224 285 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
225 286 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
226 287 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
227 288 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
228 289 MFI_STAT_MFC_HW_ERROR = 0x21,
229 290 MFI_STAT_NO_HW_PRESENT = 0x22,
230 291 MFI_STAT_NOT_FOUND = 0x23,
231 292 MFI_STAT_NOT_IN_ENCL = 0x24,
232 293 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
233 294 MFI_STAT_PD_TYPE_WRONG = 0x26,
234 295 MFI_STAT_PR_DISABLED = 0x27,
235 296 MFI_STAT_ROW_INDEX_INVALID = 0x28,
236 297 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
|
↓ open down ↓ |
36 lines elided |
↑ open up ↑ |
237 298 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
238 299 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
239 300 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
240 301 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
241 302 MFI_STAT_SCSI_IO_FAILED = 0x2e,
242 303 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
243 304 MFI_STAT_SHUTDOWN_FAILED = 0x30,
244 305 MFI_STAT_TIME_NOT_SET = 0x31,
245 306 MFI_STAT_WRONG_STATE = 0x32,
246 307 MFI_STAT_LD_OFFLINE = 0x33,
247 - /* UNUSED: 0x34 to 0xfe */
248 308 MFI_STAT_INVALID_STATUS = 0xFF
249 309 };
250 310
251 311 enum MR_EVT_CLASS {
252 312 MR_EVT_CLASS_DEBUG = -2,
253 313 MR_EVT_CLASS_PROGRESS = -1,
254 314 MR_EVT_CLASS_INFO = 0,
255 315 MR_EVT_CLASS_WARNING = 1,
256 316 MR_EVT_CLASS_CRITICAL = 2,
257 317 MR_EVT_CLASS_FATAL = 3,
258 318 MR_EVT_CLASS_DEAD = 4
259 319 };
260 320
261 321 enum MR_EVT_LOCALE {
262 322 MR_EVT_LOCALE_LD = 0x0001,
|
↓ open down ↓ |
5 lines elided |
↑ open up ↑ |
263 323 MR_EVT_LOCALE_PD = 0x0002,
264 324 MR_EVT_LOCALE_ENCL = 0x0004,
265 325 MR_EVT_LOCALE_BBU = 0x0008,
266 326 MR_EVT_LOCALE_SAS = 0x0010,
267 327 MR_EVT_LOCALE_CTRL = 0x0020,
268 328 MR_EVT_LOCALE_CONFIG = 0x0040,
269 329 MR_EVT_LOCALE_CLUSTER = 0x0080,
270 330 MR_EVT_LOCALE_ALL = 0xffff
271 331 };
272 332
333 +enum MR_EVT_ARGS {
334 + MR_EVT_ARGS_NONE,
335 + MR_EVT_ARGS_CDB_SENSE,
336 + MR_EVT_ARGS_LD,
337 + MR_EVT_ARGS_LD_COUNT,
338 + MR_EVT_ARGS_LD_LBA,
339 + MR_EVT_ARGS_LD_OWNER,
340 + MR_EVT_ARGS_LD_LBA_PD_LBA,
341 + MR_EVT_ARGS_LD_PROG,
342 + MR_EVT_ARGS_LD_STATE,
343 + MR_EVT_ARGS_LD_STRIP,
344 + MR_EVT_ARGS_PD,
345 + MR_EVT_ARGS_PD_ERR,
346 + MR_EVT_ARGS_PD_LBA,
347 + MR_EVT_ARGS_PD_LBA_LD,
348 + MR_EVT_ARGS_PD_PROG,
349 + MR_EVT_ARGS_PD_STATE,
350 + MR_EVT_ARGS_PCI,
351 + MR_EVT_ARGS_RATE,
352 + MR_EVT_ARGS_STR,
353 + MR_EVT_ARGS_TIME,
354 + MR_EVT_ARGS_ECC
355 +};
356 +
273 357 #define MR_EVT_CFG_CLEARED 0x0004
274 358 #define MR_EVT_LD_CREATED 0x008a
275 359 #define MR_EVT_LD_DELETED 0x008b
276 -#define MR_EVT_PD_REMOVED_EXT 0x00f8
277 -#define MR_EVT_PD_INSERTED_EXT 0x00f7
360 +#define MR_EVT_CFG_FP_CHANGE 0x017B
278 361
279 362 enum LD_STATE {
280 363 LD_OFFLINE = 0,
281 364 LD_PARTIALLY_DEGRADED = 1,
282 365 LD_DEGRADED = 2,
283 366 LD_OPTIMAL = 3,
284 367 LD_INVALID = 0xFF
285 368 };
286 369
287 370 enum MRSAS_EVT {
288 371 MRSAS_EVT_CONFIG_TGT = 0,
289 372 MRSAS_EVT_UNCONFIG_TGT = 1,
290 373 MRSAS_EVT_UNCONFIG_SMP = 2
291 374 };
292 375
293 376 #define DMA_OBJ_ALLOCATED 1
294 377 #define DMA_OBJ_REALLOCATED 2
|
↓ open down ↓ |
7 lines elided |
↑ open up ↑ |
295 378 #define DMA_OBJ_FREED 3
296 379
297 380 /*
298 381 * dma_obj_t - Our DMA object
299 382 * @param buffer : kernel virtual address
300 383 * @param size : size of the data to be allocated
301 384 * @param acc_handle : access handle
302 385 * @param dma_handle : dma handle
303 386 * @param dma_cookie : scatter-gather list
304 387 * @param dma_attr : dma attributes for this buffer
388 + *
305 389 * Our DMA object. The caller must initialize the size and dma attributes
306 390 * (dma_attr) fields before allocating the resources.
307 391 */
308 392 typedef struct {
309 393 caddr_t buffer;
310 394 uint32_t size;
311 395 ddi_acc_handle_t acc_handle;
312 396 ddi_dma_handle_t dma_handle;
313 397 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT];
314 398 ddi_dma_attr_t dma_attr;
315 399 uint8_t status;
316 400 uint8_t reserved[3];
317 401 } dma_obj_t;
318 402
319 403 struct mrsas_eventinfo {
320 404 struct mrsas_instance *instance;
321 405 int tgt;
322 406 int lun;
323 407 int event;
408 + uint64_t wwn;
324 409 };
325 410
326 411 struct mrsas_ld {
327 412 dev_info_t *dip;
328 413 uint8_t lun_type;
329 - uint8_t reserved[3];
414 + uint8_t flag;
415 + uint8_t reserved[2];
330 416 };
331 417
332 -struct mrsas_pd {
418 +
419 +#ifdef PDSUPPORT
420 +struct mrsas_tbolt_pd {
333 421 dev_info_t *dip;
334 422 uint8_t lun_type;
335 423 uint8_t dev_id;
336 - uint8_t flags;
424 + uint8_t flag;
337 425 uint8_t reserved;
338 426 };
339 -
340 -struct mrsas_pd_info {
427 +struct mrsas_tbolt_pd_info {
341 428 uint16_t deviceId;
342 429 uint16_t seqNum;
343 430 uint8_t inquiryData[96];
344 431 uint8_t vpdPage83[64];
345 432 uint8_t notSupported;
346 433 uint8_t scsiDevType;
347 434 uint8_t a;
348 435 uint8_t device_speed;
349 436 uint32_t mediaerrcnt;
350 437 uint32_t other;
351 438 uint32_t pred;
352 439 uint32_t lastpred;
353 440 uint16_t fwState;
354 441 uint8_t disabled;
355 442 uint8_t linkspwwd;
|
↓ open down ↓ |
5 lines elided |
↑ open up ↑ |
356 443 uint32_t ddfType;
357 444 struct {
358 445 uint8_t count;
359 446 uint8_t isPathBroken;
360 447 uint8_t connectorIndex[2];
361 448 uint8_t reserved[4];
362 449 uint64_t sasAddr[2];
363 450 uint8_t reserved2[16];
364 451 } pathInfo;
365 452 };
453 +#endif
366 454
367 455 typedef struct mrsas_instance {
368 456 uint32_t *producer;
369 457 uint32_t *consumer;
370 458
371 459 uint32_t *reply_queue;
372 460 dma_obj_t mfi_internal_dma_obj;
373 461 uint16_t adapterresetinprogress;
374 462 uint16_t deadadapter;
463 + /* ThunderBolt (TB) specific */
464 + dma_obj_t mpi2_frame_pool_dma_obj;
465 + dma_obj_t request_desc_dma_obj;
466 + dma_obj_t reply_desc_dma_obj;
467 + dma_obj_t ld_map_obj[2];
468 +
375 469 uint8_t init_id;
376 470 uint8_t flag_ieee;
377 471 uint8_t disable_online_ctrl_reset;
378 472 uint8_t fw_fault_count_after_ocr;
379 473
380 474 uint16_t max_num_sge;
381 475 uint16_t max_fw_cmds;
382 476 uint32_t max_sectors_per_req;
383 477
384 478 struct mrsas_cmd **cmd_list;
479 +
385 480 mlist_t cmd_pool_list;
386 481 kmutex_t cmd_pool_mtx;
482 + kmutex_t sync_map_mtx;
387 483
388 484 mlist_t app_cmd_pool_list;
389 485 kmutex_t app_cmd_pool_mtx;
486 + mlist_t cmd_app_pool_list;
487 + kmutex_t cmd_app_pool_mtx;
488 +
489 +
390 490 mlist_t cmd_pend_list;
391 491 kmutex_t cmd_pend_mtx;
392 492
393 493 dma_obj_t mfi_evt_detail_obj;
394 494 struct mrsas_cmd *aen_cmd;
395 495
396 496 uint32_t aen_seq_num;
397 497 uint32_t aen_class_locale_word;
398 498
399 499 scsi_hba_tran_t *tran;
400 500
401 501 kcondvar_t int_cmd_cv;
402 502 kmutex_t int_cmd_mtx;
403 503
404 504 kcondvar_t aen_cmd_cv;
405 505 kmutex_t aen_cmd_mtx;
406 506
407 507 kcondvar_t abort_cmd_cv;
408 508 kmutex_t abort_cmd_mtx;
409 509
510 + kmutex_t reg_write_mtx;
511 + kmutex_t chip_mtx;
512 +
410 513 dev_info_t *dip;
411 514 ddi_acc_handle_t pci_handle;
412 515
413 516 timeout_id_t timeout_id;
414 517 uint32_t unique_id;
415 518 uint16_t fw_outstanding;
416 519 caddr_t regmap;
417 520 ddi_acc_handle_t regmap_handle;
418 521 uint8_t isr_level;
419 522 ddi_iblock_cookie_t iblock_cookie;
420 523 ddi_iblock_cookie_t soft_iblock_cookie;
421 524 ddi_softintr_t soft_intr_id;
422 525 uint8_t softint_running;
526 + uint8_t tbolt_softint_running;
423 527 kmutex_t completed_pool_mtx;
424 528 mlist_t completed_pool_list;
425 529
426 530 caddr_t internal_buf;
427 531 uint32_t internal_buf_dmac_add;
428 532 uint32_t internal_buf_size;
429 533
430 534 uint16_t vendor_id;
431 535 uint16_t device_id;
432 536 uint16_t subsysvid;
433 537 uint16_t subsysid;
434 538 int instance;
435 539 int baseaddress;
436 540 char iocnode[16];
437 541
438 542 int fm_capabilities;
543 + /*
544 + * Driver resources unroll flags. The flag is set for resources that
545 + * are needed to be free'd at detach() time.
546 + */
547 + struct _unroll {
548 + uint8_t softs; /* The software state was allocated. */
549 + uint8_t regs; /* Controller registers mapped. */
550 + uint8_t intr; /* Interrupt handler added. */
551 + uint8_t reqs; /* Request structs allocated. */
552 + uint8_t mutexs; /* Mutex's allocated. */
553 + uint8_t taskq; /* Task q's created. */
554 + uint8_t tran; /* Tran struct allocated */
555 + uint8_t tranSetup; /* Tran attached to the ddi. */
556 + uint8_t devctl; /* Device nodes for cfgadm created. */
557 + uint8_t scsictl; /* Device nodes for cfgadm created. */
558 + uint8_t ioctl; /* Device nodes for ioctl's created. */
559 + uint8_t timer; /* Timer started. */
560 + uint8_t aenPend; /* AEN cmd pending f/w. */
561 + uint8_t mapUpdate_pend; /* LD MAP update cmd pending f/w. */
562 + uint8_t soft_isr; /* Soft interrupt handler allocated. */
563 + uint8_t ldlist_buff; /* Logical disk list allocated. */
564 + uint8_t pdlist_buff; /* Physical disk list allocated. */
565 + uint8_t syncCmd; /* Sync map command allocated. */
566 + uint8_t verBuff; /* 2108 MFI buffer allocated. */
567 + uint8_t alloc_space_mfi; /* Allocated space for 2108 MFI. */
568 + uint8_t alloc_space_mpi2; /* Allocated space for 2208 MPI2. */
569 + } unroll;
439 570
440 - struct mrsas_func_ptr *func_ptr;
571 +
572 + /* function template pointer */
573 + struct mrsas_function_template *func_ptr;
574 +
575 +
441 576 /* MSI interrupts specific */
442 - ddi_intr_handle_t *intr_htable;
577 + ddi_intr_handle_t *intr_htable; /* Interrupt handle array */
578 + size_t intr_htable_size; /* Int. handle array size */
443 579 int intr_type;
444 580 int intr_cnt;
445 - size_t intr_size;
446 581 uint_t intr_pri;
447 582 int intr_cap;
448 583
449 584 ddi_taskq_t *taskq;
450 585 struct mrsas_ld *mr_ld_list;
586 + kmutex_t config_dev_mtx;
587 + /* ThunderBolt (TB) specific */
588 + ddi_softintr_t tbolt_soft_intr_id;
589 +
590 +#ifdef PDSUPPORT
591 + uint32_t mr_tbolt_pd_max;
592 + struct mrsas_tbolt_pd *mr_tbolt_pd_list;
593 +#endif
594 +
595 + uint8_t fast_path_io;
596 +
597 + uint16_t tbolt;
598 + uint16_t reply_read_index;
599 + uint16_t reply_size; /* Single Reply struct size */
600 + uint16_t raid_io_msg_size; /* Single message size */
601 + uint32_t io_request_frames_phy;
602 + uint8_t *io_request_frames;
603 + /* Virtual address of request desc frame pool */
604 + MRSAS_REQUEST_DESCRIPTOR_UNION *request_message_pool;
605 + /* Physical address of request desc frame pool */
606 + uint32_t request_message_pool_phy;
607 + /* Virtual address of reply Frame */
608 + MPI2_REPLY_DESCRIPTORS_UNION *reply_frame_pool;
609 + /* Physical address of reply Frame */
610 + uint32_t reply_frame_pool_phy;
611 + uint8_t *reply_pool_limit; /* Last reply frame address */
612 + /* Physical address of Last reply frame */
613 + uint32_t reply_pool_limit_phy;
614 + uint32_t reply_q_depth; /* Reply Queue Depth */
615 + uint8_t max_sge_in_main_msg;
616 + uint8_t max_sge_in_chain;
617 + uint8_t chain_offset_io_req;
618 + uint8_t chain_offset_mpt_msg;
619 + MR_FW_RAID_MAP_ALL *ld_map[2];
620 + uint32_t ld_map_phy[2];
621 + uint32_t size_map_info;
622 + uint64_t map_id;
623 + LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
624 + struct mrsas_cmd *map_update_cmd;
625 + uint32_t SyncRequired;
451 626 kmutex_t ocr_flags_mtx;
627 + dma_obj_t drv_ver_dma_obj;
452 628 } mrsas_t;
453 629
454 -struct mrsas_func_ptr {
455 - int (*read_fw_status_reg)(struct mrsas_instance *);
630 +
631 +/*
632 + * Function templates for various controller specific functions
633 + */
634 +struct mrsas_function_template {
635 + uint32_t (*read_fw_status_reg)(struct mrsas_instance *);
456 636 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *);
457 637 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
458 638 struct mrsas_cmd *);
459 639 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
460 640 struct mrsas_cmd *);
461 641 void (*enable_intr)(struct mrsas_instance *);
462 642 void (*disable_intr)(struct mrsas_instance *);
463 643 int (*intr_ack)(struct mrsas_instance *);
644 + int (*init_adapter)(struct mrsas_instance *);
645 +/* int (*reset_adapter)(struct mrsas_instance *); */
464 646 };
465 647
466 648 /*
467 649 * ### Helper routines ###
468 650 */
469 651
470 652 /*
471 653 * con_log() - console log routine
472 654 * @param level : indicates the severity of the message.
473 655 * @fparam mt : format string
474 656 *
475 657 * con_log displays the error messages on the console based on the current
476 658 * debug level. Also it attaches the appropriate kernel severity level with
477 659 * the message.
478 660 *
479 661 *
480 662 * console messages debug levels
481 663 */
482 664 #define CL_NONE 0 /* No debug information */
483 -#define CL_TEST_OCR 1
484 -#define CL_ANN 2 /* print unconditionally, announcements */
485 -#define CL_ANN1 3 /* No o/p */
486 -#define CL_DLEVEL1 4 /* debug level 1, informative */
487 -#define CL_DLEVEL2 5 /* debug level 2, verbose */
488 -#define CL_DLEVEL3 6 /* debug level 3, very verbose */
665 +#define CL_ANN 1 /* print unconditionally, announcements */
666 +#define CL_ANN1 2 /* No-op */
667 +#define CL_DLEVEL1 3 /* debug level 1, informative */
668 +#define CL_DLEVEL2 4 /* debug level 2, verbose */
669 +#define CL_DLEVEL3 5 /* debug level 3, very verbose */
489 670
490 -
491 671 #ifdef __SUNPRO_C
492 672 #define __func__ ""
493 673 #endif
494 674
495 675 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
496 676
497 677 /*
498 678 * ### SCSA definitions ###
499 679 */
500 680 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target)
501 681 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun)
502 682 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran)
503 683 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
504 684
505 685 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private)
506 686 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap))
507 687
508 688 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private)
509 689 #define CMD2PKT(sp) ((sp)->cmd_pkt)
510 690 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request))
511 691
512 692 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address)
513 693 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran)
514 694 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd)))
515 695
516 696 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */
517 697 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */
518 698 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */
519 699
520 700 /*
521 701 * ### Data structures for ioctl inteface and internal commands ###
522 702 */
523 703
524 704 /*
525 705 * Data direction flags
526 706 */
527 707 #define UIOC_RD 0x00001
528 708 #define UIOC_WR 0x00002
529 709
530 710 #define SCP2HOST(scp) (scp)->device->host /* to host */
531 711 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */
532 712 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */
533 713 #define SCP2TARGET(scp) (scp)->device->id /* to target */
534 714 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */
535 715
536 716 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
537 717 #define SCP2ADAPTER(scp) \
538 718 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
539 719
|
↓ open down ↓ |
39 lines elided |
↑ open up ↑ |
540 720 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \
541 721 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0
542 722 #define MRDRV_IS_LOGICAL(ap) \
543 723 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0
544 724 #define MAP_DEVICE_ID(instance, ap) \
545 725 (ap->a_target)
546 726
547 727 #define HIGH_LEVEL_INTR 1
548 728 #define NORMAL_LEVEL_INTR 0
549 729
730 +#define IO_TIMEOUT_VAL 0
550 731 #define IO_RETRY_COUNT 3
551 732 #define MAX_FW_RESET_COUNT 3
552 -
553 733 /*
554 734 * scsa_cmd - Per-command mr private data
555 735 * @param cmd_dmahandle : dma handle
556 736 * @param cmd_dmacookies : current dma cookies
557 737 * @param cmd_pkt : scsi_pkt reference
558 738 * @param cmd_dmacount : dma count
559 739 * @param cmd_cookie : next cookie
560 740 * @param cmd_ncookies : cookies per window
561 741 * @param cmd_cookiecnt : cookies per sub-win
562 742 * @param cmd_nwin : number of dma windows
563 743 * @param cmd_curwin : current dma window
564 744 * @param cmd_dma_offset : current window offset
565 745 * @param cmd_dma_len : current window length
566 746 * @param cmd_flags : private flags
567 747 * @param cmd_cdblen : length of cdb
568 748 * @param cmd_scblen : length of scb
569 749 * @param cmd_buf : command buffer
570 750 * @param channel : channel for scsi sub-system
571 751 * @param target : target for scsi sub-system
572 752 * @param lun : LUN for scsi sub-system
573 753 *
574 754 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E)
575 755 * - Pointed to by pkt_ha_private field in scsi_pkt
576 756 */
577 757 struct scsa_cmd {
578 758 ddi_dma_handle_t cmd_dmahandle;
579 759 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT];
580 760 struct scsi_pkt *cmd_pkt;
581 761 ulong_t cmd_dmacount;
582 762 uint_t cmd_cookie;
583 763 uint_t cmd_ncookies;
584 764 uint_t cmd_cookiecnt;
585 765 uint_t cmd_nwin;
586 766 uint_t cmd_curwin;
587 767 off_t cmd_dma_offset;
588 768 ulong_t cmd_dma_len;
589 769 ulong_t cmd_flags;
590 770 uint_t cmd_cdblen;
|
↓ open down ↓ |
28 lines elided |
↑ open up ↑ |
591 771 uint_t cmd_scblen;
592 772 struct buf *cmd_buf;
593 773 ushort_t device_id;
594 774 uchar_t islogical;
595 775 uchar_t lun;
596 776 struct mrsas_device *mrsas_dev;
597 777 };
598 778
599 779
600 780 struct mrsas_cmd {
781 + /*
782 + * ThunderBolt(TB) We would be needing to have a placeholder
783 + * for RAID_MSG_IO_REQUEST inside this structure. We are
784 + * supposed to embed the mr_frame inside the RAID_MSG and post
785 + * it down to the firmware.
786 + */
601 787 union mrsas_frame *frame;
602 788 uint32_t frame_phys_addr;
603 789 uint8_t *sense;
790 + uint8_t *sense1;
604 791 uint32_t sense_phys_addr;
792 + uint32_t sense_phys_addr1;
605 793 dma_obj_t frame_dma_obj;
606 794 uint8_t frame_dma_obj_status;
607 -
608 795 uint32_t index;
609 796 uint8_t sync_cmd;
610 797 uint8_t cmd_status;
611 798 uint16_t abort_aen;
612 799 mlist_t list;
613 800 uint32_t frame_count;
614 801 struct scsa_cmd *cmd;
615 802 struct scsi_pkt *pkt;
803 + Mpi2RaidSCSIIORequest_t *scsi_io_request;
804 + Mpi2SGEIOUnion_t *sgl;
805 + uint32_t sgl_phys_addr;
806 + uint32_t scsi_io_request_phys_addr;
807 + MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
808 + uint16_t SMID;
616 809 uint16_t retry_count_for_ocr;
617 810 uint16_t drv_pkt_time;
811 + uint16_t load_balance_flag;
812 +
618 813 };
619 814
620 815 #define MAX_MGMT_ADAPTERS 1024
621 816 #define IOC_SIGNATURE "MR-SAS"
622 817
623 818 #define IOC_CMD_FIRMWARE 0x0
624 819 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000
625 820 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
626 821 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
627 822 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300
628 823
629 824
|
↓ open down ↓ |
2 lines elided |
↑ open up ↑ |
630 825 #define MRSAS_MAX_SENSE_LENGTH 32
631 826
632 827 struct mrsas_mgmt_info {
633 828
634 829 uint16_t count;
635 830 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS];
636 831 uint16_t map[MAX_MGMT_ADAPTERS];
637 832 int max_index;
638 833 };
639 834
640 -#pragma pack(1)
641 835
836 +#pragma pack(1)
642 837 /*
643 838 * SAS controller properties
644 839 */
645 840 struct mrsas_ctrl_prop {
646 841 uint16_t seq_num;
647 842 uint16_t pred_fail_poll_interval;
648 843 uint16_t intr_throttle_count;
649 844 uint16_t intr_throttle_timeouts;
650 845
651 846 uint8_t rebuild_rate;
652 847 uint8_t patrol_read_rate;
653 848 uint8_t bgi_rate;
654 849 uint8_t cc_rate;
|
↓ open down ↓ |
3 lines elided |
↑ open up ↑ |
655 850 uint8_t recon_rate;
656 851
657 852 uint8_t cache_flush_interval;
658 853
659 854 uint8_t spinup_drv_count;
660 855 uint8_t spinup_delay;
661 856
662 857 uint8_t cluster_enable;
663 858 uint8_t coercion_mode;
664 859 uint8_t alarm_enable;
860 +
665 861 uint8_t reserved_1[13];
666 862 uint32_t on_off_properties;
667 863 uint8_t reserved_4[28];
668 864 };
669 865
670 866
671 867 /*
672 868 * SAS controller information
673 869 */
674 870 struct mrsas_ctrl_info {
675 871 /* PCI device information */
676 872 struct {
677 873 uint16_t vendor_id;
678 874 uint16_t device_id;
679 875 uint16_t sub_vendor_id;
680 876 uint16_t sub_device_id;
681 877 uint8_t reserved[24];
682 878 } pci;
683 879
684 880 /* Host interface information */
685 881 struct {
686 882 uint8_t PCIX : 1;
687 883 uint8_t PCIE : 1;
688 884 uint8_t iSCSI : 1;
689 885 uint8_t SAS_3G : 1;
690 886 uint8_t reserved_0 : 4;
691 887 uint8_t reserved_1[6];
692 888 uint8_t port_count;
693 889 uint64_t port_addr[8];
694 890 } host_interface;
695 891
696 892 /* Device (backend) interface information */
697 893 struct {
698 894 uint8_t SPI : 1;
699 895 uint8_t SAS_3G : 1;
700 896 uint8_t SATA_1_5G : 1;
701 897 uint8_t SATA_3G : 1;
702 898 uint8_t reserved_0 : 4;
703 899 uint8_t reserved_1[6];
704 900 uint8_t port_count;
705 901 uint64_t port_addr[8];
706 902 } device_interface;
707 903
708 904 /* List of components residing in flash. All str are null terminated */
709 905 uint32_t image_check_word;
710 906 uint32_t image_component_count;
711 907
712 908 struct {
713 909 char name[8];
714 910 char version[32];
715 911 char build_date[16];
716 912 char built_time[16];
717 913 } image_component[8];
718 914
719 915 /*
720 916 * List of flash components that have been flashed on the card, but
721 917 * are not in use, pending reset of the adapter. This list will be
722 918 * empty if a flash operation has not occurred. All stings are null
723 919 * terminated
724 920 */
725 921 uint32_t pending_image_component_count;
726 922
727 923 struct {
728 924 char name[8];
729 925 char version[32];
730 926 char build_date[16];
731 927 char build_time[16];
732 928 } pending_image_component[8];
733 929
734 930 uint8_t max_arms;
735 931 uint8_t max_spans;
736 932 uint8_t max_arrays;
737 933 uint8_t max_lds;
738 934
739 935 char product_name[80];
740 936 char serial_no[32];
741 937
742 938 /*
743 939 * Other physical/controller/operation information. Indicates the
744 940 * presence of the hardware
745 941 */
746 942 struct {
747 943 uint32_t bbu : 1;
748 944 uint32_t alarm : 1;
749 945 uint32_t nvram : 1;
750 946 uint32_t uart : 1;
751 947 uint32_t reserved : 28;
752 948 } hw_present;
753 949
754 950 uint32_t current_fw_time;
755 951
756 952 /* Maximum data transfer sizes */
757 953 uint16_t max_concurrent_cmds;
758 954 uint16_t max_sge_count;
759 955 uint32_t max_request_size;
760 956
761 957 /* Logical and physical device counts */
762 958 uint16_t ld_present_count;
763 959 uint16_t ld_degraded_count;
764 960 uint16_t ld_offline_count;
765 961
766 962 uint16_t pd_present_count;
767 963 uint16_t pd_disk_present_count;
768 964 uint16_t pd_disk_pred_failure_count;
769 965 uint16_t pd_disk_failed_count;
770 966
771 967 /* Memory size information */
772 968 uint16_t nvram_size;
773 969 uint16_t memory_size;
774 970 uint16_t flash_size;
775 971
776 972 /* Error counters */
777 973 uint16_t mem_correctable_error_count;
778 974 uint16_t mem_uncorrectable_error_count;
779 975
780 976 /* Cluster information */
781 977 uint8_t cluster_permitted;
782 978 uint8_t cluster_active;
783 979 uint8_t reserved_1[2];
784 980
785 981 /* Controller capabilities structures */
786 982 struct {
787 983 uint32_t raid_level_0 : 1;
788 984 uint32_t raid_level_1 : 1;
789 985 uint32_t raid_level_5 : 1;
790 986 uint32_t raid_level_1E : 1;
791 987 uint32_t reserved : 28;
792 988 } raid_levels;
793 989
794 990 struct {
795 991 uint32_t rbld_rate : 1;
796 992 uint32_t cc_rate : 1;
797 993 uint32_t bgi_rate : 1;
798 994 uint32_t recon_rate : 1;
799 995 uint32_t patrol_rate : 1;
800 996 uint32_t alarm_control : 1;
801 997 uint32_t cluster_supported : 1;
802 998 uint32_t bbu : 1;
803 999 uint32_t spanning_allowed : 1;
804 1000 uint32_t dedicated_hotspares : 1;
805 1001 uint32_t revertible_hotspares : 1;
806 1002 uint32_t foreign_config_import : 1;
807 1003 uint32_t self_diagnostic : 1;
808 1004 uint32_t reserved : 19;
809 1005 } adapter_operations;
810 1006
811 1007 struct {
812 1008 uint32_t read_policy : 1;
813 1009 uint32_t write_policy : 1;
814 1010 uint32_t io_policy : 1;
815 1011 uint32_t access_policy : 1;
816 1012 uint32_t reserved : 28;
817 1013 } ld_operations;
818 1014
819 1015 struct {
820 1016 uint8_t min;
821 1017 uint8_t max;
822 1018 uint8_t reserved[2];
823 1019 } stripe_size_operations;
824 1020
825 1021 struct {
826 1022 uint32_t force_online : 1;
827 1023 uint32_t force_offline : 1;
828 1024 uint32_t force_rebuild : 1;
829 1025 uint32_t reserved : 29;
830 1026 } pd_operations;
831 1027
832 1028 struct {
833 1029 uint32_t ctrl_supports_sas : 1;
834 1030 uint32_t ctrl_supports_sata : 1;
835 1031 uint32_t allow_mix_in_encl : 1;
836 1032 uint32_t allow_mix_in_ld : 1;
837 1033 uint32_t allow_sata_in_cluster : 1;
838 1034 uint32_t reserved : 27;
839 1035 } pd_mix_support;
840 1036
841 1037 /* Include the controller properties (changeable items) */
842 1038 uint8_t reserved_2[12];
843 1039 struct mrsas_ctrl_prop properties;
844 1040
845 1041 uint8_t pad[0x800 - 0x640];
846 1042 };
847 1043
848 1044 /*
849 1045 * ==================================
850 1046 * MegaRAID SAS2.0 driver definitions
851 1047 * ==================================
852 1048 */
853 1049 #define MRDRV_MAX_NUM_CMD 1024
854 1050
855 1051 #define MRDRV_MAX_PD_CHANNELS 2
856 1052 #define MRDRV_MAX_LD_CHANNELS 2
857 1053 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \
858 1054 MRDRV_MAX_LD_CHANNELS)
859 1055 #define MRDRV_MAX_DEV_PER_CHANNEL 128
|
↓ open down ↓ |
185 lines elided |
↑ open up ↑ |
860 1056 #define MRDRV_DEFAULT_INIT_ID -1
861 1057 #define MRDRV_MAX_CMD_PER_LUN 1000
862 1058 #define MRDRV_MAX_LUN 1
863 1059 #define MRDRV_MAX_LD 64
864 1060
865 1061 #define MRDRV_RESET_WAIT_TIME 300
866 1062 #define MRDRV_RESET_NOTICE_INTERVAL 5
867 1063
868 1064 #define MRSAS_IOCTL_CMD 0
869 1065
1066 +#define MRDRV_TGT_VALID 1
1067 +
870 1068 /*
871 1069 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
872 1070 * SGLs based on the size of dma_addr_t
873 1071 */
874 1072 #define IS_DMA64 (sizeof (dma_addr_t) == 8)
875 1073
1074 +#define RESERVED0_REGISTER 0x00 /* XScale */
876 1075 #define IB_MSG_0_OFF 0x10 /* XScale */
877 1076 #define OB_MSG_0_OFF 0x18 /* XScale */
878 1077 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */
879 1078 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */
880 1079 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */
881 1080 #define IB_QPORT_OFF 0x40 /* XScale & ROC */
882 1081 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */
883 1082 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */
884 1083 #define OB_INTR_MASK 0xFFFFFFFF
885 1084 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF
886 -#define WRITE_SEQ_OFF 0x000000FC
887 -#define HOST_DIAG_OFF 0x000000F8
888 -#define DIAG_RESET_ADAPTER 0x00000004
889 -#define DIAG_WRITE_ENABLE 0x00000080
890 -/*
891 - * All MFI register set macros accept mrsas_register_set*
892 - */
1085 +#define SYSTOIOP_INTERRUPT_MASK 0x80000000
1086 +#define OB_SCRATCH_PAD_2_OFF 0xB4
1087 +#define WRITE_TBOLT_SEQ_OFF 0x00000004
1088 +#define DIAG_TBOLT_RESET_ADAPTER 0x00000004
1089 +#define HOST_TBOLT_DIAG_OFF 0x00000008
1090 +#define RESET_TBOLT_STATUS_OFF 0x000003C3
1091 +#define WRITE_SEQ_OFF 0x000000FC
1092 +#define HOST_DIAG_OFF 0x000000F8
1093 +#define DIAG_RESET_ADAPTER 0x00000004
1094 +#define DIAG_WRITE_ENABLE 0x00000080
1095 +#define SYSTOIOP_INTERRUPT_MASK 0x80000000
1096 +
893 1097 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \
894 1098 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v))
895 1099
896 1100 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \
897 1101 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF))
898 1102
899 1103 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \
900 1104 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v))
901 1105
1106 +#define IB_LOW_QPORT 0xC0
1107 +#define IB_HIGH_QPORT 0xC4
1108 +#define OB_DOORBELL_REGISTER 0x9C /* 1078 implementation */
1109 +
1110 +/*
1111 + * All MFI register set macros accept mrsas_register_set*
1112 + */
902 1113 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \
903 1114 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
904 1115
905 1116 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \
906 1117 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
907 1118
908 1119 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \
909 1120 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
910 1121
911 1122 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \
912 1123 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
913 1124
914 1125 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \
915 1126 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
916 1127
917 1128 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \
918 1129 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
919 1130
920 1131 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \
921 1132 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
922 1133
923 1134 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \
924 1135 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
925 1136
|
↓ open down ↓ |
14 lines elided |
↑ open up ↑ |
926 1137 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
927 1138 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
928 1139
929 1140 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
930 1141 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
931 1142 (v))
932 1143
933 1144 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \
934 1145 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
935 1146
1147 +/* Thunderbolt specific registers */
1148 +#define RD_OB_SCRATCH_PAD_2(instance) ddi_get32((instance)->regmap_handle, \
1149 + (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_2_OFF))
1150 +
1151 +#define WR_TBOLT_IB_WRITE_SEQ(v, instance) \
1152 + ddi_put32((instance)->regmap_handle, \
1153 + (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_TBOLT_SEQ_OFF), (v))
1154 +
1155 +#define RD_TBOLT_HOST_DIAG(instance) ddi_get32((instance)->regmap_handle, \
1156 + (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF))
1157 +
1158 +#define WR_TBOLT_HOST_DIAG(v, instance) ddi_put32((instance)->regmap_handle, \
1159 + (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF), (v))
1160 +
1161 +#define RD_TBOLT_RESET_STAT(instance) ddi_get32((instance)->regmap_handle, \
1162 + (uint32_t *)((uintptr_t)(instance)->regmap + RESET_TBOLT_STATUS_OFF))
1163 +
1164 +
1165 +#define WR_MPI2_REPLY_POST_INDEX(v, instance)\
1166 + ddi_put32((instance)->regmap_handle,\
1167 + (uint32_t *)\
1168 + ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET),\
1169 + (v))
1170 +
1171 +
1172 +#define RD_MPI2_REPLY_POST_INDEX(instance)\
1173 + ddi_get32((instance)->regmap_handle,\
1174 + (uint32_t *)\
1175 + ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET))
1176 +
1177 +#define WR_IB_LOW_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1178 + (uint32_t *)((uintptr_t)(instance)->regmap + IB_LOW_QPORT), (v))
1179 +
1180 +#define WR_IB_HIGH_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1181 + (uint32_t *)((uintptr_t)(instance)->regmap + IB_HIGH_QPORT), (v))
1182 +
1183 +#define WR_OB_DOORBELL_REGISTER_CLEAR(v, instance)\
1184 + ddi_put32((instance)->regmap_handle,\
1185 + (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_REGISTER), \
1186 + (v))
1187 +
1188 +#define WR_RESERVED0_REGISTER(v, instance) ddi_put32((instance)->regmap_handle,\
1189 + (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER), \
1190 + (v))
1191 +
1192 +#define RD_RESERVED0_REGISTER(instance) ddi_get32((instance)->regmap_handle, \
1193 + (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER))
1194 +
1195 +
1196 +
936 1197 /*
937 1198 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
938 1199 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
939 1200 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
940 1201 */
941 1202 #define MFI_OB_INTR_STATUS_MASK 0x00000002
942 1203
943 1204 /*
944 1205 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also
945 1206 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
946 1207 * been set in this flag along with bit 1.
947 1208 */
948 1209 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001
949 1210 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005
950 1211
1212 +/* Fusion interrupt mask */
1213 +#define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008)
1214 +
951 1215 #define MFI_POLL_TIMEOUT_SECS 60
952 1216
953 1217 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \
954 1218 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
955 1219 #define MFI_DISABLE_INTR(instance) \
956 1220 { \
957 1221 uint32_t disable = 1; \
958 1222 uint32_t mask = ddi_get32((instance)->regmap_handle, \
959 1223 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
960 1224 mask &= ~disable; \
961 1225 ddi_put32((instance)->regmap_handle, (uint32_t *) \
962 1226 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \
963 1227 }
964 1228
965 1229 /* By default, the firmware programs for 8 Kbytes of memory */
|
↓ open down ↓ |
5 lines elided |
↑ open up ↑ |
966 1230 #define DEFAULT_MFI_MEM_SZ 8192
967 1231 #define MINIMUM_MFI_MEM_SZ 4096
968 1232
969 1233 /* DCMD Message Frame MAILBOX0-11 */
970 1234 #define DCMD_MBOX_SZ 12
971 1235
972 1236 /*
973 1237 * on_off_property of mrsas_ctrl_prop
974 1238 * bit0-9, 11-31 are reserved
975 1239 */
976 -#define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */
1240 +#define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */
977 1241
978 1242 struct mrsas_register_set {
979 - uint32_t reserved_0[4];
1243 + uint32_t reserved_0[4]; /* 0000h */
980 1244
981 - uint32_t inbound_msg_0;
982 - uint32_t inbound_msg_1;
983 - uint32_t outbound_msg_0;
984 - uint32_t outbound_msg_1;
1245 + uint32_t inbound_msg_0; /* 0010h */
1246 + uint32_t inbound_msg_1; /* 0014h */
1247 + uint32_t outbound_msg_0; /* 0018h */
1248 + uint32_t outbound_msg_1; /* 001Ch */
985 1249
986 - uint32_t inbound_doorbell;
987 - uint32_t inbound_intr_status;
988 - uint32_t inbound_intr_mask;
1250 + uint32_t inbound_doorbell; /* 0020h */
1251 + uint32_t inbound_intr_status; /* 0024h */
1252 + uint32_t inbound_intr_mask; /* 0028h */
989 1253
990 - uint32_t outbound_doorbell;
991 - uint32_t outbound_intr_status;
992 - uint32_t outbound_intr_mask;
1254 + uint32_t outbound_doorbell; /* 002Ch */
1255 + uint32_t outbound_intr_status; /* 0030h */
1256 + uint32_t outbound_intr_mask; /* 0034h */
993 1257
994 - uint32_t reserved_1[2];
1258 + uint32_t reserved_1[2]; /* 0038h */
995 1259
996 - uint32_t inbound_queue_port;
997 - uint32_t outbound_queue_port;
1260 + uint32_t inbound_queue_port; /* 0040h */
1261 + uint32_t outbound_queue_port; /* 0044h */
998 1262
999 - uint32_t reserved_2[22];
1263 + uint32_t reserved_2[22]; /* 0048h */
1000 1264
1001 - uint32_t outbound_doorbell_clear;
1265 + uint32_t outbound_doorbell_clear; /* 00A0h */
1002 1266
1003 - uint32_t reserved_3[3];
1267 + uint32_t reserved_3[3]; /* 00A4h */
1004 1268
1005 - uint32_t outbound_scratch_pad;
1269 + uint32_t outbound_scratch_pad; /* 00B0h */
1006 1270
1007 - uint32_t reserved_4[3];
1271 + uint32_t reserved_4[3]; /* 00B4h */
1008 1272
1009 - uint32_t inbound_low_queue_port;
1273 + uint32_t inbound_low_queue_port; /* 00C0h */
1010 1274
1011 - uint32_t inbound_high_queue_port;
1275 + uint32_t inbound_high_queue_port; /* 00C4h */
1012 1276
1013 - uint32_t reserved_5;
1014 - uint32_t index_registers[820];
1277 + uint32_t reserved_5; /* 00C8h */
1278 + uint32_t index_registers[820]; /* 00CCh */
1015 1279 };
1016 1280
1017 1281 struct mrsas_sge32 {
1018 1282 uint32_t phys_addr;
1019 1283 uint32_t length;
1020 1284 };
1021 1285
1022 1286 struct mrsas_sge64 {
1023 1287 uint64_t phys_addr;
1024 1288 uint32_t length;
1025 1289 };
1026 1290
1027 1291 struct mrsas_sge_ieee {
1028 1292 uint64_t phys_addr;
1029 1293 uint32_t length;
|
↓ open down ↓ |
5 lines elided |
↑ open up ↑ |
1030 1294 uint32_t flag;
1031 1295 };
1032 1296
1033 1297 union mrsas_sgl {
1034 1298 struct mrsas_sge32 sge32[1];
1035 1299 struct mrsas_sge64 sge64[1];
1036 1300 struct mrsas_sge_ieee sge_ieee[1];
1037 1301 };
1038 1302
1039 1303 struct mrsas_header {
1040 - uint8_t cmd;
1041 - uint8_t sense_len;
1042 - uint8_t cmd_status;
1043 - uint8_t scsi_status;
1304 + uint8_t cmd; /* 00h */
1305 + uint8_t sense_len; /* 01h */
1306 + uint8_t cmd_status; /* 02h */
1307 + uint8_t scsi_status; /* 03h */
1044 1308
1045 - uint8_t target_id;
1046 - uint8_t lun;
1047 - uint8_t cdb_len;
1048 - uint8_t sge_count;
1309 + uint8_t target_id; /* 04h */
1310 + uint8_t lun; /* 05h */
1311 + uint8_t cdb_len; /* 06h */
1312 + uint8_t sge_count; /* 07h */
1049 1313
1050 - uint32_t context;
1051 - uint8_t req_id;
1052 - uint8_t msgvector;
1053 - uint16_t pad_0;
1314 + uint32_t context; /* 08h */
1315 + uint8_t req_id; /* 0Ch */
1316 + uint8_t msgvector; /* 0Dh */
1317 + uint16_t pad_0; /* 0Eh */
1054 1318
1055 - uint16_t flags;
1056 - uint16_t timeout;
1057 - uint32_t data_xferlen;
1319 + uint16_t flags; /* 10h */
1320 + uint16_t timeout; /* 12h */
1321 + uint32_t data_xferlen; /* 14h */
1058 1322 };
1059 1323
1060 1324 union mrsas_sgl_frame {
1061 1325 struct mrsas_sge32 sge32[8];
1062 1326 struct mrsas_sge64 sge64[5];
1063 1327 };
1064 1328
1065 1329 struct mrsas_init_frame {
1066 - uint8_t cmd;
1067 - uint8_t reserved_0;
1068 - uint8_t cmd_status;
1330 + uint8_t cmd; /* 00h */
1331 + uint8_t reserved_0; /* 01h */
1332 + uint8_t cmd_status; /* 02h */
1069 1333
1070 - uint8_t reserved_1;
1071 - uint32_t reserved_2;
1334 + uint8_t reserved_1; /* 03h */
1335 + uint32_t reserved_2; /* 04h */
1072 1336
1073 - uint32_t context;
1074 - uint8_t req_id;
1075 - uint8_t msgvector;
1076 - uint16_t pad_0;
1337 + uint32_t context; /* 08h */
1338 + uint8_t req_id; /* 0Ch */
1339 + uint8_t msgvector; /* 0Dh */
1340 + uint16_t pad_0; /* 0Eh */
1077 1341
1078 - uint16_t flags;
1079 - uint16_t reserved_3;
1080 - uint32_t data_xfer_len;
1342 + uint16_t flags; /* 10h */
1343 + uint16_t reserved_3; /* 12h */
1344 + uint32_t data_xfer_len; /* 14h */
1081 1345
1082 - uint32_t queue_info_new_phys_addr_lo;
1083 - uint32_t queue_info_new_phys_addr_hi;
1084 - uint32_t queue_info_old_phys_addr_lo;
1085 - uint32_t queue_info_old_phys_addr_hi;
1086 -
1087 - uint32_t reserved_4[6];
1346 + uint32_t queue_info_new_phys_addr_lo; /* 18h */
1347 + uint32_t queue_info_new_phys_addr_hi; /* 1Ch */
1348 + uint32_t queue_info_old_phys_addr_lo; /* 20h */
1349 + uint32_t queue_info_old_phys_addr_hi; /* 24h */
1350 + uint64_t driverversion; /* 28h */
1351 + uint32_t reserved_4[4]; /* 30h */
1088 1352 };
1089 1353
1090 1354 struct mrsas_init_queue_info {
1091 - uint32_t init_flags;
1092 - uint32_t reply_queue_entries;
1355 + uint32_t init_flags; /* 00h */
1356 + uint32_t reply_queue_entries; /* 04h */
1093 1357
1094 - uint32_t reply_queue_start_phys_addr_lo;
1095 - uint32_t reply_queue_start_phys_addr_hi;
1096 - uint32_t producer_index_phys_addr_lo;
1097 - uint32_t producer_index_phys_addr_hi;
1098 - uint32_t consumer_index_phys_addr_lo;
1099 - uint32_t consumer_index_phys_addr_hi;
1358 + uint32_t reply_queue_start_phys_addr_lo; /* 08h */
1359 + uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */
1360 + uint32_t producer_index_phys_addr_lo; /* 10h */
1361 + uint32_t producer_index_phys_addr_hi; /* 14h */
1362 + uint32_t consumer_index_phys_addr_lo; /* 18h */
1363 + uint32_t consumer_index_phys_addr_hi; /* 1Ch */
1100 1364 };
1101 1365
1102 1366 struct mrsas_io_frame {
1103 - uint8_t cmd;
1104 - uint8_t sense_len;
1105 - uint8_t cmd_status;
1106 - uint8_t scsi_status;
1367 + uint8_t cmd; /* 00h */
1368 + uint8_t sense_len; /* 01h */
1369 + uint8_t cmd_status; /* 02h */
1370 + uint8_t scsi_status; /* 03h */
1107 1371
1108 - uint8_t target_id;
1109 - uint8_t access_byte;
1110 - uint8_t reserved_0;
1111 - uint8_t sge_count;
1372 + uint8_t target_id; /* 04h */
1373 + uint8_t access_byte; /* 05h */
1374 + uint8_t reserved_0; /* 06h */
1375 + uint8_t sge_count; /* 07h */
1112 1376
1113 - uint32_t context;
1114 - uint8_t req_id;
1115 - uint8_t msgvector;
1116 - uint16_t pad_0;
1377 + uint32_t context; /* 08h */
1378 + uint8_t req_id; /* 0Ch */
1379 + uint8_t msgvector; /* 0Dh */
1380 + uint16_t pad_0; /* 0Eh */
1117 1381
1118 - uint16_t flags;
1119 - uint16_t timeout;
1120 - uint32_t lba_count;
1382 + uint16_t flags; /* 10h */
1383 + uint16_t timeout; /* 12h */
1384 + uint32_t lba_count; /* 14h */
1121 1385
1122 - uint32_t sense_buf_phys_addr_lo;
1123 - uint32_t sense_buf_phys_addr_hi;
1386 + uint32_t sense_buf_phys_addr_lo; /* 18h */
1387 + uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1124 1388
1125 - uint32_t start_lba_lo;
1126 - uint32_t start_lba_hi;
1389 + uint32_t start_lba_lo; /* 20h */
1390 + uint32_t start_lba_hi; /* 24h */
1127 1391
1128 - union mrsas_sgl sgl;
1392 + union mrsas_sgl sgl; /* 28h */
1129 1393 };
1130 1394
1131 1395 struct mrsas_pthru_frame {
1132 - uint8_t cmd;
1133 - uint8_t sense_len;
1134 - uint8_t cmd_status;
1135 - uint8_t scsi_status;
1396 + uint8_t cmd; /* 00h */
1397 + uint8_t sense_len; /* 01h */
1398 + uint8_t cmd_status; /* 02h */
1399 + uint8_t scsi_status; /* 03h */
1136 1400
1137 - uint8_t target_id;
1138 - uint8_t lun;
1139 - uint8_t cdb_len;
1140 - uint8_t sge_count;
1401 + uint8_t target_id; /* 04h */
1402 + uint8_t lun; /* 05h */
1403 + uint8_t cdb_len; /* 06h */
1404 + uint8_t sge_count; /* 07h */
1141 1405
1142 - uint32_t context;
1143 - uint8_t req_id;
1144 - uint8_t msgvector;
1145 - uint16_t pad_0;
1406 + uint32_t context; /* 08h */
1407 + uint8_t req_id; /* 0Ch */
1408 + uint8_t msgvector; /* 0Dh */
1409 + uint16_t pad_0; /* 0Eh */
1146 1410
1147 - uint16_t flags;
1148 - uint16_t timeout;
1149 - uint32_t data_xfer_len;
1411 + uint16_t flags; /* 10h */
1412 + uint16_t timeout; /* 12h */
1413 + uint32_t data_xfer_len; /* 14h */
1150 1414
1151 - uint32_t sense_buf_phys_addr_lo;
1152 - uint32_t sense_buf_phys_addr_hi;
1415 + uint32_t sense_buf_phys_addr_lo; /* 18h */
1416 + uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1153 1417
1154 - uint8_t cdb[16];
1155 - union mrsas_sgl sgl;
1418 + uint8_t cdb[16]; /* 20h */
1419 + union mrsas_sgl sgl; /* 30h */
1156 1420 };
1157 1421
1158 1422 struct mrsas_dcmd_frame {
1159 - uint8_t cmd;
1160 - uint8_t reserved_0;
1161 - uint8_t cmd_status;
1162 - uint8_t reserved_1[4];
1163 - uint8_t sge_count;
1423 + uint8_t cmd; /* 00h */
1424 + uint8_t reserved_0; /* 01h */
1425 + uint8_t cmd_status; /* 02h */
1426 + uint8_t reserved_1[4]; /* 03h */
1427 + uint8_t sge_count; /* 07h */
1164 1428
1165 - uint32_t context;
1166 - uint8_t req_id;
1167 - uint8_t msgvector;
1168 - uint16_t pad_0;
1429 + uint32_t context; /* 08h */
1430 + uint8_t req_id; /* 0Ch */
1431 + uint8_t msgvector; /* 0Dh */
1432 + uint16_t pad_0; /* 0Eh */
1169 1433
1170 - uint16_t flags;
1171 - uint16_t timeout;
1434 + uint16_t flags; /* 10h */
1435 + uint16_t timeout; /* 12h */
1172 1436
1173 - uint32_t data_xfer_len;
1174 - uint32_t opcode;
1437 + uint32_t data_xfer_len; /* 14h */
1438 + uint32_t opcode; /* 18h */
1175 1439
1176 - union {
1440 + /* uint8_t mbox[DCMD_MBOX_SZ]; */ /* 1Ch */
1441 + union { /* 1Ch */
1177 1442 uint8_t b[DCMD_MBOX_SZ];
1178 1443 uint16_t s[6];
1179 1444 uint32_t w[3];
1180 1445 } mbox;
1181 1446
1182 - union mrsas_sgl sgl;
1447 + union mrsas_sgl sgl; /* 28h */
1183 1448 };
1184 1449
1185 1450 struct mrsas_abort_frame {
1186 - uint8_t cmd;
1187 - uint8_t reserved_0;
1188 - uint8_t cmd_status;
1451 + uint8_t cmd; /* 00h */
1452 + uint8_t reserved_0; /* 01h */
1453 + uint8_t cmd_status; /* 02h */
1189 1454
1190 - uint8_t reserved_1;
1191 - uint32_t reserved_2;
1455 + uint8_t reserved_1; /* 03h */
1456 + uint32_t reserved_2; /* 04h */
1192 1457
1193 - uint32_t context;
1194 - uint8_t req_id;
1195 - uint8_t msgvector;
1196 - uint16_t pad_0;
1458 + uint32_t context; /* 08h */
1459 + uint8_t req_id; /* 0Ch */
1460 + uint8_t msgvector; /* 0Dh */
1461 + uint16_t pad_0; /* 0Eh */
1197 1462
1198 - uint16_t flags;
1199 - uint16_t reserved_3;
1200 - uint32_t reserved_4;
1463 + uint16_t flags; /* 10h */
1464 + uint16_t reserved_3; /* 12h */
1465 + uint32_t reserved_4; /* 14h */
1201 1466
1202 - uint32_t abort_context;
1203 - uint32_t pad_1;
1467 + uint32_t abort_context; /* 18h */
1468 + uint32_t pad_1; /* 1Ch */
1204 1469
1205 - uint32_t abort_mfi_phys_addr_lo;
1206 - uint32_t abort_mfi_phys_addr_hi;
1470 + uint32_t abort_mfi_phys_addr_lo; /* 20h */
1471 + uint32_t abort_mfi_phys_addr_hi; /* 24h */
1207 1472
1208 - uint32_t reserved_5[6];
1473 + uint32_t reserved_5[6]; /* 28h */
1209 1474 };
1210 1475
1211 1476 struct mrsas_smp_frame {
1212 - uint8_t cmd;
1213 - uint8_t reserved_1;
1214 - uint8_t cmd_status;
1215 - uint8_t connection_status;
1477 + uint8_t cmd; /* 00h */
1478 + uint8_t reserved_1; /* 01h */
1479 + uint8_t cmd_status; /* 02h */
1480 + uint8_t connection_status; /* 03h */
1216 1481
1217 - uint8_t reserved_2[3];
1218 - uint8_t sge_count;
1482 + uint8_t reserved_2[3]; /* 04h */
1483 + uint8_t sge_count; /* 07h */
1219 1484
1220 - uint32_t context;
1221 - uint8_t req_id;
1222 - uint8_t msgvector;
1223 - uint16_t pad_0;
1485 + uint32_t context; /* 08h */
1486 + uint8_t req_id; /* 0Ch */
1487 + uint8_t msgvector; /* 0Dh */
1488 + uint16_t pad_0; /* 0Eh */
1224 1489
1225 - uint16_t flags;
1226 - uint16_t timeout;
1490 + uint16_t flags; /* 10h */
1491 + uint16_t timeout; /* 12h */
1227 1492
1228 - uint32_t data_xfer_len;
1493 + uint32_t data_xfer_len; /* 14h */
1229 1494
1230 - uint64_t sas_addr;
1495 + uint64_t sas_addr; /* 20h */
1231 1496
1232 - union mrsas_sgl sgl[2];
1497 + union mrsas_sgl sgl[2]; /* 28h */
1233 1498 };
1234 1499
1235 1500 struct mrsas_stp_frame {
1236 - uint8_t cmd;
1237 - uint8_t reserved_1;
1238 - uint8_t cmd_status;
1239 - uint8_t connection_status;
1501 + uint8_t cmd; /* 00h */
1502 + uint8_t reserved_1; /* 01h */
1503 + uint8_t cmd_status; /* 02h */
1504 + uint8_t connection_status; /* 03h */
1240 1505
1241 - uint8_t target_id;
1242 - uint8_t reserved_2[2];
1243 - uint8_t sge_count;
1506 + uint8_t target_id; /* 04h */
1507 + uint8_t reserved_2[2]; /* 04h */
1508 + uint8_t sge_count; /* 07h */
1244 1509
1245 - uint32_t context;
1246 - uint8_t req_id;
1247 - uint8_t msgvector;
1248 - uint16_t pad_0;
1510 + uint32_t context; /* 08h */
1511 + uint8_t req_id; /* 0Ch */
1512 + uint8_t msgvector; /* 0Dh */
1513 + uint16_t pad_0; /* 0Eh */
1249 1514
1250 - uint16_t flags;
1251 - uint16_t timeout;
1515 + uint16_t flags; /* 10h */
1516 + uint16_t timeout; /* 12h */
1252 1517
1253 - uint32_t data_xfer_len;
1518 + uint32_t data_xfer_len; /* 14h */
1254 1519
1255 - uint16_t fis[10];
1256 - uint32_t stp_flags;
1257 - union mrsas_sgl sgl;
1520 + uint16_t fis[10]; /* 28h */
1521 + uint32_t stp_flags; /* 3C */
1522 + union mrsas_sgl sgl; /* 40 */
1258 1523 };
1259 1524
1260 1525 union mrsas_frame {
1261 1526 struct mrsas_header hdr;
1262 1527 struct mrsas_init_frame init;
1263 1528 struct mrsas_io_frame io;
1264 1529 struct mrsas_pthru_frame pthru;
1265 1530 struct mrsas_dcmd_frame dcmd;
1266 1531 struct mrsas_abort_frame abort;
1267 1532 struct mrsas_smp_frame smp;
1268 1533 struct mrsas_stp_frame stp;
1269 1534
1270 1535 uint8_t raw_bytes[64];
1271 1536 };
1272 1537
1273 1538 typedef struct mrsas_pd_address {
1274 1539 uint16_t device_id;
1275 1540 uint16_t encl_id;
1276 1541
1277 1542 union {
1278 1543 struct {
1279 1544 uint8_t encl_index;
1280 1545 uint8_t slot_number;
1281 1546 } pd_address;
1282 1547 struct {
1283 1548 uint8_t encl_position;
1284 1549 uint8_t encl_connector_index;
1285 1550 } encl_address;
1286 1551 }address;
1287 1552
1288 1553 uint8_t scsi_dev_type;
1289 1554
1290 1555 union {
1291 1556 uint8_t port_bitmap;
1292 1557 uint8_t port_numbers;
1293 1558 } connected;
1294 1559
1295 1560 uint64_t sas_addr[2];
1296 1561 } mrsas_pd_address_t;
1297 1562
1298 1563 union mrsas_evt_class_locale {
1299 1564 struct {
1300 1565 uint16_t locale;
1301 1566 uint8_t reserved;
1302 1567 int8_t class;
1303 1568 } members;
1304 1569
1305 1570 uint32_t word;
1306 1571 };
1307 1572
1308 1573 struct mrsas_evt_log_info {
1309 1574 uint32_t newest_seq_num;
1310 1575 uint32_t oldest_seq_num;
1311 1576 uint32_t clear_seq_num;
1312 1577 uint32_t shutdown_seq_num;
1313 1578 uint32_t boot_seq_num;
1314 1579 };
1315 1580
1316 1581 struct mrsas_progress {
1317 1582 uint16_t progress;
1318 1583 uint16_t elapsed_seconds;
1319 1584 };
1320 1585
1321 1586 struct mrsas_evtarg_ld {
1322 1587 uint16_t target_id;
1323 1588 uint8_t ld_index;
1324 1589 uint8_t reserved;
1325 1590 };
1326 1591
1327 1592 struct mrsas_evtarg_pd {
1328 1593 uint16_t device_id;
1329 1594 uint8_t encl_index;
1330 1595 uint8_t slot_number;
1331 1596 };
1332 1597
1333 1598 struct mrsas_evt_detail {
1334 1599 uint32_t seq_num;
1335 1600 uint32_t time_stamp;
1336 1601 uint32_t code;
1337 1602 union mrsas_evt_class_locale cl;
1338 1603 uint8_t arg_type;
1339 1604 uint8_t reserved1[15];
1340 1605
1341 1606 union {
1342 1607 struct {
1343 1608 struct mrsas_evtarg_pd pd;
1344 1609 uint8_t cdb_length;
1345 1610 uint8_t sense_length;
1346 1611 uint8_t reserved[2];
1347 1612 uint8_t cdb[16];
1348 1613 uint8_t sense[64];
1349 1614 } cdbSense;
1350 1615
1351 1616 struct mrsas_evtarg_ld ld;
1352 1617
1353 1618 struct {
1354 1619 struct mrsas_evtarg_ld ld;
1355 1620 uint64_t count;
1356 1621 } ld_count;
1357 1622
1358 1623 struct {
1359 1624 uint64_t lba;
1360 1625 struct mrsas_evtarg_ld ld;
1361 1626 } ld_lba;
1362 1627
1363 1628 struct {
1364 1629 struct mrsas_evtarg_ld ld;
1365 1630 uint32_t prevOwner;
1366 1631 uint32_t newOwner;
1367 1632 } ld_owner;
1368 1633
1369 1634 struct {
1370 1635 uint64_t ld_lba;
1371 1636 uint64_t pd_lba;
1372 1637 struct mrsas_evtarg_ld ld;
1373 1638 struct mrsas_evtarg_pd pd;
1374 1639 } ld_lba_pd_lba;
1375 1640
1376 1641 struct {
1377 1642 struct mrsas_evtarg_ld ld;
1378 1643 struct mrsas_progress prog;
1379 1644 } ld_prog;
1380 1645
1381 1646 struct {
1382 1647 struct mrsas_evtarg_ld ld;
1383 1648 uint32_t prev_state;
1384 1649 uint32_t new_state;
1385 1650 } ld_state;
1386 1651
1387 1652 struct {
1388 1653 uint64_t strip;
1389 1654 struct mrsas_evtarg_ld ld;
1390 1655 } ld_strip;
1391 1656
1392 1657 struct mrsas_evtarg_pd pd;
1393 1658
1394 1659 struct {
1395 1660 struct mrsas_evtarg_pd pd;
1396 1661 uint32_t err;
1397 1662 } pd_err;
1398 1663
1399 1664 struct {
1400 1665 uint64_t lba;
1401 1666 struct mrsas_evtarg_pd pd;
1402 1667 } pd_lba;
1403 1668
1404 1669 struct {
1405 1670 uint64_t lba;
1406 1671 struct mrsas_evtarg_pd pd;
1407 1672 struct mrsas_evtarg_ld ld;
1408 1673 } pd_lba_ld;
1409 1674
1410 1675 struct {
1411 1676 struct mrsas_evtarg_pd pd;
1412 1677 struct mrsas_progress prog;
1413 1678 } pd_prog;
1414 1679
1415 1680 struct {
1416 1681 struct mrsas_evtarg_pd pd;
1417 1682 uint32_t prevState;
1418 1683 uint32_t newState;
1419 1684 } pd_state;
1420 1685
1421 1686 struct {
1422 1687 uint16_t vendorId;
1423 1688 uint16_t deviceId;
1424 1689 uint16_t subVendorId;
1425 1690 uint16_t subDeviceId;
1426 1691 } pci;
1427 1692
1428 1693 uint32_t rate;
1429 1694 char str[96];
1430 1695
1431 1696 struct {
1432 1697 uint32_t rtc;
1433 1698 uint32_t elapsedSeconds;
1434 1699 } time;
1435 1700
1436 1701 struct {
1437 1702 uint32_t ecar;
1438 1703 uint32_t elog;
1439 1704 char str[64];
1440 1705 } ecc;
1441 1706
1442 1707 mrsas_pd_address_t pd_addr;
1443 1708
1444 1709 uint8_t b[96];
1445 1710 uint16_t s[48];
1446 1711 uint32_t w[24];
1447 1712 uint64_t d[12];
1448 1713 } args;
1449 1714
1450 1715 char description[128];
1451 1716
1452 1717 };
1453 1718
1454 1719 /* only 63 are usable by the application */
1455 1720 #define MAX_LOGICAL_DRIVES 64
1456 1721 /* only 255 physical devices may be used */
1457 1722 #define MAX_PHYSICAL_DEVICES 256
1458 1723 #define MAX_PD_PER_ENCLOSURE 64
1459 1724 /* maximum disks per array */
1460 1725 #define MAX_ROW_SIZE 32
1461 1726 /* maximum spans per logical drive */
1462 1727 #define MAX_SPAN_DEPTH 8
1463 1728 /* maximum number of arrays a hot spare may be dedicated to */
1464 1729 #define MAX_ARRAYS_DEDICATED 16
1465 1730 /* maximum number of arrays which may exist */
1466 1731 #define MAX_ARRAYS 128
1467 1732 /* maximum number of foreign configs that may ha managed at once */
1468 1733 #define MAX_FOREIGN_CONFIGS 8
1469 1734 /* maximum spares (global and dedicated combined) */
1470 1735 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES
1471 1736 /* maximum possible Target IDs (i.e. 0 to 63) */
1472 1737 #define MAX_TARGET_ID 63
1473 1738 /* maximum number of supported enclosures */
1474 1739 #define MAX_ENCLOSURES 32
1475 1740 /* maximum number of PHYs per controller */
1476 1741 #define MAX_PHYS_PER_CONTROLLER 16
1477 1742 /* maximum number of LDs per array (due to DDF limitations) */
1478 1743 #define MAX_LDS_PER_ARRAY 16
1479 1744
1480 1745 /*
1481 1746 * -----------------------------------------------------------------------------
1482 1747 * -----------------------------------------------------------------------------
1483 1748 *
1484 1749 * Logical Drive commands
1485 1750 *
1486 1751 * -----------------------------------------------------------------------------
1487 1752 * -----------------------------------------------------------------------------
1488 1753 */
1489 1754 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */
1490 1755
1491 1756 /*
1492 1757 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST
1493 1758 * dcmd.mbox - reserved
1494 1759 * dcmd.sge IN - ptr to returned MR_LD_LIST structure
1495 1760 * Desc: Return the logical drive list structure
1496 1761 * Status: No error
1497 1762 */
1498 1763
1499 1764 /*
1500 1765 * defines the logical drive reference structure
1501 1766 */
1502 1767 typedef union _MR_LD_REF { /* LD reference structure */
1503 1768 struct {
1504 1769 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */
1505 1770 uint8_t reserved; /* reserved for in line with MR_PD_REF */
1506 1771 uint16_t seqNum; /* Sequence Number */
1507 1772 } ld_ref;
1508 1773 uint32_t ref; /* shorthand reference to full 32-bits */
1509 1774 } MR_LD_REF; /* 4 bytes */
1510 1775
1511 1776 /*
1512 1777 * defines the logical drive list structure
1513 1778 */
1514 1779 typedef struct _MR_LD_LIST {
1515 1780 uint32_t ldCount; /* number of LDs */
1516 1781 uint32_t reserved; /* pad to 8-byte boundary */
1517 1782 struct {
1518 1783 MR_LD_REF ref; /* LD reference */
1519 1784 uint8_t state; /* current LD state (MR_LD_STATE) */
1520 1785 uint8_t reserved[3]; /* pad to 8-byte boundary */
1521 1786 uint64_t size; /* LD size */
1522 1787 } ldList[MAX_LOGICAL_DRIVES];
1523 1788 } MR_LD_LIST;
1524 1789
1525 1790 struct mrsas_drv_ver {
1526 1791 uint8_t signature[12];
1527 1792 uint8_t os_name[16];
1528 1793 uint8_t os_ver[12];
1529 1794 uint8_t drv_name[20];
1530 1795 uint8_t drv_ver[32];
1531 1796 uint8_t drv_rel_date[20];
1532 1797 };
1533 1798
1534 1799 #define PCI_TYPE0_ADDRESSES 6
1535 1800 #define PCI_TYPE1_ADDRESSES 2
1536 1801 #define PCI_TYPE2_ADDRESSES 5
1537 1802
1538 1803 struct mrsas_pci_common_header {
1539 1804 uint16_t vendorID; /* (ro) */
1540 1805 uint16_t deviceID; /* (ro) */
1541 1806 uint16_t command; /* Device control */
1542 1807 uint16_t status;
1543 1808 uint8_t revisionID; /* (ro) */
1544 1809 uint8_t progIf; /* (ro) */
1545 1810 uint8_t subClass; /* (ro) */
1546 1811 uint8_t baseClass; /* (ro) */
1547 1812 uint8_t cacheLineSize; /* (ro+) */
1548 1813 uint8_t latencyTimer; /* (ro+) */
1549 1814 uint8_t headerType; /* (ro) */
1550 1815 uint8_t bist; /* Built in self test */
1551 1816
1552 1817 union {
1553 1818 struct {
1554 1819 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES];
1555 1820 uint32_t cis;
1556 1821 uint16_t subVendorID;
1557 1822 uint16_t subSystemID;
1558 1823 uint32_t romBaseAddress;
1559 1824 uint8_t capabilitiesPtr;
1560 1825 uint8_t reserved1[3];
1561 1826 uint32_t reserved2;
1562 1827 uint8_t interruptLine;
1563 1828 uint8_t interruptPin; /* (ro) */
1564 1829 uint8_t minimumGrant; /* (ro) */
1565 1830 uint8_t maximumLatency; /* (ro) */
1566 1831 } type_0;
1567 1832
1568 1833 struct {
1569 1834 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES];
1570 1835 uint8_t primaryBus;
1571 1836 uint8_t secondaryBus;
1572 1837 uint8_t subordinateBus;
1573 1838 uint8_t secondaryLatency;
1574 1839 uint8_t ioBase;
1575 1840 uint8_t ioLimit;
1576 1841 uint16_t secondaryStatus;
1577 1842 uint16_t memoryBase;
1578 1843 uint16_t memoryLimit;
1579 1844 uint16_t prefetchBase;
1580 1845 uint16_t prefetchLimit;
1581 1846 uint32_t prefetchBaseUpper32;
1582 1847 uint32_t prefetchLimitUpper32;
1583 1848 uint16_t ioBaseUpper16;
1584 1849 uint16_t ioLimitUpper16;
1585 1850 uint8_t capabilitiesPtr;
1586 1851 uint8_t reserved1[3];
1587 1852 uint32_t romBaseAddress;
1588 1853 uint8_t interruptLine;
1589 1854 uint8_t interruptPin;
1590 1855 uint16_t bridgeControl;
1591 1856 } type_1;
1592 1857
1593 1858 struct {
1594 1859 uint32_t socketRegistersBaseAddress;
1595 1860 uint8_t capabilitiesPtr;
1596 1861 uint8_t reserved;
1597 1862 uint16_t secondaryStatus;
1598 1863 uint8_t primaryBus;
1599 1864 uint8_t secondaryBus;
1600 1865 uint8_t subordinateBus;
1601 1866 uint8_t secondaryLatency;
1602 1867 struct {
1603 1868 uint32_t base;
1604 1869 uint32_t limit;
1605 1870 } range[PCI_TYPE2_ADDRESSES-1];
1606 1871 uint8_t interruptLine;
1607 1872 uint8_t interruptPin;
1608 1873 uint16_t bridgeControl;
1609 1874 } type_2;
1610 1875 } header;
1611 1876 };
1612 1877
1613 1878 struct mrsas_pci_link_capability {
1614 1879 union {
1615 1880 struct {
1616 1881 uint32_t linkSpeed :4;
1617 1882 uint32_t linkWidth :6;
1618 1883 uint32_t aspmSupport :2;
1619 1884 uint32_t losExitLatency :3;
1620 1885 uint32_t l1ExitLatency :3;
1621 1886 uint32_t rsvdp :6;
1622 1887 uint32_t portNumber :8;
1623 1888 } bits;
1624 1889
1625 1890 uint32_t asUlong;
1626 1891 } cap;
1627 1892
1628 1893 };
1629 1894
1630 1895 struct mrsas_pci_link_status_capability {
1631 1896 union {
1632 1897 struct {
1633 1898 uint16_t linkSpeed :4;
1634 1899 uint16_t negotiatedLinkWidth :6;
1635 1900 uint16_t linkTrainingError :1;
1636 1901 uint16_t linkTraning :1;
1637 1902 uint16_t slotClockConfig :1;
1638 1903 uint16_t rsvdZ :3;
1639 1904 } bits;
1640 1905
1641 1906 uint16_t asUshort;
1642 1907 } stat_cap;
1643 1908
1644 1909 uint16_t reserved;
1645 1910
1646 1911 };
1647 1912
1648 1913 struct mrsas_pci_capabilities {
1649 1914 struct mrsas_pci_link_capability linkCapability;
1650 1915 struct mrsas_pci_link_status_capability linkStatusCapability;
1651 1916 };
1652 1917
1653 1918 struct mrsas_pci_information
1654 1919 {
1655 1920 uint32_t busNumber;
1656 1921 uint8_t deviceNumber;
1657 1922 uint8_t functionNumber;
1658 1923 uint8_t interruptVector;
1659 1924 uint8_t reserved;
1660 1925 struct mrsas_pci_common_header pciHeaderInfo;
1661 1926 struct mrsas_pci_capabilities capability;
1662 1927 uint8_t reserved2[32];
1663 1928 };
1664 1929
1665 1930 struct mrsas_ioctl {
1666 1931 uint16_t version;
1667 1932 uint16_t controller_id;
1668 1933 uint8_t signature[8];
1669 1934 uint32_t reserved_1;
1670 1935 uint32_t control_code;
1671 1936 uint32_t reserved_2[2];
1672 1937 uint8_t frame[64];
1673 1938 union mrsas_sgl_frame sgl_frame;
|
↓ open down ↓ |
406 lines elided |
↑ open up ↑ |
1674 1939 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH];
1675 1940 uint8_t data[1];
1676 1941 };
1677 1942
1678 1943 struct mrsas_aen {
1679 1944 uint16_t host_no;
1680 1945 uint16_t cmd_status;
1681 1946 uint32_t seq_num;
1682 1947 uint32_t class_locale_word;
1683 1948 };
1949 +
1684 1950 #pragma pack()
1685 1951
1686 1952 #ifndef DDI_VENDOR_LSI
1687 1953 #define DDI_VENDOR_LSI "LSI"
1688 1954 #endif /* DDI_VENDOR_LSI */
1689 1955
1690 -#ifndef KMDB_MODULE
1691 -static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
1692 -static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t);
1693 -#ifdef __sparc
1694 -static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t);
1695 -#else /* __sparc */
1696 -static int mrsas_quiesce(dev_info_t *);
1697 -#endif /* __sparc */
1698 -static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t);
1699 -static int mrsas_open(dev_t *, int, int, cred_t *);
1700 -static int mrsas_close(dev_t, int, int, cred_t *);
1701 -static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
1956 +int mrsas_config_scsi_device(struct mrsas_instance *,
1957 + struct scsi_device *, dev_info_t **);
1702 1958
1703 -static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *,
1704 - scsi_hba_tran_t *, struct scsi_device *);
1705 -static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register
1959 +#ifdef PDSUPPORT
1960 +int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t,
1961 + uint8_t, dev_info_t **);
1962 +#endif
1963 +
1964 +dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, uint8_t);
1965 +int mrsas_service_evt(struct mrsas_instance *, int, int, int, uint64_t);
1966 +void return_raid_msg_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1967 +struct mrsas_cmd *get_raid_msg_mfi_pkt(struct mrsas_instance *);
1968 +void return_raid_msg_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1969 +
1970 +int alloc_space_for_mpi2(struct mrsas_instance *);
1971 +void fill_up_drv_ver(struct mrsas_drv_ver *dv);
1972 +
1973 +int mrsas_issue_init_mpi2(struct mrsas_instance *);
1974 +struct scsi_pkt *mrsas_tbolt_tran_init_pkt(struct scsi_address *, register
1706 1975 struct scsi_pkt *, struct buf *, int, int, int, int,
1707 1976 int (*)(), caddr_t);
1708 -static int mrsas_tran_start(struct scsi_address *,
1977 +int mrsas_tbolt_tran_start(struct scsi_address *,
1709 1978 register struct scsi_pkt *);
1710 -static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *);
1711 -static int mrsas_tran_reset(struct scsi_address *, int);
1712 -static int mrsas_tran_getcap(struct scsi_address *, char *, int);
1713 -static int mrsas_tran_setcap(struct scsi_address *, char *, int, int);
1714 -static void mrsas_tran_destroy_pkt(struct scsi_address *,
1715 - struct scsi_pkt *);
1716 -static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *);
1717 -static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *);
1718 -static uint_t mrsas_isr();
1719 -static uint_t mrsas_softintr();
1720 -
1721 -static int init_mfi(struct mrsas_instance *);
1722 -static int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
1723 -static int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
1724 - uchar_t);
1725 -static struct mrsas_cmd *get_mfi_pkt(struct mrsas_instance *);
1726 -static void return_mfi_pkt(struct mrsas_instance *,
1979 +uint32_t tbolt_read_fw_status_reg(struct mrsas_instance *);
1980 +void tbolt_issue_cmd(struct mrsas_cmd *, struct mrsas_instance *);
1981 +int tbolt_issue_cmd_in_poll_mode(struct mrsas_instance *,
1727 1982 struct mrsas_cmd *);
1728 -
1729 -static void free_space_for_mfi(struct mrsas_instance *);
1730 -static void free_additional_dma_buffer(struct mrsas_instance *);
1731 -static int alloc_additional_dma_buffer(struct mrsas_instance *);
1732 -static int read_fw_status_reg_ppc(struct mrsas_instance *);
1733 -static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *);
1734 -static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *,
1983 +int tbolt_issue_cmd_in_sync_mode(struct mrsas_instance *,
1735 1984 struct mrsas_cmd *);
1736 -static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *,
1737 - struct mrsas_cmd *);
1738 -static void enable_intr_ppc(struct mrsas_instance *);
1739 -static void disable_intr_ppc(struct mrsas_instance *);
1740 -static int intr_ack_ppc(struct mrsas_instance *);
1741 -static int mfi_state_transition_to_ready(struct mrsas_instance *);
1742 -static void destroy_mfi_frame_pool(struct mrsas_instance *);
1743 -static int create_mfi_frame_pool(struct mrsas_instance *);
1744 -static int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
1985 +void tbolt_enable_intr(struct mrsas_instance *);
1986 +void tbolt_disable_intr(struct mrsas_instance *);
1987 +int tbolt_intr_ack(struct mrsas_instance *);
1988 +uint_t mr_sas_tbolt_process_outstanding_cmd(struct mrsas_instance *);
1989 + uint_t tbolt_softintr();
1990 +int mrsas_tbolt_dma(struct mrsas_instance *, uint32_t, int, int (*)());
1991 +int mrsas_check_dma_handle(ddi_dma_handle_t handle);
1992 +int mrsas_check_acc_handle(ddi_acc_handle_t handle);
1993 +int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
1745 1994 struct buf *, int, int (*)());
1746 -static int mrsas_dma_move(struct mrsas_instance *,
1995 +int mrsas_dma_move(struct mrsas_instance *,
1747 1996 struct scsi_pkt *, struct buf *);
1748 -static void flush_cache(struct mrsas_instance *instance);
1749 -static void display_scsi_inquiry(caddr_t);
1750 -static int start_mfi_aen(struct mrsas_instance *instance);
1751 -static int handle_drv_ioctl(struct mrsas_instance *instance,
1752 - struct mrsas_ioctl *ioctl, int mode);
1753 -static int handle_mfi_ioctl(struct mrsas_instance *instance,
1754 - struct mrsas_ioctl *ioctl, int mode);
1755 -static int handle_mfi_aen(struct mrsas_instance *instance,
1756 - struct mrsas_aen *aen);
1757 -static void fill_up_drv_ver(struct mrsas_drv_ver *dv);
1758 -static struct mrsas_cmd *build_cmd(struct mrsas_instance *instance,
1759 - struct scsi_address *ap, struct scsi_pkt *pkt,
1760 - uchar_t *cmd_done);
1761 -#ifndef __sparc
1762 -static int wait_for_outstanding(struct mrsas_instance *instance);
1763 -#endif /* __sparc */
1764 -static int register_mfi_aen(struct mrsas_instance *instance,
1765 - uint32_t seq_num, uint32_t class_locale_word);
1766 -static int issue_mfi_pthru(struct mrsas_instance *instance, struct
1767 - mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1768 -static int issue_mfi_dcmd(struct mrsas_instance *instance, struct
1769 - mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1770 -static int issue_mfi_smp(struct mrsas_instance *instance, struct
1771 - mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1772 -static int issue_mfi_stp(struct mrsas_instance *instance, struct
1773 - mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1774 -static int abort_aen_cmd(struct mrsas_instance *instance,
1775 - struct mrsas_cmd *cmd_to_abort);
1997 +int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
1998 + uchar_t);
1999 +void mr_sas_tbolt_build_mfi_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2000 +int mrsas_dma_alloc_dmd(struct mrsas_instance *, dma_obj_t *);
2001 +void tbolt_complete_cmd_in_sync_mode(struct mrsas_instance *,
2002 + struct mrsas_cmd *);
2003 +int alloc_req_rep_desc(struct mrsas_instance *);
2004 +int mrsas_mode_sense_build(struct scsi_pkt *);
2005 +void push_pending_mfi_pkt(struct mrsas_instance *,
2006 + struct mrsas_cmd *);
2007 +int mrsas_issue_pending_cmds(struct mrsas_instance *);
2008 +int mrsas_print_pending_cmds(struct mrsas_instance *);
2009 +int mrsas_complete_pending_cmds(struct mrsas_instance *);
1776 2010
1777 -static int mrsas_common_check(struct mrsas_instance *instance,
1778 - struct mrsas_cmd *cmd);
1779 -static void mrsas_fm_init(struct mrsas_instance *instance);
1780 -static void mrsas_fm_fini(struct mrsas_instance *instance);
1781 -static int mrsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *,
1782 - const void *);
1783 -static void mrsas_fm_ereport(struct mrsas_instance *instance,
1784 - char *detail);
1785 -static int mrsas_check_dma_handle(ddi_dma_handle_t handle);
1786 -static int mrsas_check_acc_handle(ddi_acc_handle_t handle);
2011 +int create_mfi_frame_pool(struct mrsas_instance *);
2012 +void destroy_mfi_frame_pool(struct mrsas_instance *);
2013 +int create_mfi_mpi_frame_pool(struct mrsas_instance *);
2014 +void destroy_mfi_mpi_frame_pool(struct mrsas_instance *);
2015 +int create_mpi2_frame_pool(struct mrsas_instance *);
2016 +void destroy_mpi2_frame_pool(struct mrsas_instance *);
2017 +int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
2018 +void mrsas_tbolt_free_additional_dma_buffer(struct mrsas_instance *);
2019 +void free_req_desc_pool(struct mrsas_instance *);
2020 +void free_space_for_mpi2(struct mrsas_instance *);
2021 +void mrsas_dump_reply_desc(struct mrsas_instance *);
2022 +void tbolt_complete_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2023 +void display_scsi_inquiry(caddr_t);
2024 +void service_mfi_aen(struct mrsas_instance *, struct mrsas_cmd *);
2025 +int mrsas_mode_sense_build(struct scsi_pkt *);
2026 +int mrsas_tbolt_get_ld_map_info(struct mrsas_instance *);
2027 +struct mrsas_cmd *mrsas_tbolt_build_poll_cmd(struct mrsas_instance *,
2028 + struct scsi_address *, struct scsi_pkt *, uchar_t *);
2029 +int mrsas_tbolt_reset_ppc(struct mrsas_instance *instance);
2030 +void mrsas_tbolt_kill_adapter(struct mrsas_instance *instance);
2031 +int abort_syncmap_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2032 +void mrsas_tbolt_prepare_cdb(struct mrsas_instance *instance, U8 cdb[],
2033 + struct IO_REQUEST_INFO *, Mpi2RaidSCSIIORequest_t *, U32);
1787 2034
1788 -static void mrsas_rem_intrs(struct mrsas_instance *instance);
1789 -static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type);
1790 2035
1791 -static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *,
1792 - scsi_hba_tran_t *, struct scsi_device *);
1793 -static int mrsas_tran_bus_config(dev_info_t *, uint_t,
1794 - ddi_bus_config_op_t, void *, dev_info_t **);
1795 -static int mrsas_parse_devname(char *, int *, int *);
1796 -static int mrsas_config_all_devices(struct mrsas_instance *);
1797 -static int mrsas_config_scsi_device(struct mrsas_instance *,
1798 - struct scsi_device *, dev_info_t **);
1799 -static int mrsas_config_ld(struct mrsas_instance *, uint16_t,
1800 - uint8_t, dev_info_t **);
1801 -static dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t,
1802 - uint8_t);
1803 -static int mrsas_name_node(dev_info_t *, char *, int);
1804 -static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *);
1805 -static int mrsas_service_evt(struct mrsas_instance *, int, int, int,
1806 - uint64_t);
1807 -static int mrsas_mode_sense_build(struct scsi_pkt *);
1808 -static void push_pending_mfi_pkt(struct mrsas_instance *,
1809 - struct mrsas_cmd *);
1810 -static int mrsas_issue_init_mfi(struct mrsas_instance *);
1811 -static int mrsas_issue_pending_cmds(struct mrsas_instance *);
1812 -static int mrsas_print_pending_cmds(struct mrsas_instance *);
1813 -static int mrsas_complete_pending_cmds(struct mrsas_instance *);
1814 -static int mrsas_reset_ppc(struct mrsas_instance *);
1815 -static uint32_t mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *);
1816 -static int mrsas_kill_adapter(struct mrsas_instance *);
1817 -static void io_timeout_checker(void *instance);
1818 -static void complete_cmd_in_sync_mode(struct mrsas_instance *,
1819 - struct mrsas_cmd *);
2036 +int mrsas_init_adapter_ppc(struct mrsas_instance *instance);
2037 +int mrsas_init_adapter_tbolt(struct mrsas_instance *instance);
2038 +int mrsas_init_adapter(struct mrsas_instance *instance);
1820 2039
1821 -#endif /* KMDB_MODULE */
2040 +int mrsas_alloc_cmd_pool(struct mrsas_instance *instance);
2041 +void mrsas_free_cmd_pool(struct mrsas_instance *instance);
1822 2042
2043 +void mrsas_print_cmd_details(struct mrsas_instance *, struct mrsas_cmd *, int);
2044 +struct mrsas_cmd *get_raid_msg_pkt(struct mrsas_instance *);
1823 2045
2046 +int mfi_state_transition_to_ready(struct mrsas_instance *);
2047 +
2048 +
2049 +/* FMA functions. */
2050 +int mrsas_common_check(struct mrsas_instance *, struct mrsas_cmd *);
2051 +void mrsas_fm_ereport(struct mrsas_instance *, char *);
2052 +
2053 +
1824 2054 #ifdef __cplusplus
1825 2055 }
1826 2056 #endif
1827 2057
1828 2058 #endif /* _MR_SAS_H_ */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX