1 /*
2 * mr_sas.h: header for mr_sas
3 *
4 * Solaris MegaRAID driver for SAS2.0 controllers
5 * Copyright (c) 2008-2009, LSI Logic Corporation.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 *
14 * 2. Redistributions in binary form must reproduce the above copyright notice,
15 * this list of conditions and the following disclaimer in the documentation
16 * and/or other materials provided with the distribution.
17 *
18 * 3. Neither the name of the author nor the names of its contributors may be
19 * used to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 * DAMAGE.
34 */
35
36 /*
37 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
38 */
39 #ifndef _MR_SAS_H_
40 #define _MR_SAS_H_
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #include <sys/scsi/scsi.h>
47 #include "mr_sas_list.h"
48
49 /*
50 * MegaRAID SAS2.0 Driver meta data
51 */
52 #define MRSAS_VERSION "LSIv2.7"
53 #define MRSAS_RELDATE "Apr 21, 2010"
54
55 #define MRSAS_TRUE 1
56 #define MRSAS_FALSE 0
57
58 #define ADAPTER_RESET_NOT_REQUIRED 0
59 #define ADAPTER_RESET_REQUIRED 1
60
61 /*
62 * MegaRAID SAS2.0 device id conversion definitions.
63 */
64 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT)
65
66 /*
67 * MegaRAID SAS2.0 supported controllers
68 */
69 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078
70 #define PCI_DEVICE_ID_LSI_2108V 0x0079
71
72 /*
73 * Register Index for 2108 Controllers.
74 */
75 #define REGISTER_SET_IO_2108 (2)
76
77 #define MRSAS_MAX_SGE_CNT 0x50
78
79 #define MRSAS_IOCTL_DRIVER 0x12341234
80 #define MRSAS_IOCTL_FIRMWARE 0x12345678
81 #define MRSAS_IOCTL_AEN 0x87654321
82
83 #define MRSAS_1_SECOND 1000000
84
85 /* Dynamic Enumeration Flags */
86 #define MRSAS_PD_LUN 1
87 #define MRSAS_LD_LUN 0
88 #define MRSAS_PD_TGT_MAX 255
89 #define MRSAS_GET_PD_MAX(s) ((s)->mr_pd_max)
90 #define WWN_STRLEN 17
91 #define APP_RESERVE_CMDS 32
92 /*
93 * =====================================
94 * MegaRAID SAS2.0 MFI firmware definitions
95 * =====================================
96 */
97 /*
98 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for
99 * protocol between the software and firmware. Commands are issued using
100 * "message frames"
101 */
102
103 /*
104 * FW posts its state in upper 4 bits of outbound_msg_0 register
105 */
106 #define MFI_STATE_SHIFT 28
107 #define MFI_STATE_MASK ((uint32_t)0xF<<MFI_STATE_SHIFT)
108 #define MFI_STATE_UNDEFINED ((uint32_t)0x0<<MFI_STATE_SHIFT)
109 #define MFI_STATE_BB_INIT ((uint32_t)0x1<<MFI_STATE_SHIFT)
110 #define MFI_STATE_FW_INIT ((uint32_t)0x4<<MFI_STATE_SHIFT)
111 #define MFI_STATE_WAIT_HANDSHAKE ((uint32_t)0x6<<MFI_STATE_SHIFT)
112 #define MFI_STATE_FW_INIT_2 ((uint32_t)0x7<<MFI_STATE_SHIFT)
113 #define MFI_STATE_DEVICE_SCAN ((uint32_t)0x8<<MFI_STATE_SHIFT)
114 #define MFI_STATE_BOOT_MESSAGE_PENDING ((uint32_t)0x9<<MFI_STATE_SHIFT)
115 #define MFI_STATE_FLUSH_CACHE ((uint32_t)0xA<<MFI_STATE_SHIFT)
116 #define MFI_STATE_READY ((uint32_t)0xB<<MFI_STATE_SHIFT)
117 #define MFI_STATE_OPERATIONAL ((uint32_t)0xC<<MFI_STATE_SHIFT)
118 #define MFI_STATE_FAULT ((uint32_t)0xF<<MFI_STATE_SHIFT)
119
120 #define MRMFI_FRAME_SIZE 64
121
122 /*
123 * During FW init, clear pending cmds & reset state using inbound_msg_0
124 *
125 * ABORT : Abort all pending cmds
126 * READY : Move from OPERATIONAL to READY state; discard queue info
127 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
128 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
129 */
130 #define MFI_INIT_ABORT 0x00000001
131 #define MFI_INIT_READY 0x00000002
132 #define MFI_INIT_MFIMODE 0x00000004
133 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
134 #define MFI_INIT_HOTPLUG 0x00000010
135 #define MFI_STOP_ADP 0x00000020
136 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
137
138 /*
165 #define MFI_CMD_OP_LD_SCSI 0x03
166 #define MFI_CMD_OP_PD_SCSI 0x04
167 #define MFI_CMD_OP_DCMD 0x05
168 #define MFI_CMD_OP_ABORT 0x06
169 #define MFI_CMD_OP_SMP 0x07
170 #define MFI_CMD_OP_STP 0x08
171
172 #define MR_DCMD_CTRL_GET_INFO 0x01010000
173
174 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
175 #define MR_FLUSH_CTRL_CACHE 0x01
176 #define MR_FLUSH_DISK_CACHE 0x02
177
178 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
179 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01
180
181 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
182 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
183 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
184 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
185 #define MR_DCMD_PD_GET_INFO 0x02020000
186
187 /*
188 * Solaris Specific MAX values
189 */
190 #define MAX_SGL 24
191 /*
192 * MFI command completion codes
193 */
194 enum MFI_STAT {
195 MFI_STAT_OK = 0x00,
196 MFI_STAT_INVALID_CMD = 0x01,
197 MFI_STAT_INVALID_DCMD = 0x02,
198 MFI_STAT_INVALID_PARAMETER = 0x03,
199 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
200 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
201 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
202 MFI_STAT_APP_IN_USE = 0x07,
203 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
204 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
205 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
206 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
207 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
208 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
209 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
210 MFI_STAT_FLASH_BUSY = 0x0f,
227 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
228 MFI_STAT_MFC_HW_ERROR = 0x21,
229 MFI_STAT_NO_HW_PRESENT = 0x22,
230 MFI_STAT_NOT_FOUND = 0x23,
231 MFI_STAT_NOT_IN_ENCL = 0x24,
232 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
233 MFI_STAT_PD_TYPE_WRONG = 0x26,
234 MFI_STAT_PR_DISABLED = 0x27,
235 MFI_STAT_ROW_INDEX_INVALID = 0x28,
236 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
237 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
238 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
239 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
240 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
241 MFI_STAT_SCSI_IO_FAILED = 0x2e,
242 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
243 MFI_STAT_SHUTDOWN_FAILED = 0x30,
244 MFI_STAT_TIME_NOT_SET = 0x31,
245 MFI_STAT_WRONG_STATE = 0x32,
246 MFI_STAT_LD_OFFLINE = 0x33,
247 /* UNUSED: 0x34 to 0xfe */
248 MFI_STAT_INVALID_STATUS = 0xFF
249 };
250
251 enum MR_EVT_CLASS {
252 MR_EVT_CLASS_DEBUG = -2,
253 MR_EVT_CLASS_PROGRESS = -1,
254 MR_EVT_CLASS_INFO = 0,
255 MR_EVT_CLASS_WARNING = 1,
256 MR_EVT_CLASS_CRITICAL = 2,
257 MR_EVT_CLASS_FATAL = 3,
258 MR_EVT_CLASS_DEAD = 4
259 };
260
261 enum MR_EVT_LOCALE {
262 MR_EVT_LOCALE_LD = 0x0001,
263 MR_EVT_LOCALE_PD = 0x0002,
264 MR_EVT_LOCALE_ENCL = 0x0004,
265 MR_EVT_LOCALE_BBU = 0x0008,
266 MR_EVT_LOCALE_SAS = 0x0010,
267 MR_EVT_LOCALE_CTRL = 0x0020,
268 MR_EVT_LOCALE_CONFIG = 0x0040,
269 MR_EVT_LOCALE_CLUSTER = 0x0080,
270 MR_EVT_LOCALE_ALL = 0xffff
271 };
272
273 #define MR_EVT_CFG_CLEARED 0x0004
274 #define MR_EVT_LD_CREATED 0x008a
275 #define MR_EVT_LD_DELETED 0x008b
276 #define MR_EVT_PD_REMOVED_EXT 0x00f8
277 #define MR_EVT_PD_INSERTED_EXT 0x00f7
278
279 enum LD_STATE {
280 LD_OFFLINE = 0,
281 LD_PARTIALLY_DEGRADED = 1,
282 LD_DEGRADED = 2,
283 LD_OPTIMAL = 3,
284 LD_INVALID = 0xFF
285 };
286
287 enum MRSAS_EVT {
288 MRSAS_EVT_CONFIG_TGT = 0,
289 MRSAS_EVT_UNCONFIG_TGT = 1,
290 MRSAS_EVT_UNCONFIG_SMP = 2
291 };
292
293 #define DMA_OBJ_ALLOCATED 1
294 #define DMA_OBJ_REALLOCATED 2
295 #define DMA_OBJ_FREED 3
296
297 /*
298 * dma_obj_t - Our DMA object
299 * @param buffer : kernel virtual address
300 * @param size : size of the data to be allocated
301 * @param acc_handle : access handle
302 * @param dma_handle : dma handle
303 * @param dma_cookie : scatter-gather list
304 * @param dma_attr : dma attributes for this buffer
305 * Our DMA object. The caller must initialize the size and dma attributes
306 * (dma_attr) fields before allocating the resources.
307 */
308 typedef struct {
309 caddr_t buffer;
310 uint32_t size;
311 ddi_acc_handle_t acc_handle;
312 ddi_dma_handle_t dma_handle;
313 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT];
314 ddi_dma_attr_t dma_attr;
315 uint8_t status;
316 uint8_t reserved[3];
317 } dma_obj_t;
318
319 struct mrsas_eventinfo {
320 struct mrsas_instance *instance;
321 int tgt;
322 int lun;
323 int event;
324 };
325
326 struct mrsas_ld {
327 dev_info_t *dip;
328 uint8_t lun_type;
329 uint8_t reserved[3];
330 };
331
332 struct mrsas_pd {
333 dev_info_t *dip;
334 uint8_t lun_type;
335 uint8_t dev_id;
336 uint8_t flags;
337 uint8_t reserved;
338 };
339
340 struct mrsas_pd_info {
341 uint16_t deviceId;
342 uint16_t seqNum;
343 uint8_t inquiryData[96];
344 uint8_t vpdPage83[64];
345 uint8_t notSupported;
346 uint8_t scsiDevType;
347 uint8_t a;
348 uint8_t device_speed;
349 uint32_t mediaerrcnt;
350 uint32_t other;
351 uint32_t pred;
352 uint32_t lastpred;
353 uint16_t fwState;
354 uint8_t disabled;
355 uint8_t linkspwwd;
356 uint32_t ddfType;
357 struct {
358 uint8_t count;
359 uint8_t isPathBroken;
360 uint8_t connectorIndex[2];
361 uint8_t reserved[4];
362 uint64_t sasAddr[2];
363 uint8_t reserved2[16];
364 } pathInfo;
365 };
366
367 typedef struct mrsas_instance {
368 uint32_t *producer;
369 uint32_t *consumer;
370
371 uint32_t *reply_queue;
372 dma_obj_t mfi_internal_dma_obj;
373 uint16_t adapterresetinprogress;
374 uint16_t deadadapter;
375 uint8_t init_id;
376 uint8_t flag_ieee;
377 uint8_t disable_online_ctrl_reset;
378 uint8_t fw_fault_count_after_ocr;
379
380 uint16_t max_num_sge;
381 uint16_t max_fw_cmds;
382 uint32_t max_sectors_per_req;
383
384 struct mrsas_cmd **cmd_list;
385 mlist_t cmd_pool_list;
386 kmutex_t cmd_pool_mtx;
387
388 mlist_t app_cmd_pool_list;
389 kmutex_t app_cmd_pool_mtx;
390 mlist_t cmd_pend_list;
391 kmutex_t cmd_pend_mtx;
392
393 dma_obj_t mfi_evt_detail_obj;
394 struct mrsas_cmd *aen_cmd;
395
396 uint32_t aen_seq_num;
397 uint32_t aen_class_locale_word;
398
399 scsi_hba_tran_t *tran;
400
401 kcondvar_t int_cmd_cv;
402 kmutex_t int_cmd_mtx;
403
404 kcondvar_t aen_cmd_cv;
405 kmutex_t aen_cmd_mtx;
406
407 kcondvar_t abort_cmd_cv;
408 kmutex_t abort_cmd_mtx;
409
410 dev_info_t *dip;
411 ddi_acc_handle_t pci_handle;
412
413 timeout_id_t timeout_id;
414 uint32_t unique_id;
415 uint16_t fw_outstanding;
416 caddr_t regmap;
417 ddi_acc_handle_t regmap_handle;
418 uint8_t isr_level;
419 ddi_iblock_cookie_t iblock_cookie;
420 ddi_iblock_cookie_t soft_iblock_cookie;
421 ddi_softintr_t soft_intr_id;
422 uint8_t softint_running;
423 kmutex_t completed_pool_mtx;
424 mlist_t completed_pool_list;
425
426 caddr_t internal_buf;
427 uint32_t internal_buf_dmac_add;
428 uint32_t internal_buf_size;
429
430 uint16_t vendor_id;
431 uint16_t device_id;
432 uint16_t subsysvid;
433 uint16_t subsysid;
434 int instance;
435 int baseaddress;
436 char iocnode[16];
437
438 int fm_capabilities;
439
440 struct mrsas_func_ptr *func_ptr;
441 /* MSI interrupts specific */
442 ddi_intr_handle_t *intr_htable;
443 int intr_type;
444 int intr_cnt;
445 size_t intr_size;
446 uint_t intr_pri;
447 int intr_cap;
448
449 ddi_taskq_t *taskq;
450 struct mrsas_ld *mr_ld_list;
451 kmutex_t ocr_flags_mtx;
452 } mrsas_t;
453
454 struct mrsas_func_ptr {
455 int (*read_fw_status_reg)(struct mrsas_instance *);
456 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *);
457 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
458 struct mrsas_cmd *);
459 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
460 struct mrsas_cmd *);
461 void (*enable_intr)(struct mrsas_instance *);
462 void (*disable_intr)(struct mrsas_instance *);
463 int (*intr_ack)(struct mrsas_instance *);
464 };
465
466 /*
467 * ### Helper routines ###
468 */
469
470 /*
471 * con_log() - console log routine
472 * @param level : indicates the severity of the message.
473 * @fparam mt : format string
474 *
475 * con_log displays the error messages on the console based on the current
476 * debug level. Also it attaches the appropriate kernel severity level with
477 * the message.
478 *
479 *
480 * console messages debug levels
481 */
482 #define CL_NONE 0 /* No debug information */
483 #define CL_TEST_OCR 1
484 #define CL_ANN 2 /* print unconditionally, announcements */
485 #define CL_ANN1 3 /* No o/p */
486 #define CL_DLEVEL1 4 /* debug level 1, informative */
487 #define CL_DLEVEL2 5 /* debug level 2, verbose */
488 #define CL_DLEVEL3 6 /* debug level 3, very verbose */
489
490
491 #ifdef __SUNPRO_C
492 #define __func__ ""
493 #endif
494
495 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
496
497 /*
498 * ### SCSA definitions ###
499 */
500 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target)
501 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun)
502 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran)
503 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
504
505 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private)
506 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap))
507
508 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private)
509 #define CMD2PKT(sp) ((sp)->cmd_pkt)
510 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request))
530 #define SCP2HOST(scp) (scp)->device->host /* to host */
531 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */
532 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */
533 #define SCP2TARGET(scp) (scp)->device->id /* to target */
534 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */
535
536 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
537 #define SCP2ADAPTER(scp) \
538 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
539
540 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \
541 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0
542 #define MRDRV_IS_LOGICAL(ap) \
543 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0
544 #define MAP_DEVICE_ID(instance, ap) \
545 (ap->a_target)
546
547 #define HIGH_LEVEL_INTR 1
548 #define NORMAL_LEVEL_INTR 0
549
550 #define IO_RETRY_COUNT 3
551 #define MAX_FW_RESET_COUNT 3
552
553 /*
554 * scsa_cmd - Per-command mr private data
555 * @param cmd_dmahandle : dma handle
556 * @param cmd_dmacookies : current dma cookies
557 * @param cmd_pkt : scsi_pkt reference
558 * @param cmd_dmacount : dma count
559 * @param cmd_cookie : next cookie
560 * @param cmd_ncookies : cookies per window
561 * @param cmd_cookiecnt : cookies per sub-win
562 * @param cmd_nwin : number of dma windows
563 * @param cmd_curwin : current dma window
564 * @param cmd_dma_offset : current window offset
565 * @param cmd_dma_len : current window length
566 * @param cmd_flags : private flags
567 * @param cmd_cdblen : length of cdb
568 * @param cmd_scblen : length of scb
569 * @param cmd_buf : command buffer
570 * @param channel : channel for scsi sub-system
571 * @param target : target for scsi sub-system
572 * @param lun : LUN for scsi sub-system
581 ulong_t cmd_dmacount;
582 uint_t cmd_cookie;
583 uint_t cmd_ncookies;
584 uint_t cmd_cookiecnt;
585 uint_t cmd_nwin;
586 uint_t cmd_curwin;
587 off_t cmd_dma_offset;
588 ulong_t cmd_dma_len;
589 ulong_t cmd_flags;
590 uint_t cmd_cdblen;
591 uint_t cmd_scblen;
592 struct buf *cmd_buf;
593 ushort_t device_id;
594 uchar_t islogical;
595 uchar_t lun;
596 struct mrsas_device *mrsas_dev;
597 };
598
599
600 struct mrsas_cmd {
601 union mrsas_frame *frame;
602 uint32_t frame_phys_addr;
603 uint8_t *sense;
604 uint32_t sense_phys_addr;
605 dma_obj_t frame_dma_obj;
606 uint8_t frame_dma_obj_status;
607
608 uint32_t index;
609 uint8_t sync_cmd;
610 uint8_t cmd_status;
611 uint16_t abort_aen;
612 mlist_t list;
613 uint32_t frame_count;
614 struct scsa_cmd *cmd;
615 struct scsi_pkt *pkt;
616 uint16_t retry_count_for_ocr;
617 uint16_t drv_pkt_time;
618 };
619
620 #define MAX_MGMT_ADAPTERS 1024
621 #define IOC_SIGNATURE "MR-SAS"
622
623 #define IOC_CMD_FIRMWARE 0x0
624 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000
625 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
626 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
627 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300
628
629
630 #define MRSAS_MAX_SENSE_LENGTH 32
631
632 struct mrsas_mgmt_info {
633
634 uint16_t count;
635 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS];
636 uint16_t map[MAX_MGMT_ADAPTERS];
637 int max_index;
638 };
639
640 #pragma pack(1)
641
642 /*
643 * SAS controller properties
644 */
645 struct mrsas_ctrl_prop {
646 uint16_t seq_num;
647 uint16_t pred_fail_poll_interval;
648 uint16_t intr_throttle_count;
649 uint16_t intr_throttle_timeouts;
650
651 uint8_t rebuild_rate;
652 uint8_t patrol_read_rate;
653 uint8_t bgi_rate;
654 uint8_t cc_rate;
655 uint8_t recon_rate;
656
657 uint8_t cache_flush_interval;
658
659 uint8_t spinup_drv_count;
660 uint8_t spinup_delay;
661
662 uint8_t cluster_enable;
663 uint8_t coercion_mode;
664 uint8_t alarm_enable;
665 uint8_t reserved_1[13];
666 uint32_t on_off_properties;
667 uint8_t reserved_4[28];
668 };
669
670
671 /*
672 * SAS controller information
673 */
674 struct mrsas_ctrl_info {
675 /* PCI device information */
676 struct {
677 uint16_t vendor_id;
678 uint16_t device_id;
679 uint16_t sub_vendor_id;
680 uint16_t sub_device_id;
681 uint8_t reserved[24];
682 } pci;
683
684 /* Host interface information */
850 * MegaRAID SAS2.0 driver definitions
851 * ==================================
852 */
853 #define MRDRV_MAX_NUM_CMD 1024
854
855 #define MRDRV_MAX_PD_CHANNELS 2
856 #define MRDRV_MAX_LD_CHANNELS 2
857 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \
858 MRDRV_MAX_LD_CHANNELS)
859 #define MRDRV_MAX_DEV_PER_CHANNEL 128
860 #define MRDRV_DEFAULT_INIT_ID -1
861 #define MRDRV_MAX_CMD_PER_LUN 1000
862 #define MRDRV_MAX_LUN 1
863 #define MRDRV_MAX_LD 64
864
865 #define MRDRV_RESET_WAIT_TIME 300
866 #define MRDRV_RESET_NOTICE_INTERVAL 5
867
868 #define MRSAS_IOCTL_CMD 0
869
870 /*
871 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
872 * SGLs based on the size of dma_addr_t
873 */
874 #define IS_DMA64 (sizeof (dma_addr_t) == 8)
875
876 #define IB_MSG_0_OFF 0x10 /* XScale */
877 #define OB_MSG_0_OFF 0x18 /* XScale */
878 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */
879 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */
880 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */
881 #define IB_QPORT_OFF 0x40 /* XScale & ROC */
882 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */
883 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */
884 #define OB_INTR_MASK 0xFFFFFFFF
885 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF
886 #define WRITE_SEQ_OFF 0x000000FC
887 #define HOST_DIAG_OFF 0x000000F8
888 #define DIAG_RESET_ADAPTER 0x00000004
889 #define DIAG_WRITE_ENABLE 0x00000080
890 /*
891 * All MFI register set macros accept mrsas_register_set*
892 */
893 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \
894 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v))
895
896 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \
897 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF))
898
899 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \
900 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v))
901
902 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \
903 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
904
905 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \
906 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
907
908 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \
909 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
910
911 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \
912 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
913
914 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \
915 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
916
917 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \
918 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
919
920 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \
921 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
922
923 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \
924 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
925
926 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
927 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
928
929 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
930 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
931 (v))
932
933 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \
934 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
935
936 /*
937 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
938 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
939 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
940 */
941 #define MFI_OB_INTR_STATUS_MASK 0x00000002
942
943 /*
944 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also
945 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
946 * been set in this flag along with bit 1.
947 */
948 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001
949 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005
950
951 #define MFI_POLL_TIMEOUT_SECS 60
952
953 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \
954 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
955 #define MFI_DISABLE_INTR(instance) \
956 { \
957 uint32_t disable = 1; \
958 uint32_t mask = ddi_get32((instance)->regmap_handle, \
959 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
960 mask &= ~disable; \
961 ddi_put32((instance)->regmap_handle, (uint32_t *) \
962 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \
963 }
964
965 /* By default, the firmware programs for 8 Kbytes of memory */
966 #define DEFAULT_MFI_MEM_SZ 8192
967 #define MINIMUM_MFI_MEM_SZ 4096
968
969 /* DCMD Message Frame MAILBOX0-11 */
970 #define DCMD_MBOX_SZ 12
971
972 /*
973 * on_off_property of mrsas_ctrl_prop
974 * bit0-9, 11-31 are reserved
975 */
976 #define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */
977
978 struct mrsas_register_set {
979 uint32_t reserved_0[4];
980
981 uint32_t inbound_msg_0;
982 uint32_t inbound_msg_1;
983 uint32_t outbound_msg_0;
984 uint32_t outbound_msg_1;
985
986 uint32_t inbound_doorbell;
987 uint32_t inbound_intr_status;
988 uint32_t inbound_intr_mask;
989
990 uint32_t outbound_doorbell;
991 uint32_t outbound_intr_status;
992 uint32_t outbound_intr_mask;
993
994 uint32_t reserved_1[2];
995
996 uint32_t inbound_queue_port;
997 uint32_t outbound_queue_port;
998
999 uint32_t reserved_2[22];
1000
1001 uint32_t outbound_doorbell_clear;
1002
1003 uint32_t reserved_3[3];
1004
1005 uint32_t outbound_scratch_pad;
1006
1007 uint32_t reserved_4[3];
1008
1009 uint32_t inbound_low_queue_port;
1010
1011 uint32_t inbound_high_queue_port;
1012
1013 uint32_t reserved_5;
1014 uint32_t index_registers[820];
1015 };
1016
1017 struct mrsas_sge32 {
1018 uint32_t phys_addr;
1019 uint32_t length;
1020 };
1021
1022 struct mrsas_sge64 {
1023 uint64_t phys_addr;
1024 uint32_t length;
1025 };
1026
1027 struct mrsas_sge_ieee {
1028 uint64_t phys_addr;
1029 uint32_t length;
1030 uint32_t flag;
1031 };
1032
1033 union mrsas_sgl {
1034 struct mrsas_sge32 sge32[1];
1035 struct mrsas_sge64 sge64[1];
1036 struct mrsas_sge_ieee sge_ieee[1];
1037 };
1038
1039 struct mrsas_header {
1040 uint8_t cmd;
1041 uint8_t sense_len;
1042 uint8_t cmd_status;
1043 uint8_t scsi_status;
1044
1045 uint8_t target_id;
1046 uint8_t lun;
1047 uint8_t cdb_len;
1048 uint8_t sge_count;
1049
1050 uint32_t context;
1051 uint8_t req_id;
1052 uint8_t msgvector;
1053 uint16_t pad_0;
1054
1055 uint16_t flags;
1056 uint16_t timeout;
1057 uint32_t data_xferlen;
1058 };
1059
1060 union mrsas_sgl_frame {
1061 struct mrsas_sge32 sge32[8];
1062 struct mrsas_sge64 sge64[5];
1063 };
1064
1065 struct mrsas_init_frame {
1066 uint8_t cmd;
1067 uint8_t reserved_0;
1068 uint8_t cmd_status;
1069
1070 uint8_t reserved_1;
1071 uint32_t reserved_2;
1072
1073 uint32_t context;
1074 uint8_t req_id;
1075 uint8_t msgvector;
1076 uint16_t pad_0;
1077
1078 uint16_t flags;
1079 uint16_t reserved_3;
1080 uint32_t data_xfer_len;
1081
1082 uint32_t queue_info_new_phys_addr_lo;
1083 uint32_t queue_info_new_phys_addr_hi;
1084 uint32_t queue_info_old_phys_addr_lo;
1085 uint32_t queue_info_old_phys_addr_hi;
1086
1087 uint32_t reserved_4[6];
1088 };
1089
1090 struct mrsas_init_queue_info {
1091 uint32_t init_flags;
1092 uint32_t reply_queue_entries;
1093
1094 uint32_t reply_queue_start_phys_addr_lo;
1095 uint32_t reply_queue_start_phys_addr_hi;
1096 uint32_t producer_index_phys_addr_lo;
1097 uint32_t producer_index_phys_addr_hi;
1098 uint32_t consumer_index_phys_addr_lo;
1099 uint32_t consumer_index_phys_addr_hi;
1100 };
1101
1102 struct mrsas_io_frame {
1103 uint8_t cmd;
1104 uint8_t sense_len;
1105 uint8_t cmd_status;
1106 uint8_t scsi_status;
1107
1108 uint8_t target_id;
1109 uint8_t access_byte;
1110 uint8_t reserved_0;
1111 uint8_t sge_count;
1112
1113 uint32_t context;
1114 uint8_t req_id;
1115 uint8_t msgvector;
1116 uint16_t pad_0;
1117
1118 uint16_t flags;
1119 uint16_t timeout;
1120 uint32_t lba_count;
1121
1122 uint32_t sense_buf_phys_addr_lo;
1123 uint32_t sense_buf_phys_addr_hi;
1124
1125 uint32_t start_lba_lo;
1126 uint32_t start_lba_hi;
1127
1128 union mrsas_sgl sgl;
1129 };
1130
1131 struct mrsas_pthru_frame {
1132 uint8_t cmd;
1133 uint8_t sense_len;
1134 uint8_t cmd_status;
1135 uint8_t scsi_status;
1136
1137 uint8_t target_id;
1138 uint8_t lun;
1139 uint8_t cdb_len;
1140 uint8_t sge_count;
1141
1142 uint32_t context;
1143 uint8_t req_id;
1144 uint8_t msgvector;
1145 uint16_t pad_0;
1146
1147 uint16_t flags;
1148 uint16_t timeout;
1149 uint32_t data_xfer_len;
1150
1151 uint32_t sense_buf_phys_addr_lo;
1152 uint32_t sense_buf_phys_addr_hi;
1153
1154 uint8_t cdb[16];
1155 union mrsas_sgl sgl;
1156 };
1157
1158 struct mrsas_dcmd_frame {
1159 uint8_t cmd;
1160 uint8_t reserved_0;
1161 uint8_t cmd_status;
1162 uint8_t reserved_1[4];
1163 uint8_t sge_count;
1164
1165 uint32_t context;
1166 uint8_t req_id;
1167 uint8_t msgvector;
1168 uint16_t pad_0;
1169
1170 uint16_t flags;
1171 uint16_t timeout;
1172
1173 uint32_t data_xfer_len;
1174 uint32_t opcode;
1175
1176 union {
1177 uint8_t b[DCMD_MBOX_SZ];
1178 uint16_t s[6];
1179 uint32_t w[3];
1180 } mbox;
1181
1182 union mrsas_sgl sgl;
1183 };
1184
1185 struct mrsas_abort_frame {
1186 uint8_t cmd;
1187 uint8_t reserved_0;
1188 uint8_t cmd_status;
1189
1190 uint8_t reserved_1;
1191 uint32_t reserved_2;
1192
1193 uint32_t context;
1194 uint8_t req_id;
1195 uint8_t msgvector;
1196 uint16_t pad_0;
1197
1198 uint16_t flags;
1199 uint16_t reserved_3;
1200 uint32_t reserved_4;
1201
1202 uint32_t abort_context;
1203 uint32_t pad_1;
1204
1205 uint32_t abort_mfi_phys_addr_lo;
1206 uint32_t abort_mfi_phys_addr_hi;
1207
1208 uint32_t reserved_5[6];
1209 };
1210
1211 struct mrsas_smp_frame {
1212 uint8_t cmd;
1213 uint8_t reserved_1;
1214 uint8_t cmd_status;
1215 uint8_t connection_status;
1216
1217 uint8_t reserved_2[3];
1218 uint8_t sge_count;
1219
1220 uint32_t context;
1221 uint8_t req_id;
1222 uint8_t msgvector;
1223 uint16_t pad_0;
1224
1225 uint16_t flags;
1226 uint16_t timeout;
1227
1228 uint32_t data_xfer_len;
1229
1230 uint64_t sas_addr;
1231
1232 union mrsas_sgl sgl[2];
1233 };
1234
1235 struct mrsas_stp_frame {
1236 uint8_t cmd;
1237 uint8_t reserved_1;
1238 uint8_t cmd_status;
1239 uint8_t connection_status;
1240
1241 uint8_t target_id;
1242 uint8_t reserved_2[2];
1243 uint8_t sge_count;
1244
1245 uint32_t context;
1246 uint8_t req_id;
1247 uint8_t msgvector;
1248 uint16_t pad_0;
1249
1250 uint16_t flags;
1251 uint16_t timeout;
1252
1253 uint32_t data_xfer_len;
1254
1255 uint16_t fis[10];
1256 uint32_t stp_flags;
1257 union mrsas_sgl sgl;
1258 };
1259
1260 union mrsas_frame {
1261 struct mrsas_header hdr;
1262 struct mrsas_init_frame init;
1263 struct mrsas_io_frame io;
1264 struct mrsas_pthru_frame pthru;
1265 struct mrsas_dcmd_frame dcmd;
1266 struct mrsas_abort_frame abort;
1267 struct mrsas_smp_frame smp;
1268 struct mrsas_stp_frame stp;
1269
1270 uint8_t raw_bytes[64];
1271 };
1272
1273 typedef struct mrsas_pd_address {
1274 uint16_t device_id;
1275 uint16_t encl_id;
1276
1277 union {
1664
1665 struct mrsas_ioctl {
1666 uint16_t version;
1667 uint16_t controller_id;
1668 uint8_t signature[8];
1669 uint32_t reserved_1;
1670 uint32_t control_code;
1671 uint32_t reserved_2[2];
1672 uint8_t frame[64];
1673 union mrsas_sgl_frame sgl_frame;
1674 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH];
1675 uint8_t data[1];
1676 };
1677
1678 struct mrsas_aen {
1679 uint16_t host_no;
1680 uint16_t cmd_status;
1681 uint32_t seq_num;
1682 uint32_t class_locale_word;
1683 };
1684 #pragma pack()
1685
1686 #ifndef DDI_VENDOR_LSI
1687 #define DDI_VENDOR_LSI "LSI"
1688 #endif /* DDI_VENDOR_LSI */
1689
1690 #ifndef KMDB_MODULE
1691 static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
1692 static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t);
1693 #ifdef __sparc
1694 static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t);
1695 #else /* __sparc */
1696 static int mrsas_quiesce(dev_info_t *);
1697 #endif /* __sparc */
1698 static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t);
1699 static int mrsas_open(dev_t *, int, int, cred_t *);
1700 static int mrsas_close(dev_t, int, int, cred_t *);
1701 static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
1702
1703 static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *,
1704 scsi_hba_tran_t *, struct scsi_device *);
1705 static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register
1706 struct scsi_pkt *, struct buf *, int, int, int, int,
1707 int (*)(), caddr_t);
1708 static int mrsas_tran_start(struct scsi_address *,
1709 register struct scsi_pkt *);
1710 static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *);
1711 static int mrsas_tran_reset(struct scsi_address *, int);
1712 static int mrsas_tran_getcap(struct scsi_address *, char *, int);
1713 static int mrsas_tran_setcap(struct scsi_address *, char *, int, int);
1714 static void mrsas_tran_destroy_pkt(struct scsi_address *,
1715 struct scsi_pkt *);
1716 static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *);
1717 static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *);
1718 static uint_t mrsas_isr();
1719 static uint_t mrsas_softintr();
1720
1721 static int init_mfi(struct mrsas_instance *);
1722 static int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
1723 static int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
1724 uchar_t);
1725 static struct mrsas_cmd *get_mfi_pkt(struct mrsas_instance *);
1726 static void return_mfi_pkt(struct mrsas_instance *,
1727 struct mrsas_cmd *);
1728
1729 static void free_space_for_mfi(struct mrsas_instance *);
1730 static void free_additional_dma_buffer(struct mrsas_instance *);
1731 static int alloc_additional_dma_buffer(struct mrsas_instance *);
1732 static int read_fw_status_reg_ppc(struct mrsas_instance *);
1733 static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *);
1734 static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *,
1735 struct mrsas_cmd *);
1736 static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *,
1737 struct mrsas_cmd *);
1738 static void enable_intr_ppc(struct mrsas_instance *);
1739 static void disable_intr_ppc(struct mrsas_instance *);
1740 static int intr_ack_ppc(struct mrsas_instance *);
1741 static int mfi_state_transition_to_ready(struct mrsas_instance *);
1742 static void destroy_mfi_frame_pool(struct mrsas_instance *);
1743 static int create_mfi_frame_pool(struct mrsas_instance *);
1744 static int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
1745 struct buf *, int, int (*)());
1746 static int mrsas_dma_move(struct mrsas_instance *,
1747 struct scsi_pkt *, struct buf *);
1748 static void flush_cache(struct mrsas_instance *instance);
1749 static void display_scsi_inquiry(caddr_t);
1750 static int start_mfi_aen(struct mrsas_instance *instance);
1751 static int handle_drv_ioctl(struct mrsas_instance *instance,
1752 struct mrsas_ioctl *ioctl, int mode);
1753 static int handle_mfi_ioctl(struct mrsas_instance *instance,
1754 struct mrsas_ioctl *ioctl, int mode);
1755 static int handle_mfi_aen(struct mrsas_instance *instance,
1756 struct mrsas_aen *aen);
1757 static void fill_up_drv_ver(struct mrsas_drv_ver *dv);
1758 static struct mrsas_cmd *build_cmd(struct mrsas_instance *instance,
1759 struct scsi_address *ap, struct scsi_pkt *pkt,
1760 uchar_t *cmd_done);
1761 #ifndef __sparc
1762 static int wait_for_outstanding(struct mrsas_instance *instance);
1763 #endif /* __sparc */
1764 static int register_mfi_aen(struct mrsas_instance *instance,
1765 uint32_t seq_num, uint32_t class_locale_word);
1766 static int issue_mfi_pthru(struct mrsas_instance *instance, struct
1767 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1768 static int issue_mfi_dcmd(struct mrsas_instance *instance, struct
1769 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1770 static int issue_mfi_smp(struct mrsas_instance *instance, struct
1771 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1772 static int issue_mfi_stp(struct mrsas_instance *instance, struct
1773 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1774 static int abort_aen_cmd(struct mrsas_instance *instance,
1775 struct mrsas_cmd *cmd_to_abort);
1776
1777 static int mrsas_common_check(struct mrsas_instance *instance,
1778 struct mrsas_cmd *cmd);
1779 static void mrsas_fm_init(struct mrsas_instance *instance);
1780 static void mrsas_fm_fini(struct mrsas_instance *instance);
1781 static int mrsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *,
1782 const void *);
1783 static void mrsas_fm_ereport(struct mrsas_instance *instance,
1784 char *detail);
1785 static int mrsas_check_dma_handle(ddi_dma_handle_t handle);
1786 static int mrsas_check_acc_handle(ddi_acc_handle_t handle);
1787
1788 static void mrsas_rem_intrs(struct mrsas_instance *instance);
1789 static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type);
1790
1791 static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *,
1792 scsi_hba_tran_t *, struct scsi_device *);
1793 static int mrsas_tran_bus_config(dev_info_t *, uint_t,
1794 ddi_bus_config_op_t, void *, dev_info_t **);
1795 static int mrsas_parse_devname(char *, int *, int *);
1796 static int mrsas_config_all_devices(struct mrsas_instance *);
1797 static int mrsas_config_scsi_device(struct mrsas_instance *,
1798 struct scsi_device *, dev_info_t **);
1799 static int mrsas_config_ld(struct mrsas_instance *, uint16_t,
1800 uint8_t, dev_info_t **);
1801 static dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t,
1802 uint8_t);
1803 static int mrsas_name_node(dev_info_t *, char *, int);
1804 static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *);
1805 static int mrsas_service_evt(struct mrsas_instance *, int, int, int,
1806 uint64_t);
1807 static int mrsas_mode_sense_build(struct scsi_pkt *);
1808 static void push_pending_mfi_pkt(struct mrsas_instance *,
1809 struct mrsas_cmd *);
1810 static int mrsas_issue_init_mfi(struct mrsas_instance *);
1811 static int mrsas_issue_pending_cmds(struct mrsas_instance *);
1812 static int mrsas_print_pending_cmds(struct mrsas_instance *);
1813 static int mrsas_complete_pending_cmds(struct mrsas_instance *);
1814 static int mrsas_reset_ppc(struct mrsas_instance *);
1815 static uint32_t mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *);
1816 static int mrsas_kill_adapter(struct mrsas_instance *);
1817 static void io_timeout_checker(void *instance);
1818 static void complete_cmd_in_sync_mode(struct mrsas_instance *,
1819 struct mrsas_cmd *);
1820
1821 #endif /* KMDB_MODULE */
1822
1823
1824 #ifdef __cplusplus
1825 }
1826 #endif
1827
1828 #endif /* _MR_SAS_H_ */
|
1 /*
2 * mr_sas.h: header for mr_sas
3 *
4 * Solaris MegaRAID driver for SAS2.0 controllers
5 * Copyright (c) 2008-2012, LSI Logic Corporation.
6 * All rights reserved.
7 *
8 * Version:
9 * Author:
10 * Swaminathan K S
11 * Arun Chandrashekhar
12 * Manju R
13 * Rasheed
14 * Shakeel Bukhari
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions are met:
18 *
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 *
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 *
26 * 3. Neither the name of the author nor the names of its contributors may be
27 * used to endorse or promote products derived from this software without
28 * specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41 * DAMAGE.
42 */
43
44 /*
45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
46 */
47
48 #ifndef _MR_SAS_H_
49 #define _MR_SAS_H_
50
51 #ifdef __cplusplus
52 extern "C" {
53 #endif
54
55 #include <sys/scsi/scsi.h>
56 #include "mr_sas_list.h"
57 #include "ld_pd_map.h"
58
59 /*
60 * MegaRAID SAS2.0 Driver meta data
61 */
62 #define MRSAS_VERSION "6.503.00.00ILLUMOS"
63 #define MRSAS_RELDATE "July 30, 2012"
64
65 #define MRSAS_TRUE 1
66 #define MRSAS_FALSE 0
67
68 #define ADAPTER_RESET_NOT_REQUIRED 0
69 #define ADAPTER_RESET_REQUIRED 1
70
71 #define PDSUPPORT 1
72
73 /*
74 * MegaRAID SAS2.0 device id conversion definitions.
75 */
76 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT)
77 #define MRSAS_GET_BOUNDARY_ALIGNED_LEN(len, new_len, boundary_len) { \
78 int rem; \
79 rem = (len / boundary_len); \
80 if ((rem * boundary_len) != len) { \
81 new_len = len + ((rem + 1) * boundary_len - len); \
82 } else { \
83 new_len = len; \
84 } \
85 }
86
87
88 /*
89 * MegaRAID SAS2.0 supported controllers
90 */
91 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078
92 #define PCI_DEVICE_ID_LSI_2108V 0x0079
93 #define PCI_DEVICE_ID_LSI_TBOLT 0x005b
94 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
95
96 /*
97 * Register Index for 2108 Controllers.
98 */
99 #define REGISTER_SET_IO_2108 (2)
100
101 #define MRSAS_MAX_SGE_CNT 0x50
102 #define MRSAS_APP_RESERVED_CMDS 32
103
104 #define MRSAS_IOCTL_DRIVER 0x12341234
105 #define MRSAS_IOCTL_FIRMWARE 0x12345678
106 #define MRSAS_IOCTL_AEN 0x87654321
107
108 #define MRSAS_1_SECOND 1000000
109
110 #ifdef PDSUPPORT
111
112 #define UNCONFIGURED_GOOD 0x0
113 #define PD_SYSTEM 0x40
114 #define MR_EVT_PD_STATE_CHANGE 0x0072
115 #define MR_EVT_PD_REMOVED_EXT 0x00f8
116 #define MR_EVT_PD_INSERTED_EXT 0x00f7
117 #define MR_DCMD_PD_GET_INFO 0x02020000
118 #define MRSAS_TBOLT_PD_LUN 1
119 #define MRSAS_TBOLT_PD_TGT_MAX 255
120 #define MRSAS_TBOLT_GET_PD_MAX(s) ((s)->mr_tbolt_pd_max)
121
122 #endif
123
124 /* Raid Context Flags */
125 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
126 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
127 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
128 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
129 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1
130 } MR_RAID_FLAGS_IO_SUB_TYPE;
131
132 /* Dynamic Enumeration Flags */
133 #define MRSAS_LD_LUN 0
134 #define WWN_STRLEN 17
135 #define LD_SYNC_BIT 1
136 #define LD_SYNC_SHIFT 14
137 /* ThunderBolt (TB) specific */
138 #define MRSAS_THUNDERBOLT_MSG_SIZE 256
139 #define MRSAS_THUNDERBOLT_MAX_COMMANDS 1024
140 #define MRSAS_THUNDERBOLT_MAX_REPLY_COUNT 1024
141 #define MRSAS_THUNDERBOLT_REPLY_SIZE 8
142 #define MRSAS_THUNDERBOLT_MAX_CHAIN_COUNT 1
143
144 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
145 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1
146
147 #define MR_EVT_LD_FAST_PATH_IO_STATUS_CHANGED (0xFFFF)
148
149 #define MR_INTERNAL_MFI_FRAMES_SMID 1
150 #define MR_CTRL_EVENT_WAIT_SMID 2
151 #define MR_INTERNAL_DRIVER_RESET_SMID 3
152
153
154 /*
155 * =====================================
156 * MegaRAID SAS2.0 MFI firmware definitions
157 * =====================================
158 */
159 /*
160 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for
161 * protocol between the software and firmware. Commands are issued using
162 * "message frames"
163 */
164
165 /*
166 * FW posts its state in upper 4 bits of outbound_msg_0 register
167 */
168 #define MFI_STATE_MASK 0xF0000000
169 #define MFI_STATE_UNDEFINED 0x00000000
170 #define MFI_STATE_BB_INIT 0x10000000
171 #define MFI_STATE_FW_INIT 0x40000000
172 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
173 #define MFI_STATE_FW_INIT_2 0x70000000
174 #define MFI_STATE_DEVICE_SCAN 0x80000000
175 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
176 #define MFI_STATE_FLUSH_CACHE 0xA0000000
177 #define MFI_STATE_READY 0xB0000000
178 #define MFI_STATE_OPERATIONAL 0xC0000000
179 #define MFI_STATE_FAULT 0xF0000000
180
181 #define MRMFI_FRAME_SIZE 64
182
183 /*
184 * During FW init, clear pending cmds & reset state using inbound_msg_0
185 *
186 * ABORT : Abort all pending cmds
187 * READY : Move from OPERATIONAL to READY state; discard queue info
188 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
189 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
190 */
191 #define MFI_INIT_ABORT 0x00000001
192 #define MFI_INIT_READY 0x00000002
193 #define MFI_INIT_MFIMODE 0x00000004
194 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
195 #define MFI_INIT_HOTPLUG 0x00000010
196 #define MFI_STOP_ADP 0x00000020
197 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
198
199 /*
226 #define MFI_CMD_OP_LD_SCSI 0x03
227 #define MFI_CMD_OP_PD_SCSI 0x04
228 #define MFI_CMD_OP_DCMD 0x05
229 #define MFI_CMD_OP_ABORT 0x06
230 #define MFI_CMD_OP_SMP 0x07
231 #define MFI_CMD_OP_STP 0x08
232
233 #define MR_DCMD_CTRL_GET_INFO 0x01010000
234
235 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
236 #define MR_FLUSH_CTRL_CACHE 0x01
237 #define MR_FLUSH_DISK_CACHE 0x02
238
239 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
240 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01
241
242 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
243 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
244 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
245 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
246
247 /*
248 * Solaris Specific MAX values
249 */
250 #define MAX_SGL 24
251
252 /*
253 * MFI command completion codes
254 */
255 enum MFI_STAT {
256 MFI_STAT_OK = 0x00,
257 MFI_STAT_INVALID_CMD = 0x01,
258 MFI_STAT_INVALID_DCMD = 0x02,
259 MFI_STAT_INVALID_PARAMETER = 0x03,
260 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
261 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
262 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
263 MFI_STAT_APP_IN_USE = 0x07,
264 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
265 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
266 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
267 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
268 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
269 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
270 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
271 MFI_STAT_FLASH_BUSY = 0x0f,
288 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
289 MFI_STAT_MFC_HW_ERROR = 0x21,
290 MFI_STAT_NO_HW_PRESENT = 0x22,
291 MFI_STAT_NOT_FOUND = 0x23,
292 MFI_STAT_NOT_IN_ENCL = 0x24,
293 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
294 MFI_STAT_PD_TYPE_WRONG = 0x26,
295 MFI_STAT_PR_DISABLED = 0x27,
296 MFI_STAT_ROW_INDEX_INVALID = 0x28,
297 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
298 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
299 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
300 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
301 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
302 MFI_STAT_SCSI_IO_FAILED = 0x2e,
303 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
304 MFI_STAT_SHUTDOWN_FAILED = 0x30,
305 MFI_STAT_TIME_NOT_SET = 0x31,
306 MFI_STAT_WRONG_STATE = 0x32,
307 MFI_STAT_LD_OFFLINE = 0x33,
308 MFI_STAT_INVALID_STATUS = 0xFF
309 };
310
311 enum MR_EVT_CLASS {
312 MR_EVT_CLASS_DEBUG = -2,
313 MR_EVT_CLASS_PROGRESS = -1,
314 MR_EVT_CLASS_INFO = 0,
315 MR_EVT_CLASS_WARNING = 1,
316 MR_EVT_CLASS_CRITICAL = 2,
317 MR_EVT_CLASS_FATAL = 3,
318 MR_EVT_CLASS_DEAD = 4
319 };
320
321 enum MR_EVT_LOCALE {
322 MR_EVT_LOCALE_LD = 0x0001,
323 MR_EVT_LOCALE_PD = 0x0002,
324 MR_EVT_LOCALE_ENCL = 0x0004,
325 MR_EVT_LOCALE_BBU = 0x0008,
326 MR_EVT_LOCALE_SAS = 0x0010,
327 MR_EVT_LOCALE_CTRL = 0x0020,
328 MR_EVT_LOCALE_CONFIG = 0x0040,
329 MR_EVT_LOCALE_CLUSTER = 0x0080,
330 MR_EVT_LOCALE_ALL = 0xffff
331 };
332
333 enum MR_EVT_ARGS {
334 MR_EVT_ARGS_NONE,
335 MR_EVT_ARGS_CDB_SENSE,
336 MR_EVT_ARGS_LD,
337 MR_EVT_ARGS_LD_COUNT,
338 MR_EVT_ARGS_LD_LBA,
339 MR_EVT_ARGS_LD_OWNER,
340 MR_EVT_ARGS_LD_LBA_PD_LBA,
341 MR_EVT_ARGS_LD_PROG,
342 MR_EVT_ARGS_LD_STATE,
343 MR_EVT_ARGS_LD_STRIP,
344 MR_EVT_ARGS_PD,
345 MR_EVT_ARGS_PD_ERR,
346 MR_EVT_ARGS_PD_LBA,
347 MR_EVT_ARGS_PD_LBA_LD,
348 MR_EVT_ARGS_PD_PROG,
349 MR_EVT_ARGS_PD_STATE,
350 MR_EVT_ARGS_PCI,
351 MR_EVT_ARGS_RATE,
352 MR_EVT_ARGS_STR,
353 MR_EVT_ARGS_TIME,
354 MR_EVT_ARGS_ECC
355 };
356
357 #define MR_EVT_CFG_CLEARED 0x0004
358 #define MR_EVT_LD_CREATED 0x008a
359 #define MR_EVT_LD_DELETED 0x008b
360 #define MR_EVT_CFG_FP_CHANGE 0x017B
361
362 enum LD_STATE {
363 LD_OFFLINE = 0,
364 LD_PARTIALLY_DEGRADED = 1,
365 LD_DEGRADED = 2,
366 LD_OPTIMAL = 3,
367 LD_INVALID = 0xFF
368 };
369
370 enum MRSAS_EVT {
371 MRSAS_EVT_CONFIG_TGT = 0,
372 MRSAS_EVT_UNCONFIG_TGT = 1,
373 MRSAS_EVT_UNCONFIG_SMP = 2
374 };
375
376 #define DMA_OBJ_ALLOCATED 1
377 #define DMA_OBJ_REALLOCATED 2
378 #define DMA_OBJ_FREED 3
379
380 /*
381 * dma_obj_t - Our DMA object
382 * @param buffer : kernel virtual address
383 * @param size : size of the data to be allocated
384 * @param acc_handle : access handle
385 * @param dma_handle : dma handle
386 * @param dma_cookie : scatter-gather list
387 * @param dma_attr : dma attributes for this buffer
388 *
389 * Our DMA object. The caller must initialize the size and dma attributes
390 * (dma_attr) fields before allocating the resources.
391 */
392 typedef struct {
393 caddr_t buffer;
394 uint32_t size;
395 ddi_acc_handle_t acc_handle;
396 ddi_dma_handle_t dma_handle;
397 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT];
398 ddi_dma_attr_t dma_attr;
399 uint8_t status;
400 uint8_t reserved[3];
401 } dma_obj_t;
402
403 struct mrsas_eventinfo {
404 struct mrsas_instance *instance;
405 int tgt;
406 int lun;
407 int event;
408 uint64_t wwn;
409 };
410
411 struct mrsas_ld {
412 dev_info_t *dip;
413 uint8_t lun_type;
414 uint8_t flag;
415 uint8_t reserved[2];
416 };
417
418
419 #ifdef PDSUPPORT
420 struct mrsas_tbolt_pd {
421 dev_info_t *dip;
422 uint8_t lun_type;
423 uint8_t dev_id;
424 uint8_t flag;
425 uint8_t reserved;
426 };
427 struct mrsas_tbolt_pd_info {
428 uint16_t deviceId;
429 uint16_t seqNum;
430 uint8_t inquiryData[96];
431 uint8_t vpdPage83[64];
432 uint8_t notSupported;
433 uint8_t scsiDevType;
434 uint8_t a;
435 uint8_t device_speed;
436 uint32_t mediaerrcnt;
437 uint32_t other;
438 uint32_t pred;
439 uint32_t lastpred;
440 uint16_t fwState;
441 uint8_t disabled;
442 uint8_t linkspwwd;
443 uint32_t ddfType;
444 struct {
445 uint8_t count;
446 uint8_t isPathBroken;
447 uint8_t connectorIndex[2];
448 uint8_t reserved[4];
449 uint64_t sasAddr[2];
450 uint8_t reserved2[16];
451 } pathInfo;
452 };
453 #endif
454
455 typedef struct mrsas_instance {
456 uint32_t *producer;
457 uint32_t *consumer;
458
459 uint32_t *reply_queue;
460 dma_obj_t mfi_internal_dma_obj;
461 uint16_t adapterresetinprogress;
462 uint16_t deadadapter;
463 /* ThunderBolt (TB) specific */
464 dma_obj_t mpi2_frame_pool_dma_obj;
465 dma_obj_t request_desc_dma_obj;
466 dma_obj_t reply_desc_dma_obj;
467 dma_obj_t ld_map_obj[2];
468
469 uint8_t init_id;
470 uint8_t flag_ieee;
471 uint8_t disable_online_ctrl_reset;
472 uint8_t fw_fault_count_after_ocr;
473
474 uint16_t max_num_sge;
475 uint16_t max_fw_cmds;
476 uint32_t max_sectors_per_req;
477
478 struct mrsas_cmd **cmd_list;
479
480 mlist_t cmd_pool_list;
481 kmutex_t cmd_pool_mtx;
482 kmutex_t sync_map_mtx;
483
484 mlist_t app_cmd_pool_list;
485 kmutex_t app_cmd_pool_mtx;
486 mlist_t cmd_app_pool_list;
487 kmutex_t cmd_app_pool_mtx;
488
489
490 mlist_t cmd_pend_list;
491 kmutex_t cmd_pend_mtx;
492
493 dma_obj_t mfi_evt_detail_obj;
494 struct mrsas_cmd *aen_cmd;
495
496 uint32_t aen_seq_num;
497 uint32_t aen_class_locale_word;
498
499 scsi_hba_tran_t *tran;
500
501 kcondvar_t int_cmd_cv;
502 kmutex_t int_cmd_mtx;
503
504 kcondvar_t aen_cmd_cv;
505 kmutex_t aen_cmd_mtx;
506
507 kcondvar_t abort_cmd_cv;
508 kmutex_t abort_cmd_mtx;
509
510 kmutex_t reg_write_mtx;
511 kmutex_t chip_mtx;
512
513 dev_info_t *dip;
514 ddi_acc_handle_t pci_handle;
515
516 timeout_id_t timeout_id;
517 uint32_t unique_id;
518 uint16_t fw_outstanding;
519 caddr_t regmap;
520 ddi_acc_handle_t regmap_handle;
521 uint8_t isr_level;
522 ddi_iblock_cookie_t iblock_cookie;
523 ddi_iblock_cookie_t soft_iblock_cookie;
524 ddi_softintr_t soft_intr_id;
525 uint8_t softint_running;
526 uint8_t tbolt_softint_running;
527 kmutex_t completed_pool_mtx;
528 mlist_t completed_pool_list;
529
530 caddr_t internal_buf;
531 uint32_t internal_buf_dmac_add;
532 uint32_t internal_buf_size;
533
534 uint16_t vendor_id;
535 uint16_t device_id;
536 uint16_t subsysvid;
537 uint16_t subsysid;
538 int instance;
539 int baseaddress;
540 char iocnode[16];
541
542 int fm_capabilities;
543 /*
544 * Driver resources unroll flags. The flag is set for resources that
545 * are needed to be free'd at detach() time.
546 */
547 struct _unroll {
548 uint8_t softs; /* The software state was allocated. */
549 uint8_t regs; /* Controller registers mapped. */
550 uint8_t intr; /* Interrupt handler added. */
551 uint8_t reqs; /* Request structs allocated. */
552 uint8_t mutexs; /* Mutex's allocated. */
553 uint8_t taskq; /* Task q's created. */
554 uint8_t tran; /* Tran struct allocated */
555 uint8_t tranSetup; /* Tran attached to the ddi. */
556 uint8_t devctl; /* Device nodes for cfgadm created. */
557 uint8_t scsictl; /* Device nodes for cfgadm created. */
558 uint8_t ioctl; /* Device nodes for ioctl's created. */
559 uint8_t timer; /* Timer started. */
560 uint8_t aenPend; /* AEN cmd pending f/w. */
561 uint8_t mapUpdate_pend; /* LD MAP update cmd pending f/w. */
562 uint8_t soft_isr; /* Soft interrupt handler allocated. */
563 uint8_t ldlist_buff; /* Logical disk list allocated. */
564 uint8_t pdlist_buff; /* Physical disk list allocated. */
565 uint8_t syncCmd; /* Sync map command allocated. */
566 uint8_t verBuff; /* 2108 MFI buffer allocated. */
567 uint8_t alloc_space_mfi; /* Allocated space for 2108 MFI. */
568 uint8_t alloc_space_mpi2; /* Allocated space for 2208 MPI2. */
569 } unroll;
570
571
572 /* function template pointer */
573 struct mrsas_function_template *func_ptr;
574
575
576 /* MSI interrupts specific */
577 ddi_intr_handle_t *intr_htable; /* Interrupt handle array */
578 size_t intr_htable_size; /* Int. handle array size */
579 int intr_type;
580 int intr_cnt;
581 uint_t intr_pri;
582 int intr_cap;
583
584 ddi_taskq_t *taskq;
585 struct mrsas_ld *mr_ld_list;
586 kmutex_t config_dev_mtx;
587 /* ThunderBolt (TB) specific */
588 ddi_softintr_t tbolt_soft_intr_id;
589
590 #ifdef PDSUPPORT
591 uint32_t mr_tbolt_pd_max;
592 struct mrsas_tbolt_pd *mr_tbolt_pd_list;
593 #endif
594
595 uint8_t fast_path_io;
596
597 uint16_t tbolt;
598 uint16_t reply_read_index;
599 uint16_t reply_size; /* Single Reply struct size */
600 uint16_t raid_io_msg_size; /* Single message size */
601 uint32_t io_request_frames_phy;
602 uint8_t *io_request_frames;
603 /* Virtual address of request desc frame pool */
604 MRSAS_REQUEST_DESCRIPTOR_UNION *request_message_pool;
605 /* Physical address of request desc frame pool */
606 uint32_t request_message_pool_phy;
607 /* Virtual address of reply Frame */
608 MPI2_REPLY_DESCRIPTORS_UNION *reply_frame_pool;
609 /* Physical address of reply Frame */
610 uint32_t reply_frame_pool_phy;
611 uint8_t *reply_pool_limit; /* Last reply frame address */
612 /* Physical address of Last reply frame */
613 uint32_t reply_pool_limit_phy;
614 uint32_t reply_q_depth; /* Reply Queue Depth */
615 uint8_t max_sge_in_main_msg;
616 uint8_t max_sge_in_chain;
617 uint8_t chain_offset_io_req;
618 uint8_t chain_offset_mpt_msg;
619 MR_FW_RAID_MAP_ALL *ld_map[2];
620 uint32_t ld_map_phy[2];
621 uint32_t size_map_info;
622 uint64_t map_id;
623 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
624 struct mrsas_cmd *map_update_cmd;
625 uint32_t SyncRequired;
626 kmutex_t ocr_flags_mtx;
627 dma_obj_t drv_ver_dma_obj;
628 } mrsas_t;
629
630
631 /*
632 * Function templates for various controller specific functions
633 */
634 struct mrsas_function_template {
635 uint32_t (*read_fw_status_reg)(struct mrsas_instance *);
636 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *);
637 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
638 struct mrsas_cmd *);
639 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
640 struct mrsas_cmd *);
641 void (*enable_intr)(struct mrsas_instance *);
642 void (*disable_intr)(struct mrsas_instance *);
643 int (*intr_ack)(struct mrsas_instance *);
644 int (*init_adapter)(struct mrsas_instance *);
645 /* int (*reset_adapter)(struct mrsas_instance *); */
646 };
647
648 /*
649 * ### Helper routines ###
650 */
651
652 /*
653 * con_log() - console log routine
654 * @param level : indicates the severity of the message.
655 * @fparam mt : format string
656 *
657 * con_log displays the error messages on the console based on the current
658 * debug level. Also it attaches the appropriate kernel severity level with
659 * the message.
660 *
661 *
662 * console messages debug levels
663 */
664 #define CL_NONE 0 /* No debug information */
665 #define CL_ANN 1 /* print unconditionally, announcements */
666 #define CL_ANN1 2 /* No-op */
667 #define CL_DLEVEL1 3 /* debug level 1, informative */
668 #define CL_DLEVEL2 4 /* debug level 2, verbose */
669 #define CL_DLEVEL3 5 /* debug level 3, very verbose */
670
671 #ifdef __SUNPRO_C
672 #define __func__ ""
673 #endif
674
675 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
676
677 /*
678 * ### SCSA definitions ###
679 */
680 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target)
681 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun)
682 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran)
683 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
684
685 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private)
686 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap))
687
688 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private)
689 #define CMD2PKT(sp) ((sp)->cmd_pkt)
690 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request))
710 #define SCP2HOST(scp) (scp)->device->host /* to host */
711 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */
712 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */
713 #define SCP2TARGET(scp) (scp)->device->id /* to target */
714 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */
715
716 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
717 #define SCP2ADAPTER(scp) \
718 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
719
720 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \
721 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0
722 #define MRDRV_IS_LOGICAL(ap) \
723 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0
724 #define MAP_DEVICE_ID(instance, ap) \
725 (ap->a_target)
726
727 #define HIGH_LEVEL_INTR 1
728 #define NORMAL_LEVEL_INTR 0
729
730 #define IO_TIMEOUT_VAL 0
731 #define IO_RETRY_COUNT 3
732 #define MAX_FW_RESET_COUNT 3
733 /*
734 * scsa_cmd - Per-command mr private data
735 * @param cmd_dmahandle : dma handle
736 * @param cmd_dmacookies : current dma cookies
737 * @param cmd_pkt : scsi_pkt reference
738 * @param cmd_dmacount : dma count
739 * @param cmd_cookie : next cookie
740 * @param cmd_ncookies : cookies per window
741 * @param cmd_cookiecnt : cookies per sub-win
742 * @param cmd_nwin : number of dma windows
743 * @param cmd_curwin : current dma window
744 * @param cmd_dma_offset : current window offset
745 * @param cmd_dma_len : current window length
746 * @param cmd_flags : private flags
747 * @param cmd_cdblen : length of cdb
748 * @param cmd_scblen : length of scb
749 * @param cmd_buf : command buffer
750 * @param channel : channel for scsi sub-system
751 * @param target : target for scsi sub-system
752 * @param lun : LUN for scsi sub-system
761 ulong_t cmd_dmacount;
762 uint_t cmd_cookie;
763 uint_t cmd_ncookies;
764 uint_t cmd_cookiecnt;
765 uint_t cmd_nwin;
766 uint_t cmd_curwin;
767 off_t cmd_dma_offset;
768 ulong_t cmd_dma_len;
769 ulong_t cmd_flags;
770 uint_t cmd_cdblen;
771 uint_t cmd_scblen;
772 struct buf *cmd_buf;
773 ushort_t device_id;
774 uchar_t islogical;
775 uchar_t lun;
776 struct mrsas_device *mrsas_dev;
777 };
778
779
780 struct mrsas_cmd {
781 /*
782 * ThunderBolt(TB) We would be needing to have a placeholder
783 * for RAID_MSG_IO_REQUEST inside this structure. We are
784 * supposed to embed the mr_frame inside the RAID_MSG and post
785 * it down to the firmware.
786 */
787 union mrsas_frame *frame;
788 uint32_t frame_phys_addr;
789 uint8_t *sense;
790 uint8_t *sense1;
791 uint32_t sense_phys_addr;
792 uint32_t sense_phys_addr1;
793 dma_obj_t frame_dma_obj;
794 uint8_t frame_dma_obj_status;
795 uint32_t index;
796 uint8_t sync_cmd;
797 uint8_t cmd_status;
798 uint16_t abort_aen;
799 mlist_t list;
800 uint32_t frame_count;
801 struct scsa_cmd *cmd;
802 struct scsi_pkt *pkt;
803 Mpi2RaidSCSIIORequest_t *scsi_io_request;
804 Mpi2SGEIOUnion_t *sgl;
805 uint32_t sgl_phys_addr;
806 uint32_t scsi_io_request_phys_addr;
807 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
808 uint16_t SMID;
809 uint16_t retry_count_for_ocr;
810 uint16_t drv_pkt_time;
811 uint16_t load_balance_flag;
812
813 };
814
815 #define MAX_MGMT_ADAPTERS 1024
816 #define IOC_SIGNATURE "MR-SAS"
817
818 #define IOC_CMD_FIRMWARE 0x0
819 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000
820 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
821 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
822 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300
823
824
825 #define MRSAS_MAX_SENSE_LENGTH 32
826
827 struct mrsas_mgmt_info {
828
829 uint16_t count;
830 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS];
831 uint16_t map[MAX_MGMT_ADAPTERS];
832 int max_index;
833 };
834
835
836 #pragma pack(1)
837 /*
838 * SAS controller properties
839 */
840 struct mrsas_ctrl_prop {
841 uint16_t seq_num;
842 uint16_t pred_fail_poll_interval;
843 uint16_t intr_throttle_count;
844 uint16_t intr_throttle_timeouts;
845
846 uint8_t rebuild_rate;
847 uint8_t patrol_read_rate;
848 uint8_t bgi_rate;
849 uint8_t cc_rate;
850 uint8_t recon_rate;
851
852 uint8_t cache_flush_interval;
853
854 uint8_t spinup_drv_count;
855 uint8_t spinup_delay;
856
857 uint8_t cluster_enable;
858 uint8_t coercion_mode;
859 uint8_t alarm_enable;
860
861 uint8_t reserved_1[13];
862 uint32_t on_off_properties;
863 uint8_t reserved_4[28];
864 };
865
866
867 /*
868 * SAS controller information
869 */
870 struct mrsas_ctrl_info {
871 /* PCI device information */
872 struct {
873 uint16_t vendor_id;
874 uint16_t device_id;
875 uint16_t sub_vendor_id;
876 uint16_t sub_device_id;
877 uint8_t reserved[24];
878 } pci;
879
880 /* Host interface information */
1046 * MegaRAID SAS2.0 driver definitions
1047 * ==================================
1048 */
1049 #define MRDRV_MAX_NUM_CMD 1024
1050
1051 #define MRDRV_MAX_PD_CHANNELS 2
1052 #define MRDRV_MAX_LD_CHANNELS 2
1053 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \
1054 MRDRV_MAX_LD_CHANNELS)
1055 #define MRDRV_MAX_DEV_PER_CHANNEL 128
1056 #define MRDRV_DEFAULT_INIT_ID -1
1057 #define MRDRV_MAX_CMD_PER_LUN 1000
1058 #define MRDRV_MAX_LUN 1
1059 #define MRDRV_MAX_LD 64
1060
1061 #define MRDRV_RESET_WAIT_TIME 300
1062 #define MRDRV_RESET_NOTICE_INTERVAL 5
1063
1064 #define MRSAS_IOCTL_CMD 0
1065
1066 #define MRDRV_TGT_VALID 1
1067
1068 /*
1069 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1070 * SGLs based on the size of dma_addr_t
1071 */
1072 #define IS_DMA64 (sizeof (dma_addr_t) == 8)
1073
1074 #define RESERVED0_REGISTER 0x00 /* XScale */
1075 #define IB_MSG_0_OFF 0x10 /* XScale */
1076 #define OB_MSG_0_OFF 0x18 /* XScale */
1077 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */
1078 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */
1079 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */
1080 #define IB_QPORT_OFF 0x40 /* XScale & ROC */
1081 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */
1082 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */
1083 #define OB_INTR_MASK 0xFFFFFFFF
1084 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF
1085 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1086 #define OB_SCRATCH_PAD_2_OFF 0xB4
1087 #define WRITE_TBOLT_SEQ_OFF 0x00000004
1088 #define DIAG_TBOLT_RESET_ADAPTER 0x00000004
1089 #define HOST_TBOLT_DIAG_OFF 0x00000008
1090 #define RESET_TBOLT_STATUS_OFF 0x000003C3
1091 #define WRITE_SEQ_OFF 0x000000FC
1092 #define HOST_DIAG_OFF 0x000000F8
1093 #define DIAG_RESET_ADAPTER 0x00000004
1094 #define DIAG_WRITE_ENABLE 0x00000080
1095 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1096
1097 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \
1098 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v))
1099
1100 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \
1101 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF))
1102
1103 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \
1104 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v))
1105
1106 #define IB_LOW_QPORT 0xC0
1107 #define IB_HIGH_QPORT 0xC4
1108 #define OB_DOORBELL_REGISTER 0x9C /* 1078 implementation */
1109
1110 /*
1111 * All MFI register set macros accept mrsas_register_set*
1112 */
1113 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \
1114 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
1115
1116 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \
1117 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
1118
1119 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \
1120 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
1121
1122 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \
1123 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
1124
1125 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \
1126 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
1127
1128 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \
1129 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
1130
1131 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \
1132 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
1133
1134 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \
1135 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
1136
1137 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1138 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
1139
1140 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
1141 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
1142 (v))
1143
1144 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \
1145 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
1146
1147 /* Thunderbolt specific registers */
1148 #define RD_OB_SCRATCH_PAD_2(instance) ddi_get32((instance)->regmap_handle, \
1149 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_2_OFF))
1150
1151 #define WR_TBOLT_IB_WRITE_SEQ(v, instance) \
1152 ddi_put32((instance)->regmap_handle, \
1153 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_TBOLT_SEQ_OFF), (v))
1154
1155 #define RD_TBOLT_HOST_DIAG(instance) ddi_get32((instance)->regmap_handle, \
1156 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF))
1157
1158 #define WR_TBOLT_HOST_DIAG(v, instance) ddi_put32((instance)->regmap_handle, \
1159 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF), (v))
1160
1161 #define RD_TBOLT_RESET_STAT(instance) ddi_get32((instance)->regmap_handle, \
1162 (uint32_t *)((uintptr_t)(instance)->regmap + RESET_TBOLT_STATUS_OFF))
1163
1164
1165 #define WR_MPI2_REPLY_POST_INDEX(v, instance)\
1166 ddi_put32((instance)->regmap_handle,\
1167 (uint32_t *)\
1168 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET),\
1169 (v))
1170
1171
1172 #define RD_MPI2_REPLY_POST_INDEX(instance)\
1173 ddi_get32((instance)->regmap_handle,\
1174 (uint32_t *)\
1175 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET))
1176
1177 #define WR_IB_LOW_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1178 (uint32_t *)((uintptr_t)(instance)->regmap + IB_LOW_QPORT), (v))
1179
1180 #define WR_IB_HIGH_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1181 (uint32_t *)((uintptr_t)(instance)->regmap + IB_HIGH_QPORT), (v))
1182
1183 #define WR_OB_DOORBELL_REGISTER_CLEAR(v, instance)\
1184 ddi_put32((instance)->regmap_handle,\
1185 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_REGISTER), \
1186 (v))
1187
1188 #define WR_RESERVED0_REGISTER(v, instance) ddi_put32((instance)->regmap_handle,\
1189 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER), \
1190 (v))
1191
1192 #define RD_RESERVED0_REGISTER(instance) ddi_get32((instance)->regmap_handle, \
1193 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER))
1194
1195
1196
1197 /*
1198 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
1199 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
1200 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
1201 */
1202 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1203
1204 /*
1205 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also
1206 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
1207 * been set in this flag along with bit 1.
1208 */
1209 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001
1210 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005
1211
1212 /* Fusion interrupt mask */
1213 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008)
1214
1215 #define MFI_POLL_TIMEOUT_SECS 60
1216
1217 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \
1218 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
1219 #define MFI_DISABLE_INTR(instance) \
1220 { \
1221 uint32_t disable = 1; \
1222 uint32_t mask = ddi_get32((instance)->regmap_handle, \
1223 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
1224 mask &= ~disable; \
1225 ddi_put32((instance)->regmap_handle, (uint32_t *) \
1226 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \
1227 }
1228
1229 /* By default, the firmware programs for 8 Kbytes of memory */
1230 #define DEFAULT_MFI_MEM_SZ 8192
1231 #define MINIMUM_MFI_MEM_SZ 4096
1232
1233 /* DCMD Message Frame MAILBOX0-11 */
1234 #define DCMD_MBOX_SZ 12
1235
1236 /*
1237 * on_off_property of mrsas_ctrl_prop
1238 * bit0-9, 11-31 are reserved
1239 */
1240 #define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */
1241
1242 struct mrsas_register_set {
1243 uint32_t reserved_0[4]; /* 0000h */
1244
1245 uint32_t inbound_msg_0; /* 0010h */
1246 uint32_t inbound_msg_1; /* 0014h */
1247 uint32_t outbound_msg_0; /* 0018h */
1248 uint32_t outbound_msg_1; /* 001Ch */
1249
1250 uint32_t inbound_doorbell; /* 0020h */
1251 uint32_t inbound_intr_status; /* 0024h */
1252 uint32_t inbound_intr_mask; /* 0028h */
1253
1254 uint32_t outbound_doorbell; /* 002Ch */
1255 uint32_t outbound_intr_status; /* 0030h */
1256 uint32_t outbound_intr_mask; /* 0034h */
1257
1258 uint32_t reserved_1[2]; /* 0038h */
1259
1260 uint32_t inbound_queue_port; /* 0040h */
1261 uint32_t outbound_queue_port; /* 0044h */
1262
1263 uint32_t reserved_2[22]; /* 0048h */
1264
1265 uint32_t outbound_doorbell_clear; /* 00A0h */
1266
1267 uint32_t reserved_3[3]; /* 00A4h */
1268
1269 uint32_t outbound_scratch_pad; /* 00B0h */
1270
1271 uint32_t reserved_4[3]; /* 00B4h */
1272
1273 uint32_t inbound_low_queue_port; /* 00C0h */
1274
1275 uint32_t inbound_high_queue_port; /* 00C4h */
1276
1277 uint32_t reserved_5; /* 00C8h */
1278 uint32_t index_registers[820]; /* 00CCh */
1279 };
1280
1281 struct mrsas_sge32 {
1282 uint32_t phys_addr;
1283 uint32_t length;
1284 };
1285
1286 struct mrsas_sge64 {
1287 uint64_t phys_addr;
1288 uint32_t length;
1289 };
1290
1291 struct mrsas_sge_ieee {
1292 uint64_t phys_addr;
1293 uint32_t length;
1294 uint32_t flag;
1295 };
1296
1297 union mrsas_sgl {
1298 struct mrsas_sge32 sge32[1];
1299 struct mrsas_sge64 sge64[1];
1300 struct mrsas_sge_ieee sge_ieee[1];
1301 };
1302
1303 struct mrsas_header {
1304 uint8_t cmd; /* 00h */
1305 uint8_t sense_len; /* 01h */
1306 uint8_t cmd_status; /* 02h */
1307 uint8_t scsi_status; /* 03h */
1308
1309 uint8_t target_id; /* 04h */
1310 uint8_t lun; /* 05h */
1311 uint8_t cdb_len; /* 06h */
1312 uint8_t sge_count; /* 07h */
1313
1314 uint32_t context; /* 08h */
1315 uint8_t req_id; /* 0Ch */
1316 uint8_t msgvector; /* 0Dh */
1317 uint16_t pad_0; /* 0Eh */
1318
1319 uint16_t flags; /* 10h */
1320 uint16_t timeout; /* 12h */
1321 uint32_t data_xferlen; /* 14h */
1322 };
1323
1324 union mrsas_sgl_frame {
1325 struct mrsas_sge32 sge32[8];
1326 struct mrsas_sge64 sge64[5];
1327 };
1328
1329 struct mrsas_init_frame {
1330 uint8_t cmd; /* 00h */
1331 uint8_t reserved_0; /* 01h */
1332 uint8_t cmd_status; /* 02h */
1333
1334 uint8_t reserved_1; /* 03h */
1335 uint32_t reserved_2; /* 04h */
1336
1337 uint32_t context; /* 08h */
1338 uint8_t req_id; /* 0Ch */
1339 uint8_t msgvector; /* 0Dh */
1340 uint16_t pad_0; /* 0Eh */
1341
1342 uint16_t flags; /* 10h */
1343 uint16_t reserved_3; /* 12h */
1344 uint32_t data_xfer_len; /* 14h */
1345
1346 uint32_t queue_info_new_phys_addr_lo; /* 18h */
1347 uint32_t queue_info_new_phys_addr_hi; /* 1Ch */
1348 uint32_t queue_info_old_phys_addr_lo; /* 20h */
1349 uint32_t queue_info_old_phys_addr_hi; /* 24h */
1350 uint64_t driverversion; /* 28h */
1351 uint32_t reserved_4[4]; /* 30h */
1352 };
1353
1354 struct mrsas_init_queue_info {
1355 uint32_t init_flags; /* 00h */
1356 uint32_t reply_queue_entries; /* 04h */
1357
1358 uint32_t reply_queue_start_phys_addr_lo; /* 08h */
1359 uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */
1360 uint32_t producer_index_phys_addr_lo; /* 10h */
1361 uint32_t producer_index_phys_addr_hi; /* 14h */
1362 uint32_t consumer_index_phys_addr_lo; /* 18h */
1363 uint32_t consumer_index_phys_addr_hi; /* 1Ch */
1364 };
1365
1366 struct mrsas_io_frame {
1367 uint8_t cmd; /* 00h */
1368 uint8_t sense_len; /* 01h */
1369 uint8_t cmd_status; /* 02h */
1370 uint8_t scsi_status; /* 03h */
1371
1372 uint8_t target_id; /* 04h */
1373 uint8_t access_byte; /* 05h */
1374 uint8_t reserved_0; /* 06h */
1375 uint8_t sge_count; /* 07h */
1376
1377 uint32_t context; /* 08h */
1378 uint8_t req_id; /* 0Ch */
1379 uint8_t msgvector; /* 0Dh */
1380 uint16_t pad_0; /* 0Eh */
1381
1382 uint16_t flags; /* 10h */
1383 uint16_t timeout; /* 12h */
1384 uint32_t lba_count; /* 14h */
1385
1386 uint32_t sense_buf_phys_addr_lo; /* 18h */
1387 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1388
1389 uint32_t start_lba_lo; /* 20h */
1390 uint32_t start_lba_hi; /* 24h */
1391
1392 union mrsas_sgl sgl; /* 28h */
1393 };
1394
1395 struct mrsas_pthru_frame {
1396 uint8_t cmd; /* 00h */
1397 uint8_t sense_len; /* 01h */
1398 uint8_t cmd_status; /* 02h */
1399 uint8_t scsi_status; /* 03h */
1400
1401 uint8_t target_id; /* 04h */
1402 uint8_t lun; /* 05h */
1403 uint8_t cdb_len; /* 06h */
1404 uint8_t sge_count; /* 07h */
1405
1406 uint32_t context; /* 08h */
1407 uint8_t req_id; /* 0Ch */
1408 uint8_t msgvector; /* 0Dh */
1409 uint16_t pad_0; /* 0Eh */
1410
1411 uint16_t flags; /* 10h */
1412 uint16_t timeout; /* 12h */
1413 uint32_t data_xfer_len; /* 14h */
1414
1415 uint32_t sense_buf_phys_addr_lo; /* 18h */
1416 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1417
1418 uint8_t cdb[16]; /* 20h */
1419 union mrsas_sgl sgl; /* 30h */
1420 };
1421
1422 struct mrsas_dcmd_frame {
1423 uint8_t cmd; /* 00h */
1424 uint8_t reserved_0; /* 01h */
1425 uint8_t cmd_status; /* 02h */
1426 uint8_t reserved_1[4]; /* 03h */
1427 uint8_t sge_count; /* 07h */
1428
1429 uint32_t context; /* 08h */
1430 uint8_t req_id; /* 0Ch */
1431 uint8_t msgvector; /* 0Dh */
1432 uint16_t pad_0; /* 0Eh */
1433
1434 uint16_t flags; /* 10h */
1435 uint16_t timeout; /* 12h */
1436
1437 uint32_t data_xfer_len; /* 14h */
1438 uint32_t opcode; /* 18h */
1439
1440 /* uint8_t mbox[DCMD_MBOX_SZ]; */ /* 1Ch */
1441 union { /* 1Ch */
1442 uint8_t b[DCMD_MBOX_SZ];
1443 uint16_t s[6];
1444 uint32_t w[3];
1445 } mbox;
1446
1447 union mrsas_sgl sgl; /* 28h */
1448 };
1449
1450 struct mrsas_abort_frame {
1451 uint8_t cmd; /* 00h */
1452 uint8_t reserved_0; /* 01h */
1453 uint8_t cmd_status; /* 02h */
1454
1455 uint8_t reserved_1; /* 03h */
1456 uint32_t reserved_2; /* 04h */
1457
1458 uint32_t context; /* 08h */
1459 uint8_t req_id; /* 0Ch */
1460 uint8_t msgvector; /* 0Dh */
1461 uint16_t pad_0; /* 0Eh */
1462
1463 uint16_t flags; /* 10h */
1464 uint16_t reserved_3; /* 12h */
1465 uint32_t reserved_4; /* 14h */
1466
1467 uint32_t abort_context; /* 18h */
1468 uint32_t pad_1; /* 1Ch */
1469
1470 uint32_t abort_mfi_phys_addr_lo; /* 20h */
1471 uint32_t abort_mfi_phys_addr_hi; /* 24h */
1472
1473 uint32_t reserved_5[6]; /* 28h */
1474 };
1475
1476 struct mrsas_smp_frame {
1477 uint8_t cmd; /* 00h */
1478 uint8_t reserved_1; /* 01h */
1479 uint8_t cmd_status; /* 02h */
1480 uint8_t connection_status; /* 03h */
1481
1482 uint8_t reserved_2[3]; /* 04h */
1483 uint8_t sge_count; /* 07h */
1484
1485 uint32_t context; /* 08h */
1486 uint8_t req_id; /* 0Ch */
1487 uint8_t msgvector; /* 0Dh */
1488 uint16_t pad_0; /* 0Eh */
1489
1490 uint16_t flags; /* 10h */
1491 uint16_t timeout; /* 12h */
1492
1493 uint32_t data_xfer_len; /* 14h */
1494
1495 uint64_t sas_addr; /* 20h */
1496
1497 union mrsas_sgl sgl[2]; /* 28h */
1498 };
1499
1500 struct mrsas_stp_frame {
1501 uint8_t cmd; /* 00h */
1502 uint8_t reserved_1; /* 01h */
1503 uint8_t cmd_status; /* 02h */
1504 uint8_t connection_status; /* 03h */
1505
1506 uint8_t target_id; /* 04h */
1507 uint8_t reserved_2[2]; /* 04h */
1508 uint8_t sge_count; /* 07h */
1509
1510 uint32_t context; /* 08h */
1511 uint8_t req_id; /* 0Ch */
1512 uint8_t msgvector; /* 0Dh */
1513 uint16_t pad_0; /* 0Eh */
1514
1515 uint16_t flags; /* 10h */
1516 uint16_t timeout; /* 12h */
1517
1518 uint32_t data_xfer_len; /* 14h */
1519
1520 uint16_t fis[10]; /* 28h */
1521 uint32_t stp_flags; /* 3C */
1522 union mrsas_sgl sgl; /* 40 */
1523 };
1524
1525 union mrsas_frame {
1526 struct mrsas_header hdr;
1527 struct mrsas_init_frame init;
1528 struct mrsas_io_frame io;
1529 struct mrsas_pthru_frame pthru;
1530 struct mrsas_dcmd_frame dcmd;
1531 struct mrsas_abort_frame abort;
1532 struct mrsas_smp_frame smp;
1533 struct mrsas_stp_frame stp;
1534
1535 uint8_t raw_bytes[64];
1536 };
1537
1538 typedef struct mrsas_pd_address {
1539 uint16_t device_id;
1540 uint16_t encl_id;
1541
1542 union {
1929
1930 struct mrsas_ioctl {
1931 uint16_t version;
1932 uint16_t controller_id;
1933 uint8_t signature[8];
1934 uint32_t reserved_1;
1935 uint32_t control_code;
1936 uint32_t reserved_2[2];
1937 uint8_t frame[64];
1938 union mrsas_sgl_frame sgl_frame;
1939 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH];
1940 uint8_t data[1];
1941 };
1942
1943 struct mrsas_aen {
1944 uint16_t host_no;
1945 uint16_t cmd_status;
1946 uint32_t seq_num;
1947 uint32_t class_locale_word;
1948 };
1949
1950 #pragma pack()
1951
1952 #ifndef DDI_VENDOR_LSI
1953 #define DDI_VENDOR_LSI "LSI"
1954 #endif /* DDI_VENDOR_LSI */
1955
1956 int mrsas_config_scsi_device(struct mrsas_instance *,
1957 struct scsi_device *, dev_info_t **);
1958
1959 #ifdef PDSUPPORT
1960 int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t,
1961 uint8_t, dev_info_t **);
1962 #endif
1963
1964 dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, uint8_t);
1965 int mrsas_service_evt(struct mrsas_instance *, int, int, int, uint64_t);
1966 void return_raid_msg_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1967 struct mrsas_cmd *get_raid_msg_mfi_pkt(struct mrsas_instance *);
1968 void return_raid_msg_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1969
1970 int alloc_space_for_mpi2(struct mrsas_instance *);
1971 void fill_up_drv_ver(struct mrsas_drv_ver *dv);
1972
1973 int mrsas_issue_init_mpi2(struct mrsas_instance *);
1974 struct scsi_pkt *mrsas_tbolt_tran_init_pkt(struct scsi_address *, register
1975 struct scsi_pkt *, struct buf *, int, int, int, int,
1976 int (*)(), caddr_t);
1977 int mrsas_tbolt_tran_start(struct scsi_address *,
1978 register struct scsi_pkt *);
1979 uint32_t tbolt_read_fw_status_reg(struct mrsas_instance *);
1980 void tbolt_issue_cmd(struct mrsas_cmd *, struct mrsas_instance *);
1981 int tbolt_issue_cmd_in_poll_mode(struct mrsas_instance *,
1982 struct mrsas_cmd *);
1983 int tbolt_issue_cmd_in_sync_mode(struct mrsas_instance *,
1984 struct mrsas_cmd *);
1985 void tbolt_enable_intr(struct mrsas_instance *);
1986 void tbolt_disable_intr(struct mrsas_instance *);
1987 int tbolt_intr_ack(struct mrsas_instance *);
1988 uint_t mr_sas_tbolt_process_outstanding_cmd(struct mrsas_instance *);
1989 uint_t tbolt_softintr();
1990 int mrsas_tbolt_dma(struct mrsas_instance *, uint32_t, int, int (*)());
1991 int mrsas_check_dma_handle(ddi_dma_handle_t handle);
1992 int mrsas_check_acc_handle(ddi_acc_handle_t handle);
1993 int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
1994 struct buf *, int, int (*)());
1995 int mrsas_dma_move(struct mrsas_instance *,
1996 struct scsi_pkt *, struct buf *);
1997 int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
1998 uchar_t);
1999 void mr_sas_tbolt_build_mfi_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2000 int mrsas_dma_alloc_dmd(struct mrsas_instance *, dma_obj_t *);
2001 void tbolt_complete_cmd_in_sync_mode(struct mrsas_instance *,
2002 struct mrsas_cmd *);
2003 int alloc_req_rep_desc(struct mrsas_instance *);
2004 int mrsas_mode_sense_build(struct scsi_pkt *);
2005 void push_pending_mfi_pkt(struct mrsas_instance *,
2006 struct mrsas_cmd *);
2007 int mrsas_issue_pending_cmds(struct mrsas_instance *);
2008 int mrsas_print_pending_cmds(struct mrsas_instance *);
2009 int mrsas_complete_pending_cmds(struct mrsas_instance *);
2010
2011 int create_mfi_frame_pool(struct mrsas_instance *);
2012 void destroy_mfi_frame_pool(struct mrsas_instance *);
2013 int create_mfi_mpi_frame_pool(struct mrsas_instance *);
2014 void destroy_mfi_mpi_frame_pool(struct mrsas_instance *);
2015 int create_mpi2_frame_pool(struct mrsas_instance *);
2016 void destroy_mpi2_frame_pool(struct mrsas_instance *);
2017 int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
2018 void mrsas_tbolt_free_additional_dma_buffer(struct mrsas_instance *);
2019 void free_req_desc_pool(struct mrsas_instance *);
2020 void free_space_for_mpi2(struct mrsas_instance *);
2021 void mrsas_dump_reply_desc(struct mrsas_instance *);
2022 void tbolt_complete_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2023 void display_scsi_inquiry(caddr_t);
2024 void service_mfi_aen(struct mrsas_instance *, struct mrsas_cmd *);
2025 int mrsas_mode_sense_build(struct scsi_pkt *);
2026 int mrsas_tbolt_get_ld_map_info(struct mrsas_instance *);
2027 struct mrsas_cmd *mrsas_tbolt_build_poll_cmd(struct mrsas_instance *,
2028 struct scsi_address *, struct scsi_pkt *, uchar_t *);
2029 int mrsas_tbolt_reset_ppc(struct mrsas_instance *instance);
2030 void mrsas_tbolt_kill_adapter(struct mrsas_instance *instance);
2031 int abort_syncmap_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2032 void mrsas_tbolt_prepare_cdb(struct mrsas_instance *instance, U8 cdb[],
2033 struct IO_REQUEST_INFO *, Mpi2RaidSCSIIORequest_t *, U32);
2034
2035
2036 int mrsas_init_adapter_ppc(struct mrsas_instance *instance);
2037 int mrsas_init_adapter_tbolt(struct mrsas_instance *instance);
2038 int mrsas_init_adapter(struct mrsas_instance *instance);
2039
2040 int mrsas_alloc_cmd_pool(struct mrsas_instance *instance);
2041 void mrsas_free_cmd_pool(struct mrsas_instance *instance);
2042
2043 void mrsas_print_cmd_details(struct mrsas_instance *, struct mrsas_cmd *, int);
2044 struct mrsas_cmd *get_raid_msg_pkt(struct mrsas_instance *);
2045
2046 int mfi_state_transition_to_ready(struct mrsas_instance *);
2047
2048
2049 /* FMA functions. */
2050 int mrsas_common_check(struct mrsas_instance *, struct mrsas_cmd *);
2051 void mrsas_fm_ereport(struct mrsas_instance *, char *);
2052
2053
2054 #ifdef __cplusplus
2055 }
2056 #endif
2057
2058 #endif /* _MR_SAS_H_ */
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