1 /*
2 * mr_sas.h: header for mr_sas
3 *
4 * Solaris MegaRAID driver for SAS2.0 controllers
5 * Copyright (c) 2008-2009, LSI Logic Corporation.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 *
14 * 2. Redistributions in binary form must reproduce the above copyright notice,
15 * this list of conditions and the following disclaimer in the documentation
16 * and/or other materials provided with the distribution.
17 *
18 * 3. Neither the name of the author nor the names of its contributors may be
19 * used to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
33 * DAMAGE.
34 */
35
36 /*
37 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
38 */
39 #ifndef _MR_SAS_H_
40 #define _MR_SAS_H_
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #include <sys/scsi/scsi.h>
47 #include "mr_sas_list.h"
48
49 /*
50 * MegaRAID SAS2.0 Driver meta data
51 */
52 #define MRSAS_VERSION "LSIv2.7"
53 #define MRSAS_RELDATE "Apr 21, 2010"
54
55 #define MRSAS_TRUE 1
56 #define MRSAS_FALSE 0
57
58 #define ADAPTER_RESET_NOT_REQUIRED 0
59 #define ADAPTER_RESET_REQUIRED 1
60
61 /*
62 * MegaRAID SAS2.0 device id conversion definitions.
63 */
64 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT)
65
66 /*
67 * MegaRAID SAS2.0 supported controllers
68 */
69 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078
70 #define PCI_DEVICE_ID_LSI_2108V 0x0079
71
72 /*
73 * Register Index for 2108 Controllers.
74 */
75 #define REGISTER_SET_IO_2108 (2)
76
77 #define MRSAS_MAX_SGE_CNT 0x50
78
79 #define MRSAS_IOCTL_DRIVER 0x12341234
80 #define MRSAS_IOCTL_FIRMWARE 0x12345678
81 #define MRSAS_IOCTL_AEN 0x87654321
82
83 #define MRSAS_1_SECOND 1000000
84
85 /* Dynamic Enumeration Flags */
86 #define MRSAS_PD_LUN 1
87 #define MRSAS_LD_LUN 0
88 #define MRSAS_PD_TGT_MAX 255
89 #define MRSAS_GET_PD_MAX(s) ((s)->mr_pd_max)
90 #define WWN_STRLEN 17
91 #define APP_RESERVE_CMDS 32
92 /*
93 * =====================================
94 * MegaRAID SAS2.0 MFI firmware definitions
95 * =====================================
96 */
97 /*
98 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for
99 * protocol between the software and firmware. Commands are issued using
100 * "message frames"
101 */
102
103 /*
104 * FW posts its state in upper 4 bits of outbound_msg_0 register
105 */
106 #define MFI_STATE_SHIFT 28
107 #define MFI_STATE_MASK ((uint32_t)0xF<<MFI_STATE_SHIFT)
108 #define MFI_STATE_UNDEFINED ((uint32_t)0x0<<MFI_STATE_SHIFT)
109 #define MFI_STATE_BB_INIT ((uint32_t)0x1<<MFI_STATE_SHIFT)
110 #define MFI_STATE_FW_INIT ((uint32_t)0x4<<MFI_STATE_SHIFT)
111 #define MFI_STATE_WAIT_HANDSHAKE ((uint32_t)0x6<<MFI_STATE_SHIFT)
112 #define MFI_STATE_FW_INIT_2 ((uint32_t)0x7<<MFI_STATE_SHIFT)
113 #define MFI_STATE_DEVICE_SCAN ((uint32_t)0x8<<MFI_STATE_SHIFT)
114 #define MFI_STATE_BOOT_MESSAGE_PENDING ((uint32_t)0x9<<MFI_STATE_SHIFT)
115 #define MFI_STATE_FLUSH_CACHE ((uint32_t)0xA<<MFI_STATE_SHIFT)
116 #define MFI_STATE_READY ((uint32_t)0xB<<MFI_STATE_SHIFT)
117 #define MFI_STATE_OPERATIONAL ((uint32_t)0xC<<MFI_STATE_SHIFT)
118 #define MFI_STATE_FAULT ((uint32_t)0xF<<MFI_STATE_SHIFT)
119
120 #define MRMFI_FRAME_SIZE 64
121
122 /*
123 * During FW init, clear pending cmds & reset state using inbound_msg_0
124 *
125 * ABORT : Abort all pending cmds
126 * READY : Move from OPERATIONAL to READY state; discard queue info
127 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
128 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
129 */
130 #define MFI_INIT_ABORT 0x00000001
131 #define MFI_INIT_READY 0x00000002
132 #define MFI_INIT_MFIMODE 0x00000004
133 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
134 #define MFI_INIT_HOTPLUG 0x00000010
135 #define MFI_STOP_ADP 0x00000020
136 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
137
138 /*
139 * MFI frame flags
140 */
141 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
142 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
143 #define MFI_FRAME_SGL32 0x0000
144 #define MFI_FRAME_SGL64 0x0002
145 #define MFI_FRAME_SENSE32 0x0000
146 #define MFI_FRAME_SENSE64 0x0004
147 #define MFI_FRAME_DIR_NONE 0x0000
148 #define MFI_FRAME_DIR_WRITE 0x0008
149 #define MFI_FRAME_DIR_READ 0x0010
150 #define MFI_FRAME_DIR_BOTH 0x0018
151 #define MFI_FRAME_IEEE 0x0020
152
153 /*
154 * Definition for cmd_status
155 */
156 #define MFI_CMD_STATUS_POLL_MODE 0xFF
157 #define MFI_CMD_STATUS_SYNC_MODE 0xFF
158
159 /*
160 * MFI command opcodes
161 */
162 #define MFI_CMD_OP_INIT 0x00
163 #define MFI_CMD_OP_LD_READ 0x01
164 #define MFI_CMD_OP_LD_WRITE 0x02
165 #define MFI_CMD_OP_LD_SCSI 0x03
166 #define MFI_CMD_OP_PD_SCSI 0x04
167 #define MFI_CMD_OP_DCMD 0x05
168 #define MFI_CMD_OP_ABORT 0x06
169 #define MFI_CMD_OP_SMP 0x07
170 #define MFI_CMD_OP_STP 0x08
171
172 #define MR_DCMD_CTRL_GET_INFO 0x01010000
173
174 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
175 #define MR_FLUSH_CTRL_CACHE 0x01
176 #define MR_FLUSH_DISK_CACHE 0x02
177
178 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
179 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01
180
181 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
182 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
183 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
184 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
185 #define MR_DCMD_PD_GET_INFO 0x02020000
186
187 /*
188 * Solaris Specific MAX values
189 */
190 #define MAX_SGL 24
191 /*
192 * MFI command completion codes
193 */
194 enum MFI_STAT {
195 MFI_STAT_OK = 0x00,
196 MFI_STAT_INVALID_CMD = 0x01,
197 MFI_STAT_INVALID_DCMD = 0x02,
198 MFI_STAT_INVALID_PARAMETER = 0x03,
199 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
200 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
201 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
202 MFI_STAT_APP_IN_USE = 0x07,
203 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
204 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
205 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
206 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
207 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
208 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
209 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
210 MFI_STAT_FLASH_BUSY = 0x0f,
211 MFI_STAT_FLASH_ERROR = 0x10,
212 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
213 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
214 MFI_STAT_FLASH_NOT_OPEN = 0x13,
215 MFI_STAT_FLASH_NOT_STARTED = 0x14,
216 MFI_STAT_FLUSH_FAILED = 0x15,
217 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
218 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
219 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
220 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
221 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
222 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
223 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
224 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
225 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
226 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
227 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
228 MFI_STAT_MFC_HW_ERROR = 0x21,
229 MFI_STAT_NO_HW_PRESENT = 0x22,
230 MFI_STAT_NOT_FOUND = 0x23,
231 MFI_STAT_NOT_IN_ENCL = 0x24,
232 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
233 MFI_STAT_PD_TYPE_WRONG = 0x26,
234 MFI_STAT_PR_DISABLED = 0x27,
235 MFI_STAT_ROW_INDEX_INVALID = 0x28,
236 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
237 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
238 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
239 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
240 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
241 MFI_STAT_SCSI_IO_FAILED = 0x2e,
242 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
243 MFI_STAT_SHUTDOWN_FAILED = 0x30,
244 MFI_STAT_TIME_NOT_SET = 0x31,
245 MFI_STAT_WRONG_STATE = 0x32,
246 MFI_STAT_LD_OFFLINE = 0x33,
247 /* UNUSED: 0x34 to 0xfe */
248 MFI_STAT_INVALID_STATUS = 0xFF
249 };
250
251 enum MR_EVT_CLASS {
252 MR_EVT_CLASS_DEBUG = -2,
253 MR_EVT_CLASS_PROGRESS = -1,
254 MR_EVT_CLASS_INFO = 0,
255 MR_EVT_CLASS_WARNING = 1,
256 MR_EVT_CLASS_CRITICAL = 2,
257 MR_EVT_CLASS_FATAL = 3,
258 MR_EVT_CLASS_DEAD = 4
259 };
260
261 enum MR_EVT_LOCALE {
262 MR_EVT_LOCALE_LD = 0x0001,
263 MR_EVT_LOCALE_PD = 0x0002,
264 MR_EVT_LOCALE_ENCL = 0x0004,
265 MR_EVT_LOCALE_BBU = 0x0008,
266 MR_EVT_LOCALE_SAS = 0x0010,
267 MR_EVT_LOCALE_CTRL = 0x0020,
268 MR_EVT_LOCALE_CONFIG = 0x0040,
269 MR_EVT_LOCALE_CLUSTER = 0x0080,
270 MR_EVT_LOCALE_ALL = 0xffff
271 };
272
273 #define MR_EVT_CFG_CLEARED 0x0004
274 #define MR_EVT_LD_CREATED 0x008a
275 #define MR_EVT_LD_DELETED 0x008b
276 #define MR_EVT_PD_REMOVED_EXT 0x00f8
277 #define MR_EVT_PD_INSERTED_EXT 0x00f7
278
279 enum LD_STATE {
280 LD_OFFLINE = 0,
281 LD_PARTIALLY_DEGRADED = 1,
282 LD_DEGRADED = 2,
283 LD_OPTIMAL = 3,
284 LD_INVALID = 0xFF
285 };
286
287 enum MRSAS_EVT {
288 MRSAS_EVT_CONFIG_TGT = 0,
289 MRSAS_EVT_UNCONFIG_TGT = 1,
290 MRSAS_EVT_UNCONFIG_SMP = 2
291 };
292
293 #define DMA_OBJ_ALLOCATED 1
294 #define DMA_OBJ_REALLOCATED 2
295 #define DMA_OBJ_FREED 3
296
297 /*
298 * dma_obj_t - Our DMA object
299 * @param buffer : kernel virtual address
300 * @param size : size of the data to be allocated
301 * @param acc_handle : access handle
302 * @param dma_handle : dma handle
303 * @param dma_cookie : scatter-gather list
304 * @param dma_attr : dma attributes for this buffer
305 * Our DMA object. The caller must initialize the size and dma attributes
306 * (dma_attr) fields before allocating the resources.
307 */
308 typedef struct {
309 caddr_t buffer;
310 uint32_t size;
311 ddi_acc_handle_t acc_handle;
312 ddi_dma_handle_t dma_handle;
313 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT];
314 ddi_dma_attr_t dma_attr;
315 uint8_t status;
316 uint8_t reserved[3];
317 } dma_obj_t;
318
319 struct mrsas_eventinfo {
320 struct mrsas_instance *instance;
321 int tgt;
322 int lun;
323 int event;
324 };
325
326 struct mrsas_ld {
327 dev_info_t *dip;
328 uint8_t lun_type;
329 uint8_t reserved[3];
330 };
331
332 struct mrsas_pd {
333 dev_info_t *dip;
334 uint8_t lun_type;
335 uint8_t dev_id;
336 uint8_t flags;
337 uint8_t reserved;
338 };
339
340 struct mrsas_pd_info {
341 uint16_t deviceId;
342 uint16_t seqNum;
343 uint8_t inquiryData[96];
344 uint8_t vpdPage83[64];
345 uint8_t notSupported;
346 uint8_t scsiDevType;
347 uint8_t a;
348 uint8_t device_speed;
349 uint32_t mediaerrcnt;
350 uint32_t other;
351 uint32_t pred;
352 uint32_t lastpred;
353 uint16_t fwState;
354 uint8_t disabled;
355 uint8_t linkspwwd;
356 uint32_t ddfType;
357 struct {
358 uint8_t count;
359 uint8_t isPathBroken;
360 uint8_t connectorIndex[2];
361 uint8_t reserved[4];
362 uint64_t sasAddr[2];
363 uint8_t reserved2[16];
364 } pathInfo;
365 };
366
367 typedef struct mrsas_instance {
368 uint32_t *producer;
369 uint32_t *consumer;
370
371 uint32_t *reply_queue;
372 dma_obj_t mfi_internal_dma_obj;
373 uint16_t adapterresetinprogress;
374 uint16_t deadadapter;
375 uint8_t init_id;
376 uint8_t flag_ieee;
377 uint8_t disable_online_ctrl_reset;
378 uint8_t fw_fault_count_after_ocr;
379
380 uint16_t max_num_sge;
381 uint16_t max_fw_cmds;
382 uint32_t max_sectors_per_req;
383
384 struct mrsas_cmd **cmd_list;
385 mlist_t cmd_pool_list;
386 kmutex_t cmd_pool_mtx;
387
388 mlist_t app_cmd_pool_list;
389 kmutex_t app_cmd_pool_mtx;
390 mlist_t cmd_pend_list;
391 kmutex_t cmd_pend_mtx;
392
393 dma_obj_t mfi_evt_detail_obj;
394 struct mrsas_cmd *aen_cmd;
395
396 uint32_t aen_seq_num;
397 uint32_t aen_class_locale_word;
398
399 scsi_hba_tran_t *tran;
400
401 kcondvar_t int_cmd_cv;
402 kmutex_t int_cmd_mtx;
403
404 kcondvar_t aen_cmd_cv;
405 kmutex_t aen_cmd_mtx;
406
407 kcondvar_t abort_cmd_cv;
408 kmutex_t abort_cmd_mtx;
409
410 dev_info_t *dip;
411 ddi_acc_handle_t pci_handle;
412
413 timeout_id_t timeout_id;
414 uint32_t unique_id;
415 uint16_t fw_outstanding;
416 caddr_t regmap;
417 ddi_acc_handle_t regmap_handle;
418 uint8_t isr_level;
419 ddi_iblock_cookie_t iblock_cookie;
420 ddi_iblock_cookie_t soft_iblock_cookie;
421 ddi_softintr_t soft_intr_id;
422 uint8_t softint_running;
423 kmutex_t completed_pool_mtx;
424 mlist_t completed_pool_list;
425
426 caddr_t internal_buf;
427 uint32_t internal_buf_dmac_add;
428 uint32_t internal_buf_size;
429
430 uint16_t vendor_id;
431 uint16_t device_id;
432 uint16_t subsysvid;
433 uint16_t subsysid;
434 int instance;
435 int baseaddress;
436 char iocnode[16];
437
438 int fm_capabilities;
439
440 struct mrsas_func_ptr *func_ptr;
441 /* MSI interrupts specific */
442 ddi_intr_handle_t *intr_htable;
443 int intr_type;
444 int intr_cnt;
445 size_t intr_size;
446 uint_t intr_pri;
447 int intr_cap;
448
449 ddi_taskq_t *taskq;
450 struct mrsas_ld *mr_ld_list;
451 kmutex_t ocr_flags_mtx;
452 } mrsas_t;
453
454 struct mrsas_func_ptr {
455 int (*read_fw_status_reg)(struct mrsas_instance *);
456 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *);
457 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
458 struct mrsas_cmd *);
459 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
460 struct mrsas_cmd *);
461 void (*enable_intr)(struct mrsas_instance *);
462 void (*disable_intr)(struct mrsas_instance *);
463 int (*intr_ack)(struct mrsas_instance *);
464 };
465
466 /*
467 * ### Helper routines ###
468 */
469
470 /*
471 * con_log() - console log routine
472 * @param level : indicates the severity of the message.
473 * @fparam mt : format string
474 *
475 * con_log displays the error messages on the console based on the current
476 * debug level. Also it attaches the appropriate kernel severity level with
477 * the message.
478 *
479 *
480 * console messages debug levels
481 */
482 #define CL_NONE 0 /* No debug information */
483 #define CL_TEST_OCR 1
484 #define CL_ANN 2 /* print unconditionally, announcements */
485 #define CL_ANN1 3 /* No o/p */
486 #define CL_DLEVEL1 4 /* debug level 1, informative */
487 #define CL_DLEVEL2 5 /* debug level 2, verbose */
488 #define CL_DLEVEL3 6 /* debug level 3, very verbose */
489
490
491 #ifdef __SUNPRO_C
492 #define __func__ ""
493 #endif
494
495 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
496
497 /*
498 * ### SCSA definitions ###
499 */
500 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target)
501 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun)
502 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran)
503 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
504
505 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private)
506 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap))
507
508 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private)
509 #define CMD2PKT(sp) ((sp)->cmd_pkt)
510 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request))
511
512 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address)
513 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran)
514 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd)))
515
516 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */
517 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */
518 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */
519
520 /*
521 * ### Data structures for ioctl inteface and internal commands ###
522 */
523
524 /*
525 * Data direction flags
526 */
527 #define UIOC_RD 0x00001
528 #define UIOC_WR 0x00002
529
530 #define SCP2HOST(scp) (scp)->device->host /* to host */
531 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */
532 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */
533 #define SCP2TARGET(scp) (scp)->device->id /* to target */
534 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */
535
536 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
537 #define SCP2ADAPTER(scp) \
538 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
539
540 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \
541 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0
542 #define MRDRV_IS_LOGICAL(ap) \
543 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0
544 #define MAP_DEVICE_ID(instance, ap) \
545 (ap->a_target)
546
547 #define HIGH_LEVEL_INTR 1
548 #define NORMAL_LEVEL_INTR 0
549
550 #define IO_RETRY_COUNT 3
551 #define MAX_FW_RESET_COUNT 3
552
553 /*
554 * scsa_cmd - Per-command mr private data
555 * @param cmd_dmahandle : dma handle
556 * @param cmd_dmacookies : current dma cookies
557 * @param cmd_pkt : scsi_pkt reference
558 * @param cmd_dmacount : dma count
559 * @param cmd_cookie : next cookie
560 * @param cmd_ncookies : cookies per window
561 * @param cmd_cookiecnt : cookies per sub-win
562 * @param cmd_nwin : number of dma windows
563 * @param cmd_curwin : current dma window
564 * @param cmd_dma_offset : current window offset
565 * @param cmd_dma_len : current window length
566 * @param cmd_flags : private flags
567 * @param cmd_cdblen : length of cdb
568 * @param cmd_scblen : length of scb
569 * @param cmd_buf : command buffer
570 * @param channel : channel for scsi sub-system
571 * @param target : target for scsi sub-system
572 * @param lun : LUN for scsi sub-system
573 *
574 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E)
575 * - Pointed to by pkt_ha_private field in scsi_pkt
576 */
577 struct scsa_cmd {
578 ddi_dma_handle_t cmd_dmahandle;
579 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT];
580 struct scsi_pkt *cmd_pkt;
581 ulong_t cmd_dmacount;
582 uint_t cmd_cookie;
583 uint_t cmd_ncookies;
584 uint_t cmd_cookiecnt;
585 uint_t cmd_nwin;
586 uint_t cmd_curwin;
587 off_t cmd_dma_offset;
588 ulong_t cmd_dma_len;
589 ulong_t cmd_flags;
590 uint_t cmd_cdblen;
591 uint_t cmd_scblen;
592 struct buf *cmd_buf;
593 ushort_t device_id;
594 uchar_t islogical;
595 uchar_t lun;
596 struct mrsas_device *mrsas_dev;
597 };
598
599
600 struct mrsas_cmd {
601 union mrsas_frame *frame;
602 uint32_t frame_phys_addr;
603 uint8_t *sense;
604 uint32_t sense_phys_addr;
605 dma_obj_t frame_dma_obj;
606 uint8_t frame_dma_obj_status;
607
608 uint32_t index;
609 uint8_t sync_cmd;
610 uint8_t cmd_status;
611 uint16_t abort_aen;
612 mlist_t list;
613 uint32_t frame_count;
614 struct scsa_cmd *cmd;
615 struct scsi_pkt *pkt;
616 uint16_t retry_count_for_ocr;
617 uint16_t drv_pkt_time;
618 };
619
620 #define MAX_MGMT_ADAPTERS 1024
621 #define IOC_SIGNATURE "MR-SAS"
622
623 #define IOC_CMD_FIRMWARE 0x0
624 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000
625 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
626 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
627 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300
628
629
630 #define MRSAS_MAX_SENSE_LENGTH 32
631
632 struct mrsas_mgmt_info {
633
634 uint16_t count;
635 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS];
636 uint16_t map[MAX_MGMT_ADAPTERS];
637 int max_index;
638 };
639
640 #pragma pack(1)
641
642 /*
643 * SAS controller properties
644 */
645 struct mrsas_ctrl_prop {
646 uint16_t seq_num;
647 uint16_t pred_fail_poll_interval;
648 uint16_t intr_throttle_count;
649 uint16_t intr_throttle_timeouts;
650
651 uint8_t rebuild_rate;
652 uint8_t patrol_read_rate;
653 uint8_t bgi_rate;
654 uint8_t cc_rate;
655 uint8_t recon_rate;
656
657 uint8_t cache_flush_interval;
658
659 uint8_t spinup_drv_count;
660 uint8_t spinup_delay;
661
662 uint8_t cluster_enable;
663 uint8_t coercion_mode;
664 uint8_t alarm_enable;
665 uint8_t reserved_1[13];
666 uint32_t on_off_properties;
667 uint8_t reserved_4[28];
668 };
669
670
671 /*
672 * SAS controller information
673 */
674 struct mrsas_ctrl_info {
675 /* PCI device information */
676 struct {
677 uint16_t vendor_id;
678 uint16_t device_id;
679 uint16_t sub_vendor_id;
680 uint16_t sub_device_id;
681 uint8_t reserved[24];
682 } pci;
683
684 /* Host interface information */
685 struct {
686 uint8_t PCIX : 1;
687 uint8_t PCIE : 1;
688 uint8_t iSCSI : 1;
689 uint8_t SAS_3G : 1;
690 uint8_t reserved_0 : 4;
691 uint8_t reserved_1[6];
692 uint8_t port_count;
693 uint64_t port_addr[8];
694 } host_interface;
695
696 /* Device (backend) interface information */
697 struct {
698 uint8_t SPI : 1;
699 uint8_t SAS_3G : 1;
700 uint8_t SATA_1_5G : 1;
701 uint8_t SATA_3G : 1;
702 uint8_t reserved_0 : 4;
703 uint8_t reserved_1[6];
704 uint8_t port_count;
705 uint64_t port_addr[8];
706 } device_interface;
707
708 /* List of components residing in flash. All str are null terminated */
709 uint32_t image_check_word;
710 uint32_t image_component_count;
711
712 struct {
713 char name[8];
714 char version[32];
715 char build_date[16];
716 char built_time[16];
717 } image_component[8];
718
719 /*
720 * List of flash components that have been flashed on the card, but
721 * are not in use, pending reset of the adapter. This list will be
722 * empty if a flash operation has not occurred. All stings are null
723 * terminated
724 */
725 uint32_t pending_image_component_count;
726
727 struct {
728 char name[8];
729 char version[32];
730 char build_date[16];
731 char build_time[16];
732 } pending_image_component[8];
733
734 uint8_t max_arms;
735 uint8_t max_spans;
736 uint8_t max_arrays;
737 uint8_t max_lds;
738
739 char product_name[80];
740 char serial_no[32];
741
742 /*
743 * Other physical/controller/operation information. Indicates the
744 * presence of the hardware
745 */
746 struct {
747 uint32_t bbu : 1;
748 uint32_t alarm : 1;
749 uint32_t nvram : 1;
750 uint32_t uart : 1;
751 uint32_t reserved : 28;
752 } hw_present;
753
754 uint32_t current_fw_time;
755
756 /* Maximum data transfer sizes */
757 uint16_t max_concurrent_cmds;
758 uint16_t max_sge_count;
759 uint32_t max_request_size;
760
761 /* Logical and physical device counts */
762 uint16_t ld_present_count;
763 uint16_t ld_degraded_count;
764 uint16_t ld_offline_count;
765
766 uint16_t pd_present_count;
767 uint16_t pd_disk_present_count;
768 uint16_t pd_disk_pred_failure_count;
769 uint16_t pd_disk_failed_count;
770
771 /* Memory size information */
772 uint16_t nvram_size;
773 uint16_t memory_size;
774 uint16_t flash_size;
775
776 /* Error counters */
777 uint16_t mem_correctable_error_count;
778 uint16_t mem_uncorrectable_error_count;
779
780 /* Cluster information */
781 uint8_t cluster_permitted;
782 uint8_t cluster_active;
783 uint8_t reserved_1[2];
784
785 /* Controller capabilities structures */
786 struct {
787 uint32_t raid_level_0 : 1;
788 uint32_t raid_level_1 : 1;
789 uint32_t raid_level_5 : 1;
790 uint32_t raid_level_1E : 1;
791 uint32_t reserved : 28;
792 } raid_levels;
793
794 struct {
795 uint32_t rbld_rate : 1;
796 uint32_t cc_rate : 1;
797 uint32_t bgi_rate : 1;
798 uint32_t recon_rate : 1;
799 uint32_t patrol_rate : 1;
800 uint32_t alarm_control : 1;
801 uint32_t cluster_supported : 1;
802 uint32_t bbu : 1;
803 uint32_t spanning_allowed : 1;
804 uint32_t dedicated_hotspares : 1;
805 uint32_t revertible_hotspares : 1;
806 uint32_t foreign_config_import : 1;
807 uint32_t self_diagnostic : 1;
808 uint32_t reserved : 19;
809 } adapter_operations;
810
811 struct {
812 uint32_t read_policy : 1;
813 uint32_t write_policy : 1;
814 uint32_t io_policy : 1;
815 uint32_t access_policy : 1;
816 uint32_t reserved : 28;
817 } ld_operations;
818
819 struct {
820 uint8_t min;
821 uint8_t max;
822 uint8_t reserved[2];
823 } stripe_size_operations;
824
825 struct {
826 uint32_t force_online : 1;
827 uint32_t force_offline : 1;
828 uint32_t force_rebuild : 1;
829 uint32_t reserved : 29;
830 } pd_operations;
831
832 struct {
833 uint32_t ctrl_supports_sas : 1;
834 uint32_t ctrl_supports_sata : 1;
835 uint32_t allow_mix_in_encl : 1;
836 uint32_t allow_mix_in_ld : 1;
837 uint32_t allow_sata_in_cluster : 1;
838 uint32_t reserved : 27;
839 } pd_mix_support;
840
841 /* Include the controller properties (changeable items) */
842 uint8_t reserved_2[12];
843 struct mrsas_ctrl_prop properties;
844
845 uint8_t pad[0x800 - 0x640];
846 };
847
848 /*
849 * ==================================
850 * MegaRAID SAS2.0 driver definitions
851 * ==================================
852 */
853 #define MRDRV_MAX_NUM_CMD 1024
854
855 #define MRDRV_MAX_PD_CHANNELS 2
856 #define MRDRV_MAX_LD_CHANNELS 2
857 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \
858 MRDRV_MAX_LD_CHANNELS)
859 #define MRDRV_MAX_DEV_PER_CHANNEL 128
860 #define MRDRV_DEFAULT_INIT_ID -1
861 #define MRDRV_MAX_CMD_PER_LUN 1000
862 #define MRDRV_MAX_LUN 1
863 #define MRDRV_MAX_LD 64
864
865 #define MRDRV_RESET_WAIT_TIME 300
866 #define MRDRV_RESET_NOTICE_INTERVAL 5
867
868 #define MRSAS_IOCTL_CMD 0
869
870 /*
871 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
872 * SGLs based on the size of dma_addr_t
873 */
874 #define IS_DMA64 (sizeof (dma_addr_t) == 8)
875
876 #define IB_MSG_0_OFF 0x10 /* XScale */
877 #define OB_MSG_0_OFF 0x18 /* XScale */
878 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */
879 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */
880 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */
881 #define IB_QPORT_OFF 0x40 /* XScale & ROC */
882 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */
883 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */
884 #define OB_INTR_MASK 0xFFFFFFFF
885 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF
886 #define WRITE_SEQ_OFF 0x000000FC
887 #define HOST_DIAG_OFF 0x000000F8
888 #define DIAG_RESET_ADAPTER 0x00000004
889 #define DIAG_WRITE_ENABLE 0x00000080
890 /*
891 * All MFI register set macros accept mrsas_register_set*
892 */
893 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \
894 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v))
895
896 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \
897 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF))
898
899 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \
900 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v))
901
902 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \
903 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
904
905 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \
906 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
907
908 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \
909 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
910
911 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \
912 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
913
914 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \
915 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
916
917 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \
918 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
919
920 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \
921 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
922
923 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \
924 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
925
926 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
927 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
928
929 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
930 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
931 (v))
932
933 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \
934 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
935
936 /*
937 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
938 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
939 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
940 */
941 #define MFI_OB_INTR_STATUS_MASK 0x00000002
942
943 /*
944 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also
945 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
946 * been set in this flag along with bit 1.
947 */
948 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001
949 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005
950
951 #define MFI_POLL_TIMEOUT_SECS 60
952
953 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \
954 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
955 #define MFI_DISABLE_INTR(instance) \
956 { \
957 uint32_t disable = 1; \
958 uint32_t mask = ddi_get32((instance)->regmap_handle, \
959 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
960 mask &= ~disable; \
961 ddi_put32((instance)->regmap_handle, (uint32_t *) \
962 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \
963 }
964
965 /* By default, the firmware programs for 8 Kbytes of memory */
966 #define DEFAULT_MFI_MEM_SZ 8192
967 #define MINIMUM_MFI_MEM_SZ 4096
968
969 /* DCMD Message Frame MAILBOX0-11 */
970 #define DCMD_MBOX_SZ 12
971
972 /*
973 * on_off_property of mrsas_ctrl_prop
974 * bit0-9, 11-31 are reserved
975 */
976 #define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */
977
978 struct mrsas_register_set {
979 uint32_t reserved_0[4];
980
981 uint32_t inbound_msg_0;
982 uint32_t inbound_msg_1;
983 uint32_t outbound_msg_0;
984 uint32_t outbound_msg_1;
985
986 uint32_t inbound_doorbell;
987 uint32_t inbound_intr_status;
988 uint32_t inbound_intr_mask;
989
990 uint32_t outbound_doorbell;
991 uint32_t outbound_intr_status;
992 uint32_t outbound_intr_mask;
993
994 uint32_t reserved_1[2];
995
996 uint32_t inbound_queue_port;
997 uint32_t outbound_queue_port;
998
999 uint32_t reserved_2[22];
1000
1001 uint32_t outbound_doorbell_clear;
1002
1003 uint32_t reserved_3[3];
1004
1005 uint32_t outbound_scratch_pad;
1006
1007 uint32_t reserved_4[3];
1008
1009 uint32_t inbound_low_queue_port;
1010
1011 uint32_t inbound_high_queue_port;
1012
1013 uint32_t reserved_5;
1014 uint32_t index_registers[820];
1015 };
1016
1017 struct mrsas_sge32 {
1018 uint32_t phys_addr;
1019 uint32_t length;
1020 };
1021
1022 struct mrsas_sge64 {
1023 uint64_t phys_addr;
1024 uint32_t length;
1025 };
1026
1027 struct mrsas_sge_ieee {
1028 uint64_t phys_addr;
1029 uint32_t length;
1030 uint32_t flag;
1031 };
1032
1033 union mrsas_sgl {
1034 struct mrsas_sge32 sge32[1];
1035 struct mrsas_sge64 sge64[1];
1036 struct mrsas_sge_ieee sge_ieee[1];
1037 };
1038
1039 struct mrsas_header {
1040 uint8_t cmd;
1041 uint8_t sense_len;
1042 uint8_t cmd_status;
1043 uint8_t scsi_status;
1044
1045 uint8_t target_id;
1046 uint8_t lun;
1047 uint8_t cdb_len;
1048 uint8_t sge_count;
1049
1050 uint32_t context;
1051 uint8_t req_id;
1052 uint8_t msgvector;
1053 uint16_t pad_0;
1054
1055 uint16_t flags;
1056 uint16_t timeout;
1057 uint32_t data_xferlen;
1058 };
1059
1060 union mrsas_sgl_frame {
1061 struct mrsas_sge32 sge32[8];
1062 struct mrsas_sge64 sge64[5];
1063 };
1064
1065 struct mrsas_init_frame {
1066 uint8_t cmd;
1067 uint8_t reserved_0;
1068 uint8_t cmd_status;
1069
1070 uint8_t reserved_1;
1071 uint32_t reserved_2;
1072
1073 uint32_t context;
1074 uint8_t req_id;
1075 uint8_t msgvector;
1076 uint16_t pad_0;
1077
1078 uint16_t flags;
1079 uint16_t reserved_3;
1080 uint32_t data_xfer_len;
1081
1082 uint32_t queue_info_new_phys_addr_lo;
1083 uint32_t queue_info_new_phys_addr_hi;
1084 uint32_t queue_info_old_phys_addr_lo;
1085 uint32_t queue_info_old_phys_addr_hi;
1086
1087 uint32_t reserved_4[6];
1088 };
1089
1090 struct mrsas_init_queue_info {
1091 uint32_t init_flags;
1092 uint32_t reply_queue_entries;
1093
1094 uint32_t reply_queue_start_phys_addr_lo;
1095 uint32_t reply_queue_start_phys_addr_hi;
1096 uint32_t producer_index_phys_addr_lo;
1097 uint32_t producer_index_phys_addr_hi;
1098 uint32_t consumer_index_phys_addr_lo;
1099 uint32_t consumer_index_phys_addr_hi;
1100 };
1101
1102 struct mrsas_io_frame {
1103 uint8_t cmd;
1104 uint8_t sense_len;
1105 uint8_t cmd_status;
1106 uint8_t scsi_status;
1107
1108 uint8_t target_id;
1109 uint8_t access_byte;
1110 uint8_t reserved_0;
1111 uint8_t sge_count;
1112
1113 uint32_t context;
1114 uint8_t req_id;
1115 uint8_t msgvector;
1116 uint16_t pad_0;
1117
1118 uint16_t flags;
1119 uint16_t timeout;
1120 uint32_t lba_count;
1121
1122 uint32_t sense_buf_phys_addr_lo;
1123 uint32_t sense_buf_phys_addr_hi;
1124
1125 uint32_t start_lba_lo;
1126 uint32_t start_lba_hi;
1127
1128 union mrsas_sgl sgl;
1129 };
1130
1131 struct mrsas_pthru_frame {
1132 uint8_t cmd;
1133 uint8_t sense_len;
1134 uint8_t cmd_status;
1135 uint8_t scsi_status;
1136
1137 uint8_t target_id;
1138 uint8_t lun;
1139 uint8_t cdb_len;
1140 uint8_t sge_count;
1141
1142 uint32_t context;
1143 uint8_t req_id;
1144 uint8_t msgvector;
1145 uint16_t pad_0;
1146
1147 uint16_t flags;
1148 uint16_t timeout;
1149 uint32_t data_xfer_len;
1150
1151 uint32_t sense_buf_phys_addr_lo;
1152 uint32_t sense_buf_phys_addr_hi;
1153
1154 uint8_t cdb[16];
1155 union mrsas_sgl sgl;
1156 };
1157
1158 struct mrsas_dcmd_frame {
1159 uint8_t cmd;
1160 uint8_t reserved_0;
1161 uint8_t cmd_status;
1162 uint8_t reserved_1[4];
1163 uint8_t sge_count;
1164
1165 uint32_t context;
1166 uint8_t req_id;
1167 uint8_t msgvector;
1168 uint16_t pad_0;
1169
1170 uint16_t flags;
1171 uint16_t timeout;
1172
1173 uint32_t data_xfer_len;
1174 uint32_t opcode;
1175
1176 union {
1177 uint8_t b[DCMD_MBOX_SZ];
1178 uint16_t s[6];
1179 uint32_t w[3];
1180 } mbox;
1181
1182 union mrsas_sgl sgl;
1183 };
1184
1185 struct mrsas_abort_frame {
1186 uint8_t cmd;
1187 uint8_t reserved_0;
1188 uint8_t cmd_status;
1189
1190 uint8_t reserved_1;
1191 uint32_t reserved_2;
1192
1193 uint32_t context;
1194 uint8_t req_id;
1195 uint8_t msgvector;
1196 uint16_t pad_0;
1197
1198 uint16_t flags;
1199 uint16_t reserved_3;
1200 uint32_t reserved_4;
1201
1202 uint32_t abort_context;
1203 uint32_t pad_1;
1204
1205 uint32_t abort_mfi_phys_addr_lo;
1206 uint32_t abort_mfi_phys_addr_hi;
1207
1208 uint32_t reserved_5[6];
1209 };
1210
1211 struct mrsas_smp_frame {
1212 uint8_t cmd;
1213 uint8_t reserved_1;
1214 uint8_t cmd_status;
1215 uint8_t connection_status;
1216
1217 uint8_t reserved_2[3];
1218 uint8_t sge_count;
1219
1220 uint32_t context;
1221 uint8_t req_id;
1222 uint8_t msgvector;
1223 uint16_t pad_0;
1224
1225 uint16_t flags;
1226 uint16_t timeout;
1227
1228 uint32_t data_xfer_len;
1229
1230 uint64_t sas_addr;
1231
1232 union mrsas_sgl sgl[2];
1233 };
1234
1235 struct mrsas_stp_frame {
1236 uint8_t cmd;
1237 uint8_t reserved_1;
1238 uint8_t cmd_status;
1239 uint8_t connection_status;
1240
1241 uint8_t target_id;
1242 uint8_t reserved_2[2];
1243 uint8_t sge_count;
1244
1245 uint32_t context;
1246 uint8_t req_id;
1247 uint8_t msgvector;
1248 uint16_t pad_0;
1249
1250 uint16_t flags;
1251 uint16_t timeout;
1252
1253 uint32_t data_xfer_len;
1254
1255 uint16_t fis[10];
1256 uint32_t stp_flags;
1257 union mrsas_sgl sgl;
1258 };
1259
1260 union mrsas_frame {
1261 struct mrsas_header hdr;
1262 struct mrsas_init_frame init;
1263 struct mrsas_io_frame io;
1264 struct mrsas_pthru_frame pthru;
1265 struct mrsas_dcmd_frame dcmd;
1266 struct mrsas_abort_frame abort;
1267 struct mrsas_smp_frame smp;
1268 struct mrsas_stp_frame stp;
1269
1270 uint8_t raw_bytes[64];
1271 };
1272
1273 typedef struct mrsas_pd_address {
1274 uint16_t device_id;
1275 uint16_t encl_id;
1276
1277 union {
1278 struct {
1279 uint8_t encl_index;
1280 uint8_t slot_number;
1281 } pd_address;
1282 struct {
1283 uint8_t encl_position;
1284 uint8_t encl_connector_index;
1285 } encl_address;
1286 }address;
1287
1288 uint8_t scsi_dev_type;
1289
1290 union {
1291 uint8_t port_bitmap;
1292 uint8_t port_numbers;
1293 } connected;
1294
1295 uint64_t sas_addr[2];
1296 } mrsas_pd_address_t;
1297
1298 union mrsas_evt_class_locale {
1299 struct {
1300 uint16_t locale;
1301 uint8_t reserved;
1302 int8_t class;
1303 } members;
1304
1305 uint32_t word;
1306 };
1307
1308 struct mrsas_evt_log_info {
1309 uint32_t newest_seq_num;
1310 uint32_t oldest_seq_num;
1311 uint32_t clear_seq_num;
1312 uint32_t shutdown_seq_num;
1313 uint32_t boot_seq_num;
1314 };
1315
1316 struct mrsas_progress {
1317 uint16_t progress;
1318 uint16_t elapsed_seconds;
1319 };
1320
1321 struct mrsas_evtarg_ld {
1322 uint16_t target_id;
1323 uint8_t ld_index;
1324 uint8_t reserved;
1325 };
1326
1327 struct mrsas_evtarg_pd {
1328 uint16_t device_id;
1329 uint8_t encl_index;
1330 uint8_t slot_number;
1331 };
1332
1333 struct mrsas_evt_detail {
1334 uint32_t seq_num;
1335 uint32_t time_stamp;
1336 uint32_t code;
1337 union mrsas_evt_class_locale cl;
1338 uint8_t arg_type;
1339 uint8_t reserved1[15];
1340
1341 union {
1342 struct {
1343 struct mrsas_evtarg_pd pd;
1344 uint8_t cdb_length;
1345 uint8_t sense_length;
1346 uint8_t reserved[2];
1347 uint8_t cdb[16];
1348 uint8_t sense[64];
1349 } cdbSense;
1350
1351 struct mrsas_evtarg_ld ld;
1352
1353 struct {
1354 struct mrsas_evtarg_ld ld;
1355 uint64_t count;
1356 } ld_count;
1357
1358 struct {
1359 uint64_t lba;
1360 struct mrsas_evtarg_ld ld;
1361 } ld_lba;
1362
1363 struct {
1364 struct mrsas_evtarg_ld ld;
1365 uint32_t prevOwner;
1366 uint32_t newOwner;
1367 } ld_owner;
1368
1369 struct {
1370 uint64_t ld_lba;
1371 uint64_t pd_lba;
1372 struct mrsas_evtarg_ld ld;
1373 struct mrsas_evtarg_pd pd;
1374 } ld_lba_pd_lba;
1375
1376 struct {
1377 struct mrsas_evtarg_ld ld;
1378 struct mrsas_progress prog;
1379 } ld_prog;
1380
1381 struct {
1382 struct mrsas_evtarg_ld ld;
1383 uint32_t prev_state;
1384 uint32_t new_state;
1385 } ld_state;
1386
1387 struct {
1388 uint64_t strip;
1389 struct mrsas_evtarg_ld ld;
1390 } ld_strip;
1391
1392 struct mrsas_evtarg_pd pd;
1393
1394 struct {
1395 struct mrsas_evtarg_pd pd;
1396 uint32_t err;
1397 } pd_err;
1398
1399 struct {
1400 uint64_t lba;
1401 struct mrsas_evtarg_pd pd;
1402 } pd_lba;
1403
1404 struct {
1405 uint64_t lba;
1406 struct mrsas_evtarg_pd pd;
1407 struct mrsas_evtarg_ld ld;
1408 } pd_lba_ld;
1409
1410 struct {
1411 struct mrsas_evtarg_pd pd;
1412 struct mrsas_progress prog;
1413 } pd_prog;
1414
1415 struct {
1416 struct mrsas_evtarg_pd pd;
1417 uint32_t prevState;
1418 uint32_t newState;
1419 } pd_state;
1420
1421 struct {
1422 uint16_t vendorId;
1423 uint16_t deviceId;
1424 uint16_t subVendorId;
1425 uint16_t subDeviceId;
1426 } pci;
1427
1428 uint32_t rate;
1429 char str[96];
1430
1431 struct {
1432 uint32_t rtc;
1433 uint32_t elapsedSeconds;
1434 } time;
1435
1436 struct {
1437 uint32_t ecar;
1438 uint32_t elog;
1439 char str[64];
1440 } ecc;
1441
1442 mrsas_pd_address_t pd_addr;
1443
1444 uint8_t b[96];
1445 uint16_t s[48];
1446 uint32_t w[24];
1447 uint64_t d[12];
1448 } args;
1449
1450 char description[128];
1451
1452 };
1453
1454 /* only 63 are usable by the application */
1455 #define MAX_LOGICAL_DRIVES 64
1456 /* only 255 physical devices may be used */
1457 #define MAX_PHYSICAL_DEVICES 256
1458 #define MAX_PD_PER_ENCLOSURE 64
1459 /* maximum disks per array */
1460 #define MAX_ROW_SIZE 32
1461 /* maximum spans per logical drive */
1462 #define MAX_SPAN_DEPTH 8
1463 /* maximum number of arrays a hot spare may be dedicated to */
1464 #define MAX_ARRAYS_DEDICATED 16
1465 /* maximum number of arrays which may exist */
1466 #define MAX_ARRAYS 128
1467 /* maximum number of foreign configs that may ha managed at once */
1468 #define MAX_FOREIGN_CONFIGS 8
1469 /* maximum spares (global and dedicated combined) */
1470 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES
1471 /* maximum possible Target IDs (i.e. 0 to 63) */
1472 #define MAX_TARGET_ID 63
1473 /* maximum number of supported enclosures */
1474 #define MAX_ENCLOSURES 32
1475 /* maximum number of PHYs per controller */
1476 #define MAX_PHYS_PER_CONTROLLER 16
1477 /* maximum number of LDs per array (due to DDF limitations) */
1478 #define MAX_LDS_PER_ARRAY 16
1479
1480 /*
1481 * -----------------------------------------------------------------------------
1482 * -----------------------------------------------------------------------------
1483 *
1484 * Logical Drive commands
1485 *
1486 * -----------------------------------------------------------------------------
1487 * -----------------------------------------------------------------------------
1488 */
1489 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */
1490
1491 /*
1492 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST
1493 * dcmd.mbox - reserved
1494 * dcmd.sge IN - ptr to returned MR_LD_LIST structure
1495 * Desc: Return the logical drive list structure
1496 * Status: No error
1497 */
1498
1499 /*
1500 * defines the logical drive reference structure
1501 */
1502 typedef union _MR_LD_REF { /* LD reference structure */
1503 struct {
1504 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */
1505 uint8_t reserved; /* reserved for in line with MR_PD_REF */
1506 uint16_t seqNum; /* Sequence Number */
1507 } ld_ref;
1508 uint32_t ref; /* shorthand reference to full 32-bits */
1509 } MR_LD_REF; /* 4 bytes */
1510
1511 /*
1512 * defines the logical drive list structure
1513 */
1514 typedef struct _MR_LD_LIST {
1515 uint32_t ldCount; /* number of LDs */
1516 uint32_t reserved; /* pad to 8-byte boundary */
1517 struct {
1518 MR_LD_REF ref; /* LD reference */
1519 uint8_t state; /* current LD state (MR_LD_STATE) */
1520 uint8_t reserved[3]; /* pad to 8-byte boundary */
1521 uint64_t size; /* LD size */
1522 } ldList[MAX_LOGICAL_DRIVES];
1523 } MR_LD_LIST;
1524
1525 struct mrsas_drv_ver {
1526 uint8_t signature[12];
1527 uint8_t os_name[16];
1528 uint8_t os_ver[12];
1529 uint8_t drv_name[20];
1530 uint8_t drv_ver[32];
1531 uint8_t drv_rel_date[20];
1532 };
1533
1534 #define PCI_TYPE0_ADDRESSES 6
1535 #define PCI_TYPE1_ADDRESSES 2
1536 #define PCI_TYPE2_ADDRESSES 5
1537
1538 struct mrsas_pci_common_header {
1539 uint16_t vendorID; /* (ro) */
1540 uint16_t deviceID; /* (ro) */
1541 uint16_t command; /* Device control */
1542 uint16_t status;
1543 uint8_t revisionID; /* (ro) */
1544 uint8_t progIf; /* (ro) */
1545 uint8_t subClass; /* (ro) */
1546 uint8_t baseClass; /* (ro) */
1547 uint8_t cacheLineSize; /* (ro+) */
1548 uint8_t latencyTimer; /* (ro+) */
1549 uint8_t headerType; /* (ro) */
1550 uint8_t bist; /* Built in self test */
1551
1552 union {
1553 struct {
1554 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES];
1555 uint32_t cis;
1556 uint16_t subVendorID;
1557 uint16_t subSystemID;
1558 uint32_t romBaseAddress;
1559 uint8_t capabilitiesPtr;
1560 uint8_t reserved1[3];
1561 uint32_t reserved2;
1562 uint8_t interruptLine;
1563 uint8_t interruptPin; /* (ro) */
1564 uint8_t minimumGrant; /* (ro) */
1565 uint8_t maximumLatency; /* (ro) */
1566 } type_0;
1567
1568 struct {
1569 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES];
1570 uint8_t primaryBus;
1571 uint8_t secondaryBus;
1572 uint8_t subordinateBus;
1573 uint8_t secondaryLatency;
1574 uint8_t ioBase;
1575 uint8_t ioLimit;
1576 uint16_t secondaryStatus;
1577 uint16_t memoryBase;
1578 uint16_t memoryLimit;
1579 uint16_t prefetchBase;
1580 uint16_t prefetchLimit;
1581 uint32_t prefetchBaseUpper32;
1582 uint32_t prefetchLimitUpper32;
1583 uint16_t ioBaseUpper16;
1584 uint16_t ioLimitUpper16;
1585 uint8_t capabilitiesPtr;
1586 uint8_t reserved1[3];
1587 uint32_t romBaseAddress;
1588 uint8_t interruptLine;
1589 uint8_t interruptPin;
1590 uint16_t bridgeControl;
1591 } type_1;
1592
1593 struct {
1594 uint32_t socketRegistersBaseAddress;
1595 uint8_t capabilitiesPtr;
1596 uint8_t reserved;
1597 uint16_t secondaryStatus;
1598 uint8_t primaryBus;
1599 uint8_t secondaryBus;
1600 uint8_t subordinateBus;
1601 uint8_t secondaryLatency;
1602 struct {
1603 uint32_t base;
1604 uint32_t limit;
1605 } range[PCI_TYPE2_ADDRESSES-1];
1606 uint8_t interruptLine;
1607 uint8_t interruptPin;
1608 uint16_t bridgeControl;
1609 } type_2;
1610 } header;
1611 };
1612
1613 struct mrsas_pci_link_capability {
1614 union {
1615 struct {
1616 uint32_t linkSpeed :4;
1617 uint32_t linkWidth :6;
1618 uint32_t aspmSupport :2;
1619 uint32_t losExitLatency :3;
1620 uint32_t l1ExitLatency :3;
1621 uint32_t rsvdp :6;
1622 uint32_t portNumber :8;
1623 } bits;
1624
1625 uint32_t asUlong;
1626 } cap;
1627
1628 };
1629
1630 struct mrsas_pci_link_status_capability {
1631 union {
1632 struct {
1633 uint16_t linkSpeed :4;
1634 uint16_t negotiatedLinkWidth :6;
1635 uint16_t linkTrainingError :1;
1636 uint16_t linkTraning :1;
1637 uint16_t slotClockConfig :1;
1638 uint16_t rsvdZ :3;
1639 } bits;
1640
1641 uint16_t asUshort;
1642 } stat_cap;
1643
1644 uint16_t reserved;
1645
1646 };
1647
1648 struct mrsas_pci_capabilities {
1649 struct mrsas_pci_link_capability linkCapability;
1650 struct mrsas_pci_link_status_capability linkStatusCapability;
1651 };
1652
1653 struct mrsas_pci_information
1654 {
1655 uint32_t busNumber;
1656 uint8_t deviceNumber;
1657 uint8_t functionNumber;
1658 uint8_t interruptVector;
1659 uint8_t reserved;
1660 struct mrsas_pci_common_header pciHeaderInfo;
1661 struct mrsas_pci_capabilities capability;
1662 uint8_t reserved2[32];
1663 };
1664
1665 struct mrsas_ioctl {
1666 uint16_t version;
1667 uint16_t controller_id;
1668 uint8_t signature[8];
1669 uint32_t reserved_1;
1670 uint32_t control_code;
1671 uint32_t reserved_2[2];
1672 uint8_t frame[64];
1673 union mrsas_sgl_frame sgl_frame;
1674 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH];
1675 uint8_t data[1];
1676 };
1677
1678 struct mrsas_aen {
1679 uint16_t host_no;
1680 uint16_t cmd_status;
1681 uint32_t seq_num;
1682 uint32_t class_locale_word;
1683 };
1684 #pragma pack()
1685
1686 #ifndef DDI_VENDOR_LSI
1687 #define DDI_VENDOR_LSI "LSI"
1688 #endif /* DDI_VENDOR_LSI */
1689
1690 #ifndef KMDB_MODULE
1691 static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
1692 static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t);
1693 #ifdef __sparc
1694 static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t);
1695 #else /* __sparc */
1696 static int mrsas_quiesce(dev_info_t *);
1697 #endif /* __sparc */
1698 static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t);
1699 static int mrsas_open(dev_t *, int, int, cred_t *);
1700 static int mrsas_close(dev_t, int, int, cred_t *);
1701 static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
1702
1703 static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *,
1704 scsi_hba_tran_t *, struct scsi_device *);
1705 static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register
1706 struct scsi_pkt *, struct buf *, int, int, int, int,
1707 int (*)(), caddr_t);
1708 static int mrsas_tran_start(struct scsi_address *,
1709 register struct scsi_pkt *);
1710 static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *);
1711 static int mrsas_tran_reset(struct scsi_address *, int);
1712 static int mrsas_tran_getcap(struct scsi_address *, char *, int);
1713 static int mrsas_tran_setcap(struct scsi_address *, char *, int, int);
1714 static void mrsas_tran_destroy_pkt(struct scsi_address *,
1715 struct scsi_pkt *);
1716 static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *);
1717 static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *);
1718 static uint_t mrsas_isr();
1719 static uint_t mrsas_softintr();
1720
1721 static int init_mfi(struct mrsas_instance *);
1722 static int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
1723 static int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
1724 uchar_t);
1725 static struct mrsas_cmd *get_mfi_pkt(struct mrsas_instance *);
1726 static void return_mfi_pkt(struct mrsas_instance *,
1727 struct mrsas_cmd *);
1728
1729 static void free_space_for_mfi(struct mrsas_instance *);
1730 static void free_additional_dma_buffer(struct mrsas_instance *);
1731 static int alloc_additional_dma_buffer(struct mrsas_instance *);
1732 static int read_fw_status_reg_ppc(struct mrsas_instance *);
1733 static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *);
1734 static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *,
1735 struct mrsas_cmd *);
1736 static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *,
1737 struct mrsas_cmd *);
1738 static void enable_intr_ppc(struct mrsas_instance *);
1739 static void disable_intr_ppc(struct mrsas_instance *);
1740 static int intr_ack_ppc(struct mrsas_instance *);
1741 static int mfi_state_transition_to_ready(struct mrsas_instance *);
1742 static void destroy_mfi_frame_pool(struct mrsas_instance *);
1743 static int create_mfi_frame_pool(struct mrsas_instance *);
1744 static int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
1745 struct buf *, int, int (*)());
1746 static int mrsas_dma_move(struct mrsas_instance *,
1747 struct scsi_pkt *, struct buf *);
1748 static void flush_cache(struct mrsas_instance *instance);
1749 static void display_scsi_inquiry(caddr_t);
1750 static int start_mfi_aen(struct mrsas_instance *instance);
1751 static int handle_drv_ioctl(struct mrsas_instance *instance,
1752 struct mrsas_ioctl *ioctl, int mode);
1753 static int handle_mfi_ioctl(struct mrsas_instance *instance,
1754 struct mrsas_ioctl *ioctl, int mode);
1755 static int handle_mfi_aen(struct mrsas_instance *instance,
1756 struct mrsas_aen *aen);
1757 static void fill_up_drv_ver(struct mrsas_drv_ver *dv);
1758 static struct mrsas_cmd *build_cmd(struct mrsas_instance *instance,
1759 struct scsi_address *ap, struct scsi_pkt *pkt,
1760 uchar_t *cmd_done);
1761 #ifndef __sparc
1762 static int wait_for_outstanding(struct mrsas_instance *instance);
1763 #endif /* __sparc */
1764 static int register_mfi_aen(struct mrsas_instance *instance,
1765 uint32_t seq_num, uint32_t class_locale_word);
1766 static int issue_mfi_pthru(struct mrsas_instance *instance, struct
1767 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1768 static int issue_mfi_dcmd(struct mrsas_instance *instance, struct
1769 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1770 static int issue_mfi_smp(struct mrsas_instance *instance, struct
1771 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1772 static int issue_mfi_stp(struct mrsas_instance *instance, struct
1773 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1774 static int abort_aen_cmd(struct mrsas_instance *instance,
1775 struct mrsas_cmd *cmd_to_abort);
1776
1777 static int mrsas_common_check(struct mrsas_instance *instance,
1778 struct mrsas_cmd *cmd);
1779 static void mrsas_fm_init(struct mrsas_instance *instance);
1780 static void mrsas_fm_fini(struct mrsas_instance *instance);
1781 static int mrsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *,
1782 const void *);
1783 static void mrsas_fm_ereport(struct mrsas_instance *instance,
1784 char *detail);
1785 static int mrsas_check_dma_handle(ddi_dma_handle_t handle);
1786 static int mrsas_check_acc_handle(ddi_acc_handle_t handle);
1787
1788 static void mrsas_rem_intrs(struct mrsas_instance *instance);
1789 static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type);
1790
1791 static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *,
1792 scsi_hba_tran_t *, struct scsi_device *);
1793 static int mrsas_tran_bus_config(dev_info_t *, uint_t,
1794 ddi_bus_config_op_t, void *, dev_info_t **);
1795 static int mrsas_parse_devname(char *, int *, int *);
1796 static int mrsas_config_all_devices(struct mrsas_instance *);
1797 static int mrsas_config_scsi_device(struct mrsas_instance *,
1798 struct scsi_device *, dev_info_t **);
1799 static int mrsas_config_ld(struct mrsas_instance *, uint16_t,
1800 uint8_t, dev_info_t **);
1801 static dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t,
1802 uint8_t);
1803 static int mrsas_name_node(dev_info_t *, char *, int);
1804 static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *);
1805 static int mrsas_service_evt(struct mrsas_instance *, int, int, int,
1806 uint64_t);
1807 static int mrsas_mode_sense_build(struct scsi_pkt *);
1808 static void push_pending_mfi_pkt(struct mrsas_instance *,
1809 struct mrsas_cmd *);
1810 static int mrsas_issue_init_mfi(struct mrsas_instance *);
1811 static int mrsas_issue_pending_cmds(struct mrsas_instance *);
1812 static int mrsas_print_pending_cmds(struct mrsas_instance *);
1813 static int mrsas_complete_pending_cmds(struct mrsas_instance *);
1814 static int mrsas_reset_ppc(struct mrsas_instance *);
1815 static uint32_t mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *);
1816 static int mrsas_kill_adapter(struct mrsas_instance *);
1817 static void io_timeout_checker(void *instance);
1818 static void complete_cmd_in_sync_mode(struct mrsas_instance *,
1819 struct mrsas_cmd *);
1820
1821 #endif /* KMDB_MODULE */
1822
1823
1824 #ifdef __cplusplus
1825 }
1826 #endif
1827
1828 #endif /* _MR_SAS_H_ */