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@@ -14,11 +14,10 @@
* Rasheed
* Shakeel Bukhari
*/
-#include <stddef.h>
#include <sys/types.h>
#include <sys/file.h>
#include <sys/atomic.h>
#include <sys/scsi/scsi.h>
#include <sys/byteorder.h>
@@ -202,11 +201,11 @@
instance->io_request_frames_phy =
(uint32_t)
instance->mpi2_frame_pool_dma_obj.dma_cookie[0].dmac_address;
con_log(CL_DLEVEL3, (CE_NOTE,
- "io_request_frames 0x%x",
+ "io_request_frames 0x%p",
instance->io_request_frames));
con_log(CL_DLEVEL3, (CE_NOTE,
"io_request_frames_phy 0x%x",
instance->io_request_frames_phy));
@@ -248,28 +247,28 @@
cmd->SMID = i+1;
con_log(CL_DLEVEL3, (CE_NOTE,
- "Frame Pool Addr [%x]0x%x",
+ "Frame Pool Addr [%x]0x%p",
cmd->index, cmd->scsi_io_request));
con_log(CL_DLEVEL3, (CE_NOTE,
"Frame Pool Phys Addr [%x]0x%x",
cmd->index, cmd->scsi_io_request_phys_addr));
con_log(CL_DLEVEL3, (CE_NOTE,
- "Sense Addr [%x]0x%x",
+ "Sense Addr [%x]0x%p",
cmd->index, cmd->sense1));
con_log(CL_DLEVEL3, (CE_NOTE,
"Sense Addr Phys [%x]0x%x",
cmd->index, cmd->sense_phys_addr1));
con_log(CL_DLEVEL3, (CE_NOTE,
- "Sgl bufffers [%x]0x%x",
+ "Sgl bufffers [%x]0x%p",
cmd->index, cmd->sgl));
con_log(CL_DLEVEL3, (CE_NOTE,
"Sgl bufffers phys [%x]0x%x",
cmd->index, cmd->sgl_phys_addr));
@@ -431,20 +430,20 @@
* to allocate memory for 1024 reply descriptors
*/
/* Allocate Reply Descriptors */
con_log(CL_ANN1, (CE_NOTE, " reply q desc len = %x\n",
- sizeof (MPI2_REPLY_DESCRIPTORS_UNION)));
+ (uint_t)sizeof (MPI2_REPLY_DESCRIPTORS_UNION)));
// reply queue size should be multiple of 16
max_reply_q_sz = ((instance->max_fw_cmds + 1 + 15)/16)*16;
reply_q_sz = 8 * max_reply_q_sz;
con_log(CL_ANN1, (CE_NOTE, " reply q desc len = %x\n",
- sizeof (MPI2_REPLY_DESCRIPTORS_UNION)));
+ (uint_t)sizeof (MPI2_REPLY_DESCRIPTORS_UNION)));
instance->reply_desc_dma_obj.size = reply_q_sz;
instance->reply_desc_dma_obj.dma_attr = mrsas_generic_dma_attr;
instance->reply_desc_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
instance->reply_desc_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
@@ -468,11 +467,11 @@
instance->reply_q_depth = max_reply_q_sz;
con_log(CL_ANN1, (CE_NOTE, "[reply queue depth]0x%x",
instance->reply_q_depth));
- con_log(CL_ANN1, (CE_NOTE, "[reply queue virt addr]0x%x",
+ con_log(CL_ANN1, (CE_NOTE, "[reply queue virt addr]0x%p",
instance->reply_frame_pool));
/* initializing reply address to 0xFFFFFFFF */
reply_desc = instance->reply_frame_pool;
@@ -495,15 +494,15 @@
con_log(CL_ANN1, (CE_NOTE, "[reply pool limit phys addr]0x%x",
instance->reply_pool_limit_phy));
con_log(CL_ANN1, (CE_NOTE, " request q desc len = %x\n",
- sizeof (MRSAS_REQUEST_DESCRIPTOR_UNION)));
+ (int)sizeof (MRSAS_REQUEST_DESCRIPTOR_UNION)));
/* Allocate Request Descriptors */
con_log(CL_ANN1, (CE_NOTE, " request q desc len = %x\n",
- sizeof (MRSAS_REQUEST_DESCRIPTOR_UNION)));
+ (int)sizeof (MRSAS_REQUEST_DESCRIPTOR_UNION)));
request_q_sz = 8 *
(instance->max_fw_cmds);
instance->request_desc_dma_obj.size = request_q_sz;
@@ -904,16 +903,16 @@
con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
#ifdef DEBUG
con_log(CL_ANN1, (CE_CONT, " mfiFrameInit2 len = %x\n",
- sizeof (*mfiFrameInit2)));
- con_log(CL_ANN1, (CE_CONT, " MPI len = %x\n", sizeof (*init)));
+ (int)sizeof (*mfiFrameInit2)));
+ con_log(CL_ANN1, (CE_CONT, " MPI len = %x\n", (int)sizeof (*init)));
con_log(CL_ANN1, (CE_CONT, " mfiFrameInit2 len = %x\n",
- sizeof (struct mrsas_init_frame2)));
+ (int)sizeof (struct mrsas_init_frame2)));
con_log(CL_ANN1, (CE_CONT, " MPI len = %x\n",
- sizeof (Mpi2IOCInitRequest_t)));
+ (int)sizeof (Mpi2IOCInitRequest_t)));
#endif
init = (Mpi2IOCInitRequest_t *)mpi2_dma_obj->buffer;
numbytes = sizeof (*init);
bzero(init, numbytes);
@@ -967,11 +966,11 @@
cmd->retry_count_for_ocr = 0;
cmd->pkt = NULL;
cmd->drv_pkt_time = 0;
mfiFrameInit2 = (struct mrsas_init_frame2 *)cmd->scsi_io_request;
- con_log(CL_ANN1, (CE_CONT, "[mfi vaddr]%x", mfiFrameInit2));
+ con_log(CL_ANN1, (CE_CONT, "[mfi vaddr]%p", mfiFrameInit2));
frame_hdr = &cmd->frame->hdr;
ddi_put8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status,
MFI_CMD_STATUS_POLL_MODE);
@@ -1004,11 +1003,11 @@
ddi_put32(instance->mpi2_frame_pool_dma_obj.acc_handle,
&mfiFrameInit2->data_xfer_len,
sizeof (Mpi2IOCInitRequest_t));
con_log(CL_ANN1, (CE_CONT, "[reply q desc addr]%x",
- init->ReplyDescriptorPostQueueAddress));
+ (int)init->ReplyDescriptorPostQueueAddress));
/* fill driver version information*/
fill_up_drv_ver(&drv_ver_info);
/* allocate the driver version data transfer buffer */
@@ -1036,16 +1035,17 @@
ddi_put64(cmd->frame_dma_obj.acc_handle,
&mfiFrameInit2->driverversion, instance->drv_ver_dma_obj.dma_cookie[0].dmac_address);
con_log(CL_ANN1, (CE_CONT, "[MPIINIT2 frame Phys addr ]0x%x len = %x",
mfiFrameInit2->queue_info_new_phys_addr_lo,
- sizeof (Mpi2IOCInitRequest_t)));
+ (int)sizeof (Mpi2IOCInitRequest_t)));
con_log(CL_ANN1, (CE_CONT, "[Length]%x", mfiFrameInit2->data_xfer_len));
con_log(CL_ANN1, (CE_CONT, "[MFI frame Phys Address]%x len = %x",
- cmd->scsi_io_request_phys_addr, sizeof (struct mrsas_init_frame2)));
+ cmd->scsi_io_request_phys_addr,
+ (int) sizeof (struct mrsas_init_frame2)));
/* disable interrupts before sending INIT2 frame */
instance->func_ptr->disable_intr(instance);
req_desc = (MRSAS_REQUEST_DESCRIPTOR_UNION *)
@@ -1182,11 +1182,11 @@
/* Synchronize the Cmd frame for the controller */
(void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 0, 0,
DDI_DMA_SYNC_FORDEV);
con_log(CL_ANN, (CE_CONT, "tbolt_issue_cmd: SCSI CDB[0]=0x%x "
- "cmd->index:0x%x SMID %0x%x\n", pkt->pkt_cdbp[0], cmd->index, cmd->SMID));
+ "cmd->index:0x%x SMID 0x%x\n", pkt->pkt_cdbp[0], cmd->index, cmd->SMID));
instance->func_ptr->issue_cmd(cmd, instance);
return (TRAN_ACCEPT);
@@ -1314,11 +1314,11 @@
}
*datalen += acmd->cmd_dmacookies[i].dmac_size;
#ifdef DEBUG
- con_log(CL_DLEVEL1, (CE_NOTE, "[SGL Address]:%llx",
+ con_log(CL_DLEVEL1, (CE_NOTE, "[SGL Address]: %" PRIx64,
scsi_raid_io_sgl_ieee->Address));
con_log(CL_DLEVEL1, (CE_NOTE, "[SGL Length]:%x",
scsi_raid_io_sgl_ieee->Length));
con_log(CL_DLEVEL1, (CE_NOTE, "[SGL Flags]:%x",
scsi_raid_io_sgl_ieee->Flags));
@@ -1404,11 +1404,11 @@
*datalen += acmd->cmd_dmacookies[i].dmac_size;
#if DEBUG
con_log(CL_DLEVEL1, (CE_NOTE,
- "[SGL Address]:%llx",
+ "[SGL Address]: %" PRIx64,
scsi_raid_io_sgl_ieee->Address));
con_log(CL_DLEVEL1, (CE_NOTE,
"[SGL Length]:%x", scsi_raid_io_sgl_ieee->Length));
con_log(CL_DLEVEL1, (CE_NOTE,
"[SGL Flags]:%x", scsi_raid_io_sgl_ieee->Flags));
@@ -1984,15 +1984,16 @@
struct scsi_pkt *pkt;
con_log(CL_ANN1, (CE_NOTE, "tbolt_issue_cmd: cmd->[SMID]=0x%X", cmd->SMID));
con_log(CL_DLEVEL1, (CE_CONT,
- " [req desc Words] %llx \n", req_desc->Words));
+ " [req desc Words] %" PRIx64 " \n", req_desc->Words));
con_log(CL_DLEVEL1, (CE_CONT,
- " [req desc low part] %x \n", req_desc->Words));
+ " [req desc low part] %x \n",
+ (uint_t)(req_desc->Words & 0xffffffffff)));
con_log(CL_DLEVEL1, (CE_CONT,
- " [req desc high part] %x \n", (req_desc->Words >> 32)));
+ " [req desc high part] %x \n", (uint_t)(req_desc->Words >> 32)));
pkt = cmd->pkt;
if (pkt) {
con_log(CL_ANN1, (CE_CONT, "%llx :TBOLT issue_cmd_ppc:"
"ISSUED CMD TO FW : called : cmd:"
@@ -2055,14 +2056,14 @@
con_log(CL_ANN1, (CE_NOTE, "tbolt_issue_cmd_in_sync_mode: pushing the pkt\n"));
push_pending_mfi_pkt(instance, cmd);
}
con_log(CL_DLEVEL2, (CE_NOTE,
- "HighQport offset :%lx",
+ "HighQport offset :%p",
(uint32_t *)((uintptr_t)(instance)->regmap + IB_HIGH_QPORT)));
con_log(CL_DLEVEL2, (CE_NOTE,
- "LowQport offset :%lx",
+ "LowQport offset :%p",
(uint32_t *)((uintptr_t)(instance)->regmap + IB_LOW_QPORT)));
cmd->sync_cmd = MRSAS_TRUE;
cmd->cmd_status = ENODATA;
@@ -2071,13 +2072,13 @@
WR_IB_LOW_QPORT((uint32_t)(req_desc->Words), instance);
WR_IB_HIGH_QPORT((uint32_t)(req_desc->Words >> 32), instance);
mutex_exit(&instance->reg_write_mtx);
con_log(CL_ANN1, (CE_NOTE,
- " req desc high part %x \n", (req_desc->Words >> 32)));
+ " req desc high part %x \n", (uint_t)(req_desc->Words >> 32)));
con_log(CL_ANN1, (CE_NOTE,
- " req desc low part %x \n", req_desc->Words));
+ " req desc low part %x \n", (uint_t)(req_desc->Words & 0xffffffff)));
mutex_enter(&instance->int_cmd_mtx);
for (i = 0; i < msecs && (cmd->cmd_status == ENODATA); i++) {
cv_wait(&instance->int_cmd_cv, &instance->int_cmd_mtx);
}
@@ -2113,13 +2114,13 @@
flags = ddi_get16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags);
flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
ddi_put16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags, flags);
con_log(CL_ANN1, (CE_NOTE,
- " req desc low part %x \n", req_desc->Words));
+ " req desc low part %x \n", (uint_t)(req_desc->Words & 0xffffffff)));
con_log(CL_ANN1, (CE_NOTE,
- " req desc high part %x \n", (req_desc->Words >> 32)));
+ " req desc high part %x \n", (uint_t)(req_desc->Words >> 32)));
/* issue the frame using inbound queue port */
mutex_enter(&instance->reg_write_mtx);
WR_IB_LOW_QPORT((uint32_t)(req_desc->Words), instance);
WR_IB_HIGH_QPORT((uint32_t)(req_desc->Words >> 32), instance);
@@ -2133,11 +2134,11 @@
}
if (ddi_get8(cmd->frame_dma_obj.acc_handle,
&frame_hdr->cmd_status) == MFI_CMD_STATUS_POLL_MODE) {
con_log(CL_ANN1, (CE_NOTE,
- " cmd failed %x \n", (req_desc->Words)));
+ " cmd failed %" PRIx64 " \n", (req_desc->Words)));
return (DDI_FAILURE);
}
return (DDI_SUCCESS);
}
@@ -2310,11 +2311,11 @@
ReqDescUnion =
mr_sas_get_request_descriptor(instance, index, cmd);
if (!ReqDescUnion) {
- con_log(CL_ANN1, (CE_NOTE, "[NULL REQDESC]%x"));
+ con_log(CL_ANN1, (CE_NOTE, "[NULL REQDESC]"));
return;
}
con_log(CL_ANN1, (CE_NOTE, "[SMID]%x", cmd->SMID));
@@ -2368,11 +2369,11 @@
MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR));
ddi_put32(instance->mpi2_frame_pool_dma_obj.acc_handle,
&scsi_raid_io_sgl_ieee->Length, 1024); //MEGASAS_MAX_SZ_CHAIN_FRAME
con_log(CL_ANN1, (CE_NOTE,
- "[MFI CMD PHY ADDRESS]:%x",
+ "[MFI CMD PHY ADDRESS]:%" PRIx64,
scsi_raid_io_sgl_ieee->Address));
con_log(CL_ANN1, (CE_NOTE,
"[SGL Length]:%x", scsi_raid_io_sgl_ieee->Length));
con_log(CL_ANN1, (CE_NOTE, "[SGL Flags]:%x",
scsi_raid_io_sgl_ieee->Flags));
@@ -2628,11 +2629,11 @@
"map sync failed, status = 0x%x.\n",cmd->frame->hdr.cmd_status);
}
else {
instance->map_id++;
cmn_err(CE_NOTE,
- "map sync received, switched map_id to %ld \n",instance->map_id);
+ "map sync received, switched map_id to %" PRIu64 " \n",instance->map_id);
}
if (MR_ValidateMapInfo(instance->ld_map[(instance->map_id & 1)], instance->load_balance_info))
instance->fast_path_io = 1;
else
@@ -2722,11 +2723,11 @@
MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
if (replyType == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
return (DDI_INTR_UNCLAIMED);
- con_log(CL_ANN1, (CE_NOTE, "Reply Desc = %llx Words = %llx \n",
+ con_log(CL_ANN1, (CE_NOTE, "Reply Desc = %p Words = %" PRIx64 " \n",
desc, desc->Words));
d_val.word = desc->Words;
@@ -2739,11 +2740,11 @@
smid = replyDesc->SMID;
if (!smid || smid > instance->max_fw_cmds + 1) {
con_log(CL_ANN1, (CE_NOTE,
- "Reply Desc at Break = %llx Words = %llx \n",
+ "Reply Desc at Break = %p Words = %" PRIx64 " \n",
desc, desc->Words));
break;
}
cmd = instance->cmd_list[smid - 1];
@@ -2795,11 +2796,11 @@
replyDesc = (MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *)desc;
d_val.word = desc->Words;
con_log(CL_ANN1, (CE_NOTE,
- "Next Reply Desc = %llx Words = %llx\n",
+ "Next Reply Desc = %p Words = %" PRIx64 "\n",
desc, desc->Words));
replyType = replyDesc->ReplyFlags &
MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;