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--- old/./mr_sas.h
+++ new/./mr_sas.h
1 1 /*
2 2 * mr_sas.h: header for mr_sas
3 3 *
4 4 * Solaris MegaRAID driver for SAS2.0 controllers
5 5 * Copyright (c) 2008-2012, LSI Logic Corporation.
6 6 * All rights reserved.
7 7 *
8 8 * Version:
9 9 * Author:
10 10 * Swaminathan K S
11 11 * Arun Chandrashekhar
12 12 * Manju R
13 13 * Rasheed
14 14 * Shakeel Bukhari
15 15 */
16 16
17 17 #ifndef _MR_SAS_H_
18 18 #define _MR_SAS_H_
19 19
20 20 #ifdef __cplusplus
21 21 extern "C" {
22 22 #endif
23 23
24 24 #include <sys/scsi/scsi.h>
25 25 #include "mr_sas_list.h"
26 26 #include "ld_pd_map.h"
27 27
28 28 /*
29 29 * MegaRAID SAS2.0 Driver meta data
30 30 */
31 31 #define MRSAS_VERSION "6.503.00.00JOYENT"
32 32 #define MRSAS_RELDATE "July 30, 2012"
33 33
34 34 #define MRSAS_TRUE 1
35 35 #define MRSAS_FALSE 0
36 36
37 37 #define ADAPTER_RESET_NOT_REQUIRED 0
38 38 #define ADAPTER_RESET_REQUIRED 1
39 39
40 40 #define PDSUPPORT 1
41 41
42 42 #define SWAP_BYTES(w) ((((w)>>8)&0xFF) | (((w)&0xFF)<<8))
43 43 #define BIG_ENDIAN(d) (SWAP_BYTES((d) >> 16) | (SWAP_BYTES(d) << 16))
44 44 /*
45 45 * MegaRAID SAS2.0 device id conversion definitions.
46 46 */
47 47 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT)
48 48 #define MRSAS_GET_BOUNDARY_ALIGNED_LEN(len, new_len, boundary_len) { \
49 49 int rem; \
50 50 rem = (len / boundary_len); \
51 51 if ((rem * boundary_len) != len) { \
52 52 new_len = len + ((rem + 1) * boundary_len - len); \
53 53 } else { \
54 54 new_len = len; \
55 55 } \
56 56 } \
57 57
58 58
59 59 /*
60 60 * MegaRAID SAS2.0 supported controllers
61 61 */
62 62 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078
63 63 #define PCI_DEVICE_ID_LSI_2108V 0x0079
64 64 #define PCI_DEVICE_ID_LSI_TBOLT 0x005b
65 65 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
66 66
67 67 /*
68 68 * Register Index for 2108 Controllers.
69 69 */
70 70 #define REGISTER_SET_IO_2108 (2)
71 71
72 72 #define MRSAS_MAX_SGE_CNT 0x50
73 73 #define MRSAS_APP_RESERVED_CMDS 32
74 74
75 75 #define MRSAS_IOCTL_DRIVER 0x12341234
76 76 #define MRSAS_IOCTL_FIRMWARE 0x12345678
77 77 #define MRSAS_IOCTL_AEN 0x87654321
78 78
79 79 #define MRSAS_1_SECOND 1000000
80 80
81 81 #ifdef PDSUPPORT
82 82
83 83 #define UNCONFIGURED_GOOD 0x0
84 84 #define PD_SYSTEM 0x40
85 85 #define MR_EVT_PD_STATE_CHANGE 0x0072
86 86 #define MR_EVT_PD_REMOVED_EXT 0x00f8
87 87 #define MR_EVT_PD_INSERTED_EXT 0x00f7
88 88 #define MR_DCMD_PD_GET_INFO 0x02020000
89 89 #define MRSAS_TBOLT_PD_LUN 1
90 90 #define MRSAS_TBOLT_PD_TGT_MAX 255
91 91 #define MRSAS_TBOLT_GET_PD_MAX(s) ((s)->mr_tbolt_pd_max)
92 92
93 93 #endif
94 94
95 95 /* Raid Context Flags */
96 96 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
97 97 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
98 98 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
99 99 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
100 100 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1
101 101 } MR_RAID_FLAGS_IO_SUB_TYPE;
102 102
103 103 /* Dynamic Enumeration Flags */
104 104 #define MRSAS_LD_LUN 0
105 105 #define WWN_STRLEN 17
106 106 #define LD_SYNC_BIT 1
107 107 #define LD_SYNC_SHIFT 14
108 108 /* ThunderBolt (TB) specific */
109 109 #define MRSAS_THUNDERBOLT_MSG_SIZE 256
110 110 #define MRSAS_THUNDERBOLT_MAX_COMMANDS 1024
111 111 #define MRSAS_THUNDERBOLT_MAX_REPLY_COUNT 1024
112 112 #define MRSAS_THUNDERBOLT_REPLY_SIZE 8
113 113 #define MRSAS_THUNDERBOLT_MAX_CHAIN_COUNT 1
114 114
115 115 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
116 116 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1
117 117
118 118 #define MR_EVT_LD_FAST_PATH_IO_STATUS_CHANGED (0xFFFF)
119 119
120 120 #define MR_INTERNAL_MFI_FRAMES_SMID 1
121 121 #define MR_CTRL_EVENT_WAIT_SMID 2
122 122 #define MR_INTERNAL_DRIVER_RESET_SMID 3
123 123
124 124
125 125 /*
126 126 * =====================================
127 127 * MegaRAID SAS2.0 MFI firmware definitions
128 128 * =====================================
129 129 */
130 130 /*
131 131 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for
132 132 * protocol between the software and firmware. Commands are issued using
133 133 * "message frames"
134 134 */
135 135
136 136 /*
137 137 * FW posts its state in upper 4 bits of outbound_msg_0 register
138 138 */
139 139 #define MFI_STATE_MASK 0xF0000000
140 140 #define MFI_STATE_UNDEFINED 0x00000000
141 141 #define MFI_STATE_BB_INIT 0x10000000
142 142 #define MFI_STATE_FW_INIT 0x40000000
143 143 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
144 144 #define MFI_STATE_FW_INIT_2 0x70000000
145 145 #define MFI_STATE_DEVICE_SCAN 0x80000000
146 146 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
147 147 #define MFI_STATE_FLUSH_CACHE 0xA0000000
148 148 #define MFI_STATE_READY 0xB0000000
149 149 #define MFI_STATE_OPERATIONAL 0xC0000000
150 150 #define MFI_STATE_FAULT 0xF0000000
151 151
152 152 #define MRMFI_FRAME_SIZE 64
153 153
154 154 /*
155 155 * During FW init, clear pending cmds & reset state using inbound_msg_0
156 156 *
157 157 * ABORT : Abort all pending cmds
158 158 * READY : Move from OPERATIONAL to READY state; discard queue info
159 159 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
160 160 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
161 161 */
162 162 #define MFI_INIT_ABORT 0x00000001
163 163 #define MFI_INIT_READY 0x00000002
164 164 #define MFI_INIT_MFIMODE 0x00000004
165 165 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
166 166 #define MFI_INIT_HOTPLUG 0x00000010
167 167 #define MFI_STOP_ADP 0x00000020
168 168 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
169 169
170 170 /*
171 171 * MFI frame flags
172 172 */
173 173 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
174 174 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
175 175 #define MFI_FRAME_SGL32 0x0000
176 176 #define MFI_FRAME_SGL64 0x0002
177 177 #define MFI_FRAME_SENSE32 0x0000
178 178 #define MFI_FRAME_SENSE64 0x0004
179 179 #define MFI_FRAME_DIR_NONE 0x0000
180 180 #define MFI_FRAME_DIR_WRITE 0x0008
181 181 #define MFI_FRAME_DIR_READ 0x0010
182 182 #define MFI_FRAME_DIR_BOTH 0x0018
183 183 #define MFI_FRAME_IEEE 0x0020
184 184
185 185 /*
186 186 * Definition for cmd_status
187 187 */
188 188 #define MFI_CMD_STATUS_POLL_MODE 0xFF
189 189 #define MFI_CMD_STATUS_SYNC_MODE 0xFF
190 190
191 191 /*
192 192 * MFI command opcodes
193 193 */
194 194 #define MFI_CMD_OP_INIT 0x00
195 195 #define MFI_CMD_OP_LD_READ 0x01
196 196 #define MFI_CMD_OP_LD_WRITE 0x02
197 197 #define MFI_CMD_OP_LD_SCSI 0x03
198 198 #define MFI_CMD_OP_PD_SCSI 0x04
199 199 #define MFI_CMD_OP_DCMD 0x05
200 200 #define MFI_CMD_OP_ABORT 0x06
201 201 #define MFI_CMD_OP_SMP 0x07
202 202 #define MFI_CMD_OP_STP 0x08
203 203
204 204 #define MR_DCMD_CTRL_GET_INFO 0x01010000
205 205
206 206 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
207 207 #define MR_FLUSH_CTRL_CACHE 0x01
208 208 #define MR_FLUSH_DISK_CACHE 0x02
209 209
210 210 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
211 211 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01
212 212
213 213 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
214 214 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
215 215 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
216 216 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
217 217
218 218 /*
219 219 * Solaris Specific MAX values
220 220 */
221 221 #define MAX_SGL 24
222 222
223 223 /*
224 224 * MFI command completion codes
225 225 */
226 226 enum MFI_STAT {
227 227 MFI_STAT_OK = 0x00,
228 228 MFI_STAT_INVALID_CMD = 0x01,
229 229 MFI_STAT_INVALID_DCMD = 0x02,
230 230 MFI_STAT_INVALID_PARAMETER = 0x03,
231 231 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
232 232 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
233 233 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
234 234 MFI_STAT_APP_IN_USE = 0x07,
235 235 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
236 236 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
237 237 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
238 238 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
239 239 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
240 240 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
241 241 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
242 242 MFI_STAT_FLASH_BUSY = 0x0f,
243 243 MFI_STAT_FLASH_ERROR = 0x10,
244 244 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
245 245 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
246 246 MFI_STAT_FLASH_NOT_OPEN = 0x13,
247 247 MFI_STAT_FLASH_NOT_STARTED = 0x14,
248 248 MFI_STAT_FLUSH_FAILED = 0x15,
249 249 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
250 250 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
251 251 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
252 252 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
253 253 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
254 254 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
255 255 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
256 256 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
257 257 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
258 258 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
259 259 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
260 260 MFI_STAT_MFC_HW_ERROR = 0x21,
261 261 MFI_STAT_NO_HW_PRESENT = 0x22,
262 262 MFI_STAT_NOT_FOUND = 0x23,
263 263 MFI_STAT_NOT_IN_ENCL = 0x24,
264 264 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
265 265 MFI_STAT_PD_TYPE_WRONG = 0x26,
266 266 MFI_STAT_PR_DISABLED = 0x27,
267 267 MFI_STAT_ROW_INDEX_INVALID = 0x28,
268 268 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
269 269 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
270 270 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
271 271 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
272 272 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
273 273 MFI_STAT_SCSI_IO_FAILED = 0x2e,
274 274 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
275 275 MFI_STAT_SHUTDOWN_FAILED = 0x30,
276 276 MFI_STAT_TIME_NOT_SET = 0x31,
277 277 MFI_STAT_WRONG_STATE = 0x32,
278 278 MFI_STAT_LD_OFFLINE = 0x33,
279 279 MFI_STAT_INVALID_STATUS = 0xFF
280 280 };
281 281
282 282 enum MR_EVT_CLASS {
283 283 MR_EVT_CLASS_DEBUG = -2,
284 284 MR_EVT_CLASS_PROGRESS = -1,
285 285 MR_EVT_CLASS_INFO = 0,
286 286 MR_EVT_CLASS_WARNING = 1,
287 287 MR_EVT_CLASS_CRITICAL = 2,
288 288 MR_EVT_CLASS_FATAL = 3,
289 289 MR_EVT_CLASS_DEAD = 4
290 290 };
291 291
292 292 enum MR_EVT_LOCALE {
293 293 MR_EVT_LOCALE_LD = 0x0001,
294 294 MR_EVT_LOCALE_PD = 0x0002,
295 295 MR_EVT_LOCALE_ENCL = 0x0004,
296 296 MR_EVT_LOCALE_BBU = 0x0008,
297 297 MR_EVT_LOCALE_SAS = 0x0010,
298 298 MR_EVT_LOCALE_CTRL = 0x0020,
299 299 MR_EVT_LOCALE_CONFIG = 0x0040,
300 300 MR_EVT_LOCALE_CLUSTER = 0x0080,
301 301 MR_EVT_LOCALE_ALL = 0xffff
302 302 };
303 303
304 304 enum MR_EVT_ARGS {
305 305 MR_EVT_ARGS_NONE,
306 306 MR_EVT_ARGS_CDB_SENSE,
307 307 MR_EVT_ARGS_LD,
308 308 MR_EVT_ARGS_LD_COUNT,
309 309 MR_EVT_ARGS_LD_LBA,
310 310 MR_EVT_ARGS_LD_OWNER,
311 311 MR_EVT_ARGS_LD_LBA_PD_LBA,
312 312 MR_EVT_ARGS_LD_PROG,
313 313 MR_EVT_ARGS_LD_STATE,
314 314 MR_EVT_ARGS_LD_STRIP,
315 315 MR_EVT_ARGS_PD,
316 316 MR_EVT_ARGS_PD_ERR,
317 317 MR_EVT_ARGS_PD_LBA,
318 318 MR_EVT_ARGS_PD_LBA_LD,
319 319 MR_EVT_ARGS_PD_PROG,
320 320 MR_EVT_ARGS_PD_STATE,
321 321 MR_EVT_ARGS_PCI,
322 322 MR_EVT_ARGS_RATE,
323 323 MR_EVT_ARGS_STR,
324 324 MR_EVT_ARGS_TIME,
325 325 MR_EVT_ARGS_ECC
326 326 };
327 327
328 328 #define MR_EVT_CFG_CLEARED 0x0004
329 329 #define MR_EVT_LD_CREATED 0x008a
330 330 #define MR_EVT_LD_DELETED 0x008b
331 331 #define MR_EVT_CFG_FP_CHANGE 0x017B
332 332
333 333 enum LD_STATE {
334 334 LD_OFFLINE = 0,
335 335 LD_PARTIALLY_DEGRADED = 1,
336 336 LD_DEGRADED = 2,
337 337 LD_OPTIMAL = 3,
338 338 LD_INVALID = 0xFF
339 339 };
340 340
341 341 enum MRSAS_EVT {
342 342 MRSAS_EVT_CONFIG_TGT = 0,
343 343 MRSAS_EVT_UNCONFIG_TGT = 1,
344 344 MRSAS_EVT_UNCONFIG_SMP = 2
345 345 };
346 346
347 347 #define DMA_OBJ_ALLOCATED 1
348 348 #define DMA_OBJ_REALLOCATED 2
349 349 #define DMA_OBJ_FREED 3
350 350
351 351 /*
352 352 * dma_obj_t - Our DMA object
353 353 * @param buffer : kernel virtual address
354 354 * @param size : size of the data to be allocated
355 355 * @param acc_handle : access handle
356 356 * @param dma_handle : dma handle
357 357 * @param dma_cookie : scatter-gather list
358 358 * @param dma_attr : dma attributes for this buffer
359 359 *
360 360 * Our DMA object. The caller must initialize the size and dma attributes
361 361 * (dma_attr) fields before allocating the resources.
362 362 */
363 363 typedef struct {
364 364 caddr_t buffer;
365 365 uint32_t size;
366 366 ddi_acc_handle_t acc_handle;
367 367 ddi_dma_handle_t dma_handle;
368 368 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT];
369 369 ddi_dma_attr_t dma_attr;
370 370 uint8_t status;
371 371 uint8_t reserved[3];
372 372 } dma_obj_t;
373 373
374 374 struct mrsas_eventinfo {
375 375 struct mrsas_instance *instance;
376 376 int tgt;
377 377 int lun;
378 378 int event;
379 379 uint64_t wwn;
380 380 };
381 381
382 382 struct mrsas_ld {
383 383 dev_info_t *dip;
384 384 uint8_t lun_type;
385 385 uint8_t flag;
386 386 uint8_t reserved[2];
387 387 };
388 388
389 389
390 390 #ifdef PDSUPPORT
391 391 struct mrsas_tbolt_pd {
392 392 dev_info_t *dip;
393 393 uint8_t lun_type;
394 394 uint8_t dev_id;
395 395 uint8_t flag;
396 396 uint8_t reserved;
397 397 };
398 398 struct mrsas_tbolt_pd_info {
399 399 uint16_t deviceId;
400 400 uint16_t seqNum;
401 401 uint8_t inquiryData[96];
402 402 uint8_t vpdPage83[64];
403 403 uint8_t notSupported;
404 404 uint8_t scsiDevType;
405 405 uint8_t a;
406 406 uint8_t device_speed;
407 407 uint32_t mediaerrcnt;
408 408 uint32_t other;
409 409 uint32_t pred;
410 410 uint32_t lastpred;
411 411 uint16_t fwState;
412 412 uint8_t disabled;
413 413 uint8_t linkspwwd;
414 414 uint32_t ddfType;
415 415 struct {
416 416 uint8_t count;
417 417 uint8_t isPathBroken;
418 418 uint8_t connectorIndex[2];
419 419 uint8_t reserved[4];
420 420 uint64_t sasAddr[2];
421 421 uint8_t reserved2[16];
422 422 } pathInfo;
423 423 };
424 424 #endif
425 425
426 426 typedef struct mrsas_instance {
427 427 uint32_t *producer;
428 428 uint32_t *consumer;
429 429
430 430 uint32_t *reply_queue;
431 431 dma_obj_t mfi_internal_dma_obj;
432 432 uint16_t adapterresetinprogress;
433 433 uint16_t deadadapter;
434 434 /* ThunderBolt (TB) specific */
435 435 dma_obj_t mpi2_frame_pool_dma_obj;
436 436 dma_obj_t request_desc_dma_obj;
437 437 dma_obj_t reply_desc_dma_obj;
438 438 dma_obj_t ld_map_obj[2];
439 439
440 440 uint8_t init_id;
441 441 uint8_t flag_ieee;
442 442 uint8_t disable_online_ctrl_reset;
443 443 uint8_t fw_fault_count_after_ocr;
444 444
445 445 uint16_t max_num_sge;
446 446 uint16_t max_fw_cmds;
447 447 uint32_t max_sectors_per_req;
448 448
449 449 struct mrsas_cmd **cmd_list;
450 450
451 451 mlist_t cmd_pool_list;
452 452 kmutex_t cmd_pool_mtx;
453 453 kmutex_t sync_map_mtx;
454 454
455 455 mlist_t app_cmd_pool_list;
456 456 kmutex_t app_cmd_pool_mtx;
457 457 mlist_t cmd_app_pool_list;
458 458 kmutex_t cmd_app_pool_mtx;
459 459
460 460
461 461 mlist_t cmd_pend_list;
462 462 kmutex_t cmd_pend_mtx;
463 463
464 464 dma_obj_t mfi_evt_detail_obj;
465 465 struct mrsas_cmd *aen_cmd;
466 466
467 467 uint32_t aen_seq_num;
468 468 uint32_t aen_class_locale_word;
469 469
470 470 scsi_hba_tran_t *tran;
471 471
472 472 kcondvar_t int_cmd_cv;
473 473 kmutex_t int_cmd_mtx;
474 474
475 475 kcondvar_t aen_cmd_cv;
476 476 kmutex_t aen_cmd_mtx;
477 477
478 478 kcondvar_t abort_cmd_cv;
479 479 kmutex_t abort_cmd_mtx;
480 480
481 481 kmutex_t reg_write_mtx;
482 482 kmutex_t chip_mtx;
483 483
484 484 dev_info_t *dip;
485 485 ddi_acc_handle_t pci_handle;
486 486
487 487 timeout_id_t timeout_id;
488 488 uint32_t unique_id;
489 489 uint16_t fw_outstanding;
490 490 caddr_t regmap;
491 491 ddi_acc_handle_t regmap_handle;
492 492 uint8_t isr_level;
493 493 ddi_iblock_cookie_t iblock_cookie;
494 494 ddi_iblock_cookie_t soft_iblock_cookie;
495 495 ddi_softintr_t soft_intr_id;
496 496 uint8_t softint_running;
497 497 uint8_t tbolt_softint_running;
498 498 kmutex_t completed_pool_mtx;
499 499 mlist_t completed_pool_list;
500 500
501 501 caddr_t internal_buf;
502 502 uint32_t internal_buf_dmac_add;
503 503 uint32_t internal_buf_size;
504 504
505 505 uint16_t vendor_id;
506 506 uint16_t device_id;
507 507 uint16_t subsysvid;
508 508 uint16_t subsysid;
509 509 int instance;
510 510 int baseaddress;
511 511 char iocnode[16];
512 512
513 513 /*Driver resources unroll flags.
514 514 The flag is set for resources that are needed to be free'd at detach() time */
515 515
516 516 struct _unroll {
517 517 uint8_t softs; // The software state was allocated.
518 518 uint8_t regs; // Controller registers mapped.
519 519 uint8_t intr; // Interrupt handler added.
520 520 uint8_t reqs; // Request structs allocated.
521 521 uint8_t mutexs; // Mutex's allocated.
522 522 uint8_t taskq; // Task q's created.
523 523 uint8_t tran; // Tran struct allocated
524 524 uint8_t tranSetup; // Tran attached to the ddi.
525 525 uint8_t devctl; // Device nodes for cfgadm created.
526 526 uint8_t scsictl; // Device nodes for cfgadm created.
527 527 uint8_t ioctl; // Device nodes for ioctl's created.
528 528 uint8_t timer; // Timer started.
529 529 uint8_t aenPend; // AEN cmd pending f/w.
530 530 uint8_t mapUpdate_pend; // LD MAP update cmd pending f/w.
531 531 uint8_t soft_isr;
532 532 uint8_t ldlist_buff;
533 533 uint8_t pdlist_buff;
534 534 uint8_t syncCmd;
535 535 uint8_t verBuff;
536 536 uint8_t alloc_space_mfi;
537 537 uint8_t alloc_space_mpi2;
538 538 } unroll;
539 539
540 540
541 541 /* function template pointer */
542 542 struct mrsas_function_template *func_ptr;
543 543
544 544
545 545 /* MSI interrupts specific */
546 546 ddi_intr_handle_t *intr_htable; //Interrupt handle array
547 547 size_t intr_htable_size; //Interrupt handle array size
548 548 int intr_type;
549 549 int intr_cnt;
550 550 uint_t intr_pri;
551 551 int intr_cap;
552 552
553 553 ddi_taskq_t *taskq;
554 554 struct mrsas_ld *mr_ld_list;
555 555 kmutex_t config_dev_mtx;
556 556 /* ThunderBolt (TB) specific */
557 557 ddi_softintr_t tbolt_soft_intr_id;
558 558
559 559 #ifdef PDSUPPORT
560 560 uint32_t mr_tbolt_pd_max;
561 561 struct mrsas_tbolt_pd *mr_tbolt_pd_list;
562 562 #endif
563 563
564 564 uint8_t fast_path_io;
565 565
566 566 uint16_t tbolt;
567 567 uint16_t reply_read_index;
568 568 uint16_t reply_size; // Single Reply structure size
569 569 uint16_t raid_io_msg_size; // Single message size
570 570 uint32_t io_request_frames_phy;
571 571 uint8_t *io_request_frames;
572 572 MRSAS_REQUEST_DESCRIPTOR_UNION *request_message_pool; // Virtual address of request desc frame pool
573 573 uint32_t request_message_pool_phy; // Physical address of request desc frame pool
574 574 MPI2_REPLY_DESCRIPTORS_UNION *reply_frame_pool; // Virtual address of reply Frame
575 575 uint32_t reply_frame_pool_phy; // Physical address of reply Frame
576 576 uint8_t *reply_pool_limit; // Last reply frame address
577 577 uint32_t reply_pool_limit_phy; // Physical address of Last reply frame
578 578 uint32_t reply_q_depth; // Reply Queue Depth
579 579 uint8_t max_sge_in_main_msg;
580 580 uint8_t max_sge_in_chain;
581 581 uint8_t chain_offset_io_req;
582 582 uint8_t chain_offset_mpt_msg;
583 583 MR_FW_RAID_MAP_ALL *ld_map[2];
584 584 uint32_t ld_map_phy[2];
585 585 uint32_t size_map_info;
586 586 uint64_t map_id;
587 587 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
588 588 struct mrsas_cmd *map_update_cmd;
589 589 uint32_t SyncRequired;
590 590 kmutex_t ocr_flags_mtx;
591 591 dma_obj_t drv_ver_dma_obj;
592 592 } mrsas_t;
593 593
594 594
595 595 /*
596 596 * Function templates for various controller specific functions
597 597 */
598 598 struct mrsas_function_template {
599 599 uint32_t (*read_fw_status_reg)(struct mrsas_instance *);
600 600 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *);
601 601 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
602 602 struct mrsas_cmd *);
603 603 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
604 604 struct mrsas_cmd *);
605 605 void (*enable_intr)(struct mrsas_instance *);
606 606 void (*disable_intr)(struct mrsas_instance *);
607 607 int (*intr_ack)(struct mrsas_instance *);
608 608 int (*init_adapter)(struct mrsas_instance *);
609 609 // int (*reset_adapter)(struct mrsas_instance *);
610 610 };
611 611
612 612 /*
613 613 * ### Helper routines ###
614 614 */
615 615
616 616 /*
617 617 * con_log() - console log routine
618 618 * @param level : indicates the severity of the message.
619 619 * @fparam mt : format string
620 620 *
621 621 * con_log displays the error messages on the console based on the current
622 622 * debug level. Also it attaches the appropriate kernel severity level with
623 623 * the message.
624 624 *
625 625 *
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625 lines elided |
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626 626 * console messages debug levels
627 627 */
628 628 #define CL_NONE 0 /* No debug information */
629 629 #define CL_ANN 1 /* print unconditionally, announcements */
630 630 #define CL_ANN1 2 /* No o/p */
631 631 #define CL_DLEVEL1 3 /* debug level 1, informative */
632 632 #define CL_DLEVEL2 4 /* debug level 2, verbose */
633 633 #define CL_DLEVEL3 5 /* debug level 3, very verbose */
634 634
635 635 #ifdef __SUNPRO_C
636 -#define __func__ __FUNCTION__ //""
636 +#define __func__ ""
637 637 #endif
638 638
639 639 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
640 640
641 641 /*
642 642 * ### SCSA definitions ###
643 643 */
644 644 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target)
645 645 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun)
646 646 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran)
647 647 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
648 648
649 649 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private)
650 650 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap))
651 651
652 652 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private)
653 653 #define CMD2PKT(sp) ((sp)->cmd_pkt)
654 654 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request))
655 655
656 656 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address)
657 657 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran)
658 658 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd)))
659 659
660 660 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */
661 661 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */
662 662 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */
663 663
664 664 /*
665 665 * ### Data structures for ioctl inteface and internal commands ###
666 666 */
667 667
668 668 /*
669 669 * Data direction flags
670 670 */
671 671 #define UIOC_RD 0x00001
672 672 #define UIOC_WR 0x00002
673 673
674 674 #define SCP2HOST(scp) (scp)->device->host /* to host */
675 675 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */
676 676 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */
677 677 #define SCP2TARGET(scp) (scp)->device->id /* to target */
678 678 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */
679 679
680 680 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
681 681 #define SCP2ADAPTER(scp) \
682 682 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
683 683
684 684 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \
685 685 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0
686 686 #define MRDRV_IS_LOGICAL(ap) \
687 687 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0
688 688 #define MAP_DEVICE_ID(instance, ap) \
689 689 (ap->a_target)
690 690
691 691 #define HIGH_LEVEL_INTR 1
692 692 #define NORMAL_LEVEL_INTR 0
693 693
694 694 #define IO_TIMEOUT_VAL 0
695 695 #define IO_RETRY_COUNT 3
696 696 #define MAX_FW_RESET_COUNT 3
697 697 /*
698 698 * scsa_cmd - Per-command mr private data
699 699 * @param cmd_dmahandle : dma handle
700 700 * @param cmd_dmacookies : current dma cookies
701 701 * @param cmd_pkt : scsi_pkt reference
702 702 * @param cmd_dmacount : dma count
703 703 * @param cmd_cookie : next cookie
704 704 * @param cmd_ncookies : cookies per window
705 705 * @param cmd_cookiecnt : cookies per sub-win
706 706 * @param cmd_nwin : number of dma windows
707 707 * @param cmd_curwin : current dma window
708 708 * @param cmd_dma_offset : current window offset
709 709 * @param cmd_dma_len : current window length
710 710 * @param cmd_flags : private flags
711 711 * @param cmd_cdblen : length of cdb
712 712 * @param cmd_scblen : length of scb
713 713 * @param cmd_buf : command buffer
714 714 * @param channel : channel for scsi sub-system
715 715 * @param target : target for scsi sub-system
716 716 * @param lun : LUN for scsi sub-system
717 717 *
718 718 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E)
719 719 * - Pointed to by pkt_ha_private field in scsi_pkt
720 720 */
721 721 struct scsa_cmd {
722 722 ddi_dma_handle_t cmd_dmahandle;
723 723 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT];
724 724 struct scsi_pkt *cmd_pkt;
725 725 ulong_t cmd_dmacount;
726 726 uint_t cmd_cookie;
727 727 uint_t cmd_ncookies;
728 728 uint_t cmd_cookiecnt;
729 729 uint_t cmd_nwin;
730 730 uint_t cmd_curwin;
731 731 off_t cmd_dma_offset;
732 732 ulong_t cmd_dma_len;
733 733 ulong_t cmd_flags;
734 734 uint_t cmd_cdblen;
735 735 uint_t cmd_scblen;
736 736 struct buf *cmd_buf;
737 737 ushort_t device_id;
738 738 uchar_t islogical;
739 739 uchar_t lun;
740 740 struct mrsas_device *mrsas_dev;
741 741 };
742 742
743 743
744 744 struct mrsas_cmd {
745 745 /*
746 746 * ThunderBolt(TB) We would be needing to have a placeholder
747 747 * for RAID_MSG_IO_REQUEST inside this structure. We are
748 748 * supposed to embed the mr_frame inside the RAID_MSG and post
749 749 * it down to the firmware.
750 750 */
751 751 union mrsas_frame *frame;
752 752 uint32_t frame_phys_addr;
753 753 uint8_t *sense;
754 754 uint8_t *sense1;
755 755 uint32_t sense_phys_addr;
756 756 uint32_t sense_phys_addr1;
757 757 dma_obj_t frame_dma_obj;
758 758 uint8_t frame_dma_obj_status;
759 759 uint32_t index;
760 760 uint8_t sync_cmd;
761 761 uint8_t cmd_status;
762 762 uint16_t abort_aen;
763 763 mlist_t list;
764 764 uint32_t frame_count;
765 765 struct scsa_cmd *cmd;
766 766 struct scsi_pkt *pkt;
767 767 Mpi2RaidSCSIIORequest_t *scsi_io_request;
768 768 Mpi2SGEIOUnion_t *sgl;
769 769 uint32_t sgl_phys_addr;
770 770 uint32_t scsi_io_request_phys_addr;
771 771 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
772 772 uint16_t SMID;
773 773 uint16_t retry_count_for_ocr;
774 774 uint16_t drv_pkt_time;
775 775 uint16_t load_balance_flag;
776 776
777 777 };
778 778
779 779 #define MAX_MGMT_ADAPTERS 1024
780 780 #define IOC_SIGNATURE "MR-SAS"
781 781
782 782 #define IOC_CMD_FIRMWARE 0x0
783 783 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000
784 784 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
785 785 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
786 786 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300
787 787
788 788
789 789 #define MRSAS_MAX_SENSE_LENGTH 32
790 790
791 791 struct mrsas_mgmt_info {
792 792
793 793 uint16_t count;
794 794 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS];
795 795 uint16_t map[MAX_MGMT_ADAPTERS];
796 796 int max_index;
797 797 };
798 798
799 799
800 800 #pragma pack(1)
801 801 /*
802 802 * SAS controller properties
803 803 */
804 804 struct mrsas_ctrl_prop {
805 805 uint16_t seq_num;
806 806 uint16_t pred_fail_poll_interval;
807 807 uint16_t intr_throttle_count;
808 808 uint16_t intr_throttle_timeouts;
809 809
810 810 uint8_t rebuild_rate;
811 811 uint8_t patrol_read_rate;
812 812 uint8_t bgi_rate;
813 813 uint8_t cc_rate;
814 814 uint8_t recon_rate;
815 815
816 816 uint8_t cache_flush_interval;
817 817
818 818 uint8_t spinup_drv_count;
819 819 uint8_t spinup_delay;
820 820
821 821 uint8_t cluster_enable;
822 822 uint8_t coercion_mode;
823 823 uint8_t alarm_enable;
824 824
825 825 uint8_t reserved_1[13];
826 826 uint32_t on_off_properties;
827 827 uint8_t reserved_4[28];
828 828 };
829 829
830 830
831 831 /*
832 832 * SAS controller information
833 833 */
834 834 struct mrsas_ctrl_info {
835 835 /* PCI device information */
836 836 struct {
837 837 uint16_t vendor_id;
838 838 uint16_t device_id;
839 839 uint16_t sub_vendor_id;
840 840 uint16_t sub_device_id;
841 841 uint8_t reserved[24];
842 842 } pci;
843 843
844 844 /* Host interface information */
845 845 struct {
846 846 uint8_t PCIX : 1;
847 847 uint8_t PCIE : 1;
848 848 uint8_t iSCSI : 1;
849 849 uint8_t SAS_3G : 1;
850 850 uint8_t reserved_0 : 4;
851 851 uint8_t reserved_1[6];
852 852 uint8_t port_count;
853 853 uint64_t port_addr[8];
854 854 } host_interface;
855 855
856 856 /* Device (backend) interface information */
857 857 struct {
858 858 uint8_t SPI : 1;
859 859 uint8_t SAS_3G : 1;
860 860 uint8_t SATA_1_5G : 1;
861 861 uint8_t SATA_3G : 1;
862 862 uint8_t reserved_0 : 4;
863 863 uint8_t reserved_1[6];
864 864 uint8_t port_count;
865 865 uint64_t port_addr[8];
866 866 } device_interface;
867 867
868 868 /* List of components residing in flash. All str are null terminated */
869 869 uint32_t image_check_word;
870 870 uint32_t image_component_count;
871 871
872 872 struct {
873 873 char name[8];
874 874 char version[32];
875 875 char build_date[16];
876 876 char built_time[16];
877 877 } image_component[8];
878 878
879 879 /*
880 880 * List of flash components that have been flashed on the card, but
881 881 * are not in use, pending reset of the adapter. This list will be
882 882 * empty if a flash operation has not occurred. All stings are null
883 883 * terminated
884 884 */
885 885 uint32_t pending_image_component_count;
886 886
887 887 struct {
888 888 char name[8];
889 889 char version[32];
890 890 char build_date[16];
891 891 char build_time[16];
892 892 } pending_image_component[8];
893 893
894 894 uint8_t max_arms;
895 895 uint8_t max_spans;
896 896 uint8_t max_arrays;
897 897 uint8_t max_lds;
898 898
899 899 char product_name[80];
900 900 char serial_no[32];
901 901
902 902 /*
903 903 * Other physical/controller/operation information. Indicates the
904 904 * presence of the hardware
905 905 */
906 906 struct {
907 907 uint32_t bbu : 1;
908 908 uint32_t alarm : 1;
909 909 uint32_t nvram : 1;
910 910 uint32_t uart : 1;
911 911 uint32_t reserved : 28;
912 912 } hw_present;
913 913
914 914 uint32_t current_fw_time;
915 915
916 916 /* Maximum data transfer sizes */
917 917 uint16_t max_concurrent_cmds;
918 918 uint16_t max_sge_count;
919 919 uint32_t max_request_size;
920 920
921 921 /* Logical and physical device counts */
922 922 uint16_t ld_present_count;
923 923 uint16_t ld_degraded_count;
924 924 uint16_t ld_offline_count;
925 925
926 926 uint16_t pd_present_count;
927 927 uint16_t pd_disk_present_count;
928 928 uint16_t pd_disk_pred_failure_count;
929 929 uint16_t pd_disk_failed_count;
930 930
931 931 /* Memory size information */
932 932 uint16_t nvram_size;
933 933 uint16_t memory_size;
934 934 uint16_t flash_size;
935 935
936 936 /* Error counters */
937 937 uint16_t mem_correctable_error_count;
938 938 uint16_t mem_uncorrectable_error_count;
939 939
940 940 /* Cluster information */
941 941 uint8_t cluster_permitted;
942 942 uint8_t cluster_active;
943 943 uint8_t reserved_1[2];
944 944
945 945 /* Controller capabilities structures */
946 946 struct {
947 947 uint32_t raid_level_0 : 1;
948 948 uint32_t raid_level_1 : 1;
949 949 uint32_t raid_level_5 : 1;
950 950 uint32_t raid_level_1E : 1;
951 951 uint32_t reserved : 28;
952 952 } raid_levels;
953 953
954 954 struct {
955 955 uint32_t rbld_rate : 1;
956 956 uint32_t cc_rate : 1;
957 957 uint32_t bgi_rate : 1;
958 958 uint32_t recon_rate : 1;
959 959 uint32_t patrol_rate : 1;
960 960 uint32_t alarm_control : 1;
961 961 uint32_t cluster_supported : 1;
962 962 uint32_t bbu : 1;
963 963 uint32_t spanning_allowed : 1;
964 964 uint32_t dedicated_hotspares : 1;
965 965 uint32_t revertible_hotspares : 1;
966 966 uint32_t foreign_config_import : 1;
967 967 uint32_t self_diagnostic : 1;
968 968 uint32_t reserved : 19;
969 969 } adapter_operations;
970 970
971 971 struct {
972 972 uint32_t read_policy : 1;
973 973 uint32_t write_policy : 1;
974 974 uint32_t io_policy : 1;
975 975 uint32_t access_policy : 1;
976 976 uint32_t reserved : 28;
977 977 } ld_operations;
978 978
979 979 struct {
980 980 uint8_t min;
981 981 uint8_t max;
982 982 uint8_t reserved[2];
983 983 } stripe_size_operations;
984 984
985 985 struct {
986 986 uint32_t force_online : 1;
987 987 uint32_t force_offline : 1;
988 988 uint32_t force_rebuild : 1;
989 989 uint32_t reserved : 29;
990 990 } pd_operations;
991 991
992 992 struct {
993 993 uint32_t ctrl_supports_sas : 1;
994 994 uint32_t ctrl_supports_sata : 1;
995 995 uint32_t allow_mix_in_encl : 1;
996 996 uint32_t allow_mix_in_ld : 1;
997 997 uint32_t allow_sata_in_cluster : 1;
998 998 uint32_t reserved : 27;
999 999 } pd_mix_support;
1000 1000
1001 1001 /* Include the controller properties (changeable items) */
1002 1002 uint8_t reserved_2[12];
1003 1003 struct mrsas_ctrl_prop properties;
1004 1004
1005 1005 uint8_t pad[0x800 - 0x640];
1006 1006 };
1007 1007
1008 1008 /*
1009 1009 * ==================================
1010 1010 * MegaRAID SAS2.0 driver definitions
1011 1011 * ==================================
1012 1012 */
1013 1013 #define MRDRV_MAX_NUM_CMD 1024
1014 1014
1015 1015 #define MRDRV_MAX_PD_CHANNELS 2
1016 1016 #define MRDRV_MAX_LD_CHANNELS 2
1017 1017 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \
1018 1018 MRDRV_MAX_LD_CHANNELS)
1019 1019 #define MRDRV_MAX_DEV_PER_CHANNEL 128
1020 1020 #define MRDRV_DEFAULT_INIT_ID -1
1021 1021 #define MRDRV_MAX_CMD_PER_LUN 1000
1022 1022 #define MRDRV_MAX_LUN 1
1023 1023 #define MRDRV_MAX_LD 64
1024 1024
1025 1025 #define MRDRV_RESET_WAIT_TIME 300
1026 1026 #define MRDRV_RESET_NOTICE_INTERVAL 5
1027 1027
1028 1028 #define MRSAS_IOCTL_CMD 0
1029 1029
1030 1030 #define MRDRV_TGT_VALID 1
1031 1031
1032 1032 /*
1033 1033 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1034 1034 * SGLs based on the size of dma_addr_t
1035 1035 */
1036 1036 #define IS_DMA64 (sizeof (dma_addr_t) == 8)
1037 1037
1038 1038 #define RESERVED0_REGISTER 0x00 /* XScale */
1039 1039 #define IB_MSG_0_OFF 0x10 /* XScale */
1040 1040 #define OB_MSG_0_OFF 0x18 /* XScale */
1041 1041 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */
1042 1042 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */
1043 1043 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */
1044 1044 #define IB_QPORT_OFF 0x40 /* XScale & ROC */
1045 1045 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */
1046 1046 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */
1047 1047 #define OB_INTR_MASK 0xFFFFFFFF
1048 1048 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF
1049 1049 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1050 1050 #define OB_SCRATCH_PAD_2_OFF 0xB4
1051 1051 #define WRITE_TBOLT_SEQ_OFF 0x00000004
1052 1052 #define DIAG_TBOLT_RESET_ADAPTER 0x00000004
1053 1053 #define HOST_TBOLT_DIAG_OFF 0x00000008
1054 1054 #define RESET_TBOLT_STATUS_OFF 0x000003C3
1055 1055 #define WRITE_SEQ_OFF 0x000000FC
1056 1056 #define HOST_DIAG_OFF 0x000000F8
1057 1057 #define DIAG_RESET_ADAPTER 0x00000004
1058 1058 #define DIAG_WRITE_ENABLE 0x00000080
1059 1059 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1060 1060
1061 1061 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \
1062 1062 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v))
1063 1063
1064 1064 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \
1065 1065 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF))
1066 1066
1067 1067 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \
1068 1068 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v))
1069 1069
1070 1070 #define IB_LOW_QPORT 0xC0
1071 1071 #define IB_HIGH_QPORT 0xC4
1072 1072 #define OB_DOORBELL_REGISTER 0x9C /* 1078 implementation */
1073 1073
1074 1074 /*
1075 1075 * All MFI register set macros accept mrsas_register_set*
1076 1076 */
1077 1077 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \
1078 1078 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
1079 1079
1080 1080 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \
1081 1081 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
1082 1082
1083 1083 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \
1084 1084 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
1085 1085
1086 1086 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \
1087 1087 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
1088 1088
1089 1089 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \
1090 1090 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
1091 1091
1092 1092 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \
1093 1093 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
1094 1094
1095 1095 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \
1096 1096 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
1097 1097
1098 1098 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \
1099 1099 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
1100 1100
1101 1101 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1102 1102 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
1103 1103
1104 1104 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
1105 1105 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
1106 1106 (v))
1107 1107
1108 1108 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \
1109 1109 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
1110 1110
1111 1111 /* Thunderbolt specific registers */
1112 1112 #define RD_OB_SCRATCH_PAD_2(instance) ddi_get32((instance)->regmap_handle, \
1113 1113 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_2_OFF))
1114 1114
1115 1115 #define WR_TBOLT_IB_WRITE_SEQ(v, instance) \
1116 1116 ddi_put32((instance)->regmap_handle, \
1117 1117 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_TBOLT_SEQ_OFF), (v))
1118 1118
1119 1119 #define RD_TBOLT_HOST_DIAG(instance) ddi_get32((instance)->regmap_handle, \
1120 1120 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF))
1121 1121
1122 1122 #define WR_TBOLT_HOST_DIAG(v, instance) ddi_put32((instance)->regmap_handle, \
1123 1123 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF), (v))
1124 1124
1125 1125 #define RD_TBOLT_RESET_STAT(instance) ddi_get32((instance)->regmap_handle, \
1126 1126 (uint32_t *)((uintptr_t)(instance)->regmap + RESET_TBOLT_STATUS_OFF))
1127 1127
1128 1128
1129 1129 #define WR_MPI2_REPLY_POST_INDEX(v, instance)\
1130 1130 ddi_put32((instance)->regmap_handle,\
1131 1131 (uint32_t *)\
1132 1132 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET),\
1133 1133 (v))
1134 1134
1135 1135
1136 1136 #define RD_MPI2_REPLY_POST_INDEX(instance)\
1137 1137 ddi_get32((instance)->regmap_handle,\
1138 1138 (uint32_t *)\
1139 1139 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET))
1140 1140
1141 1141 #define WR_IB_LOW_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1142 1142 (uint32_t *)((uintptr_t)(instance)->regmap + IB_LOW_QPORT), (v))
1143 1143
1144 1144 #define WR_IB_HIGH_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1145 1145 (uint32_t *)((uintptr_t)(instance)->regmap + IB_HIGH_QPORT), (v))
1146 1146
1147 1147 #define WR_OB_DOORBELL_REGISTER_CLEAR(v, instance)\
1148 1148 ddi_put32((instance)->regmap_handle,\
1149 1149 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_REGISTER), \
1150 1150 (v))
1151 1151
1152 1152 #define WR_RESERVED0_REGISTER(v, instance) ddi_put32((instance)->regmap_handle,\
1153 1153 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER), \
1154 1154 (v))
1155 1155
1156 1156 #define RD_RESERVED0_REGISTER(instance) ddi_get32((instance)->regmap_handle, \
1157 1157 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER))
1158 1158
1159 1159
1160 1160
1161 1161 /*
1162 1162 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
1163 1163 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
1164 1164 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
1165 1165 */
1166 1166 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1167 1167
1168 1168 /*
1169 1169 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also
1170 1170 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
1171 1171 * been set in this flag along with bit 1.
1172 1172 */
1173 1173 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001
1174 1174 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005
1175 1175
1176 1176 /* Fusion interrupt mask */
1177 1177 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008)
1178 1178
1179 1179 #define MFI_POLL_TIMEOUT_SECS 60
1180 1180
1181 1181 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \
1182 1182 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
1183 1183 #define MFI_DISABLE_INTR(instance) \
1184 1184 { \
1185 1185 uint32_t disable = 1; \
1186 1186 uint32_t mask = ddi_get32((instance)->regmap_handle, \
1187 1187 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
1188 1188 mask &= ~disable; \
1189 1189 ddi_put32((instance)->regmap_handle, (uint32_t *) \
1190 1190 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \
1191 1191 }
1192 1192
1193 1193 /* By default, the firmware programs for 8 Kbytes of memory */
1194 1194 #define DEFAULT_MFI_MEM_SZ 8192
1195 1195 #define MINIMUM_MFI_MEM_SZ 4096
1196 1196
1197 1197 /* DCMD Message Frame MAILBOX0-11 */
1198 1198 #define DCMD_MBOX_SZ 12
1199 1199
1200 1200 /*
1201 1201 * on_off_property of mrsas_ctrl_prop
1202 1202 * bit0-9, 11-31 are reserved
1203 1203 */
1204 1204 #define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */
1205 1205
1206 1206 struct mrsas_register_set {
1207 1207 uint32_t reserved_0[4]; /* 0000h */
1208 1208
1209 1209 uint32_t inbound_msg_0; /* 0010h */
1210 1210 uint32_t inbound_msg_1; /* 0014h */
1211 1211 uint32_t outbound_msg_0; /* 0018h */
1212 1212 uint32_t outbound_msg_1; /* 001Ch */
1213 1213
1214 1214 uint32_t inbound_doorbell; /* 0020h */
1215 1215 uint32_t inbound_intr_status; /* 0024h */
1216 1216 uint32_t inbound_intr_mask; /* 0028h */
1217 1217
1218 1218 uint32_t outbound_doorbell; /* 002Ch */
1219 1219 uint32_t outbound_intr_status; /* 0030h */
1220 1220 uint32_t outbound_intr_mask; /* 0034h */
1221 1221
1222 1222 uint32_t reserved_1[2]; /* 0038h */
1223 1223
1224 1224 uint32_t inbound_queue_port; /* 0040h */
1225 1225 uint32_t outbound_queue_port; /* 0044h */
1226 1226
1227 1227 uint32_t reserved_2[22]; /* 0048h */
1228 1228
1229 1229 uint32_t outbound_doorbell_clear; /* 00A0h */
1230 1230
1231 1231 uint32_t reserved_3[3]; /* 00A4h */
1232 1232
1233 1233 uint32_t outbound_scratch_pad; /* 00B0h */
1234 1234
1235 1235 uint32_t reserved_4[3]; /* 00B4h */
1236 1236
1237 1237 uint32_t inbound_low_queue_port; /* 00C0h */
1238 1238
1239 1239 uint32_t inbound_high_queue_port; /* 00C4h */
1240 1240
1241 1241 uint32_t reserved_5; /* 00C8h */
1242 1242 uint32_t index_registers[820]; /* 00CCh */
1243 1243 };
1244 1244
1245 1245 struct mrsas_sge32 {
1246 1246 uint32_t phys_addr;
1247 1247 uint32_t length;
1248 1248 };
1249 1249
1250 1250 struct mrsas_sge64 {
1251 1251 uint64_t phys_addr;
1252 1252 uint32_t length;
1253 1253 };
1254 1254
1255 1255 struct mrsas_sge_ieee {
1256 1256 uint64_t phys_addr;
1257 1257 uint32_t length;
1258 1258 uint32_t flag;
1259 1259 };
1260 1260
1261 1261 union mrsas_sgl {
1262 1262 struct mrsas_sge32 sge32[1];
1263 1263 struct mrsas_sge64 sge64[1];
1264 1264 struct mrsas_sge_ieee sge_ieee[1];
1265 1265 };
1266 1266
1267 1267 struct mrsas_header {
1268 1268 uint8_t cmd; /* 00h */
1269 1269 uint8_t sense_len; /* 01h */
1270 1270 uint8_t cmd_status; /* 02h */
1271 1271 uint8_t scsi_status; /* 03h */
1272 1272
1273 1273 uint8_t target_id; /* 04h */
1274 1274 uint8_t lun; /* 05h */
1275 1275 uint8_t cdb_len; /* 06h */
1276 1276 uint8_t sge_count; /* 07h */
1277 1277
1278 1278 uint32_t context; /* 08h */
1279 1279 uint8_t req_id; /* 0Ch */
1280 1280 uint8_t msgvector; /* 0Dh */
1281 1281 uint16_t pad_0; /* 0Eh */
1282 1282
1283 1283 uint16_t flags; /* 10h */
1284 1284 uint16_t timeout; /* 12h */
1285 1285 uint32_t data_xferlen; /* 14h */
1286 1286 };
1287 1287
1288 1288 union mrsas_sgl_frame {
1289 1289 struct mrsas_sge32 sge32[8];
1290 1290 struct mrsas_sge64 sge64[5];
1291 1291 };
1292 1292
1293 1293 struct mrsas_init_frame {
1294 1294 uint8_t cmd; /* 00h */
1295 1295 uint8_t reserved_0; /* 01h */
1296 1296 uint8_t cmd_status; /* 02h */
1297 1297
1298 1298 uint8_t reserved_1; /* 03h */
1299 1299 uint32_t reserved_2; /* 04h */
1300 1300
1301 1301 uint32_t context; /* 08h */
1302 1302 uint8_t req_id; /* 0Ch */
1303 1303 uint8_t msgvector; /* 0Dh */
1304 1304 uint16_t pad_0; /* 0Eh */
1305 1305
1306 1306 uint16_t flags; /* 10h */
1307 1307 uint16_t reserved_3; /* 12h */
1308 1308 uint32_t data_xfer_len; /* 14h */
1309 1309
1310 1310 uint32_t queue_info_new_phys_addr_lo; /* 18h */
1311 1311 uint32_t queue_info_new_phys_addr_hi; /* 1Ch */
1312 1312 uint32_t queue_info_old_phys_addr_lo; /* 20h */
1313 1313 uint32_t queue_info_old_phys_addr_hi; /* 24h */
1314 1314 uint64_t driverversion; /* 28h */
1315 1315 uint32_t reserved_4[4]; /* 30h */
1316 1316 };
1317 1317
1318 1318 struct mrsas_init_queue_info {
1319 1319 uint32_t init_flags; /* 00h */
1320 1320 uint32_t reply_queue_entries; /* 04h */
1321 1321
1322 1322 uint32_t reply_queue_start_phys_addr_lo; /* 08h */
1323 1323 uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */
1324 1324 uint32_t producer_index_phys_addr_lo; /* 10h */
1325 1325 uint32_t producer_index_phys_addr_hi; /* 14h */
1326 1326 uint32_t consumer_index_phys_addr_lo; /* 18h */
1327 1327 uint32_t consumer_index_phys_addr_hi; /* 1Ch */
1328 1328 };
1329 1329
1330 1330 struct mrsas_io_frame {
1331 1331 uint8_t cmd; /* 00h */
1332 1332 uint8_t sense_len; /* 01h */
1333 1333 uint8_t cmd_status; /* 02h */
1334 1334 uint8_t scsi_status; /* 03h */
1335 1335
1336 1336 uint8_t target_id; /* 04h */
1337 1337 uint8_t access_byte; /* 05h */
1338 1338 uint8_t reserved_0; /* 06h */
1339 1339 uint8_t sge_count; /* 07h */
1340 1340
1341 1341 uint32_t context; /* 08h */
1342 1342 uint8_t req_id; /* 0Ch */
1343 1343 uint8_t msgvector; /* 0Dh */
1344 1344 uint16_t pad_0; /* 0Eh */
1345 1345
1346 1346 uint16_t flags; /* 10h */
1347 1347 uint16_t timeout; /* 12h */
1348 1348 uint32_t lba_count; /* 14h */
1349 1349
1350 1350 uint32_t sense_buf_phys_addr_lo; /* 18h */
1351 1351 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1352 1352
1353 1353 uint32_t start_lba_lo; /* 20h */
1354 1354 uint32_t start_lba_hi; /* 24h */
1355 1355
1356 1356 union mrsas_sgl sgl; /* 28h */
1357 1357 };
1358 1358
1359 1359 struct mrsas_pthru_frame {
1360 1360 uint8_t cmd; /* 00h */
1361 1361 uint8_t sense_len; /* 01h */
1362 1362 uint8_t cmd_status; /* 02h */
1363 1363 uint8_t scsi_status; /* 03h */
1364 1364
1365 1365 uint8_t target_id; /* 04h */
1366 1366 uint8_t lun; /* 05h */
1367 1367 uint8_t cdb_len; /* 06h */
1368 1368 uint8_t sge_count; /* 07h */
1369 1369
1370 1370 uint32_t context; /* 08h */
1371 1371 uint8_t req_id; /* 0Ch */
1372 1372 uint8_t msgvector; /* 0Dh */
1373 1373 uint16_t pad_0; /* 0Eh */
1374 1374
1375 1375 uint16_t flags; /* 10h */
1376 1376 uint16_t timeout; /* 12h */
1377 1377 uint32_t data_xfer_len; /* 14h */
1378 1378
1379 1379 uint32_t sense_buf_phys_addr_lo; /* 18h */
1380 1380 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1381 1381
1382 1382 uint8_t cdb[16]; /* 20h */
1383 1383 union mrsas_sgl sgl; /* 30h */
1384 1384 };
1385 1385
1386 1386 struct mrsas_dcmd_frame {
1387 1387 uint8_t cmd; /* 00h */
1388 1388 uint8_t reserved_0; /* 01h */
1389 1389 uint8_t cmd_status; /* 02h */
1390 1390 uint8_t reserved_1[4]; /* 03h */
1391 1391 uint8_t sge_count; /* 07h */
1392 1392
1393 1393 uint32_t context; /* 08h */
1394 1394 uint8_t req_id; /* 0Ch */
1395 1395 uint8_t msgvector; /* 0Dh */
1396 1396 uint16_t pad_0; /* 0Eh */
1397 1397
1398 1398 uint16_t flags; /* 10h */
1399 1399 uint16_t timeout; /* 12h */
1400 1400
1401 1401 uint32_t data_xfer_len; /* 14h */
1402 1402 uint32_t opcode; /* 18h */
1403 1403
1404 1404 /* uint8_t mbox[DCMD_MBOX_SZ]; */ /* 1Ch */
1405 1405 union { /* 1Ch */
1406 1406 uint8_t b[DCMD_MBOX_SZ];
1407 1407 uint16_t s[6];
1408 1408 uint32_t w[3];
1409 1409 } mbox;
1410 1410
1411 1411 union mrsas_sgl sgl; /* 28h */
1412 1412 };
1413 1413
1414 1414 struct mrsas_abort_frame {
1415 1415 uint8_t cmd; /* 00h */
1416 1416 uint8_t reserved_0; /* 01h */
1417 1417 uint8_t cmd_status; /* 02h */
1418 1418
1419 1419 uint8_t reserved_1; /* 03h */
1420 1420 uint32_t reserved_2; /* 04h */
1421 1421
1422 1422 uint32_t context; /* 08h */
1423 1423 uint8_t req_id; /* 0Ch */
1424 1424 uint8_t msgvector; /* 0Dh */
1425 1425 uint16_t pad_0; /* 0Eh */
1426 1426
1427 1427 uint16_t flags; /* 10h */
1428 1428 uint16_t reserved_3; /* 12h */
1429 1429 uint32_t reserved_4; /* 14h */
1430 1430
1431 1431 uint32_t abort_context; /* 18h */
1432 1432 uint32_t pad_1; /* 1Ch */
1433 1433
1434 1434 uint32_t abort_mfi_phys_addr_lo; /* 20h */
1435 1435 uint32_t abort_mfi_phys_addr_hi; /* 24h */
1436 1436
1437 1437 uint32_t reserved_5[6]; /* 28h */
1438 1438 };
1439 1439
1440 1440 struct mrsas_smp_frame {
1441 1441 uint8_t cmd; /* 00h */
1442 1442 uint8_t reserved_1; /* 01h */
1443 1443 uint8_t cmd_status; /* 02h */
1444 1444 uint8_t connection_status; /* 03h */
1445 1445
1446 1446 uint8_t reserved_2[3]; /* 04h */
1447 1447 uint8_t sge_count; /* 07h */
1448 1448
1449 1449 uint32_t context; /* 08h */
1450 1450 uint8_t req_id; /* 0Ch */
1451 1451 uint8_t msgvector; /* 0Dh */
1452 1452 uint16_t pad_0; /* 0Eh */
1453 1453
1454 1454 uint16_t flags; /* 10h */
1455 1455 uint16_t timeout; /* 12h */
1456 1456
1457 1457 uint32_t data_xfer_len; /* 14h */
1458 1458
1459 1459 uint64_t sas_addr; /* 20h */
1460 1460
1461 1461 union mrsas_sgl sgl[2]; /* 28h */
1462 1462 };
1463 1463
1464 1464 struct mrsas_stp_frame {
1465 1465 uint8_t cmd; /* 00h */
1466 1466 uint8_t reserved_1; /* 01h */
1467 1467 uint8_t cmd_status; /* 02h */
1468 1468 uint8_t connection_status; /* 03h */
1469 1469
1470 1470 uint8_t target_id; /* 04h */
1471 1471 uint8_t reserved_2[2]; /* 04h */
1472 1472 uint8_t sge_count; /* 07h */
1473 1473
1474 1474 uint32_t context; /* 08h */
1475 1475 uint8_t req_id; /* 0Ch */
1476 1476 uint8_t msgvector; /* 0Dh */
1477 1477 uint16_t pad_0; /* 0Eh */
1478 1478
1479 1479 uint16_t flags; /* 10h */
1480 1480 uint16_t timeout; /* 12h */
1481 1481
1482 1482 uint32_t data_xfer_len; /* 14h */
1483 1483
1484 1484 uint16_t fis[10]; /* 28h */
1485 1485 uint32_t stp_flags; /* 3C */
1486 1486 union mrsas_sgl sgl; /* 40 */
1487 1487 };
1488 1488
1489 1489 union mrsas_frame {
1490 1490 struct mrsas_header hdr;
1491 1491 struct mrsas_init_frame init;
1492 1492 struct mrsas_io_frame io;
1493 1493 struct mrsas_pthru_frame pthru;
1494 1494 struct mrsas_dcmd_frame dcmd;
1495 1495 struct mrsas_abort_frame abort;
1496 1496 struct mrsas_smp_frame smp;
1497 1497 struct mrsas_stp_frame stp;
1498 1498
1499 1499 uint8_t raw_bytes[64];
1500 1500 };
1501 1501
1502 1502 typedef struct mrsas_pd_address {
1503 1503 uint16_t device_id;
1504 1504 uint16_t encl_id;
1505 1505
1506 1506 union {
1507 1507 struct {
1508 1508 uint8_t encl_index;
1509 1509 uint8_t slot_number;
1510 1510 } pd_address;
1511 1511 struct {
1512 1512 uint8_t encl_position;
1513 1513 uint8_t encl_connector_index;
1514 1514 } encl_address;
1515 1515 }address;
1516 1516
1517 1517 uint8_t scsi_dev_type;
1518 1518
1519 1519 union {
1520 1520 uint8_t port_bitmap;
1521 1521 uint8_t port_numbers;
1522 1522 } connected;
1523 1523
1524 1524 uint64_t sas_addr[2];
1525 1525 } mrsas_pd_address_t;
1526 1526
1527 1527 union mrsas_evt_class_locale {
1528 1528 struct {
1529 1529 uint16_t locale;
1530 1530 uint8_t reserved;
1531 1531 int8_t class;
1532 1532 } members;
1533 1533
1534 1534 uint32_t word;
1535 1535 };
1536 1536
1537 1537 struct mrsas_evt_log_info {
1538 1538 uint32_t newest_seq_num;
1539 1539 uint32_t oldest_seq_num;
1540 1540 uint32_t clear_seq_num;
1541 1541 uint32_t shutdown_seq_num;
1542 1542 uint32_t boot_seq_num;
1543 1543 };
1544 1544
1545 1545 struct mrsas_progress {
1546 1546 uint16_t progress;
1547 1547 uint16_t elapsed_seconds;
1548 1548 };
1549 1549
1550 1550 struct mrsas_evtarg_ld {
1551 1551 uint16_t target_id;
1552 1552 uint8_t ld_index;
1553 1553 uint8_t reserved;
1554 1554 };
1555 1555
1556 1556 struct mrsas_evtarg_pd {
1557 1557 uint16_t device_id;
1558 1558 uint8_t encl_index;
1559 1559 uint8_t slot_number;
1560 1560 };
1561 1561
1562 1562 struct mrsas_evt_detail {
1563 1563 uint32_t seq_num;
1564 1564 uint32_t time_stamp;
1565 1565 uint32_t code;
1566 1566 union mrsas_evt_class_locale cl;
1567 1567 uint8_t arg_type;
1568 1568 uint8_t reserved1[15];
1569 1569
1570 1570 union {
1571 1571 struct {
1572 1572 struct mrsas_evtarg_pd pd;
1573 1573 uint8_t cdb_length;
1574 1574 uint8_t sense_length;
1575 1575 uint8_t reserved[2];
1576 1576 uint8_t cdb[16];
1577 1577 uint8_t sense[64];
1578 1578 } cdbSense;
1579 1579
1580 1580 struct mrsas_evtarg_ld ld;
1581 1581
1582 1582 struct {
1583 1583 struct mrsas_evtarg_ld ld;
1584 1584 uint64_t count;
1585 1585 } ld_count;
1586 1586
1587 1587 struct {
1588 1588 uint64_t lba;
1589 1589 struct mrsas_evtarg_ld ld;
1590 1590 } ld_lba;
1591 1591
1592 1592 struct {
1593 1593 struct mrsas_evtarg_ld ld;
1594 1594 uint32_t prevOwner;
1595 1595 uint32_t newOwner;
1596 1596 } ld_owner;
1597 1597
1598 1598 struct {
1599 1599 uint64_t ld_lba;
1600 1600 uint64_t pd_lba;
1601 1601 struct mrsas_evtarg_ld ld;
1602 1602 struct mrsas_evtarg_pd pd;
1603 1603 } ld_lba_pd_lba;
1604 1604
1605 1605 struct {
1606 1606 struct mrsas_evtarg_ld ld;
1607 1607 struct mrsas_progress prog;
1608 1608 } ld_prog;
1609 1609
1610 1610 struct {
1611 1611 struct mrsas_evtarg_ld ld;
1612 1612 uint32_t prev_state;
1613 1613 uint32_t new_state;
1614 1614 } ld_state;
1615 1615
1616 1616 struct {
1617 1617 uint64_t strip;
1618 1618 struct mrsas_evtarg_ld ld;
1619 1619 } ld_strip;
1620 1620
1621 1621 struct mrsas_evtarg_pd pd;
1622 1622
1623 1623 struct {
1624 1624 struct mrsas_evtarg_pd pd;
1625 1625 uint32_t err;
1626 1626 } pd_err;
1627 1627
1628 1628 struct {
1629 1629 uint64_t lba;
1630 1630 struct mrsas_evtarg_pd pd;
1631 1631 } pd_lba;
1632 1632
1633 1633 struct {
1634 1634 uint64_t lba;
1635 1635 struct mrsas_evtarg_pd pd;
1636 1636 struct mrsas_evtarg_ld ld;
1637 1637 } pd_lba_ld;
1638 1638
1639 1639 struct {
1640 1640 struct mrsas_evtarg_pd pd;
1641 1641 struct mrsas_progress prog;
1642 1642 } pd_prog;
1643 1643
1644 1644 struct {
1645 1645 struct mrsas_evtarg_pd pd;
1646 1646 uint32_t prevState;
1647 1647 uint32_t newState;
1648 1648 } pd_state;
1649 1649
1650 1650 struct {
1651 1651 uint16_t vendorId;
1652 1652 uint16_t deviceId;
1653 1653 uint16_t subVendorId;
1654 1654 uint16_t subDeviceId;
1655 1655 } pci;
1656 1656
1657 1657 uint32_t rate;
1658 1658 char str[96];
1659 1659
1660 1660 struct {
1661 1661 uint32_t rtc;
1662 1662 uint32_t elapsedSeconds;
1663 1663 } time;
1664 1664
1665 1665 struct {
1666 1666 uint32_t ecar;
1667 1667 uint32_t elog;
1668 1668 char str[64];
1669 1669 } ecc;
1670 1670
1671 1671 mrsas_pd_address_t pd_addr;
1672 1672
1673 1673 uint8_t b[96];
1674 1674 uint16_t s[48];
1675 1675 uint32_t w[24];
1676 1676 uint64_t d[12];
1677 1677 } args;
1678 1678
1679 1679 char description[128];
1680 1680
1681 1681 };
1682 1682
1683 1683 /* only 63 are usable by the application */
1684 1684 #define MAX_LOGICAL_DRIVES 64
1685 1685 /* only 255 physical devices may be used */
1686 1686 #define MAX_PHYSICAL_DEVICES 256
1687 1687 #define MAX_PD_PER_ENCLOSURE 64
1688 1688 /* maximum disks per array */
1689 1689 #define MAX_ROW_SIZE 32
1690 1690 /* maximum spans per logical drive */
1691 1691 #define MAX_SPAN_DEPTH 8
1692 1692 /* maximum number of arrays a hot spare may be dedicated to */
1693 1693 #define MAX_ARRAYS_DEDICATED 16
1694 1694 /* maximum number of arrays which may exist */
1695 1695 #define MAX_ARRAYS 128
1696 1696 /* maximum number of foreign configs that may ha managed at once */
1697 1697 #define MAX_FOREIGN_CONFIGS 8
1698 1698 /* maximum spares (global and dedicated combined) */
1699 1699 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES
1700 1700 /* maximum possible Target IDs (i.e. 0 to 63) */
1701 1701 #define MAX_TARGET_ID 63
1702 1702 /* maximum number of supported enclosures */
1703 1703 #define MAX_ENCLOSURES 32
1704 1704 /* maximum number of PHYs per controller */
1705 1705 #define MAX_PHYS_PER_CONTROLLER 16
1706 1706 /* maximum number of LDs per array (due to DDF limitations) */
1707 1707 #define MAX_LDS_PER_ARRAY 16
1708 1708
1709 1709 /*
1710 1710 * -----------------------------------------------------------------------------
1711 1711 * -----------------------------------------------------------------------------
1712 1712 *
1713 1713 * Logical Drive commands
1714 1714 *
1715 1715 * -----------------------------------------------------------------------------
1716 1716 * -----------------------------------------------------------------------------
1717 1717 */
1718 1718 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */
1719 1719
1720 1720 /*
1721 1721 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST
1722 1722 * dcmd.mbox - reserved
1723 1723 * dcmd.sge IN - ptr to returned MR_LD_LIST structure
1724 1724 * Desc: Return the logical drive list structure
1725 1725 * Status: No error
1726 1726 */
1727 1727
1728 1728 /*
1729 1729 * defines the logical drive reference structure
1730 1730 */
1731 1731 typedef union _MR_LD_REF { /* LD reference structure */
1732 1732 struct {
1733 1733 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */
1734 1734 uint8_t reserved; /* reserved for in line with MR_PD_REF */
1735 1735 uint16_t seqNum; /* Sequence Number */
1736 1736 } ld_ref;
1737 1737 uint32_t ref; /* shorthand reference to full 32-bits */
1738 1738 } MR_LD_REF; /* 4 bytes */
1739 1739
1740 1740 /*
1741 1741 * defines the logical drive list structure
1742 1742 */
1743 1743 typedef struct _MR_LD_LIST {
1744 1744 uint32_t ldCount; /* number of LDs */
1745 1745 uint32_t reserved; /* pad to 8-byte boundary */
1746 1746 struct {
1747 1747 MR_LD_REF ref; /* LD reference */
1748 1748 uint8_t state; /* current LD state (MR_LD_STATE) */
1749 1749 uint8_t reserved[3]; /* pad to 8-byte boundary */
1750 1750 uint64_t size; /* LD size */
1751 1751 } ldList[MAX_LOGICAL_DRIVES];
1752 1752 } MR_LD_LIST;
1753 1753
1754 1754 struct mrsas_drv_ver {
1755 1755 uint8_t signature[12];
1756 1756 uint8_t os_name[16];
1757 1757 uint8_t os_ver[12];
1758 1758 uint8_t drv_name[20];
1759 1759 uint8_t drv_ver[32];
1760 1760 uint8_t drv_rel_date[20];
1761 1761 };
1762 1762
1763 1763 #define PCI_TYPE0_ADDRESSES 6
1764 1764 #define PCI_TYPE1_ADDRESSES 2
1765 1765 #define PCI_TYPE2_ADDRESSES 5
1766 1766
1767 1767 struct mrsas_pci_common_header {
1768 1768 uint16_t vendorID; /* (ro) */
1769 1769 uint16_t deviceID; /* (ro) */
1770 1770 uint16_t command; /* Device control */
1771 1771 uint16_t status;
1772 1772 uint8_t revisionID; /* (ro) */
1773 1773 uint8_t progIf; /* (ro) */
1774 1774 uint8_t subClass; /* (ro) */
1775 1775 uint8_t baseClass; /* (ro) */
1776 1776 uint8_t cacheLineSize; /* (ro+) */
1777 1777 uint8_t latencyTimer; /* (ro+) */
1778 1778 uint8_t headerType; /* (ro) */
1779 1779 uint8_t bist; /* Built in self test */
1780 1780
1781 1781 union {
1782 1782 struct {
1783 1783 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES];
1784 1784 uint32_t cis;
1785 1785 uint16_t subVendorID;
1786 1786 uint16_t subSystemID;
1787 1787 uint32_t romBaseAddress;
1788 1788 uint8_t capabilitiesPtr;
1789 1789 uint8_t reserved1[3];
1790 1790 uint32_t reserved2;
1791 1791 uint8_t interruptLine;
1792 1792 uint8_t interruptPin; /* (ro) */
1793 1793 uint8_t minimumGrant; /* (ro) */
1794 1794 uint8_t maximumLatency; /* (ro) */
1795 1795 } type_0;
1796 1796
1797 1797 struct {
1798 1798 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES];
1799 1799 uint8_t primaryBus;
1800 1800 uint8_t secondaryBus;
1801 1801 uint8_t subordinateBus;
1802 1802 uint8_t secondaryLatency;
1803 1803 uint8_t ioBase;
1804 1804 uint8_t ioLimit;
1805 1805 uint16_t secondaryStatus;
1806 1806 uint16_t memoryBase;
1807 1807 uint16_t memoryLimit;
1808 1808 uint16_t prefetchBase;
1809 1809 uint16_t prefetchLimit;
1810 1810 uint32_t prefetchBaseUpper32;
1811 1811 uint32_t prefetchLimitUpper32;
1812 1812 uint16_t ioBaseUpper16;
1813 1813 uint16_t ioLimitUpper16;
1814 1814 uint8_t capabilitiesPtr;
1815 1815 uint8_t reserved1[3];
1816 1816 uint32_t romBaseAddress;
1817 1817 uint8_t interruptLine;
1818 1818 uint8_t interruptPin;
1819 1819 uint16_t bridgeControl;
1820 1820 } type_1;
1821 1821
1822 1822 struct {
1823 1823 uint32_t socketRegistersBaseAddress;
1824 1824 uint8_t capabilitiesPtr;
1825 1825 uint8_t reserved;
1826 1826 uint16_t secondaryStatus;
1827 1827 uint8_t primaryBus;
1828 1828 uint8_t secondaryBus;
1829 1829 uint8_t subordinateBus;
1830 1830 uint8_t secondaryLatency;
1831 1831 struct {
1832 1832 uint32_t base;
1833 1833 uint32_t limit;
1834 1834 } range[PCI_TYPE2_ADDRESSES-1];
1835 1835 uint8_t interruptLine;
1836 1836 uint8_t interruptPin;
1837 1837 uint16_t bridgeControl;
1838 1838 } type_2;
1839 1839 } header;
1840 1840 };
1841 1841
1842 1842 struct mrsas_pci_link_capability {
1843 1843 union {
1844 1844 struct {
1845 1845 uint32_t linkSpeed :4;
1846 1846 uint32_t linkWidth :6;
1847 1847 uint32_t aspmSupport :2;
1848 1848 uint32_t losExitLatency :3;
1849 1849 uint32_t l1ExitLatency :3;
1850 1850 uint32_t rsvdp :6;
1851 1851 uint32_t portNumber :8;
1852 1852 } bits;
1853 1853
1854 1854 uint32_t asUlong;
1855 1855 } cap;
1856 1856
1857 1857 };
1858 1858
1859 1859 struct mrsas_pci_link_status_capability {
1860 1860 union {
1861 1861 struct {
1862 1862 uint16_t linkSpeed :4;
1863 1863 uint16_t negotiatedLinkWidth :6;
1864 1864 uint16_t linkTrainingError :1;
1865 1865 uint16_t linkTraning :1;
1866 1866 uint16_t slotClockConfig :1;
1867 1867 uint16_t rsvdZ :3;
1868 1868 } bits;
1869 1869
1870 1870 uint16_t asUshort;
1871 1871 } stat_cap;
1872 1872
1873 1873 uint16_t reserved;
1874 1874
1875 1875 };
1876 1876
1877 1877 struct mrsas_pci_capabilities {
1878 1878 struct mrsas_pci_link_capability linkCapability;
1879 1879 struct mrsas_pci_link_status_capability linkStatusCapability;
1880 1880 };
1881 1881
1882 1882 struct mrsas_pci_information
1883 1883 {
1884 1884 uint32_t busNumber;
1885 1885 uint8_t deviceNumber;
1886 1886 uint8_t functionNumber;
1887 1887 uint8_t interruptVector;
1888 1888 uint8_t reserved;
1889 1889 struct mrsas_pci_common_header pciHeaderInfo;
1890 1890 struct mrsas_pci_capabilities capability;
1891 1891 uint8_t reserved2[32];
1892 1892 };
1893 1893
1894 1894 struct mrsas_ioctl {
1895 1895 uint16_t version;
1896 1896 uint16_t controller_id;
1897 1897 uint8_t signature[8];
1898 1898 uint32_t reserved_1;
1899 1899 uint32_t control_code;
1900 1900 uint32_t reserved_2[2];
1901 1901 uint8_t frame[64];
1902 1902 union mrsas_sgl_frame sgl_frame;
1903 1903 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH];
1904 1904 uint8_t data[1];
1905 1905 };
1906 1906
1907 1907 struct mrsas_aen {
1908 1908 uint16_t host_no;
1909 1909 uint16_t cmd_status;
1910 1910 uint32_t seq_num;
1911 1911 uint32_t class_locale_word;
1912 1912 };
1913 1913
1914 1914 #pragma pack()
1915 1915
1916 1916 #ifndef DDI_VENDOR_LSI
1917 1917 #define DDI_VENDOR_LSI "LSI"
1918 1918 #endif /* DDI_VENDOR_LSI */
1919 1919
1920 1920 static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
1921 1921 static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t);
1922 1922 static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t);
1923 1923 int mrsas_quiesce(dev_info_t *);
1924 1924 static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t);
1925 1925 static int mrsas_open(dev_t *, int, int, cred_t *);
1926 1926 static int mrsas_close(dev_t, int, int, cred_t *);
1927 1927 static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
1928 1928
1929 1929 static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *,
1930 1930 scsi_hba_tran_t *, struct scsi_device *);
1931 1931 static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register
1932 1932 struct scsi_pkt *, struct buf *, int, int, int, int,
1933 1933 int (*)(), caddr_t);
1934 1934 static int mrsas_tran_start(struct scsi_address *,
1935 1935 register struct scsi_pkt *);
1936 1936 static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *);
1937 1937 static int mrsas_tran_reset(struct scsi_address *, int);
1938 1938 static int mrsas_tran_bus_reset(dev_info_t *, int);
1939 1939 static int mrsas_tran_getcap(struct scsi_address *, char *, int);
1940 1940 static int mrsas_tran_setcap(struct scsi_address *, char *, int, int);
1941 1941 static void mrsas_tran_destroy_pkt(struct scsi_address *,
1942 1942 struct scsi_pkt *);
1943 1943 static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *);
1944 1944 static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *);
1945 1945 static int mrsas_tran_quiesce(dev_info_t *dip);
1946 1946 static int mrsas_tran_unquiesce(dev_info_t *dip);
1947 1947 static uint_t mrsas_isr();
1948 1948 static uint_t mrsas_softintr();
1949 1949
1950 1950 static struct mrsas_cmd *get_mfi_pkt(struct mrsas_instance *);
1951 1951 static void return_mfi_pkt(struct mrsas_instance *,
1952 1952 struct mrsas_cmd *);
1953 1953
1954 1954 static void free_space_for_mfi(struct mrsas_instance *);
1955 1955 static int mrsas_tbolt_alloc_additional_dma_buffer
1956 1956 (struct mrsas_instance *);
1957 1957 int mrsas_tbolt_sync_map_info(struct mrsas_instance *instance);
1958 1958 static int alloc_additional_dma_buffer(struct mrsas_instance *);
1959 1959 static uint32_t read_fw_status_reg_ppc(struct mrsas_instance *);
1960 1960 static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *);
1961 1961 static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *,
1962 1962 struct mrsas_cmd *);
1963 1963 static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *,
1964 1964 struct mrsas_cmd *);
1965 1965 static void enable_intr_ppc(struct mrsas_instance *);
1966 1966 static void disable_intr_ppc(struct mrsas_instance *);
1967 1967 static int intr_ack_ppc(struct mrsas_instance *);
1968 1968 int mfi_state_transition_to_ready(struct mrsas_instance *);
1969 1969 static void flush_cache(struct mrsas_instance *instance);
1970 1970 void display_scsi_inquiry(caddr_t);
1971 1971 static int start_mfi_aen(struct mrsas_instance *instance);
1972 1972 static int handle_drv_ioctl(struct mrsas_instance *instance,
1973 1973 struct mrsas_ioctl *ioctl, int mode);
1974 1974 static int handle_mfi_ioctl(struct mrsas_instance *instance,
1975 1975 struct mrsas_ioctl *ioctl, int mode);
1976 1976 static int handle_mfi_aen(struct mrsas_instance *instance,
1977 1977 struct mrsas_aen *aen);
1978 1978 void fill_up_drv_ver(struct mrsas_drv_ver *dv);
1979 1979 static struct mrsas_cmd *build_cmd(struct mrsas_instance *instance,
1980 1980 struct scsi_address *ap, struct scsi_pkt *pkt,
1981 1981 uchar_t *cmd_done);
1982 1982 static struct mrsas_cmd *mrsas_tbolt_build_cmd(struct mrsas_instance *instance,
1983 1983 struct scsi_address *ap, struct scsi_pkt *pkt,
1984 1984 uchar_t *cmd_done);
1985 1985 static int wait_for_outstanding(struct mrsas_instance *instance);
1986 1986 static int register_mfi_aen(struct mrsas_instance *instance,
1987 1987 uint32_t seq_num, uint32_t class_locale_word);
1988 1988 static int issue_mfi_pthru(struct mrsas_instance *instance, struct
1989 1989 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1990 1990 static int issue_mfi_dcmd(struct mrsas_instance *instance, struct
1991 1991 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1992 1992 static int issue_mfi_smp(struct mrsas_instance *instance, struct
1993 1993 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1994 1994 static int issue_mfi_stp(struct mrsas_instance *instance, struct
1995 1995 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1996 1996 static int abort_aen_cmd(struct mrsas_instance *instance,
1997 1997 struct mrsas_cmd *cmd_to_abort);
1998 1998
1999 1999
2000 2000 static void mrsas_rem_intrs(struct mrsas_instance *instance);
2001 2001 static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type);
2002 2002
2003 2003 static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *,
2004 2004 scsi_hba_tran_t *, struct scsi_device *);
2005 2005 static int mrsas_tran_bus_config(dev_info_t *, uint_t,
2006 2006 ddi_bus_config_op_t, void *, dev_info_t **);
2007 2007 static int mrsas_parse_devname(char *, int *, int *);
2008 2008 static int mrsas_config_all_devices(struct mrsas_instance *);
2009 2009 int mrsas_config_scsi_device(struct mrsas_instance *,
2010 2010 struct scsi_device *, dev_info_t **);
2011 2011 static int mrsas_config_ld(struct mrsas_instance *, uint16_t,
2012 2012 uint8_t, dev_info_t **);
2013 2013
2014 2014 #ifdef PDSUPPORT
2015 2015 int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t,
2016 2016 uint8_t, dev_info_t **);
2017 2017 static void mrsas_tbolt_get_pd_info(struct mrsas_instance *,
2018 2018 struct mrsas_tbolt_pd_info *, int);
2019 2019 #endif
2020 2020
2021 2021 dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t,
2022 2022 uint8_t);
2023 2023 static int mrsas_name_node(dev_info_t *, char *, int);
2024 2024 static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *);
2025 2025 int mrsas_service_evt(struct mrsas_instance *, int, int, int,
2026 2026 uint64_t);
2027 2027 static void free_additional_dma_buffer(struct mrsas_instance *);
2028 2028
2029 2029 struct mrsas_cmd *get_raid_msg_pkt(struct mrsas_instance *);
2030 2030 void return_raid_msg_pkt(struct mrsas_instance *, struct mrsas_cmd *);
2031 2031 struct mrsas_cmd *get_raid_msg_mfi_pkt(struct mrsas_instance *);
2032 2032 void return_raid_msg_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
2033 2033
2034 2034 int alloc_space_for_mpi2(struct mrsas_instance *);
2035 2035 int alloc_additional_dma_buffer(struct mrsas_instance *);
2036 2036
2037 2037 int mrsas_issue_init_mpi2(struct mrsas_instance *);
2038 2038 struct scsi_pkt *mrsas_tbolt_tran_init_pkt(struct scsi_address *, register
2039 2039 struct scsi_pkt *, struct buf *, int, int, int, int,
2040 2040 int (*)(), caddr_t);
2041 2041 int mrsas_tbolt_tran_start(struct scsi_address *,
2042 2042 register struct scsi_pkt *);
2043 2043 uint32_t tbolt_read_fw_status_reg(struct mrsas_instance *);
2044 2044 void tbolt_issue_cmd(struct mrsas_cmd *, struct mrsas_instance *);
2045 2045 int tbolt_issue_cmd_in_poll_mode(struct mrsas_instance *,
2046 2046 struct mrsas_cmd *);
2047 2047 int tbolt_issue_cmd_in_sync_mode(struct mrsas_instance *,
2048 2048 struct mrsas_cmd *);
2049 2049 void tbolt_enable_intr(struct mrsas_instance *);
2050 2050 void tbolt_disable_intr(struct mrsas_instance *);
2051 2051 int tbolt_intr_ack(struct mrsas_instance *);
2052 2052 uint_t mr_sas_tbolt_process_outstanding_cmd(struct mrsas_instance *);
2053 2053 uint_t tbolt_softintr();
2054 2054 int mrsas_tbolt_dma(struct mrsas_instance *, uint32_t, int, int (*)());
2055 2055 int mrsas_check_dma_handle(ddi_dma_handle_t handle);
2056 2056 int mrsas_check_acc_handle(ddi_acc_handle_t handle);
2057 2057 int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
2058 2058 struct buf *, int, int (*)());
2059 2059 int mrsas_dma_move(struct mrsas_instance *,
2060 2060 struct scsi_pkt *, struct buf *);
2061 2061 int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
2062 2062 uchar_t);
2063 2063 int mrsas_tbolt_ioc_init(struct mrsas_instance *, dma_obj_t *,
2064 2064 ddi_acc_handle_t);
2065 2065 int mrsas_tbolt_prepare_pkt(struct scsa_cmd *);
2066 2066 void mr_sas_tbolt_build_mfi_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2067 2067 int mrsas_dma_alloc_dmd(struct mrsas_instance *, dma_obj_t *);
2068 2068 int mr_sas_tbolt_build_sgl(struct mrsas_instance *,
2069 2069 struct scsa_cmd *,
2070 2070 struct mrsas_cmd *,
2071 2071 Mpi2RaidSCSIIORequest_t *,
2072 2072 uint32_t *);
2073 2073 void tbolt_complete_cmd_in_sync_mode(struct mrsas_instance *,
2074 2074 struct mrsas_cmd *);
2075 2075 int alloc_req_rep_desc(struct mrsas_instance *);
2076 2076 static void complete_cmd_in_sync_mode(struct mrsas_instance *,
2077 2077 struct mrsas_cmd *);
2078 2078 static void io_timeout_checker(void *instance);
2079 2079 static int mrsas_kill_adapter(struct mrsas_instance *);
2080 2080 int mrsas_mode_sense_build(struct scsi_pkt *);
2081 2081 void push_pending_mfi_pkt(struct mrsas_instance *,
2082 2082 struct mrsas_cmd *);
2083 2083 static int mrsas_issue_init_mfi(struct mrsas_instance *);
2084 2084 int mrsas_issue_pending_cmds(struct mrsas_instance *);
2085 2085 int mrsas_print_pending_cmds(struct mrsas_instance *);
2086 2086 int mrsas_complete_pending_cmds(struct mrsas_instance *);
2087 2087 static int mrsas_reset_ppc(struct mrsas_instance *);
2088 2088 static uint32_t mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *);
2089 2089
2090 2090 MRSAS_REQUEST_DESCRIPTOR_UNION *\
2091 2091 mr_sas_get_request_descriptor(struct mrsas_instance *,
2092 2092 uint16_t, struct mrsas_cmd *);
2093 2093
2094 2094 int create_mfi_frame_pool(struct mrsas_instance *);
2095 2095 void destroy_mfi_frame_pool(struct mrsas_instance *);
2096 2096 int create_mfi_mpi_frame_pool(struct mrsas_instance *);
2097 2097 void destroy_mfi_mpi_frame_pool(struct mrsas_instance *);
2098 2098 int create_mpi2_frame_pool(struct mrsas_instance *);
2099 2099 void destroy_mpi2_frame_pool(struct mrsas_instance *);
2100 2100 int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
2101 2101 void mrsas_tbolt_free_additional_dma_buffer(struct mrsas_instance *);
2102 2102 void free_req_desc_pool(struct mrsas_instance *);
2103 2103 void free_space_for_mpi2(struct mrsas_instance *);
2104 2104 void mrsas_dump_reply_desc(struct mrsas_instance *);
2105 2105 void tbolt_complete_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2106 2106 void io_timeout_checker(void *);
2107 2107 void display_scsi_inquiry(caddr_t);
2108 2108 void service_mfi_aen(struct mrsas_instance *, struct mrsas_cmd *);
2109 2109 int mrsas_mode_sense_build(struct scsi_pkt *);
2110 2110 int mrsas_tbolt_get_ld_map_info(struct mrsas_instance *);
2111 2111 void mrsas_tbolt_set_pd_lba(U8 cdb[], uint8_t *cdb_len, U64 start_blk, U32 num_blocks, U8 DifCapable);
2112 2112 U8 mrsas_tbolt_check_map_info(struct mrsas_instance *);
2113 2113 struct mrsas_cmd *mrsas_tbolt_build_poll_cmd(struct mrsas_instance *,
2114 2114 struct scsi_address *, struct scsi_pkt *, uchar_t *);
2115 2115 int mrsas_tbolt_reset_ppc(struct mrsas_instance *instance);
2116 2116 int mrsas_tbolt_kill_adapter(struct mrsas_instance *instance);
2117 2117 int abort_syncmap_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2118 2118 void mrsas_tbolt_prepare_cdb(struct mrsas_instance *instance, U8 cdb[],struct IO_REQUEST_INFO *,
2119 2119 Mpi2RaidSCSIIORequest_t *, U32);
2120 2120
2121 2121
2122 2122 static int
2123 2123 mrsas_undo_resources (dev_info_t *dip, struct mrsas_instance *instance);
2124 2124
2125 2125 int mrsas_init_adapter_ppc (struct mrsas_instance *instance);
2126 2126 int mrsas_init_adapter_tbolt (struct mrsas_instance *instance);
2127 2127 int mrsas_init_adapter (struct mrsas_instance *instance);
2128 2128
2129 2129 int mrsas_alloc_cmd_pool(struct mrsas_instance *instance);
2130 2130 void mrsas_free_cmd_pool(struct mrsas_instance *instance);
2131 2131
2132 2132 void mrsas_print_cmd_details(struct mrsas_instance *, struct mrsas_cmd *, int );
2133 2133
2134 2134 #ifdef __cplusplus
2135 2135 }
2136 2136 #endif
2137 2137
2138 2138 #endif /* _MR_SAS_H_ */
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