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--- old/./fusion.h
+++ new/./fusion.h
1 1 /*
2 2 * fusion.h
3 3 *
4 4 * Solaris MegaRAID device driver for SAS2.0 controllers
5 5 * Copyright (c) 2008-2012, LSI Logic Corporation.
6 6 * All rights reserved.
7 7 *
8 8 * Version:
9 9 * Author:
10 10 * Swaminathan K S
11 11 * Arun Chandrashekhar
12 12 * Manju R
13 13 * Rasheed
14 14 * Shakeel Bukhari
15 15 */
16 16
17 17
18 18 #ifndef _FUSION_H_
19 19 #define _FUSION_H_
20 20
21 21 #define U64 uint64_t
22 22 #define U32 uint32_t
23 23 #define U16 uint16_t
24 24 #define U8 uint8_t
25 25 #define S8 char
26 26 #define S16 short
27 27 #define S32 int
28 28
29 29 /* MPI2 defines */
30 30 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x6C)
31 31 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
32 32 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
33 33 #define MPI2_VERSION_MAJOR (0x02)
34 34 #define MPI2_VERSION_MINOR (0x00)
35 35 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
36 36 #define MPI2_VERSION_MAJOR_SHIFT (8)
37 37 #define MPI2_VERSION_MINOR_MASK (0x00FF)
38 38 #define MPI2_VERSION_MINOR_SHIFT (0)
39 39 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
40 40 MPI2_VERSION_MINOR)
41 41 #define MPI2_HEADER_VERSION_UNIT (0x10)
42 42 #define MPI2_HEADER_VERSION_DEV (0x00)
43 43 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
44 44 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
45 45 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
46 46 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
47 47 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT \
48 48 << 8) | \
49 49 MPI2_HEADER_VERSION_DEV)
50 50 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
51 51 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
52 52 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
53 53 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
54 54 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
55 55 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
56 56 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
57 57 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
58 58 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
59 59 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
60 60 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
61 61 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
62 62 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
63 63 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
64 64 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
65 65 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
66 66 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
67 67 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
68 68 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
69 69 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
70 70 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
71 71 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
72 72 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
73 73 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
74 74 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
75 75
76 76 /* Invader defines */
77 77 #define MPI2_TYPE_CUDA 0x2
78 78 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
79 79 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
80 80 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
81 81 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
82 82 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
83 83 #define MPI2_NSEG_FLAGS_SHIFT 4
84 84
85 85
86 86 #define MR_PD_INVALID 0xFFFF
87 87 #define MAX_SPAN_DEPTH 8
88 88 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
89 89 #define MAX_ROW_SIZE 32
90 90 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
91 91 #define MAX_LOGICAL_DRIVES 64
92 92 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
93 93 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
94 94 #define MAX_ARRAYS 128
95 95 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
96 96 #define MAX_PHYSICAL_DEVICES 256
97 97 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
98 98
99 99 /* get the mapping information of LD */
100 100 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
101 101
102 102 #ifndef MPI2_POINTER
103 103 #define MPI2_POINTER *
104 104 #endif
105 105
106 106 #pragma pack(1)
107 107
108 108 typedef struct _MPI25_IEEE_SGE_CHAIN64
109 109 {
110 110 U64 Address;
111 111 U32 Length;
112 112 U16 Reserved1;
113 113 U8 NextChainOffset;
114 114 U8 Flags;
115 115 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64,
116 116 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t;
117 117
118 118 typedef struct _MPI2_SGE_SIMPLE_UNION
119 119 {
120 120 U32 FlagsLength;
121 121 union
122 122 {
123 123 U32 Address32;
124 124 U64 Address64;
125 125 } u1;
126 126 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
127 127 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
128 128
129 129 typedef struct
130 130 {
131 131 U8 CDB[20]; /* 0x00 */
132 132 U32 PrimaryReferenceTag; /* 0x14 */
133 133 U16 PrimaryApplicationTag; /* 0x18 */
134 134 U16 PrimaryApplicationTagMask; /* 0x1A */
135 135 U32 TransferLength; /* 0x1C */
136 136 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32,
137 137 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t;
138 138
139 139 typedef struct _MPI2_SGE_CHAIN_UNION
140 140 {
141 141 U16 Length;
142 142 U8 NextChainOffset;
143 143 U8 Flags;
144 144 union
145 145 {
146 146 U32 Address32;
147 147 U64 Address64;
148 148 } u1;
149 149 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
150 150 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
151 151
152 152 typedef struct _MPI2_IEEE_SGE_SIMPLE32
153 153 {
154 154 U32 Address;
155 155 U32 FlagsLength;
156 156 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
157 157 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
158 158
159 159 typedef struct _MPI2_IEEE_SGE_SIMPLE64
160 160 {
161 161 U64 Address;
162 162 U32 Length;
163 163 U16 Reserved1;
164 164 U8 Reserved2;
165 165 U8 Flags;
166 166 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
167 167 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
168 168
169 169 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
170 170 {
171 171 MPI2_IEEE_SGE_SIMPLE32 Simple32;
172 172 MPI2_IEEE_SGE_SIMPLE64 Simple64;
173 173 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
174 174 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
175 175
176 176 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
177 177 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
178 178
179 179 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
180 180 {
181 181 MPI2_IEEE_SGE_CHAIN32 Chain32;
182 182 MPI2_IEEE_SGE_CHAIN64 Chain64;
183 183 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
184 184 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
185 185
186 186 typedef union _MPI2_SGE_IO_UNION
187 187 {
188 188 MPI2_SGE_SIMPLE_UNION MpiSimple;
189 189 MPI2_SGE_CHAIN_UNION MpiChain;
190 190 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
191 191 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
192 192 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
193 193 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
194 194
195 195 typedef union
196 196 {
197 197 U8 CDB32[32];
198 198 MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
199 199 MPI2_SGE_SIMPLE_UNION SGE;
200 200 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION,
201 201 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t;
202 202
203 203 /* Default Request Descriptor */
204 204 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
205 205 {
206 206 U8 RequestFlags; /* 0x00 */
207 207 U8 MSIxIndex; /* 0x01 */
208 208 U16 SMID; /* 0x02 */
209 209 U16 LMID; /* 0x04 */
210 210 U16 DescriptorTypeDependent; /* 0x06 */
211 211 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
212 212 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
213 213 Mpi2DefaultRequestDescriptor_t,
214 214 MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
215 215
216 216 /* High Priority Request Descriptor */
217 217 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
218 218 {
219 219 U8 RequestFlags; /* 0x00 */
220 220 U8 MSIxIndex; /* 0x01 */
221 221 U16 SMID; /* 0x02 */
222 222 U16 LMID; /* 0x04 */
223 223 U16 Reserved1; /* 0x06 */
224 224 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
225 225 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
226 226 Mpi2HighPriorityRequestDescriptor_t,
227 227 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
228 228
229 229 /* SCSI IO Request Descriptor */
230 230 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
231 231 {
232 232 U8 RequestFlags; /* 0x00 */
233 233 U8 MSIxIndex; /* 0x01 */
234 234 U16 SMID; /* 0x02 */
235 235 U16 LMID; /* 0x04 */
236 236 U16 DevHandle; /* 0x06 */
237 237 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
238 238 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
239 239 Mpi2SCSIIORequestDescriptor_t,
240 240 MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
241 241
242 242 /* SCSI Target Request Descriptor */
243 243 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
244 244 {
245 245 U8 RequestFlags; /* 0x00 */
246 246 U8 MSIxIndex; /* 0x01 */
247 247 U16 SMID; /* 0x02 */
248 248 U16 LMID; /* 0x04 */
249 249 U16 IoIndex; /* 0x06 */
250 250 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
251 251 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
252 252 Mpi2SCSITargetRequestDescriptor_t,
253 253 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
254 254
255 255 /* RAID Accelerator Request Descriptor */
256 256 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR
257 257 {
258 258 U8 RequestFlags; /* 0x00 */
259 259 U8 MSIxIndex; /* 0x01 */
260 260 U16 SMID; /* 0x02 */
261 261 U16 LMID; /* 0x04 */
262 262 U16 Reserved; /* 0x06 */
263 263 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
264 264 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
265 265 Mpi2RAIDAcceleratorRequestDescriptor_t,
266 266 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
267 267
268 268 /* Default Reply Descriptor */
269 269 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
270 270 {
271 271 U8 ReplyFlags; /* 0x00 */
272 272 U8 MSIxIndex; /* 0x01 */
273 273 U16 DescriptorTypeDependent1; /* 0x02 */
274 274 U32 DescriptorTypeDependent2; /* 0x04 */
275 275 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
276 276 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
277 277
278 278 /* Address Reply Descriptor */
279 279 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
280 280 {
281 281 U8 ReplyFlags; /* 0x00 */
282 282 U8 MSIxIndex; /* 0x01 */
283 283 U16 SMID; /* 0x02 */
284 284 U32 ReplyFrameAddress; /* 0x04 */
285 285 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
286 286 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
287 287
288 288 /* SCSI IO Success Reply Descriptor */
289 289 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
290 290 {
291 291 U8 ReplyFlags; /* 0x00 */
292 292 U8 MSIxIndex; /* 0x01 */
293 293 U16 SMID; /* 0x02 */
294 294 U16 TaskTag; /* 0x04 */
295 295 U16 Reserved1; /* 0x06 */
296 296 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
297 297 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
298 298 Mpi2SCSIIOSuccessReplyDescriptor_t,
299 299 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
300 300
301 301 /* TargetAssist Success Reply Descriptor */
302 302 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
303 303 {
304 304 U8 ReplyFlags; /* 0x00 */
305 305 U8 MSIxIndex; /* 0x01 */
306 306 U16 SMID; /* 0x02 */
307 307 U8 SequenceNumber; /* 0x04 */
308 308 U8 Reserved1; /* 0x05 */
309 309 U16 IoIndex; /* 0x06 */
310 310 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
311 311 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
312 312 Mpi2TargetAssistSuccessReplyDescriptor_t,
313 313 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
314 314
315 315 /* Target Command Buffer Reply Descriptor */
316 316 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
317 317 {
318 318 U8 ReplyFlags; /* 0x00 */
319 319 U8 MSIxIndex; /* 0x01 */
320 320 U8 VP_ID; /* 0x02 */
321 321 U8 Flags; /* 0x03 */
322 322 U16 InitiatorDevHandle; /* 0x04 */
323 323 U16 IoIndex; /* 0x06 */
324 324 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
325 325 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
326 326 Mpi2TargetCommandBufferReplyDescriptor_t,
327 327 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
328 328
329 329 /* RAID Accelerator Success Reply Descriptor */
330 330 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
331 331 {
332 332 U8 ReplyFlags; /* 0x00 */
333 333 U8 MSIxIndex; /* 0x01 */
334 334 U16 SMID; /* 0x02 */
335 335 U32 Reserved; /* 0x04 */
336 336 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
337 337 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
338 338 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
339 339 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
340 340
341 341 /* union of Reply Descriptors */
342 342 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
343 343 {
344 344 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
345 345 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
346 346 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
347 347 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
348 348 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
349 349 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
350 350 U64 Words;
351 351 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
352 352 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
353 353
354 354 /* IOCInit Request message */
355 355 typedef struct _MPI2_IOC_INIT_REQUEST
356 356 {
357 357 U8 WhoInit; /* 0x00 */
358 358 U8 Reserved1; /* 0x01 */
359 359 U8 ChainOffset; /* 0x02 */
360 360 U8 Function; /* 0x03 */
361 361 U16 Reserved2; /* 0x04 */
362 362 U8 Reserved3; /* 0x06 */
363 363 U8 MsgFlags; /* 0x07 */
364 364 U8 VP_ID; /* 0x08 */
365 365 U8 VF_ID; /* 0x09 */
366 366 U16 Reserved4; /* 0x0A */
367 367 U16 MsgVersion; /* 0x0C */
368 368 U16 HeaderVersion; /* 0x0E */
369 369 U32 Reserved5; /* 0x10 */
370 370 U16 Reserved6; /* 0x14 */
371 371 U8 Reserved7; /* 0x16 */
372 372 U8 HostMSIxVectors; /* 0x17 */
373 373 U16 Reserved8; /* 0x18 */
374 374 U16 SystemRequestFrameSize; /* 0x1A */
375 375 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
376 376 U16 ReplyFreeQueueDepth; /* 0x1E */
377 377 U32 SenseBufferAddressHigh; /* 0x20 */
378 378 U32 SystemReplyAddressHigh; /* 0x24 */
379 379 U64 SystemRequestFrameBaseAddress; /* 0x28 */
380 380 U64 ReplyDescriptorPostQueueAddress; /* 0x30 */
381 381 U64 ReplyFreeQueueAddress; /* 0x38 */
382 382 U64 TimeStamp; /* 0x40 */
383 383 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
384 384 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
385 385
386 386
387 387 typedef struct _MR_DEV_HANDLE_INFO {
388 388
389 389 /* Send bitmap of LDs that are idle with respect to FP */
390 390 U16 curDevHdl;
391 391
392 392 /* bitmap of valid device handles. */
393 393 U8 validHandles;
394 394 U8 reserved;
395 395 /* 0x04 dev handles for all the paths. */
396 396 U16 devHandle[2];
397 397 } MR_DEV_HANDLE_INFO; /* 0x08, Total Size */
398 398
399 399 typedef struct _MR_ARRAY_INFO {
400 400 U16 pd[MAX_RAIDMAP_ROW_SIZE];
401 401 } MR_ARRAY_INFO; /* 0x40, Total Size */
402 402
403 403 typedef struct _MR_QUAD_ELEMENT {
404 404 U64 logStart; /* 0x00 */
405 405 U64 logEnd; /* 0x08 */
406 406 U64 offsetInSpan; /* 0x10 */
407 407 U32 diff; /* 0x18 */
408 408 U32 reserved1; /* 0x1C */
409 409 } MR_QUAD_ELEMENT; /* 0x20, Total size */
410 410
411 411 typedef struct _MR_SPAN_INFO {
412 412 U32 noElements; /* 0x00 */
413 413 U32 reserved1; /* 0x04 */
414 414 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; /* 0x08 */
415 415 } MR_SPAN_INFO; /* 0x108, Total size */
416 416
417 417 typedef struct _MR_LD_SPAN_ { /* SPAN structure */
418 418 /* 0x00, starting block number in array */
419 419 U64 startBlk;
420 420
421 421 /* 0x08, number of blocks */
422 422 U64 numBlks;
423 423
424 424 /* 0x10, array reference */
425 425 U16 arrayRef;
426 426
427 427 U8 reserved[6]; /* 0x12 */
428 428 } MR_LD_SPAN; /* 0x18, Total Size */
429 429
430 430 typedef struct _MR_SPAN_BLOCK_INFO {
431 431 /* number of rows/span */
432 432 U64 num_rows;
433 433
434 434 MR_LD_SPAN span; /* 0x08 */
435 435 MR_SPAN_INFO block_span_info; /* 0x20 */
436 436 } MR_SPAN_BLOCK_INFO; /* 0x128, Total Size */
437 437
438 438 typedef struct _MR_LD_RAID {
439 439 struct {
440 440 U32 fpCapable :1;
441 441 U32 reserved5 :3;
442 442 U32 ldPiMode :4;
443 443 U32 pdPiMode :4;
444 444
445 445 /* FDE or controller encryption (MR_LD_ENCRYPTION_TYPE) */
446 446 U32 encryptionType :8;
447 447
448 448 U32 fpWriteCapable :1;
449 449 U32 fpReadCapable :1;
450 450 U32 fpWriteAcrossStripe:1;
451 451 U32 fpReadAcrossStripe:1;
452 452 U32 reserved4 :8;
453 453 } capability; /* 0x00 */
454 454 U32 reserved6;
455 455 U64 size; /* 0x08, LD size in blocks */
456 456 U8 spanDepth; /* 0x10, Total Number of Spans */
457 457 U8 level; /* 0x11, RAID level */
458 458 /* 0x12, shift-count to get stripe size (0=512, 1=1K, 7=64K, etc.) */
459 459 U8 stripeShift;
460 460 U8 rowSize; /* 0x13, number of disks in a row */
461 461 /* 0x14, number of data disks in a row */
462 462 U8 rowDataSize;
463 463 U8 writeMode; /* 0x15, WRITE_THROUGH or WRITE_BACK */
464 464
465 465 /* 0x16, To differentiate between RAID1 and RAID1E */
466 466 U8 PRL;
467 467
468 468 U8 SRL; /* 0x17 */
469 469 U16 targetId; /* 0x18, ld Target Id. */
470 470
471 471 /* 0x1a, state of ld, state corresponds to MR_LD_STATE */
472 472 U8 ldState;
473 473
474 474 /* 0x1b, Pre calculate region type requests based on MFC etc.. */
475 475 U8 regTypeReqOnWrite;
476 476
477 477 U8 modFactor; /* 0x1c, same as rowSize */
478 478 U8 regTypeReqOnRead; /* 0x1d, region lock type used for read, valid only if regTypeOnReadIsValid=1 */
479 479 U16 seqNum; /* 0x1e, LD sequence number */
480 480
481 481 struct {
482 482 /* This LD requires sync command before completing */
483 483 U32 ldSyncRequired:1;
484 484 U32 reserved:31;
485 485 } flags; /* 0x20 */
486 486
487 487 U8 reserved3[0x5C]; /* 0x24 */
488 488 } MR_LD_RAID; /* 0x80, Total Size */
489 489
490 490 typedef struct _MR_LD_SPAN_MAP {
491 491 MR_LD_RAID ldRaid; /* 0x00 */
492 492
493 493 /* 0x80, needed for GET_ARM() - R0/1/5 only. */
494 494 U8 dataArmMap[MAX_RAIDMAP_ROW_SIZE];
495 495
496 496 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; /* 0xA0 */
497 497 } MR_LD_SPAN_MAP; /* 0x9E0 */
498 498
499 499 typedef struct _MR_FW_RAID_MAP {
500 500 /* total size of this structure, including this field */
501 501 U32 totalSize;
502 502 union {
503 503 /* Simple method of version checking variables */
504 504 struct {
505 505 U32 maxLd;
506 506 U32 maxSpanDepth;
507 507 U32 maxRowSize;
508 508 U32 maxPdCount;
509 509 U32 maxArrays;
510 510 } validationInfo;
511 511 U32 version[5];
512 512 U32 reserved1[5];
513 513 } u1;
514 514
515 515 U32 ldCount; /* count of lds */
516 516 U32 Reserved1;
517 517
518 518 /* 0x20 This doesn't correspond to
519 519 * FW Ld Tgt Id to LD, but will purge. For example: if tgt Id is 4
520 520 * and FW LD is 2, and there is only one LD, FW will populate the
521 521 * array like this. [0xFF, 0xFF, 0xFF, 0xFF, 0x0.....]. This is to
522 522 * help reduce the entire strcture size if there are few LDs or
523 523 * driver is looking info for 1 LD only.
524 524 */
525 525 U8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+ \
526 526 MAX_RAIDMAP_VIEWS]; /* 0x20 */
527 527 /* timeout value used by driver in FP IOs */
528 528 U8 fpPdIoTimeoutSec;
529 529 U8 reserved2[7];
530 530 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; /* 0x00a8 */
531 531 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
532 532
533 533 /* 0x28a8-[0 -MAX_RAIDMAP_LOGICAL_DRIVES+MAX_RAIDMAP_VIEWS+1]; */
534 534 MR_LD_SPAN_MAP ldSpanMap[1];
535 535 }MR_FW_RAID_MAP; /* 0x3288, Total Size */
536 536
537 537 typedef struct _LD_TARGET_SYNC {
538 538 U8 ldTargetId;
539 539 U8 reserved;
540 540 U16 seqNum;
541 541 } LD_TARGET_SYNC;
542 542
543 543 #pragma pack()
544 544
545 545 struct IO_REQUEST_INFO {
546 546 U64 ldStartBlock;
547 547 U32 numBlocks;
548 548 U16 ldTgtId;
549 549 U8 isRead;
550 550 U16 devHandle;
551 551 U64 pdBlock;
552 552 U8 fpOkForIo;
553 553 U8 ldPI;
554 554 };
555 555
556 556 #endif /* _FUSION_H_ */
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