--- old/exception_lists/cstyle	Wed Sep  7 11:32:31 2011
+++ new/exception_lists/cstyle	Wed Sep  7 11:32:31 2011
@@ -655,6 +655,16 @@
 usr/src/uts/common/gssapi/mechs/krb5/mech/val_cred.c
 usr/src/uts/common/gssapi/mechs/krb5/mech/verify.c
 usr/src/uts/common/gssapi/mechs/krb5/mech/wrap_size_limit.c
+usr/src/uts/common/io/ixgbe/ixgbe_82598.c
+usr/src/uts/common/io/ixgbe/ixgbe_82599.c
+usr/src/uts/common/io/ixgbe/ixgbe_api.c
+usr/src/uts/common/io/ixgbe/ixgbe_api.h
+usr/src/uts/common/io/ixgbe/ixgbe_common.c
+usr/src/uts/common/io/ixgbe/ixgbe_common.h
+usr/src/uts/common/io/ixgbe/ixgbe_osdep.h
+usr/src/uts/common/io/ixgbe/ixgbe_phy.c
+usr/src/uts/common/io/ixgbe/ixgbe_phy.h
+usr/src/uts/common/io/ixgbe/ixgbe_type.h
 usr/src/lib/libkmsagent/common/ApplianceParameters.h
 usr/src/lib/libkmsagent/common/AutoMutex.h
 usr/src/lib/libkmsagent/common/ClientSoapFaultCodes.h
--- old/exception_lists/hdrchk	Wed Sep  7 11:32:32 2011
+++ new/exception_lists/hdrchk	Wed Sep  7 11:32:31 2011
@@ -168,6 +168,7 @@
 usr/src/uts/common/gssapi/mechs/krb5/include/old.h
 usr/src/uts/common/gssapi/mechs/krb5/include/raw.h
 usr/src/uts/common/gssapi/mechs/krb5/include/rsa-md4.h
+usr/src/uts/common/io/ixgbe/ixgbe_common.h
 usr/src/lib/libkmsagent/common/ApplianceParameters.h
 usr/src/lib/libkmsagent/common/AutoMutex.h
 usr/src/lib/libkmsagent/common/ClientSoapFaultCodes.h
--- old/usr/src/uts/common/io/ixgbe/ixgbe_82598.c	Wed Sep  7 11:32:32 2011
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_82598.c	Wed Sep  7 11:32:32 2011
@@ -1,35 +1,37 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at:
- *      http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When using or redistributing this file, you may do so under the
- * License only. No other modification of this header is permitted.
- *
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
+/******************************************************************************
 
-/*
- * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
- */
+  Copyright (c) 2001-2010, Intel Corporation 
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without 
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice, 
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright 
+      notice, this list of conditions and the following disclaimer in the 
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its 
+      contributors may be used to endorse or promote products derived from 
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
 
-/*
- * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
- */
+******************************************************************************/
+/*$FreeBSD$*/
 
-/* IntelVersion: 1.167 scm_061610_003709 */
-
 #include "ixgbe_type.h"
 #include "ixgbe_api.h"
 #include "ixgbe_common.h"
@@ -38,18 +40,23 @@
 u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);
 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
-    ixgbe_link_speed *speed, bool *autoneg);
+                                             ixgbe_link_speed *speed,
+                                             bool *autoneg);
 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
 					bool autoneg_wait_to_complete);
 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
-    ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete);
+                                      ixgbe_link_speed *speed, bool *link_up,
+                                      bool link_up_wait_to_complete);
 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed, bool autoneg,
-    bool autoneg_wait_to_complete);
+                                            ixgbe_link_speed speed,
+                                            bool autoneg,
+                                            bool autoneg_wait_to_complete);
 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete);
+                                               ixgbe_link_speed speed,
+                                               bool autoneg,
+                                               bool autoneg_wait_to_complete);
 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw);
 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw);
@@ -56,30 +63,28 @@
 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan,
-    u32 vind, bool vlan_on);
+                         u32 vind, bool vlan_on);
 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
-    u8 *eeprom_data);
+                                u8 *eeprom_data);
 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);
-static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw);
 
-/*
- * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
- * @hw: pointer to the HW structure
+/**
+ *  ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
+ *  @hw: pointer to the HW structure
  *
- * The defaults for 82598 should be in the range of 50us to 50ms,
- * however the hardware default for these parts is 500us to 1ms which is less
- * than the 10ms recommended by the pci-e spec.  To address this we need to
- * increase the value to either 10ms to 250ms for capability version 1 config,
- * or 16ms to 55ms for version 2.
- */
-void
-ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
+ *  The defaults for 82598 should be in the range of 50us to 50ms,
+ *  however the hardware default for these parts is 500us to 1ms which is less
+ *  than the 10ms recommended by the pci-e spec.  To address this we need to
+ *  increase the value to either 10ms to 250ms for capability version 1 config,
+ *  or 16ms to 55ms for version 2.
+ **/
+void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
 {
 	u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
 	u16 pcie_devctl2;
@@ -111,15 +116,14 @@
 	IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
 }
 
-/*
- * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
+ *  @hw: pointer to hardware structure
  *
- * Read PCIe configuration space, and get the MSI-X vector count from
- * the capabilities table.
- */
-u32
-ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
+ *  Read PCIe configuration space, and get the MSI-X vector count from
+ *  the capabilities table.
+ **/
+u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
 {
 	u32 msix_count = 18;
 
@@ -127,27 +131,24 @@
 
 	if (hw->mac.msix_vectors_from_pcie) {
 		msix_count = IXGBE_READ_PCIE_WORD(hw,
-		    IXGBE_PCIE_MSIX_82598_CAPS);
+		                                  IXGBE_PCIE_MSIX_82598_CAPS);
 		msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
 
-		/*
-		 * MSI-X count is zero-based in HW, so increment to give
-		 * proper value
-		 */
+		/* MSI-X count is zero-based in HW, so increment to give
+		 * proper value */
 		msix_count++;
 	}
-	return (msix_count);
+	return msix_count;
 }
 
-/*
- * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_init_ops_82598 - Inits func ptrs and MAC type
+ *  @hw: pointer to hardware structure
  *
- * Initialize the function pointers and assign the MAC type for 82598.
- * Does not touch the hardware.
- */
-s32
-ixgbe_init_ops_82598(struct ixgbe_hw *hw)
+ *  Initialize the function pointers and assign the MAC type for 82598.
+ *  Does not touch the hardware.
+ **/
+s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 	struct ixgbe_phy_info *phy = &hw->phy;
@@ -167,7 +168,7 @@
 	mac->ops.reset_hw = &ixgbe_reset_hw_82598;
 	mac->ops.get_media_type = &ixgbe_get_media_type_82598;
 	mac->ops.get_supported_physical_layer =
-	    &ixgbe_get_supported_physical_layer_82598;
+	                            &ixgbe_get_supported_physical_layer_82598;
 	mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
 	mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
 	mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
@@ -181,11 +182,12 @@
 	/* Flow Control */
 	mac->ops.fc_enable = &ixgbe_fc_enable_82598;
 
-	mac->mcft_size = 128;
-	mac->vft_size = 128;
+	mac->mcft_size       = 128;
+	mac->vft_size        = 128;
 	mac->num_rar_entries = 16;
-	mac->max_tx_queues = 32;
-	mac->max_rx_queues = 64;
+	mac->rx_pb_size      = 512;
+	mac->max_tx_queues   = 32;
+	mac->max_rx_queues   = 64;
 	mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
 
 	/* SFP+ Module */
@@ -196,22 +198,21 @@
 	mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
 	mac->ops.flap_tx_laser = NULL;
 	mac->ops.get_link_capabilities =
-	    &ixgbe_get_link_capabilities_82598;
+	                       &ixgbe_get_link_capabilities_82598;
 
-	return (ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_init_phy_ops_82598 - PHY/SFP specific init
+ *  @hw: pointer to hardware structure
  *
- * Initialize any function pointers that were not able to be
- * set during init_shared_code because the PHY/SFP type was
- * not known.  Perform the SFP init if necessary.
+ *  Initialize any function pointers that were not able to be
+ *  set during init_shared_code because the PHY/SFP type was
+ *  not known.  Perform the SFP init if necessary.
  *
- */
-s32
-ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
+ **/
+s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 	struct ixgbe_phy_info *phy = &hw->phy;
@@ -227,7 +228,7 @@
 	if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 		mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
 		mac->ops.get_link_capabilities =
-		    &ixgbe_get_copper_link_capabilities_generic;
+		                  &ixgbe_get_copper_link_capabilities_generic;
 	}
 
 	switch (hw->phy.type) {
@@ -235,11 +236,11 @@
 		phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
 		phy->ops.check_link = &ixgbe_check_phy_link_tnx;
 		phy->ops.get_firmware_version =
-		    &ixgbe_get_phy_firmware_version_tnx;
+		             &ixgbe_get_phy_firmware_version_tnx;
 		break;
 	case ixgbe_phy_aq:
 		phy->ops.get_firmware_version =
-		    &ixgbe_get_phy_firmware_version_generic;
+		             &ixgbe_get_phy_firmware_version_generic;
 		break;
 	case ixgbe_phy_nl:
 		phy->ops.reset = &ixgbe_reset_phy_nl;
@@ -255,7 +256,8 @@
 
 		/* Check to see if SFP+ module is supported */
 		ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
-		    &list_offset, &data_offset);
+		                                            &list_offset,
+		                                            &data_offset);
 		if (ret_val != IXGBE_SUCCESS) {
 			ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 			goto out;
@@ -264,19 +266,20 @@
 	default:
 		break;
 	}
+
 out:
-	return (ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
+ *  @hw: pointer to hardware structure
  *
- * Starts the hardware using the generic start_hw function.
- * Disables relaxed ordering Then set pcie completion timeout
- */
-s32
-ixgbe_start_hw_82598(struct ixgbe_hw *hw)
+ *  Starts the hardware using the generic start_hw function.
+ *  Disables relaxed ordering Then set pcie completion timeout
+ *
+ **/
+s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
 {
 	u32 regval;
 	u32 i;
@@ -286,11 +289,9 @@
 
 	ret_val = ixgbe_start_hw_generic(hw);
 
-	/*
-	 * Disable relaxed ordering
-	 */
+	/* Disable relaxed ordering */
 	for (i = 0; ((i < hw->mac.max_tx_queues) &&
-	    (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
+	     (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
 		regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
@@ -297,10 +298,10 @@
 	}
 
 	for (i = 0; ((i < hw->mac.max_rx_queues) &&
-	    (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
+	     (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 		regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
-		    IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+		            IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
 	}
 
@@ -308,20 +309,20 @@
 	if (ret_val == IXGBE_SUCCESS)
 		ixgbe_set_pcie_completion_timeout(hw);
 
-	return (ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_get_link_capabilities_82598 - Determines link capabilities
- * @hw: pointer to hardware structure
- * @speed: pointer to link speed
- * @autoneg: boolean auto-negotiation value
+/**
+ *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
+ *  @hw: pointer to hardware structure
+ *  @speed: pointer to link speed
+ *  @autoneg: boolean auto-negotiation value
  *
- * Determines the link capabilities by reading the AUTOC register.
- */
-static s32
-ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
-    ixgbe_link_speed *speed, bool *autoneg)
+ *  Determines the link capabilities by reading the AUTOC register.
+ **/
+static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
+                                             ixgbe_link_speed *speed,
+                                             bool *autoneg)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 autoc = 0;
@@ -341,17 +342,17 @@
 	switch (autoc & IXGBE_AUTOC_LMS_MASK) {
 	case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
-		*autoneg = false;
+		*autoneg = FALSE;
 		break;
 
 	case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
-		*autoneg = false;
+		*autoneg = FALSE;
 		break;
 
 	case IXGBE_AUTOC_LMS_1G_AN:
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
-		*autoneg = true;
+		*autoneg = TRUE;
 		break;
 
 	case IXGBE_AUTOC_LMS_KX4_AN:
@@ -361,7 +362,7 @@
 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
 		if (autoc & IXGBE_AUTOC_KX_SUPP)
 			*speed |= IXGBE_LINK_SPEED_1GB_FULL;
-		*autoneg = true;
+		*autoneg = TRUE;
 		break;
 
 	default:
@@ -369,17 +370,16 @@
 		break;
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_get_media_type_82598 - Determines media type
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_media_type_82598 - Determines media type
+ *  @hw: pointer to hardware structure
  *
- * Returns the media type (fiber, copper, backplane)
- */
-static enum ixgbe_media_type
-ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
+ *  Returns the media type (fiber, copper, backplane)
+ **/
+static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
 {
 	enum ixgbe_media_type media_type;
 
@@ -386,11 +386,14 @@
 	DEBUGFUNC("ixgbe_get_media_type_82598");
 
 	/* Detect if there is a copper PHY attached. */
-	if (hw->phy.type == ixgbe_phy_cu_unknown ||
-	    hw->phy.type == ixgbe_phy_tn ||
-	    hw->phy.type == ixgbe_phy_aq) {
+	switch (hw->phy.type) {
+	case ixgbe_phy_cu_unknown:
+	case ixgbe_phy_tn:
+	case ixgbe_phy_aq:
 		media_type = ixgbe_media_type_copper;
 		goto out;
+	default:
+		break;
 	}
 
 	/* Media type for I82598 is based on device ID */
@@ -421,23 +424,23 @@
 		break;
 	}
 out:
-	return (media_type);
+	return media_type;
 }
 
-/*
- * ixgbe_fc_enable_82598 - Enable flow control
- * @hw: pointer to hardware structure
- * @packetbuf_num: packet buffer number (0-7)
+/**
+ *  ixgbe_fc_enable_82598 - Enable flow control
+ *  @hw: pointer to hardware structure
+ *  @packetbuf_num: packet buffer number (0-7)
  *
- * Enable flow control according to the current settings.
- */
-s32
-ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
+ *  Enable flow control according to the current settings.
+ **/
+s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 {
 	s32 ret_val = IXGBE_SUCCESS;
 	u32 fctrl_reg;
 	u32 rmcs_reg;
 	u32 reg;
+	u32 rx_pba_size;
 	u32 link_speed = 0;
 	bool link_up;
 
@@ -448,7 +451,7 @@
 	 * so if it's on turn it off once we know link_speed. For
 	 * more details see 82598 Specification update.
 	 */
-	hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
+	hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
 	if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
 		switch (hw->fc.requested_mode) {
 		case ixgbe_fc_full:
@@ -481,7 +484,7 @@
 	 * 1: Rx flow control is enabled (we can receive pause frames,
 	 *    but not send pause frames).
 	 * 2: Tx flow control is enabled (we can send pause frames but
-	 *    we do not support receiving pause frames).
+	 *     we do not support receiving pause frames).
 	 * 3: Both Rx and Tx flow control (symmetric) are enabled.
 	 * other: Invalid.
 	 */
@@ -528,16 +531,19 @@
 
 	/* Set up and enable Rx high/low water mark thresholds, enable XON. */
 	if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
-		if (hw->fc.send_xon) {
-			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
-			    (hw->fc.low_water | IXGBE_FCRTL_XONE));
-		} else {
-			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
-			    hw->fc.low_water);
-		}
+		rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
+		rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
 
-		IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
-		    (hw->fc.high_water | IXGBE_FCRTH_FCEN));
+		reg = (rx_pba_size - hw->fc.low_water) << 6;
+		if (hw->fc.send_xon)
+			reg |= IXGBE_FCRTL_XONE;
+
+		IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
+
+		reg = (rx_pba_size - hw->fc.high_water) << 6;
+		reg |= IXGBE_FCRTH_FCEN;
+
+		IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
 	}
 
 	/* Configure pause time (2 TCs per register) */
@@ -551,18 +557,18 @@
 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
 
 out:
-	return (ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_start_mac_link_82598 - Configures MAC link settings
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_start_mac_link_82598 - Configures MAC link settings
+ *  @hw: pointer to hardware structure
  *
- * Configures link settings based on values in the ixgbe_hw struct.
- * Restarts the link.  Performs autonegotiation if needed.
- */
-static s32
-ixgbe_start_mac_link_82598(struct ixgbe_hw *hw, bool autoneg_wait_to_complete)
+ *  Configures link settings based on values in the ixgbe_hw struct.
+ *  Restarts the link.  Performs autonegotiation if needed.
+ **/
+static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
+                                      bool autoneg_wait_to_complete)
 {
 	u32 autoc_reg;
 	u32 links_reg;
@@ -579,9 +585,9 @@
 	/* Only poll for autoneg to complete if specified to do so */
 	if (autoneg_wait_to_complete) {
 		if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
-		    IXGBE_AUTOC_LMS_KX4_AN ||
+		     IXGBE_AUTOC_LMS_KX4_AN ||
 		    (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
-		    IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
+		     IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 			links_reg = 0; /* Just in case Autoneg time = 0 */
 			for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 				links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
@@ -599,22 +605,57 @@
 	/* Add delay to filter out noises during initial link setup */
 	msec_delay(50);
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_check_mac_link_82598 - Get link/speed status
- * @hw: pointer to hardware structure
- * @speed: pointer to link speed
- * @link_up: true is link is up, false otherwise
- * @link_up_wait_to_complete: bool used to wait for link up or not
+/**
+ *  ixgbe_validate_link_ready - Function looks for phy link
+ *  @hw: pointer to hardware structure
  *
- * Reads the links register to determine if link is up and the current speed
- */
-static s32
-ixgbe_check_mac_link_82598(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
-    bool *link_up, bool link_up_wait_to_complete)
+ *  Function indicates success when phy link is available. If phy is not ready
+ *  within 5 seconds of MAC indicating link, the function returns error.
+ **/
+static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
 {
+	u32 timeout;
+	u16 an_reg;
+
+	if (hw->device_id != IXGBE_DEV_ID_82598AT2)
+		return IXGBE_SUCCESS;
+
+	for (timeout = 0;
+	     timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
+		hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
+		                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
+
+		if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&
+		    (an_reg & IXGBE_MII_AUTONEG_LINK_UP))
+			break;
+
+		msec_delay(100);
+	}
+
+	if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
+		DEBUGOUT("Link was indicated but link is down\n");
+		return IXGBE_ERR_LINK_SETUP;
+	}
+
+	return IXGBE_SUCCESS;
+}
+
+/**
+ *  ixgbe_check_mac_link_82598 - Get link/speed status
+ *  @hw: pointer to hardware structure
+ *  @speed: pointer to link speed
+ *  @link_up: TRUE is link is up, FALSE otherwise
+ *  @link_up_wait_to_complete: bool used to wait for link up or not
+ *
+ *  Reads the links register to determine if link is up and the current speed
+ **/
+static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
+                                      ixgbe_link_speed *speed, bool *link_up,
+                                      bool link_up_wait_to_complete)
+{
 	u32 links_reg;
 	u32 i;
 	u16 link_reg, adapt_comp_reg;
@@ -631,31 +672,32 @@
 		hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 		hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 		hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
-		    &adapt_comp_reg);
+		                     &adapt_comp_reg);
 		if (link_up_wait_to_complete) {
 			for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 				if ((link_reg & 1) &&
 				    ((adapt_comp_reg & 1) == 0)) {
-					*link_up = true;
+					*link_up = TRUE;
 					break;
 				} else {
-					*link_up = false;
+					*link_up = FALSE;
 				}
 				msec_delay(100);
 				hw->phy.ops.read_reg(hw, 0xC79F,
-				    IXGBE_TWINAX_DEV, &link_reg);
+				                     IXGBE_TWINAX_DEV,
+				                     &link_reg);
 				hw->phy.ops.read_reg(hw, 0xC00C,
-				    IXGBE_TWINAX_DEV, &adapt_comp_reg);
+				                     IXGBE_TWINAX_DEV,
+				                     &adapt_comp_reg);
 			}
 		} else {
-			if ((link_reg & 1) &&
-			    ((adapt_comp_reg & 1) == 0))
-				*link_up = true;
+			if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
+				*link_up = TRUE;
 			else
-				*link_up = false;
+				*link_up = FALSE;
 		}
 
-		if (*link_up == false)
+		if (*link_up == FALSE)
 			goto out;
 	}
 
@@ -663,10 +705,10 @@
 	if (link_up_wait_to_complete) {
 		for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 			if (links_reg & IXGBE_LINKS_UP) {
-				*link_up = true;
+				*link_up = TRUE;
 				break;
 			} else {
-				*link_up = false;
+				*link_up = FALSE;
 			}
 			msec_delay(100);
 			links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
@@ -673,9 +715,9 @@
 		}
 	} else {
 		if (links_reg & IXGBE_LINKS_UP)
-			*link_up = true;
+			*link_up = TRUE;
 		else
-			*link_up = false;
+			*link_up = FALSE;
 	}
 
 	if (links_reg & IXGBE_LINKS_SPEED)
@@ -683,39 +725,37 @@
 	else
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
 
-	if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&
+	if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) &&
 	    (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
-		*link_up = false;
+		*link_up = FALSE;
 
 	/* if link is down, zero out the current_mode */
-	if (*link_up == false) {
+	if (*link_up == FALSE) {
 		hw->fc.current_mode = ixgbe_fc_none;
-		hw->fc.fc_was_autonegged = false;
+		hw->fc.fc_was_autonegged = FALSE;
 	}
-
 out:
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_setup_mac_link_82598 - Set MAC link speed
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- * @autoneg_wait_to_complete: true when waiting for completion is needed
+/**
+ *  ixgbe_setup_mac_link_82598 - Set MAC link speed
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: TRUE if autonegotiation enabled
+ *  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
  *
- * Set the link speed in the AUTOC register and restarts link.
- */
-static s32
-ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed, bool autoneg,
-    bool autoneg_wait_to_complete)
+ *  Set the link speed in the AUTOC register and restarts link.
+ **/
+static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
+                                           ixgbe_link_speed speed, bool autoneg,
+                                           bool autoneg_wait_to_complete)
 {
-	s32 status = IXGBE_SUCCESS;
+	s32              status            = IXGBE_SUCCESS;
 	ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
-	u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
-	u32 autoc = curr_autoc;
-	u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
+	u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+	u32              autoc             = curr_autoc;
+	u32              link_mode         = autoc & IXGBE_AUTOC_LMS_MASK;
 
 	DEBUGFUNC("ixgbe_setup_mac_link_82598");
 
@@ -723,11 +763,12 @@
 	(void) ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
 	speed &= link_capabilities;
 
-	if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
+	if (speed == IXGBE_LINK_SPEED_UNKNOWN)
 		status = IXGBE_ERR_LINK_SETUP;
-	} else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
-	    link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
-		/* Set KX4/KX support according to speed requested */
+
+	/* Set KX4/KX support according to speed requested */
+	else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
+	         link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 		autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
 		if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 			autoc |= IXGBE_AUTOC_KX4_SUPP;
@@ -744,26 +785,26 @@
 		 * stored values
 		 */
 		status = ixgbe_start_mac_link_82598(hw,
-		    autoneg_wait_to_complete);
+		                                    autoneg_wait_to_complete);
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- * @autoneg_wait_to_complete: true if waiting is needed to complete
+
+/**
+ *  ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: TRUE if autonegotiation enabled
+ *  @autoneg_wait_to_complete: TRUE if waiting is needed to complete
  *
- * Sets the link speed in the AUTOC register in the MAC and restarts link.
- */
-static s32
-ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed,
-    bool autoneg,
-    bool autoneg_wait_to_complete)
+ *  Sets the link speed in the AUTOC register in the MAC and restarts link.
+ **/
+static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
+                                               ixgbe_link_speed speed,
+                                               bool autoneg,
+                                               bool autoneg_wait_to_complete)
 {
 	s32 status;
 
@@ -771,24 +812,22 @@
 
 	/* Setup the PHY according to input speed */
 	status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
-	    autoneg_wait_to_complete);
-
+	                                      autoneg_wait_to_complete);
 	/* Set up MAC */
 	(void) ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_reset_hw_82598 - Performs hardware reset
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_reset_hw_82598 - Performs hardware reset
+ *  @hw: pointer to hardware structure
  *
- * Resets the hardware by resetting the transmit and receive units, masks and
- * clears all interrupts, performing a PHY reset, and performing a link (MAC)
- * reset.
- */
-static s32
-ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
+ *  Resets the hardware by resetting the transmit and receive units, masks and
+ *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
+ *  reset.
+ **/
+static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_SUCCESS;
 	s32 phy_status = IXGBE_SUCCESS;
@@ -812,32 +851,32 @@
 	if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
 		/* Enable Tx Atlas so packets can be transmitted again */
 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
-		    &analog_val);
+		                             &analog_val);
 		analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
-		    analog_val);
+		                              analog_val);
 
 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
-		    &analog_val);
+		                             &analog_val);
 		analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
-		    analog_val);
+		                              analog_val);
 
 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
-		    &analog_val);
+		                             &analog_val);
 		analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
-		    analog_val);
+		                              analog_val);
 
 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
-		    &analog_val);
+		                             &analog_val);
 		analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
-		    analog_val);
+		                              analog_val);
 	}
 
 	/* Reset PHY */
-	if (hw->phy.reset_disable == false) {
+	if (hw->phy.reset_disable == FALSE) {
 		/* PHY ops must be identified and initialized prior to reset */
 
 		/* Init PHY and function pointers, perform SFP setup */
@@ -858,7 +897,6 @@
 	(void) ixgbe_disable_pcie_master(hw);
 
 mac_reset_top:
-
 	/*
 	 * Issue global reset to the MAC.  This needs to be a SW reset.
 	 * If link reset is used, it might reset the MAC when mng is using it
@@ -891,6 +929,7 @@
 		usec_delay(1);
 		goto mac_reset_top;
 	}
+
 	msec_delay(50);
 
 	gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
@@ -903,9 +942,9 @@
 	 * AUTOC value since the reset operation sets back to deaults.
 	 */
 	autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
-	if (hw->mac.orig_link_settings_stored == false) {
+	if (hw->mac.orig_link_settings_stored == FALSE) {
 		hw->mac.orig_autoc = autoc;
-		hw->mac.orig_link_settings_stored = true;
+		hw->mac.orig_link_settings_stored = TRUE;
 	} else if (autoc != hw->mac.orig_autoc) {
 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
 	}
@@ -923,37 +962,42 @@
 	if (phy_status != IXGBE_SUCCESS)
 		status = phy_status;
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
- * @hw: pointer to hardware struct
- * @rar: receive address register index to associate with a VMDq index
- * @vmdq: VMDq set index
- */
-s32
-ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
+/**
+ *  ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
+ *  @hw: pointer to hardware struct
+ *  @rar: receive address register index to associate with a VMDq index
+ *  @vmdq: VMDq set index
+ **/
+s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 {
 	u32 rar_high;
+	u32 rar_entries = hw->mac.num_rar_entries;
 
 	DEBUGFUNC("ixgbe_set_vmdq_82598");
 
+	/* Make sure we are using a valid rar index range */
+	if (rar >= rar_entries) {
+		DEBUGOUT1("RAR index %d is out of range.\n", rar);
+		return IXGBE_ERR_INVALID_ARGUMENT;
+	}
+
 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 	rar_high &= ~IXGBE_RAH_VIND_MASK;
 	rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
 	IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
- * @hw: pointer to hardware struct
- * @rar: receive address register index to associate with a VMDq index
- * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
- */
-static s32
-ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
+/**
+ *  ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
+ *  @hw: pointer to hardware struct
+ *  @rar: receive address register index to associate with a VMDq index
+ *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)
+ **/
+static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 {
 	u32 rar_high;
 	u32 rar_entries = hw->mac.num_rar_entries;
@@ -960,30 +1004,32 @@
 
 	UNREFERENCED_PARAMETER(vmdq);
 
-	if (rar < rar_entries) {
-		rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
-		if (rar_high & IXGBE_RAH_VIND_MASK) {
-			rar_high &= ~IXGBE_RAH_VIND_MASK;
-			IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
-		}
-	} else {
+	/* Make sure we are using a valid rar index range */
+	if (rar >= rar_entries) {
 		DEBUGOUT1("RAR index %d is out of range.\n", rar);
+		return IXGBE_ERR_INVALID_ARGUMENT;
 	}
 
-	return (IXGBE_SUCCESS);
+	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
+	if (rar_high & IXGBE_RAH_VIND_MASK) {
+		rar_high &= ~IXGBE_RAH_VIND_MASK;
+		IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
+	}
+
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_set_vfta_82598 - Set VLAN filter table
- * @hw: pointer to hardware structure
- * @vlan: VLAN id to write to VLAN filter
- * @vind: VMDq output index that maps queue to VLAN id in VFTA
- * @vlan_on: boolean flag to turn on/off VLAN in VFTA
+/**
+ *  ixgbe_set_vfta_82598 - Set VLAN filter table
+ *  @hw: pointer to hardware structure
+ *  @vlan: VLAN id to write to VLAN filter
+ *  @vind: VMDq output index that maps queue to VLAN id in VFTA
+ *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
  *
- * Turn on/off specified VLAN in the VLAN filter table.
- */
-s32
-ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
+ *  Turn on/off specified VLAN in the VLAN filter table.
+ **/
+s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
+	                                              bool vlan_on)
 {
 	u32 regindex;
 	u32 bitindex;
@@ -993,7 +1039,7 @@
 	DEBUGFUNC("ixgbe_set_vfta_82598");
 
 	if (vlan > 4095)
-		return (IXGBE_ERR_PARAM);
+		return IXGBE_ERR_PARAM;
 
 	/* Determine 32-bit word position in array */
 	regindex = (vlan >> 5) & 0x7F;   /* upper seven bits */
@@ -1020,17 +1066,16 @@
 		bits &= ~(1 << bitindex);
 	IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_clear_vfta_82598 - Clear VLAN filter table
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_clear_vfta_82598 - Clear VLAN filter table
+ *  @hw: pointer to hardware structure
  *
- * Clears the VLAN filer table, and the VMDq index associated with the filter
- */
-static s32
-ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
+ *  Clears the VLAN filer table, and the VMDq index associated with the filter
+ **/
+static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
 {
 	u32 offset;
 	u32 vlanbyte;
@@ -1042,22 +1087,21 @@
 
 	for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
 		for (offset = 0; offset < hw->mac.vft_size; offset++)
-			IXGBE_WRITE_REG(hw,
-			    IXGBE_VFTAVIND(vlanbyte, offset), 0);
+			IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
+			                0);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
- * @hw: pointer to hardware structure
- * @reg: analog register to read
- * @val: read value
+/**
+ *  ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
+ *  @hw: pointer to hardware structure
+ *  @reg: analog register to read
+ *  @val: read value
  *
- * Performs read operation to Atlas analog register specified.
- */
-s32
-ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
+ *  Performs read operation to Atlas analog register specified.
+ **/
+s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
 {
 	u32  atlas_ctl;
 
@@ -1064,25 +1108,24 @@
 	DEBUGFUNC("ixgbe_read_analog_reg8_82598");
 
 	IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
-	    IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
+	                IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
 	IXGBE_WRITE_FLUSH(hw);
 	usec_delay(10);
 	atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 	*val = (u8)atlas_ctl;
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
- * @hw: pointer to hardware structure
- * @reg: atlas register to write
- * @val: value to write
+/**
+ *  ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
+ *  @hw: pointer to hardware structure
+ *  @reg: atlas register to write
+ *  @val: value to write
  *
- * Performs write operation to Atlas analog register specified.
- */
-s32
-ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
+ *  Performs write operation to Atlas analog register specified.
+ **/
+s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
 {
 	u32  atlas_ctl;
 
@@ -1093,20 +1136,19 @@
 	IXGBE_WRITE_FLUSH(hw);
 	usec_delay(10);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
- * @hw: pointer to hardware structure
- * @byte_offset: EEPROM byte offset to read
- * @eeprom_data: value read
+/**
+ *  ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: EEPROM byte offset to read
+ *  @eeprom_data: value read
  *
- * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
- */
-s32
-ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
-    u8 *eeprom_data)
+ *  Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
+ **/
+s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
+                                u8 *eeprom_data)
 {
 	s32 status = IXGBE_SUCCESS;
 	u16 sfp_addr = 0;
@@ -1124,14 +1166,17 @@
 		 */
 		sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
 		sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
-		hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
-		    IXGBE_MDIO_PMA_PMD_DEV_TYPE, sfp_addr);
+		hw->phy.ops.write_reg(hw,
+		                      IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
+		                      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+		                      sfp_addr);
 
 		/* Poll status */
 		for (i = 0; i < 100; i++) {
 			hw->phy.ops.read_reg(hw,
-			    IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
-			    IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_stat);
+			                     IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
+			                     IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+			                     &sfp_stat);
 			sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
 			if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
 				break;
@@ -1146,7 +1191,7 @@
 
 		/* Read data */
 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
-		    IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
+		                     IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
 
 		*eeprom_data = (u8)(sfp_data >> 8);
 	} else {
@@ -1155,17 +1200,16 @@
 	}
 
 out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
+ *  @hw: pointer to hardware structure
  *
- * Determines physical layer capabilities of the current configuration.
- */
-u32
-ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
+ *  Determines physical layer capabilities of the current configuration.
+ **/
+u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
 {
 	u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 	u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
@@ -1177,14 +1221,14 @@
 
 	hw->phy.ops.identify(hw);
 
-	/*
-	 * Copper PHY must be checked before AUTOC LMS to determine correct
-	 * physical layer because 10GBase-T PHYs use LMS = KX4/KX
-	 */
-	if (hw->phy.type == ixgbe_phy_tn ||
-	    hw->phy.type == ixgbe_phy_cu_unknown) {
+	/* Copper PHY must be checked before AUTOC LMS to determine correct
+	 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
+	switch (hw->phy.type) {
+	case ixgbe_phy_tn:
+	case ixgbe_phy_aq:
+	case ixgbe_phy_cu_unknown:
 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
-		    IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
+		IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 		if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 		if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
@@ -1192,6 +1236,8 @@
 		if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 		goto out;
+	default:
+		break;
 	}
 
 	switch (autoc & IXGBE_AUTOC_LMS_MASK) {
@@ -1257,22 +1303,22 @@
 	}
 
 out:
-	return (physical_layer);
+	return physical_layer;
 }
 
-/*
- * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
- * port devices.
- * @hw: pointer to the HW structure
+/**
+ *  ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
+ *  port devices.
+ *  @hw: pointer to the HW structure
  *
- * Calls common function and corrects issue with some single port devices
- * that enable LAN1 but not LAN0.
- */
-void
-ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
+ *  Calls common function and corrects issue with some single port devices
+ *  that enable LAN1 but not LAN0.
+ **/
+void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
 {
 	struct ixgbe_bus_info *bus = &hw->bus;
-	u16 pci_gen, pci_ctrl2;
+	u16 pci_gen = 0;
+	u16 pci_ctrl2 = 0;
 
 	DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598");
 
@@ -1281,6 +1327,7 @@
 	/* check if LAN0 is disabled */
 	hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
 	if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
+
 		hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
 
 		/* if LAN0 is completely disabled force function to 0 */
@@ -1287,54 +1334,19 @@
 		if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
 		    !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
 		    !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
+
 			bus->func = 0;
 		}
 	}
 }
 
-/*
- * ixgbe_validate_link_ready - Function looks for phy link
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering
+ *  @hw: pointer to hardware structure
  *
- * Function indicates success when phy link is available. If phy is not ready
- * within 5 seconds of MAC indicating link, the function returns error.
- */
-static s32
-ixgbe_validate_link_ready(struct ixgbe_hw *hw)
+ **/
+void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
 {
-	u32 timeout;
-	u16 an_reg;
-
-	if (hw->device_id != IXGBE_DEV_ID_82598AT2)
-		return (IXGBE_SUCCESS);
-
-	for (timeout = 0;
-	    timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
-		hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
-
-		if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&
-		    (an_reg & IXGBE_MII_AUTONEG_LINK_UP))
-			break;
-
-		msec_delay(100);
-	}
-
-	if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
-		DEBUGOUT("Link was indicated but link is down\n");
-		return (IXGBE_ERR_LINK_SETUP);
-	}
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering
- * @hw: pointer to hardware structure
- */
-void
-ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
-{
 	u32 regval;
 	u32 i;
 
@@ -1342,7 +1354,7 @@
 
 	/* Enable relaxed ordering */
 	for (i = 0; ((i < hw->mac.max_tx_queues) &&
-	    (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
+	     (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
 		regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
@@ -1349,10 +1361,11 @@
 	}
 
 	for (i = 0; ((i < hw->mac.max_rx_queues) &&
-	    (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
+	     (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 		regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
-		    IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+		           IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
 	}
+
 }
--- old/usr/src/uts/common/io/ixgbe/ixgbe_82599.c	Wed Sep  7 11:32:33 2011
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_82599.c	Wed Sep  7 11:32:33 2011
@@ -1,35 +1,37 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at:
- *      http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When using or redistributing this file, you may do so under the
- * License only. No other modification of this header is permitted.
- *
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
+/******************************************************************************
 
-/*
- * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
- */
+  Copyright (c) 2001-2010, Intel Corporation 
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without 
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice, 
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright 
+      notice, this list of conditions and the following disclaimer in the 
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its 
+      contributors may be used to endorse or promote products derived from 
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
 
-/*
- * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
- */
+******************************************************************************/
+/*$FreeBSD$*/
 
-/* IntelVersion: 1.217 scm_061610_003709 */
-
 #include "ixgbe_type.h"
 #include "ixgbe_api.h"
 #include "ixgbe_common.h"
@@ -37,23 +39,28 @@
 
 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
-    ixgbe_link_speed *speed, bool *autoneg);
+                                      ixgbe_link_speed *speed,
+                                      bool *autoneg);
 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete);
+                                     ixgbe_link_speed speed, bool autoneg,
+                                     bool autoneg_wait_to_complete);
 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete);
+				     ixgbe_link_speed speed, bool autoneg,
+				     bool autoneg_wait_to_complete);
 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
-    bool autoneg_wait_to_complete);
+				bool autoneg_wait_to_complete);
 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed, bool autoneg,
-    bool autoneg_wait_to_complete);
+                                     ixgbe_link_speed speed,
+                                     bool autoneg,
+                                     bool autoneg_wait_to_complete);
 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed, bool autoneg,
-    bool autoneg_wait_to_complete);
+                                               ixgbe_link_speed speed,
+                                               bool autoneg,
+                                               bool autoneg_wait_to_complete);
 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw);
 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw);
 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
@@ -60,53 +67,59 @@
 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw);
-void ixgbe_enable_relaxed_ordering_82599(struct ixgbe_hw *hw);
 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
-s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps);
 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
+bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
 
-void
-ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
+
+void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 
 	DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
 
-	if (hw->phy.multispeed_fiber) {
-		/* Set up dual speed SFP+ support */
-		mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
+	/* enable the laser control functions for SFP+ fiber */
+	if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
 		mac->ops.disable_tx_laser =
-		    &ixgbe_disable_tx_laser_multispeed_fiber;
+		                       &ixgbe_disable_tx_laser_multispeed_fiber;
 		mac->ops.enable_tx_laser =
-		    &ixgbe_enable_tx_laser_multispeed_fiber;
+		                        &ixgbe_enable_tx_laser_multispeed_fiber;
 		mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
+
 	} else {
 		mac->ops.disable_tx_laser = NULL;
 		mac->ops.enable_tx_laser = NULL;
 		mac->ops.flap_tx_laser = NULL;
+	}
+
+	if (hw->phy.multispeed_fiber) {
+		/* Set up dual speed SFP+ support */
+		mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
+	} else {
 		if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
-		    (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
-		    hw->phy.smart_speed == ixgbe_smart_speed_on))
+		     (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
+		      hw->phy.smart_speed == ixgbe_smart_speed_on) &&
+		      !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
 			mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
-		else
+		} else {
 			mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
+		}
 	}
 }
 
-/*
- * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_init_phy_ops_82599 - PHY/SFP specific init
+ *  @hw: pointer to hardware structure
  *
- * Initialize any function pointers that were not able to be
- * set during init_shared_code because the PHY/SFP type was
- * not known.  Perform the SFP init if necessary.
+ *  Initialize any function pointers that were not able to be
+ *  set during init_shared_code because the PHY/SFP type was
+ *  not known.  Perform the SFP init if necessary.
  *
- */
-s32
-ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
+ **/
+s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 	struct ixgbe_phy_info *phy = &hw->phy;
@@ -128,7 +141,7 @@
 	if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 		mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
 		mac->ops.get_link_capabilities =
-		    &ixgbe_get_copper_link_capabilities_generic;
+		                  &ixgbe_get_copper_link_capabilities_generic;
 	}
 
 	/* Set necessary function pointers based on phy type */
@@ -137,24 +150,24 @@
 		phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
 		phy->ops.check_link = &ixgbe_check_phy_link_tnx;
 		phy->ops.get_firmware_version =
-		    &ixgbe_get_phy_firmware_version_tnx;
+		             &ixgbe_get_phy_firmware_version_tnx;
 		break;
 	case ixgbe_phy_aq:
 		phy->ops.get_firmware_version =
-		    &ixgbe_get_phy_firmware_version_generic;
+		             &ixgbe_get_phy_firmware_version_generic;
 		break;
 	default:
 		break;
 	}
-
 init_phy_ops_out:
-	return (ret_val);
+	return ret_val;
 }
 
-s32
-ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
+s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
 {
 	s32 ret_val = IXGBE_SUCCESS;
+	u32 reg_anlp1 = 0;
+	u32 i = 0;
 	u16 list_offset, data_offset, data_value;
 
 	DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
@@ -165,8 +178,7 @@
 		hw->phy.ops.reset = NULL;
 
 		ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
-		    &data_offset);
-
+		                                              &data_offset);
 		if (ret_val != IXGBE_SUCCESS)
 			goto setup_sfp_out;
 
@@ -183,30 +195,49 @@
 			IXGBE_WRITE_FLUSH(hw);
 			hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 		}
-		/* Now restart DSP by setting Restart_AN */
-		IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
-		    (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
 
 		/* Release the semaphore */
 		ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
 		/* Delay obtaining semaphore again to allow FW access */
 		msec_delay(hw->eeprom.semaphore_delay);
+
+		/* Now restart DSP by setting Restart_AN and clearing LMS */
+		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
+		                IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
+		                IXGBE_AUTOC_AN_RESTART));
+
+		/* Wait for AN to leave state 0 */
+		for (i = 0; i < 10; i++) {
+			msec_delay(4);
+			reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
+			if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
+				break;
+		}
+		if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
+			DEBUGOUT("sfp module setup not complete\n");
+			ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
+			goto setup_sfp_out;
+		}
+
+		/* Restart DSP by setting Restart_AN and return to SFI mode */
+		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
+		                IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
+		                IXGBE_AUTOC_AN_RESTART));
 	}
 
 setup_sfp_out:
-	return (ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_init_ops_82599 - Inits func ptrs and MAC type
+ *  @hw: pointer to hardware structure
  *
- * Initialize the function pointers and assign the MAC type for 82599.
- * Does not touch the hardware.
- */
+ *  Initialize the function pointers and assign the MAC type for 82599.
+ *  Does not touch the hardware.
+ **/
 
-s32
-ixgbe_init_ops_82599(struct ixgbe_hw *hw)
+s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 	struct ixgbe_phy_info *phy = &hw->phy;
@@ -223,18 +254,17 @@
 
 	/* MAC */
 	mac->ops.reset_hw = &ixgbe_reset_hw_82599;
-	mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82599;
+	mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
 	mac->ops.get_media_type = &ixgbe_get_media_type_82599;
 	mac->ops.get_supported_physical_layer =
-	    &ixgbe_get_supported_physical_layer_82599;
+	                            &ixgbe_get_supported_physical_layer_82599;
 	mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
 	mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
 	mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
 	mac->ops.start_hw = &ixgbe_start_hw_rev_1_82599;
-	mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82599;
 	mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
 	mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
-	mac->ops.get_device_caps = &ixgbe_get_device_caps_82599;
+	mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
 	mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
 	mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
 
@@ -247,33 +277,36 @@
 	mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
 	mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
 	mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
+	mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
+	mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
 
 	/* Link */
 	mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
-	mac->ops.check_link = &ixgbe_check_mac_link_generic;
+	mac->ops.check_link            = &ixgbe_check_mac_link_generic;
 	ixgbe_init_mac_link_ops_82599(hw);
 
-	mac->mcft_size = 128;
-	mac->vft_size = 128;
-	mac->num_rar_entries = 128;
-	mac->max_tx_queues = 128;
-	mac->max_rx_queues = 128;
+	mac->mcft_size        = 128;
+	mac->vft_size         = 128;
+	mac->num_rar_entries  = 128;
+	mac->rx_pb_size       = 512;
+	mac->max_tx_queues    = 128;
+	mac->max_rx_queues    = 128;
 	mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
 
-	return (ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_get_link_capabilities_82599 - Determines link capabilities
- * @hw: pointer to hardware structure
- * @speed: pointer to link speed
- * @negotiation: true when autoneg or autotry is enabled
+/**
+ *  ixgbe_get_link_capabilities_82599 - Determines link capabilities
+ *  @hw: pointer to hardware structure
+ *  @speed: pointer to link speed
+ *  @negotiation: TRUE when autoneg or autotry is enabled
  *
- * Determines the link capabilities by reading the AUTOC register.
- */
-s32
-ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
-    ixgbe_link_speed *speed, bool *negotiation)
+ *  Determines the link capabilities by reading the AUTOC register.
+ **/
+s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
+                                      ixgbe_link_speed *speed,
+                                      bool *negotiation)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 autoc = 0;
@@ -280,11 +313,12 @@
 
 	DEBUGFUNC("ixgbe_get_link_capabilities_82599");
 
+
 	/* Check if 1G SFP module. */
 	if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
 	    hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
-		*negotiation = true;
+		*negotiation = TRUE;
 		goto out;
 	}
 
@@ -301,22 +335,22 @@
 	switch (autoc & IXGBE_AUTOC_LMS_MASK) {
 	case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
-		*negotiation = false;
+		*negotiation = FALSE;
 		break;
 
 	case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
-		*negotiation = false;
+		*negotiation = FALSE;
 		break;
 
 	case IXGBE_AUTOC_LMS_1G_AN:
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
-		*negotiation = true;
+		*negotiation = TRUE;
 		break;
 
 	case IXGBE_AUTOC_LMS_10G_SERIAL:
 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
-		*negotiation = false;
+		*negotiation = FALSE;
 		break;
 
 	case IXGBE_AUTOC_LMS_KX4_KX_KR:
@@ -328,7 +362,7 @@
 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
 		if (autoc & IXGBE_AUTOC_KX_SUPP)
 			*speed |= IXGBE_LINK_SPEED_1GB_FULL;
-		*negotiation = true;
+		*negotiation = TRUE;
 		break;
 
 	case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
@@ -339,12 +373,12 @@
 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
 		if (autoc & IXGBE_AUTOC_KX_SUPP)
 			*speed |= IXGBE_LINK_SPEED_1GB_FULL;
-		*negotiation = true;
+		*negotiation = TRUE;
 		break;
 
 	case IXGBE_AUTOC_LMS_SGMII_1G_100M:
 		*speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
-		*negotiation = false;
+		*negotiation = FALSE;
 		break;
 
 	default:
@@ -354,22 +388,21 @@
 
 	if (hw->phy.multispeed_fiber) {
 		*speed |= IXGBE_LINK_SPEED_10GB_FULL |
-		    IXGBE_LINK_SPEED_1GB_FULL;
-		*negotiation = true;
+		          IXGBE_LINK_SPEED_1GB_FULL;
+		*negotiation = TRUE;
 	}
 
 out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_get_media_type_82599 - Get media type
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_media_type_82599 - Get media type
+ *  @hw: pointer to hardware structure
  *
- * Returns the media type (fiber, copper, backplane)
- */
-enum ixgbe_media_type
-ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
+ *  Returns the media type (fiber, copper, backplane)
+ **/
+enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
 {
 	enum ixgbe_media_type media_type;
 
@@ -376,11 +409,14 @@
 	DEBUGFUNC("ixgbe_get_media_type_82599");
 
 	/* Detect if there is a copper PHY attached. */
-	if (hw->phy.type == ixgbe_phy_cu_unknown ||
-	    hw->phy.type == ixgbe_phy_tn ||
-	    hw->phy.type == ixgbe_phy_aq) {
+	switch (hw->phy.type) {
+	case ixgbe_phy_cu_unknown:
+	case ixgbe_phy_tn:
+	case ixgbe_phy_aq:
 		media_type = ixgbe_media_type_copper;
 		goto out;
+	default:
+		break;
 	}
 
 	switch (hw->device_id) {
@@ -387,13 +423,13 @@
 	case IXGBE_DEV_ID_82599_KX4:
 	case IXGBE_DEV_ID_82599_KX4_MEZZ:
 	case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
-	case IXGBE_DEV_ID_82599_KR:
+	case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
 	case IXGBE_DEV_ID_82599_XAUI_LOM:
 		/* Default device ID is mezzanine card KX/KX4 */
 		media_type = ixgbe_media_type_backplane;
 		break;
 	case IXGBE_DEV_ID_82599_SFP:
-	case IXGBE_DEV_ID_82599_SFP_EM:
+	case IXGBE_DEV_ID_82599_SFP_FCOE:
 		media_type = ixgbe_media_type_fiber;
 		break;
 	case IXGBE_DEV_ID_82599_CX4:
@@ -407,18 +443,19 @@
 		break;
 	}
 out:
-	return (media_type);
+	return media_type;
 }
 
-/*
- * ixgbe_start_mac_link_82599 - Setup MAC link settings
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_start_mac_link_82599 - Setup MAC link settings
+ *  @hw: pointer to hardware structure
+ *  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
  *
- * Configures link settings based on values in the ixgbe_hw struct.
- * Restarts the link.  Performs autonegotiation if needed.
- */
-s32
-ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, bool autoneg_wait_to_complete)
+ *  Configures link settings based on values in the ixgbe_hw struct.
+ *  Restarts the link.  Performs autonegotiation if needed.
+ **/
+s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
+                               bool autoneg_wait_to_complete)
 {
 	u32 autoc_reg;
 	u32 links_reg;
@@ -427,6 +464,7 @@
 
 	DEBUGFUNC("ixgbe_start_mac_link_82599");
 
+
 	/* Restart link */
 	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
@@ -435,11 +473,11 @@
 	/* Only poll for autoneg to complete if specified to do so */
 	if (autoneg_wait_to_complete) {
 		if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
-		    IXGBE_AUTOC_LMS_KX4_KX_KR ||
+		     IXGBE_AUTOC_LMS_KX4_KX_KR ||
 		    (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
-		    IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
+		     IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 		    (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
-		    IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
+		     IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 			links_reg = 0; /* Just in case Autoneg time = 0 */
 			for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 				links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
@@ -457,25 +495,22 @@
 	/* Add delay to filter out noises during initial link setup */
 	msec_delay(50);
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
+ *  @hw: pointer to hardware structure
  *
- * The base drivers may require better control over SFP+ module
- * PHY states.  This includes selectively shutting down the Tx
- * laser on the PHY, effectively halting physical link.
- */
-void
-ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
+ *  The base drivers may require better control over SFP+ module
+ *  PHY states.  This includes selectively shutting down the Tx
+ *  laser on the PHY, effectively halting physical link.
+ **/
+void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
 {
 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
 
-	/*
-	 * Disable tx laser; allow 100us to go dark per spec
-	 */
+	/* Disable tx laser; allow 100us to go dark per spec */
 	esdp_reg |= IXGBE_ESDP_SDP3;
 	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 	IXGBE_WRITE_FLUSH(hw);
@@ -482,22 +517,19 @@
 	usec_delay(100);
 }
 
-/*
- * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
+ *  @hw: pointer to hardware structure
  *
- * The base drivers may require better control over SFP+ module
- * PHY states.  This includes selectively turning on the Tx
- * laser on the PHY, effectively starting physical link.
- */
-void
-ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
+ *  The base drivers may require better control over SFP+ module
+ *  PHY states.  This includes selectively turning on the Tx
+ *  laser on the PHY, effectively starting physical link.
+ **/
+void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
 {
 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
 
-	/*
-	 * Enable tx laser; allow 100ms to light up
-	 */
+	/* Enable tx laser; allow 100ms to light up */
 	esdp_reg &= ~IXGBE_ESDP_SDP3;
 	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 	IXGBE_WRITE_FLUSH(hw);
@@ -504,20 +536,19 @@
 	msec_delay(100);
 }
 
-/*
- * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
+ *  @hw: pointer to hardware structure
  *
- * When the driver changes the link speeds that it can support,
- * it sets autotry_restart to true to indicate that we need to
- * initiate a new autotry session with the link partner.  To do
- * so, we set the speed then disable and re-enable the tx laser, to
- * alert the link partner that it also needs to restart autotry on its
- * end.  This is consistent with true clause 37 autoneg, which also
- * involves a loss of signal.
- */
-void
-ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
+ *  When the driver changes the link speeds that it can support,
+ *  it sets autotry_restart to TRUE to indicate that we need to
+ *  initiate a new autotry session with the link partner.  To do
+ *  so, we set the speed then disable and re-enable the tx laser, to
+ *  alert the link partner that it also needs to restart autotry on its
+ *  end.  This is consistent with TRUE clause 37 autoneg, which also
+ *  involves a loss of signal.
+ **/
+void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
 {
 	DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
 
@@ -524,30 +555,30 @@
 	if (hw->mac.autotry_restart) {
 		ixgbe_disable_tx_laser_multispeed_fiber(hw);
 		ixgbe_enable_tx_laser_multispeed_fiber(hw);
-		hw->mac.autotry_restart = false;
+		hw->mac.autotry_restart = FALSE;
 	}
 }
 
-/*
- * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- * @autoneg_wait_to_complete: true when waiting for completion is needed
+/**
+ *  ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: TRUE if autonegotiation enabled
+ *  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
  *
- * Set the link speed in the AUTOC register and restarts link.
- */
-s32
-ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete)
+ *  Set the link speed in the AUTOC register and restarts link.
+ **/
+s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
+                                     ixgbe_link_speed speed, bool autoneg,
+                                     bool autoneg_wait_to_complete)
 {
 	s32 status = IXGBE_SUCCESS;
-	ixgbe_link_speed link_speed;
+	ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 	ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 	u32 speedcnt = 0;
 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
 	u32 i = 0;
-	bool link_up = false;
+	bool link_up = FALSE;
 	bool negotiation;
 
 	DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
@@ -555,7 +586,7 @@
 	/* Mask off requested but non-supported speeds */
 	status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
 	if (status != IXGBE_SUCCESS)
-		return (status);
+		return status;
 
 	speed &= link_speed;
 
@@ -568,9 +599,9 @@
 		highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
 
 		/* If we already have link at this speed, just jump out */
-		status = ixgbe_check_link(hw, &link_speed, &link_up, false);
+		status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
 		if (status != IXGBE_SUCCESS)
-			return (status);
+			return status;
 
 		if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
 			goto out;
@@ -583,11 +614,12 @@
 		/* Allow module to change analog characteristics (1G->10G) */
 		msec_delay(40);
 
-		status = ixgbe_setup_mac_link_82599(
-		    hw, IXGBE_LINK_SPEED_10GB_FULL, autoneg,
-		    autoneg_wait_to_complete);
+		status = ixgbe_setup_mac_link_82599(hw,
+						IXGBE_LINK_SPEED_10GB_FULL,
+						autoneg,
+						autoneg_wait_to_complete);
 		if (status != IXGBE_SUCCESS)
-			return (status);
+			return status;
 
 		/* Flap the tx laser if it has not already been done */
 		ixgbe_flap_tx_laser(hw);
@@ -603,9 +635,9 @@
 
 			/* If we have link, just jump out */
 			status = ixgbe_check_link(hw, &link_speed,
-			    &link_up, false);
+			                          &link_up, FALSE);
 			if (status != IXGBE_SUCCESS)
-				return (status);
+				return status;
 
 			if (link_up)
 				goto out;
@@ -618,9 +650,9 @@
 			highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
 
 		/* If we already have link at this speed, just jump out */
-		status = ixgbe_check_link(hw, &link_speed, &link_up, false);
+		status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
 		if (status != IXGBE_SUCCESS)
-			return (status);
+			return status;
 
 		if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
 			goto out;
@@ -634,11 +666,12 @@
 		/* Allow module to change analog characteristics (10G->1G) */
 		msec_delay(40);
 
-		status = ixgbe_setup_mac_link_82599(
-		    hw, IXGBE_LINK_SPEED_1GB_FULL, autoneg,
-		    autoneg_wait_to_complete);
+		status = ixgbe_setup_mac_link_82599(hw,
+						    IXGBE_LINK_SPEED_1GB_FULL,
+						    autoneg,
+						    autoneg_wait_to_complete);
 		if (status != IXGBE_SUCCESS)
-			return (status);
+			return status;
 
 		/* Flap the tx laser if it has not already been done */
 		ixgbe_flap_tx_laser(hw);
@@ -647,9 +680,9 @@
 		msec_delay(100);
 
 		/* If we have link, just jump out */
-		status = ixgbe_check_link(hw, &link_speed, &link_up, false);
+		status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
 		if (status != IXGBE_SUCCESS)
-			return (status);
+			return status;
 
 		if (link_up)
 			goto out;
@@ -662,7 +695,7 @@
 	 */
 	if (speedcnt > 1)
 		status = ixgbe_setup_mac_link_multispeed_fiber(hw,
-		    highest_link_speed, autoneg, autoneg_wait_to_complete);
+		        highest_link_speed, autoneg, autoneg_wait_to_complete);
 
 out:
 	/* Set autoneg_advertised value based on input link speed */
@@ -674,31 +707,31 @@
 	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- * @autoneg_wait_to_complete: true when waiting for completion is needed
+/**
+ *  ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: TRUE if autonegotiation enabled
+ *  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
  *
- * Implements the Intel SmartSpeed algorithm.
- */
-s32
-ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete)
+ *  Implements the Intel SmartSpeed algorithm.
+ **/
+s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
+				     ixgbe_link_speed speed, bool autoneg,
+				     bool autoneg_wait_to_complete)
 {
 	s32 status = IXGBE_SUCCESS;
 	ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 	s32 i, j;
-	bool link_up = false;
+	bool link_up = FALSE;
 	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 
 	DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
 
-	/* Set autoneg_advertised value based on input link speed */
+	 /* Set autoneg_advertised value based on input link speed */
 	hw->phy.autoneg_advertised = 0;
 
 	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
@@ -718,10 +751,10 @@
 	 */
 
 	/* First, try to get link with full advertisement */
-	hw->phy.smart_speed_active = false;
+	hw->phy.smart_speed_active = FALSE;
 	for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
 		status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
-		    autoneg_wait_to_complete);
+						    autoneg_wait_to_complete);
 		if (status != IXGBE_SUCCESS)
 			goto out;
 
@@ -736,7 +769,7 @@
 
 			/* If we have link, just jump out */
 			status = ixgbe_check_link(hw, &link_speed, &link_up,
-			    false);
+						  FALSE);
 			if (status != IXGBE_SUCCESS)
 				goto out;
 
@@ -754,9 +787,9 @@
 		goto out;
 
 	/* Turn SmartSpeed on to disable KR support */
-	hw->phy.smart_speed_active = true;
+	hw->phy.smart_speed_active = TRUE;
 	status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
-	    autoneg_wait_to_complete);
+					    autoneg_wait_to_complete);
 	if (status != IXGBE_SUCCESS)
 		goto out;
 
@@ -770,7 +803,7 @@
 		msec_delay(100);
 
 		/* If we have link, just jump out */
-		status = ixgbe_check_link(hw, &link_speed, &link_up, false);
+		status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
 		if (status != IXGBE_SUCCESS)
 			goto out;
 
@@ -779,29 +812,29 @@
 	}
 
 	/* We didn't get link.  Turn SmartSpeed back off. */
-	hw->phy.smart_speed_active = false;
+	hw->phy.smart_speed_active = FALSE;
 	status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
-	    autoneg_wait_to_complete);
+					    autoneg_wait_to_complete);
 
 out:
 	if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
 		DEBUGOUT("Smartspeed has downgraded the link speed "
 		"from the maximum advertised\n");
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_setup_mac_link_82599 - Set MAC link speed
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- * @autoneg_wait_to_complete: true when waiting for completion is needed
+/**
+ *  ixgbe_setup_mac_link_82599 - Set MAC link speed
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: TRUE if autonegotiation enabled
+ *  @autoneg_wait_to_complete: TRUE when waiting for completion is needed
  *
- * Set the link speed in the AUTOC register and restarts link.
- */
-s32
-ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete)
+ *  Set the link speed in the AUTOC register and restarts link.
+ **/
+s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
+                                     ixgbe_link_speed speed, bool autoneg,
+                                     bool autoneg_wait_to_complete)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
@@ -829,9 +862,7 @@
 		goto out;
 	}
 
-	/*
-	 * Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support
-	 */
+	/* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
 	if (hw->mac.orig_link_settings_stored)
 		orig_autoc = hw->mac.orig_autoc;
 	else
@@ -846,13 +877,13 @@
 			if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 				autoc |= IXGBE_AUTOC_KX4_SUPP;
 			if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
-			    (hw->phy.smart_speed_active == false))
+			    (hw->phy.smart_speed_active == FALSE))
 				autoc |= IXGBE_AUTOC_KR_SUPP;
 		if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 			autoc |= IXGBE_AUTOC_KX_SUPP;
 	} else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
-	    (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
-	    link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
+	           (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
+	            link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
 		/* Switch from 1G SFI to 10G SFI if requested */
 		if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
 		    (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
@@ -860,7 +891,7 @@
 			autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
 		}
 	} else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
-	    (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
+	           (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
 		/* Switch from 10G SFI to 1G SFI if requested */
 		if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
 		    (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
@@ -869,7 +900,7 @@
 				autoc |= IXGBE_AUTOC_LMS_1G_AN;
 			else
 				autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
-			}
+		}
 	}
 
 	if (autoc != start_autoc) {
@@ -882,10 +913,10 @@
 			if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 			    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 			    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
-				links_reg = 0; /* Just in case Autoneg time=0 */
+				links_reg = 0; /*Just in case Autoneg time=0*/
 				for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 					links_reg =
-					    IXGBE_READ_REG(hw, IXGBE_LINKS);
+					       IXGBE_READ_REG(hw, IXGBE_LINKS);
 					if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 						break;
 					msec_delay(100);
@@ -892,7 +923,7 @@
 				}
 				if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 					status =
-					    IXGBE_ERR_AUTONEG_NOT_COMPLETE;
+						IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 					DEBUGOUT("Autoneg did not complete.\n");
 				}
 			}
@@ -903,21 +934,22 @@
 	}
 
 out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- * @autoneg_wait_to_complete: true if waiting is needed to complete
+/**
+ *  ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: TRUE if autonegotiation enabled
+ *  @autoneg_wait_to_complete: TRUE if waiting is needed to complete
  *
- * Restarts link on PHY and MAC based on settings passed in.
- */
-static s32
-ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete)
+ *  Restarts link on PHY and MAC based on settings passed in.
+ **/
+static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
+                                               ixgbe_link_speed speed,
+                                               bool autoneg,
+                                               bool autoneg_wait_to_complete)
 {
 	s32 status;
 
@@ -925,22 +957,22 @@
 
 	/* Setup the PHY according to input speed */
 	status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
-	    autoneg_wait_to_complete);
+	                                      autoneg_wait_to_complete);
 	/* Set up MAC */
 	(void) ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
 
-	return (status);
+	return status;
 }
-/*
- * ixgbe_reset_hw_82599 - Perform hardware reset
- * @hw: pointer to hardware structure
+
+/**
+ *  ixgbe_reset_hw_82599 - Perform hardware reset
+ *  @hw: pointer to hardware structure
  *
- * Resets the hardware by resetting the transmit and receive units, masks
- * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
- * reset.
- */
-s32
-ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
+ *  Resets the hardware by resetting the transmit and receive units, masks
+ *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
+ *  reset.
+ **/
+s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 ctrl;
@@ -964,7 +996,7 @@
 	/* Setup SFP module if there is one present. */
 	if (hw->phy.sfp_setup_needed) {
 		status = hw->mac.ops.setup_sfp(hw);
-		hw->phy.sfp_setup_needed = false;
+		hw->phy.sfp_setup_needed = FALSE;
 	}
 
 	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
@@ -971,7 +1003,7 @@
 		goto reset_hw_out;
 
 	/* Reset PHY */
-	if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
+	if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
 		hw->phy.ops.reset(hw);
 
 	/*
@@ -993,9 +1025,8 @@
 	for (i = 0; i < 10; i++) {
 		usec_delay(1);
 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
-		if (!(ctrl & IXGBE_CTRL_RST)) {
+		if (!(ctrl & IXGBE_CTRL_RST))
 			break;
-		}
 	}
 	if (ctrl & IXGBE_CTRL_RST) {
 		status = IXGBE_ERR_RESET_FAILED;
@@ -1024,21 +1055,20 @@
 	 */
 	autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
-	if (hw->mac.orig_link_settings_stored == false) {
+	if (hw->mac.orig_link_settings_stored == FALSE) {
 		hw->mac.orig_autoc = autoc;
 		hw->mac.orig_autoc2 = autoc2;
-		hw->mac.orig_link_settings_stored = true;
+		hw->mac.orig_link_settings_stored = TRUE;
 	} else {
-		if (autoc != hw->mac.orig_autoc) {
+		if (autoc != hw->mac.orig_autoc)
 			IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
-			    IXGBE_AUTOC_AN_RESTART));
-		}
+					IXGBE_AUTOC_AN_RESTART));
 
 		if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
 		    (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
 			autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
 			autoc2 |= (hw->mac.orig_autoc2 &
-			    IXGBE_AUTOC2_UPPER_MASK);
+			           IXGBE_AUTOC2_UPPER_MASK);
 			IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
 		}
 	}
@@ -1060,7 +1090,7 @@
 	/* Add the SAN MAC address to the RAR only if it's a valid address */
 	if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 		hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
-		    hw->mac.san_addr, 0, IXGBE_RAH_AV);
+		                    hw->mac.san_addr, 0, IXGBE_RAH_AV);
 
 		/* Reserve the last RAR for the SAN MAC address */
 		hw->mac.num_rar_entries--;
@@ -1068,18 +1098,17 @@
 
 	/* Store the alternative WWNN/WWPN prefix */
 	hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
-	    &hw->mac.wwpn_prefix);
+	                               &hw->mac.wwpn_prefix);
 
 reset_hw_out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
- * @hw: pointer to hardware structure
- */
-s32
-ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
+ *  @hw: pointer to hardware structure
+ **/
+s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
 {
 	int i;
 	u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
@@ -1093,14 +1122,14 @@
 	 */
 	for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
 		if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
-		    IXGBE_FDIRCMD_CMD_MASK))
+		      IXGBE_FDIRCMD_CMD_MASK))
 			break;
 		usec_delay(10);
 	}
 	if (i >= IXGBE_FDIRCMD_CMD_POLL) {
 		DEBUGOUT("Flow Director previous command isn't complete, "
-		    "aborting table re-initialization. \n");
-		return (IXGBE_ERR_FDIR_REINIT_FAILED);
+		         "aborting table re-initialization. \n");
+		return IXGBE_ERR_FDIR_REINIT_FAILED;
 	}
 
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
@@ -1113,12 +1142,12 @@
 	 * - write 0 to bit 8 of FDIRCMD register
 	 */
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
-	    (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
-	    IXGBE_FDIRCMD_CLEARHT));
+	                (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
+	                 IXGBE_FDIRCMD_CLEARHT));
 	IXGBE_WRITE_FLUSH(hw);
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
-	    (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
-	    ~IXGBE_FDIRCMD_CLEARHT));
+	                (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
+	                 ~IXGBE_FDIRCMD_CLEARHT));
 	IXGBE_WRITE_FLUSH(hw);
 	/*
 	 * Clear FDIR Hash register to clear any leftover hashes
@@ -1133,13 +1162,13 @@
 	/* Poll init-done after we write FDIRCTRL register */
 	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
-		    IXGBE_FDIRCTRL_INIT_DONE)
+		                   IXGBE_FDIRCTRL_INIT_DONE)
 			break;
 		usec_delay(10);
 	}
 	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
 		DEBUGOUT("Flow Director Signature poll time exceeded!\n");
-		return (IXGBE_ERR_FDIR_REINIT_FAILED);
+		return IXGBE_ERR_FDIR_REINIT_FAILED;
 	}
 
 	/* Clear FDIR statistics registers (read to clear) */
@@ -1149,16 +1178,15 @@
 	(void) IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
 	(void) IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
- * @hw: pointer to hardware structure
- * @pballoc: which mode to allocate filters with
- */
-s32
-ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
+/**
+ *  ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
+ *  @hw: pointer to hardware structure
+ *  @pballoc: which mode to allocate filters with
+ **/
+s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
 {
 	u32 fdirctrl = 0;
 	u32 pbsize;
@@ -1173,7 +1201,7 @@
 	 */
 	pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
 	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
-	    IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize);
+	    (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
 
 	/*
 	 * The defaults in the HW for RX PB 1-7 are not zero and so should be
@@ -1205,25 +1233,24 @@
 		break;
 	default:
 		/* bad value */
-		return (IXGBE_ERR_CONFIG);
+		return IXGBE_ERR_CONFIG;
 	};
 
 	/* Move the flexible bytes to use the ethertype - shift 6 words */
 	fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
 
+
 	/* Prime the keys for hashing */
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
-	    IXGBE_HTONL(IXGBE_ATR_BUCKET_HASH_KEY));
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
-	    IXGBE_HTONL(IXGBE_ATR_SIGNATURE_HASH_KEY));
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
 
 	/*
 	 * Poll init-done after we write the register.  Estimated times:
-	 *   10G: PBALLOC = 11b, timing is 60us
-	 *    1G: PBALLOC = 11b, timing is 600us
-	 *  100M: PBALLOC = 11b, timing is 6ms
+	 *      10G: PBALLOC = 11b, timing is 60us
+	 *       1G: PBALLOC = 11b, timing is 600us
+	 *     100M: PBALLOC = 11b, timing is 6ms
 	 *
-	 *   Multiple these timings by 4 if under full Rx load
+	 *     Multiple these timings by 4 if under full Rx load
 	 *
 	 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
 	 * 1 msec per poll time.  If we're at line rate and drop to 100M, then
@@ -1234,25 +1261,22 @@
 	IXGBE_WRITE_FLUSH(hw);
 	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
-		    IXGBE_FDIRCTRL_INIT_DONE)
+		                   IXGBE_FDIRCTRL_INIT_DONE)
 			break;
-
 		msec_delay(1);
 	}
-	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
+	if (i >= IXGBE_FDIR_INIT_DONE_POLL)
 		DEBUGOUT("Flow Director Signature poll time exceeded!\n");
-	}
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
- * @hw: pointer to hardware structure
- * @pballoc: which mode to allocate filters with
- */
-s32
-ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
+/**
+ *  ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
+ *  @hw: pointer to hardware structure
+ *  @pballoc: which mode to allocate filters with
+ **/
+s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
 {
 	u32 fdirctrl = 0;
 	u32 pbsize;
@@ -1265,10 +1289,9 @@
 	 * must be reduced.  The new value is the current size minus
 	 * flow director memory usage size.
 	 */
-
 	pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
 	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
-	    IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize);
+	    (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
 
 	/*
 	 * The defaults in the HW for RX PB 1-7 are not zero and so should be
@@ -1300,7 +1323,7 @@
 		break;
 	default:
 		/* bad value */
-		return (IXGBE_ERR_CONFIG);
+		return IXGBE_ERR_CONFIG;
 	};
 
 	/* Turn perfect match filtering on */
@@ -1311,18 +1334,16 @@
 	fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
 
 	/* Prime the keys for hashing */
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
-	    IXGBE_HTONL(IXGBE_ATR_BUCKET_HASH_KEY));
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
-	    IXGBE_HTONL(IXGBE_ATR_SIGNATURE_HASH_KEY));
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,IXGBE_ATR_SIGNATURE_HASH_KEY);
 
 	/*
 	 * Poll init-done after we write the register.  Estimated times:
-	 *   10G: PBALLOC = 11b, timing is 60us
-	 *    1G: PBALLOC = 11b, timing is 600us
-	 *  100M: PBALLOC = 11b, timing is 6ms
+	 *      10G: PBALLOC = 11b, timing is 60us
+	 *       1G: PBALLOC = 11b, timing is 600us
+	 *     100M: PBALLOC = 11b, timing is 6ms
 	 *
-	 *  Multiple these timings by 4 if under full Rx load
+	 *     Multiple these timings by 4 if under full Rx load
 	 *
 	 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
 	 * 1 msec per poll time.  If we're at line rate and drop to 100M, then
@@ -1337,25 +1358,23 @@
 	IXGBE_WRITE_FLUSH(hw);
 	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
-		    IXGBE_FDIRCTRL_INIT_DONE)
+		                   IXGBE_FDIRCTRL_INIT_DONE)
 			break;
-
 		msec_delay(1);
 	}
-	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
+	if (i >= IXGBE_FDIR_INIT_DONE_POLL)
 		DEBUGOUT("Flow Director Perfect poll time exceeded!\n");
-	}
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
- * @stream: input bitstream to compute the hash on
- * @key: 32-bit hash key
- */
-u16
-ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input, u32 key)
+/**
+ *  ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
+ *  @stream: input bitstream to compute the hash on
+ *  @key: 32-bit hash key
+ **/
+u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
+				 u32 key)
 {
 	/*
 	 * The algorithm is as follows:
@@ -1364,710 +1383,311 @@
 	 *    and A[n] x B[n] is bitwise AND between same length strings
 	 *
 	 *    K[n] is 16 bits, defined as:
-	 *	for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
-	 *	for n modulo 32 < 15, K[n] =
-	 *		K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
+	 *       for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
+	 *       for n modulo 32 < 15, K[n] =
+	 *             K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
 	 *
 	 *    S[n] is 16 bits, defined as:
-	 *	for n >= 15, S[n] = S[n:n - 15]
-	 *	for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
+	 *       for n >= 15, S[n] = S[n:n - 15]
+	 *       for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
 	 *
 	 *    To simplify for programming, the algorithm is implemented
 	 *    in software this way:
 	 *
-	 *    Key[31:0], Stream[335:0]
+	 *    key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
 	 *
-	 *    tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
-	 *    int_key[350:0] = tmp_key[351:1]
-	 *    int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
+	 *    for (i = 0; i < 352; i+=32)
+	 *        hi_hash_dword[31:0] ^= Stream[(i+31):i];
 	 *
-	 *    hash[15:0] = 0;
-	 *    for (i = 0; i < 351; i++) {
-	 *	if (int_key[i])
-	 *		hash ^= int_stream[(i + 15):i];
+	 *    lo_hash_dword[15:0]  ^= Stream[15:0];
+	 *    lo_hash_dword[15:0]  ^= hi_hash_dword[31:16];
+	 *    lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
+	 *
+	 *    hi_hash_dword[31:0]  ^= Stream[351:320];
+	 *
+	 *    if(key[0])
+	 *        hash[15:0] ^= Stream[15:0];
+	 *
+	 *    for (i = 0; i < 16; i++) {
+	 *        if (key[i])
+	 *            hash[15:0] ^= lo_hash_dword[(i+15):i];
+	 *        if (key[i + 16])
+	 *            hash[15:0] ^= hi_hash_dword[(i+15):i];
 	 *    }
+	 *
 	 */
+	__be32 common_hash_dword = 0;
+	u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
+	u32 hash_result = 0;
+	u8 i;
 
-	union {
-		u64 fill[6];
-		u32 key[11];
-		u8 key_stream[44];
-	} tmp_key;
+	/* record the flow_vm_vlan bits as they are a key part to the hash */
+	flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
 
-	u8 *stream = (u8 *)atr_input;
-	u8 int_key[44];		/* upper-most bit unused */
-	u8 hash_str[46];	/* upper-most 2 bits unused */
-	u16 hash_result = 0;
-	int i, j, k, h;
+	/* generate common hash dword */
+	for (i = 10; i; i -= 2)
+		common_hash_dword ^= atr_input->dword_stream[i] ^
+				     atr_input->dword_stream[i - 1];
 
-	DEBUGFUNC("ixgbe_atr_compute_hash_82599");
+	hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
 
-	/*
-	 * Initialize the fill member to prevent warnings
-	 * on some compilers
-	 */
-	tmp_key.fill[0] = 0;
+	/* low dword is word swapped version of common */
+	lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
 
-	/* First load the temporary key stream */
-	for (i = 0; i < 6; i++) {
-		u64 fillkey = ((u64)key << 32) | key;
-		tmp_key.fill[i] = fillkey;
-	}
+	/* apply flow ID/VM pool/VLAN ID bits to hash words */
+	hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
 
-	/*
-	 * Set the interim key for the hashing.  Bit 352 is unused, so we must
-	 * shift and compensate when building the key.
-	 */
-	int_key[0] = tmp_key.key_stream[0] >> 1;
-	for (i = 1, j = 0; i < 44; i++) {
-		unsigned int this_key = tmp_key.key_stream[j] << 7;
-		j++;
-		int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
-	}
+	/* Process bits 0 and 16 */
+	if (key & 0x0001) hash_result ^= lo_hash_dword;
+	if (key & 0x00010000) hash_result ^= hi_hash_dword;
 
 	/*
-	 * Set the interim bit string for the hashing.  Bits 368 and 367 are
-	 * unused, so shift and compensate when building the string.
+	 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
+	 * delay this because bit 0 of the stream should not be processed
+	 * so we do not add the vlan until after bit 0 was processed
 	 */
-	hash_str[0] = (stream[40] & 0x7f) >> 1;
-	for (i = 1, j = 40; i < 46; i++) {
-		unsigned int this_str = stream[j] << 7;
-		j++;
-		if (j > 41)
-			j = 0;
-		hash_str[i] = (u8)(this_str | (stream[j] >> 1));
-	}
+	lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
 
-	/*
-	 * Now compute the hash.  i is the index into hash_str, j is into our
-	 * key stream, k is counting the number of bits, and h interates within
-	 * each byte.
-	 */
-	for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
-		for (h = 0; h < 8 && k < 351; h++, k++) {
-			if (int_key[j] & (1 << h)) {
-				/*
-				 * Key bit is set, XOR in the current 16-bit
-				 * string.  Example of processing:
-				 *	h = 0,
-				 *	tmp = (hash_str[i - 2] & 0 << 16) |
-				 *		(hash_str[i - 1] & 0xff << 8) |
-				 *		(hash_str[i] & 0xff >> 0)
-				 *	So tmp = hash_str[15 + k:k], since the
-				 *	i + 2 clause rolls off the 16-bit value
-				 *	h = 7,
-				 *	tmp = (hash_str[i - 2] & 0x7f << 9) |
-				 *		(hash_str[i - 1] & 0xff << 1) |
-				 *		(hash_str[i] & 0x80 >> 7)
-				 */
-				int tmp = (hash_str[i] >> h);
-				tmp |= (hash_str[i - 1] << (8 - h));
-				tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
-				    << (16 - h);
-				hash_result ^= (u16)tmp;
-			}
-		}
+
+	/* process the remaining 30 bits in the key 2 bits at a time */
+	for (i = 15; i; i-- ) {
+		if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
+		if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
 	}
 
-	return (hash_result);
+	return hash_result & IXGBE_ATR_HASH_MASK;
 }
 
 /*
- * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
- * @input: input stream to modify
- * @vlan: the VLAN id to load
+ * These defines allow us to quickly generate all of the necessary instructions
+ * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
+ * for values 0 through 15
  */
-s32
-ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
-{
-	DEBUGFUNC("ixgbe_atr_set_vlan_id_82599");
-
-	input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
-	input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
-
-	return (IXGBE_SUCCESS);
+#define IXGBE_ATR_COMMON_HASH_KEY \
+		(IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
+#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
+{ \
+	u32 n = (_n); \
+	if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
+		common_hash ^= lo_hash_dword >> n; \
+	else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
+		bucket_hash ^= lo_hash_dword >> n; \
+	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
+		sig_hash ^= lo_hash_dword << (16 - n); \
+	if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
+		common_hash ^= hi_hash_dword >> n; \
+	else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
+		bucket_hash ^= hi_hash_dword >> n; \
+	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
+		sig_hash ^= hi_hash_dword << (16 - n); \
 }
 
-/*
- * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
- * @input: input stream to modify
- * @src_addr: the IP address to load
- */
-s32
-ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
-{
-	DEBUGFUNC("ixgbe_atr_set_src_ipv4_82599");
-
-	input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
-	input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
-	    (src_addr >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
-	    (src_addr >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
- * @input: input stream to modify
- * @dst_addr: the IP address to load
- */
-s32
-ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
-{
-	DEBUGFUNC("ixgbe_atr_set_dst_ipv4_82599");
-
-	input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
-	input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
-	    (dst_addr >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
-	    (dst_addr >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
- * @input: input stream to modify
- * @src_addr_1: the first 4 bytes of the IP address to load
- * @src_addr_2: the second 4 bytes of the IP address to load
- * @src_addr_3: the third 4 bytes of the IP address to load
- * @src_addr_4: the fourth 4 bytes of the IP address to load
- */
-s32
-ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
-    u32 src_addr_1, u32 src_addr_2, u32 src_addr_3, u32 src_addr_4)
-{
-	DEBUGFUNC("ixgbe_atr_set_src_ipv6_82599");
-
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
-	    (src_addr_4 >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
-	    (src_addr_4 >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
-
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
-	    (src_addr_3 >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
-	    (src_addr_3 >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
-
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
-	    (src_addr_2 >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
-	    (src_addr_2 >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
-
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
-	    (src_addr_1 >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
-	    (src_addr_1 >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
- * @input: input stream to modify
- * @dst_addr_1: the first 4 bytes of the IP address to load
- * @dst_addr_2: the second 4 bytes of the IP address to load
- * @dst_addr_3: the third 4 bytes of the IP address to load
- * @dst_addr_4: the fourth 4 bytes of the IP address to load
- */
-s32
-ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
-    u32 dst_addr_1, u32 dst_addr_2, u32 dst_addr_3, u32 dst_addr_4)
-{
-	DEBUGFUNC("ixgbe_atr_set_dst_ipv6_82599");
-
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
-	    (dst_addr_4 >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
-	    (dst_addr_4 >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
-
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
-	    (dst_addr_3 >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
-	    (dst_addr_3 >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
-
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
-	    (dst_addr_2 >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
-	    (dst_addr_2 >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
-
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
-	    (dst_addr_1 >> 8) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
-	    (dst_addr_1 >> 16) & 0xff;
-	input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_set_src_port_82599 - Sets the source port
- * @input: input stream to modify
- * @src_port: the source port to load
- */
-s32
-ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
-{
-	DEBUGFUNC("ixgbe_atr_set_src_port_82599");
-
-	input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
-	input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_set_dst_port_82599 - Sets the destination port
- * @input: input stream to modify
- * @dst_port: the destination port to load
- */
-s32
-ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
-{
-	DEBUGFUNC("ixgbe_atr_set_dst_port_82599");
-
-	input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
-	input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
- * @input: input stream to modify
- * @flex_bytes: the flexible bytes to load
- */
-s32
-ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
-{
-	DEBUGFUNC("ixgbe_atr_set_flex_byte_82599");
-
-	input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
-	input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
- * @input: input stream to modify
- * @vm_pool: the Virtual Machine pool to load
- */
-s32
-ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input, u8 vm_pool)
-{
-	DEBUGFUNC("ixgbe_atr_set_vm_pool_82599");
-
-	input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
- * @input: input stream to modify
- * @l4type: the layer 4 type value to load
- */
-s32
-ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
-{
-	DEBUGFUNC("ixgbe_atr_set_l4type_82599");
-
-	input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
- * @input: input stream to search
- * @vlan: the VLAN id to load
- */
-s32
-ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
-{
-	DEBUGFUNC("ixgbe_atr_get_vlan_id_82599");
-
-	*vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
-	*vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
- * @input: input stream to search
- * @src_addr: the IP address to load
- */
-s32
-ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input, u32 *src_addr)
-{
-	DEBUGFUNC("ixgbe_atr_get_src_ipv4_82599");
-
-	*src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
-	*src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
-	*src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
-	*src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
- * @input: input stream to search
- * @dst_addr: the IP address to load
- */
-s32
-ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 *dst_addr)
-{
-	DEBUGFUNC("ixgbe_atr_get_dst_ipv4_82599");
-
-	*dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
-	*dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
-	*dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
-	*dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
- * @input: input stream to search
- * @src_addr_1: the first 4 bytes of the IP address to load
- * @src_addr_2: the second 4 bytes of the IP address to load
- * @src_addr_3: the third 4 bytes of the IP address to load
- * @src_addr_4: the fourth 4 bytes of the IP address to load
- */
-s32
-ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
-    u32 *src_addr_1, u32 *src_addr_2, u32 *src_addr_3, u32 *src_addr_4)
-{
-	DEBUGFUNC("ixgbe_atr_get_src_ipv6_82599");
-
-	*src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
-	*src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
-	*src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
-	*src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
-
-	*src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
-	*src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
-	*src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
-	*src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
-
-	*src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
-	*src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
-	*src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
-	*src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
-
-	*src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
-	*src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
-	*src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
-	*src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
- * @input: input stream to search
- * @dst_addr_1: the first 4 bytes of the IP address to load
- * @dst_addr_2: the second 4 bytes of the IP address to load
- * @dst_addr_3: the third 4 bytes of the IP address to load
- * @dst_addr_4: the fourth 4 bytes of the IP address to load
- */
-s32
-ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
-    u32 *dst_addr_1, u32 *dst_addr_2, u32 *dst_addr_3, u32 *dst_addr_4)
-{
-	DEBUGFUNC("ixgbe_atr_get_dst_ipv6_82599");
-
-	*dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
-	*dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
-	*dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
-	*dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
-
-	*dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
-	*dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
-	*dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
-	*dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
-
-	*dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
-	*dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
-	*dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
-	*dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
-
-	*dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
-	*dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
-	*dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
-	*dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_get_src_port_82599 - Gets the source port
- * @input: input stream to modify
- * @src_port: the source port to load
+/**
+ *  ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
+ *  @stream: input bitstream to compute the hash on
  *
- * Even though the input is given in big-endian, the FDIRPORT registers
- * expect the ports to be programmed in little-endian.  Hence the need to swap
- * endianness when retrieving the data.  This can be confusing since the
- * internal hash engine expects it to be big-endian.
- */
-s32
-ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input, u16 *src_port)
+ *  This function is almost identical to the function above but contains
+ *  several optomizations such as unwinding all of the loops, letting the
+ *  compiler work out all of the conditional ifs since the keys are static
+ *  defines, and computing two keys at once since the hashed dword stream
+ *  will be the same for both keys.
+ **/
+static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
+					    union ixgbe_atr_hash_dword common)
 {
-	DEBUGFUNC("ixgbe_atr_get_src_port_82599");
+	u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
+	u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
 
-	*src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
-	*src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
+	/* record the flow_vm_vlan bits as they are a key part to the hash */
+	flow_vm_vlan = IXGBE_NTOHL(input.dword);
 
-	return (IXGBE_SUCCESS);
-}
+	/* generate common hash dword */
+	hi_hash_dword = IXGBE_NTOHL(common.dword);
 
-/*
- * ixgbe_atr_get_dst_port_82599 - Gets the destination port
- * @input: input stream to modify
- * @dst_port: the destination port to load
- *
- * Even though the input is given in big-endian, the FDIRPORT registers
- * expect the ports to be programmed in little-endian.  Hence the need to swap
- * endianness when retrieving the data.  This can be confusing since the
- * internal hash engine expects it to be big-endian.
- */
-s32
-ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input, u16 *dst_port)
-{
-	DEBUGFUNC("ixgbe_atr_get_dst_port_82599");
+	/* low dword is word swapped version of common */
+	lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
 
-	*dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
-	*dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
+	/* apply flow ID/VM pool/VLAN ID bits to hash words */
+	hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
 
-	return (IXGBE_SUCCESS);
-}
+	/* Process bits 0 and 16 */
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
 
-/*
- * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
- * @input: input stream to modify
- * @flex_bytes: the flexible bytes to load
- */
-s32
-ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input, u16 *flex_byte)
-{
-	DEBUGFUNC("ixgbe_atr_get_flex_byte_82599");
+	/*
+	 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
+	 * delay this because bit 0 of the stream should not be processed
+	 * so we do not add the vlan until after bit 0 was processed
+	 */
+	lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
 
-	*flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
-	*flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
+	/* Process remaining 30 bit of the key */
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
+	IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
 
-	return (IXGBE_SUCCESS);
-}
+	/* combine common_hash result with signature and bucket hashes */
+	bucket_hash ^= common_hash;
+	bucket_hash &= IXGBE_ATR_HASH_MASK;
 
-/*
- * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
- * @input: input stream to modify
- * @vm_pool: the Virtual Machine pool to load
- */
-s32
-ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input, u8 *vm_pool)
-{
-	DEBUGFUNC("ixgbe_atr_get_vm_pool_82599");
+	sig_hash ^= common_hash << 16;
+	sig_hash &= IXGBE_ATR_HASH_MASK << 16;
 
-	*vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
-
-	return (IXGBE_SUCCESS);
+	/* return completed signature hash */
+	return sig_hash ^ bucket_hash;
 }
 
-/*
- * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
- * @input: input stream to modify
- * @l4type: the layer 4 type value to load
- */
-s32
-ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input, u8 *l4type)
+/**
+ *  ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
+ *  @hw: pointer to hardware structure
+ *  @stream: input bitstream
+ *  @queue: queue index to direct traffic to
+ **/
+s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
+                                          union ixgbe_atr_hash_dword input,
+                                          union ixgbe_atr_hash_dword common,
+                                          u8 queue)
 {
-	DEBUGFUNC("ixgbe_atr_get_l4type__82599");
-
-	*l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
- * @hw: pointer to hardware structure
- * @stream: input bitstream
- * @queue: queue index to direct traffic to
- */
-s32
-ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
-    struct ixgbe_atr_input *input, u8 queue)
-{
 	u64  fdirhashcmd;
-	u64  fdircmd;
-	u32  fdirhash;
-	u16  bucket_hash, sig_hash;
-	u8   l4type;
+	u32  fdircmd;
 
 	DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
 
-	bucket_hash = ixgbe_atr_compute_hash_82599(input,
-	    IXGBE_ATR_BUCKET_HASH_KEY);
+	/*
+	 * Get the flow_type in order to program FDIRCMD properly
+	 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
+	 */
+	switch (input.formatted.flow_type) {
+	case IXGBE_ATR_FLOW_TYPE_TCPV4:
+	case IXGBE_ATR_FLOW_TYPE_UDPV4:
+	case IXGBE_ATR_FLOW_TYPE_SCTPV4:
+	case IXGBE_ATR_FLOW_TYPE_TCPV6:
+	case IXGBE_ATR_FLOW_TYPE_UDPV6:
+	case IXGBE_ATR_FLOW_TYPE_SCTPV6:
+		break;
+	default:
+		DEBUGOUT(" Error on flow type input\n");
+		return IXGBE_ERR_CONFIG;
+	}
 
-	/* bucket_hash is only 15 bits */
-	bucket_hash &= IXGBE_ATR_HASH_MASK;
+	/* configure FDIRCMD register */
+	fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
+	          IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
+	fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
+	fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
 
-	sig_hash = ixgbe_atr_compute_hash_82599(input,
-	    IXGBE_ATR_SIGNATURE_HASH_KEY);
-
-	/* Get the l4type in order to program FDIRCMD properly */
-	/* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
-	(void) ixgbe_atr_get_l4type_82599(input, &l4type);
-
 	/*
 	 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
 	 * is for FDIRCMD.  Then do a 64-bit register write from FDIRHASH.
 	 */
-	fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
+	fdirhashcmd = (u64)fdircmd << 32;
+	fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
+	IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
 
-	fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
-	    IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
+	DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
 
-	switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
-	case IXGBE_ATR_L4TYPE_TCP:
-		fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
-		break;
-	case IXGBE_ATR_L4TYPE_UDP:
-		fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
-		break;
-	case IXGBE_ATR_L4TYPE_SCTP:
-		fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
-		break;
-	default:
-		DEBUGOUT(" Error on l4type input\n");
-		return (IXGBE_ERR_CONFIG);
-	}
+	return IXGBE_SUCCESS;
+}
 
-	if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
-		fdircmd |= IXGBE_FDIRCMD_IPV6;
+/**
+ *  ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
+ *  @input_mask: mask to be bit swapped
+ *
+ *  The source and destination port masks for flow director are bit swapped
+ *  in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc.  In order to
+ *  generate a correctly swapped value we need to bit swap the mask and that
+ *  is what is accomplished by this function.
+ **/
+static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
+{
+	u32 mask = IXGBE_NTOHS(input_masks->dst_port_mask);
+	mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
+	mask |= IXGBE_NTOHS(input_masks->src_port_mask);
+	mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
+	mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
+	mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
+	return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
+}
 
-	fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
-	fdirhashcmd = ((fdircmd << 32) | fdirhash);
+/*
+ * These two macros are meant to address the fact that we have registers
+ * that are either all or in part big-endian.  As a result on big-endian
+ * systems we will end up byte swapping the value to little-endian before
+ * it is byte swapped again and written to the hardware in the original
+ * big-endian format.
+ */
+#define IXGBE_STORE_AS_BE32(_value) \
+	(((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
+	 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
 
-	DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, fdirhash & 0x7FFF7FFF);
-	IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
+#define IXGBE_WRITE_REG_BE32(a, reg, value) \
+	IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
 
-	return (IXGBE_SUCCESS);
-}
+#define IXGBE_STORE_AS_BE16(_value) \
+	(((u16)(_value) >> 8) | ((u16)(_value) << 8))
 
-/*
- * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
- * @hw: pointer to hardware structure
- * @input: input bitstream
- * @input_masks: masks for the input bitstream
- * @soft_id: software index for the filters
- * @queue: queue index to direct traffic to
+
+/**
+ *  ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
+ *  @hw: pointer to hardware structure
+ *  @input: input bitstream
+ *  @input_masks: masks for the input bitstream
+ *  @soft_id: software index for the filters
+ *  @queue: queue index to direct traffic to
  *
- * Note that the caller to this function must lock before calling, since the
- * hardware writes must be protected from one another.
- */
-s32
-ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
-    struct ixgbe_atr_input *input, struct ixgbe_atr_input_masks *input_masks,
-    u16 soft_id, u8 queue)
+ *  Note that the caller to this function must lock before calling, since the
+ *  hardware writes must be protected from one another.
+ **/
+s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
+                                      union ixgbe_atr_input *input,
+                                      struct ixgbe_atr_input_masks *input_masks,
+                                      u16 soft_id, u8 queue)
 {
-	u32 fdircmd = 0;
 	u32 fdirhash;
-	u32 src_ipv4 = 0, dst_ipv4 = 0;
-	u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
-	u16 src_port, dst_port, vlan_id, flex_bytes;
-	u16 bucket_hash;
-	u8  l4type;
-	u8  fdirm = 0;
+	u32 fdircmd;
+	u32 fdirport, fdirtcpm;
+	u32 fdirvlan;
+	/* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
+	u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
+		    IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
 
 	DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
 
-	/* Get our input values */
-	(void) ixgbe_atr_get_l4type_82599(input, &l4type);
-
 	/*
-	 * Check l4type formatting, and bail out before we touch the hardware
+	 * Check flow_type formatting, and bail out before we touch the hardware
 	 * if there's a configuration issue
 	 */
-	switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
-	case IXGBE_ATR_L4TYPE_TCP:
-		fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
+	switch (input->formatted.flow_type) {
+	case IXGBE_ATR_FLOW_TYPE_IPV4:
+		/* use the L4 protocol mask for raw IPv4/IPv6 traffic */
+		fdirm |= IXGBE_FDIRM_L4P;
+		/* FALLTHRU */
+	case IXGBE_ATR_FLOW_TYPE_SCTPV4:
+		if (input_masks->dst_port_mask || input_masks->src_port_mask) {
+			DEBUGOUT(" Error on src/dst port mask\n");
+			return IXGBE_ERR_CONFIG;
+		}
 		break;
-	case IXGBE_ATR_L4TYPE_UDP:
-		fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
+	case IXGBE_ATR_FLOW_TYPE_TCPV4:
 		break;
-	case IXGBE_ATR_L4TYPE_SCTP:
-		fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
+	case IXGBE_ATR_FLOW_TYPE_UDPV4:
 		break;
 	default:
-		DEBUGOUT(" Error on l4type input\n");
-		return (IXGBE_ERR_CONFIG);
+		DEBUGOUT(" Error on flow type input\n");
+		return IXGBE_ERR_CONFIG;
 	}
 
-	bucket_hash = ixgbe_atr_compute_hash_82599(input,
-	    IXGBE_ATR_BUCKET_HASH_KEY);
-
-	/* bucket_hash is only 15 bits */
-	bucket_hash &= IXGBE_ATR_HASH_MASK;
-
-	(void) ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
-	(void) ixgbe_atr_get_src_port_82599(input, &src_port);
-	(void) ixgbe_atr_get_dst_port_82599(input, &dst_port);
-	(void) ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
-
-	fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
-
-	/* Now figure out if we're IPv4 or IPv6 */
-	if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
-		/* IPv6 */
-		(void) ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1,
-		    &src_ipv6_2, &src_ipv6_3, &src_ipv6_4);
-
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
-		/* The last 4 bytes is the same register as IPv4 */
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
-
-		fdircmd |= IXGBE_FDIRCMD_IPV6;
-		fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
-	} else {
-		/* IPv4 */
-		(void) ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
-
-	}
-
-	(void) ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
-
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
-	    (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
-	IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
-	    (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
-
 	/*
 	 * Program the relevant mask registers.  If src/dst_port or src/dst_addr
 	 * are zero, then assume a full mask for that field.  Also assume that
@@ -2077,90 +1697,107 @@
 	 * This also assumes IPv4 only.  IPv6 masking isn't supported at this
 	 * point in time.
 	 */
-	if (src_ipv4 == 0)
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xffffffff);
-	else
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
 
-	if (dst_ipv4 == 0)
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xffffffff);
-	else
-		IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
-
-	switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
-	case IXGBE_ATR_L4TYPE_TCP:
-		if (src_port == 0)
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xffff);
-		else
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
-			    input_masks->src_port_mask);
-
-		if (dst_port == 0)
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
-			    (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
-			    0xffff0000));
-		else
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
-			    (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
-			    (input_masks->dst_port_mask << 16)));
+	/* Program FDIRM */
+	switch (IXGBE_NTOHS(input_masks->vlan_id_mask) & 0xEFFF) {
+	case 0xEFFF:
+		/* Unmask VLAN ID - bit 0 and fall through to unmask prio */
+		fdirm &= ~IXGBE_FDIRM_VLANID;
+		/* FALLTHRU */
+	case 0xE000:
+		/* Unmask VLAN prio - bit 1 */
+		fdirm &= ~IXGBE_FDIRM_VLANP;
 		break;
-	case IXGBE_ATR_L4TYPE_UDP:
-		if (src_port == 0)
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xffff);
-		else
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
-			    input_masks->src_port_mask);
-
-		if (dst_port == 0)
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
-			    (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
-			    0xffff0000));
-		else
-			IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
-			    (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
-			    (input_masks->src_port_mask << 16)));
+	case 0x0FFF:
+		/* Unmask VLAN ID - bit 0 */
+		fdirm &= ~IXGBE_FDIRM_VLANID;
 		break;
-	default:
-		/* this already would have failed above */
+	case 0x0000:
+		/* do nothing, vlans already masked */
 		break;
+	default:
+		DEBUGOUT(" Error on VLAN mask\n");
+		return IXGBE_ERR_CONFIG;
 	}
 
-	/* Program the last mask register, FDIRM */
-	if (input_masks->vlan_id_mask || !vlan_id)
-		/* Mask both VLAN and VLANP - bits 0 and 1 */
-		fdirm |= (IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP);
+	if (input_masks->flex_mask & 0xFFFF) {
+		if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
+			DEBUGOUT(" Error on flexible byte mask\n");
+			return IXGBE_ERR_CONFIG;
+		}
+		/* Unmask Flex Bytes - bit 4 */
+		fdirm &= ~IXGBE_FDIRM_FLEX;
+	}
 
-	if (input_masks->data_mask || !flex_bytes)
-		/* Flex bytes need masking, so mask the whole thing - bit 4 */
-		fdirm |= IXGBE_FDIRM_FLEX;
-
 	/* Now mask VM pool and destination IPv6 - bits 5 and 2 */
-	fdirm |= (IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6);
-
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 
-	fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
-	fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
-	fdircmd |= IXGBE_FDIRCMD_LAST;
-	fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
-	fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
+	/* store the TCP/UDP port masks, bit reversed from port layout */
+	fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
 
+	/* write both the same so that UDP and TCP use the same mask */
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
+
+	/* store source and destination IP masks (big-enian) */
+	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
+			     ~input_masks->src_ip_mask[0]);
+	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
+			     ~input_masks->dst_ip_mask[0]);
+
+	/* Apply masks to input data */
+	input->formatted.vlan_id &= input_masks->vlan_id_mask;
+	input->formatted.flex_bytes &= input_masks->flex_mask;
+	input->formatted.src_port &= input_masks->src_port_mask;
+	input->formatted.dst_port &= input_masks->dst_port_mask;
+	input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
+	input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
+
+	/* record vlan (little-endian) and flex_bytes(big-endian) */
+	fdirvlan =
+		IXGBE_STORE_AS_BE16(IXGBE_NTOHS(input->formatted.flex_bytes));
+	fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
+	fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
+
+	/* record source and destination port (little-endian)*/
+	fdirport = IXGBE_NTOHS(input->formatted.dst_port);
+	fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
+	fdirport |= IXGBE_NTOHS(input->formatted.src_port);
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
+
+	/* record the first 32 bits of the destination address (big-endian) */
+	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
+
+	/* record the source address (big-endian) */
+	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
+
+	/* configure FDIRCMD register */
+	fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
+		  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
+	fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
+	fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
+
+	/* we only want the bucket hash so drop the upper 16 bits */
+	fdirhash = ixgbe_atr_compute_hash_82599(input,
+						IXGBE_ATR_BUCKET_HASH_KEY);
+	fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
+
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
- * @hw: pointer to hardware structure
- * @reg: analog register to read
- * @val: read value
+/**
+ *  ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
+ *  @hw: pointer to hardware structure
+ *  @reg: analog register to read
+ *  @val: read value
  *
- * Performs read operation to Omer analog register specified.
- */
-s32
-ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
+ *  Performs read operation to Omer analog register specified.
+ **/
+s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
 {
 	u32  core_ctl;
 
@@ -2167,25 +1804,24 @@
 	DEBUGFUNC("ixgbe_read_analog_reg8_82599");
 
 	IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
-	    (reg << 8));
+	                (reg << 8));
 	IXGBE_WRITE_FLUSH(hw);
 	usec_delay(10);
 	core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
 	*val = (u8)core_ctl;
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
- * @hw: pointer to hardware structure
- * @reg: atlas register to write
- * @val: value to write
+/**
+ *  ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
+ *  @hw: pointer to hardware structure
+ *  @reg: atlas register to write
+ *  @val: value to write
  *
- * Performs write operation to Omer analog register specified.
- */
-s32
-ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
+ *  Performs write operation to Omer analog register specified.
+ **/
+s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
 {
 	u32  core_ctl;
 
@@ -2196,68 +1832,49 @@
 	IXGBE_WRITE_FLUSH(hw);
 	usec_delay(10);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx
+ *  @hw: pointer to hardware structure
  *
- * Starts the hardware using the generic start_hw function.
- * Then performs revision-specific operations:
- * Clears the rate limiter registers.
- */
-s32
-ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw)
+ *  Starts the hardware using the generic start_hw function
+ *  and the generation start_hw function.
+ *  Then performs revision-specific operations, if any.
+ **/
+s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw)
 {
-	u32 i;
-	u32 regval;
 	s32 ret_val = IXGBE_SUCCESS;
 
 	DEBUGFUNC("ixgbe_start_hw_rev_1__82599");
 
 	ret_val = ixgbe_start_hw_generic(hw);
+	if (ret_val != IXGBE_SUCCESS)
+		goto out;
 
-	/* Clear the rate limiters */
-	for (i = 0; i < hw->mac.max_tx_queues; i++) {
-		IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
-		IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
-	}
-	IXGBE_WRITE_FLUSH(hw);
+	ret_val = ixgbe_start_hw_gen2(hw);
+	if (ret_val != IXGBE_SUCCESS)
+		goto out;
 
-	/* Disable relaxed ordering */
-	for (i = 0; i < hw->mac.max_tx_queues; i++) {
-		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
-		regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
-		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
-	}
-
-	for (i = 0; i < hw->mac.max_rx_queues; i++) {
-		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
-		regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
-		    IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
-		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
-	}
-
 	/* We need to run link autotry after the driver loads */
-	hw->mac.autotry_restart = true;
+	hw->mac.autotry_restart = TRUE;
 
 	if (ret_val == IXGBE_SUCCESS)
 		ret_val = ixgbe_verify_fw_version_82599(hw);
-
-	return (ret_val);
+out:
+	return ret_val;
 }
 
-/*
- * ixgbe_identify_phy_82599 - Get physical layer module
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_identify_phy_82599 - Get physical layer module
+ *  @hw: pointer to hardware structure
  *
- * Determines the physical layer module found on the current adapter.
- * If PHY already detected, maintains current PHY type in hw struct,
- * otherwise executes the PHY detection routine.
- */
-s32
-ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
+ *  Determines the physical layer module found on the current adapter.
+ *  If PHY already detected, maintains current PHY type in hw struct,
+ *  otherwise executes the PHY detection routine.
+ **/
+s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 
@@ -2265,8 +1882,14 @@
 
 	/* Detect PHY if not unknown - returns success if already detected. */
 	status = ixgbe_identify_phy_generic(hw);
-	if (status != IXGBE_SUCCESS)
-		status = ixgbe_identify_sfp_module_generic(hw);
+	if (status != IXGBE_SUCCESS) {
+		/* 82599 10GBASE-T requires an external PHY */
+		if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
+			goto out;
+		else
+			status = ixgbe_identify_sfp_module_generic(hw);
+	}
+
 	/* Set PHY type none if no PHY detected */
 	if (hw->phy.type == ixgbe_phy_unknown) {
 		hw->phy.type = ixgbe_phy_none;
@@ -2277,17 +1900,17 @@
 	if (hw->phy.type == ixgbe_phy_sfp_unsupported)
 		status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 
-	return (status);
+out:
+	return status;
 }
 
-/*
- * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
+ *  @hw: pointer to hardware structure
  *
- * Determines physical layer capabilities of the current configuration.
- */
-u32
-ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
+ *  Determines physical layer capabilities of the current configuration.
+ **/
+u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
 {
 	u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 	u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
@@ -2303,11 +1926,12 @@
 
 	hw->phy.ops.identify(hw);
 
-	if (hw->phy.type == ixgbe_phy_tn ||
-	    hw->phy.type == ixgbe_phy_aq ||
-	    hw->phy.type == ixgbe_phy_cu_unknown) {
+	switch (hw->phy.type) {
+	case ixgbe_phy_tn:
+	case ixgbe_phy_aq:
+	case ixgbe_phy_cu_unknown:
 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
-		    IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
+		IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
 		if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 		if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
@@ -2315,6 +1939,8 @@
 		if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 		goto out;
+	default:
+		break;
 	}
 
 	switch (autoc & IXGBE_AUTOC_LMS_MASK) {
@@ -2324,10 +1950,9 @@
 			physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
 			    IXGBE_PHYSICAL_LAYER_1000BASE_BX;
 			goto out;
-		} else {
-			/* SFI mode so read SFP module */
-			goto sfp_check;
 		}
+		/* SFI mode so read SFP module */
+		goto sfp_check;
 	case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 		if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
@@ -2357,11 +1982,9 @@
 	}
 
 sfp_check:
-	/*
-	 * SFP check must be done last since DA modules are sometimes used to
+	/* SFP check must be done last since DA modules are sometimes used to
 	 * test KR mode -  we need to id KR mode correctly before SFP module.
-	 * Call identify_sfp because the pluggable module may have changed
-	 */
+	 * Call identify_sfp because the pluggable module may have changed */
 	hw->phy.ops.identify_sfp(hw);
 	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
 		goto out;
@@ -2380,9 +2003,9 @@
 	case ixgbe_phy_sfp_intel:
 	case ixgbe_phy_sfp_unknown:
 		hw->phy.ops.read_i2c_eeprom(hw,
-		    IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
+		      IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
 		hw->phy.ops.read_i2c_eeprom(hw,
-		    IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
+		      IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
 		if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
 		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
@@ -2395,20 +2018,19 @@
 	}
 
 out:
-	return (physical_layer);
+	return physical_layer;
 }
 
-/*
- * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
- * @hw: pointer to hardware structure
- * @regval: register value to write to RXCTRL
+/**
+ *  ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
+ *  @hw: pointer to hardware structure
+ *  @regval: register value to write to RXCTRL
  *
- * Enables the Rx DMA unit for 82599
- */
-s32
-ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
+ *  Enables the Rx DMA unit for 82599
+ **/
+s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
 {
-#define	IXGBE_MAX_SECRX_POLL	30
+#define IXGBE_MAX_SECRX_POLL 30
 	int i;
 	int secrxreg;
 
@@ -2435,7 +2057,7 @@
 	/* For informational purposes only */
 	if (i >= IXGBE_MAX_SECRX_POLL)
 		DEBUGOUT("Rx unit being enabled before security "
-		    "path fully disabled.	Continuing with init.\n");
+		         "path fully disabled.  Continuing with init.\n");
 
 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
 	secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
@@ -2443,39 +2065,20 @@
 	IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
 	IXGBE_WRITE_FLUSH(hw);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_get_device_caps_82599 - Get additional device capabilities
- * @hw: pointer to hardware structure
- * @device_caps: the EEPROM word with the extra device capabilities
+/**
+ *  ixgbe_verify_fw_version_82599 - verify fw version for 82599
+ *  @hw: pointer to hardware structure
  *
- * This function will read the EEPROM location for the device capabilities,
- * and return the word through device_caps.
- */
-s32
-ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
-{
-	DEBUGFUNC("ixgbe_get_device_caps_82599");
-
-	hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
-
-	return (IXGBE_SUCCESS);
-}
-
-/*
- * ixgbe_verify_fw_version_82599 - verify fw version for 82599
- * @hw: pointer to hardware structure
+ *  Verifies that installed the firmware version is 0.6 or higher
+ *  for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
  *
- * Verifies that installed the firmware version is 0.6 or higher
- * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
- *
- * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
- * if the FW version is not supported.
- */
-static s32
-ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
+ *  Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
+ *  if the FW version is not supported.
+ **/
+static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_ERR_EEPROM_VERSION;
 	u16 fw_offset, fw_ptp_cfg_offset;
@@ -2497,45 +2100,66 @@
 
 	/* get the offset to the Pass Through Patch Configuration block */
 	hw->eeprom.ops.read(hw, (fw_offset +
-	    IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), &fw_ptp_cfg_offset);
+	                         IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
+	                         &fw_ptp_cfg_offset);
 
 	if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
 		goto fw_version_out;
 
 	/* get the firmware version */
-	hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4),
-	    &fw_version);
+	hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
+	                         IXGBE_FW_PATCH_VERSION_4),
+	                         &fw_version);
 
 	if (fw_version > 0x5)
 		status = IXGBE_SUCCESS;
 
 fw_version_out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_enable_relaxed_ordering_82599 - Enable relaxed ordering
- * @hw: pointer to hardware structure
- */
-void
-ixgbe_enable_relaxed_ordering_82599(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
+ *  @hw: pointer to hardware structure
+ *
+ *  Returns TRUE if the LESM FW module is present and enabled. Otherwise
+ *  returns FALSE. Smart Speed must be disabled if LESM FW module is enabled.
+ **/
+bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
 {
-	u32 regval;
-	u32 i;
+	bool lesm_enabled = FALSE;
+	u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
+	s32 status;
 
-	DEBUGFUNC("ixgbe_enable_relaxed_ordering_82599");
+	DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
 
-	/* Enable relaxed ordering */
-	for (i = 0; i < hw->mac.max_tx_queues; i++) {
-		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
-		regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
-		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
-	}
+	/* get the offset to the Firmware Module block */
+	status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
 
-	for (i = 0; i < hw->mac.max_rx_queues; i++) {
-		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
-		regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
-		    IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
-		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
-	}
+	if ((status != IXGBE_SUCCESS) ||
+	    (fw_offset == 0) || (fw_offset == 0xFFFF))
+		goto out;
+
+	/* get the offset to the LESM Parameters block */
+	status = hw->eeprom.ops.read(hw, (fw_offset +
+	                         IXGBE_FW_LESM_PARAMETERS_PTR),
+	                         &fw_lesm_param_offset);
+
+	if ((status != IXGBE_SUCCESS) ||
+	    (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
+		goto out;
+
+	/* get the lesm state word */
+	status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
+	                             IXGBE_FW_LESM_STATE_1),
+	                             &fw_lesm_state);
+
+	if ((status == IXGBE_SUCCESS) &&
+	    (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
+		lesm_enabled = TRUE;
+
+out:
+	return lesm_enabled;
 }
+
+
--- old/usr/src/uts/common/io/ixgbe/ixgbe_api.c	Wed Sep  7 11:32:34 2011
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_api.c	Wed Sep  7 11:32:34 2011
@@ -1,35 +1,37 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at:
- *      http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When using or redistributing this file, you may do so under the
- * License only. No other modification of this header is permitted.
- *
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
+/******************************************************************************
 
-/*
- * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
- */
+  Copyright (c) 2001-2010, Intel Corporation 
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without 
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice, 
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright 
+      notice, this list of conditions and the following disclaimer in the 
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its 
+      contributors may be used to endorse or promote products derived from 
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
 
-/*
- * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
- */
+******************************************************************************/
+/*$FreeBSD$*/
 
-/* IntelVersion: 1.140 scm_061610_003709 */
-
 #include "ixgbe_api.h"
 #include "ixgbe_common.h"
 
@@ -36,20 +38,19 @@
 extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
 extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
 
-/*
- * ixgbe_init_shared_code - Initialize the shared code
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_init_shared_code - Initialize the shared code
+ *  @hw: pointer to hardware structure
  *
- * This will assign function pointers and assign the MAC type and PHY code.
- * Does not touch the hardware. This function must be called prior to any
- * other function in the shared code. The ixgbe_hw structure should be
- * memset to 0 prior to calling this function.  The following fields in
- * hw structure should be filled in prior to calling this function:
- * hw_addr, back, device_id, vendor_id, subsystem_device_id,
- * subsystem_vendor_id, and revision_id
- */
-s32
-ixgbe_init_shared_code(struct ixgbe_hw *hw)
+ *  This will assign function pointers and assign the MAC type and PHY code.
+ *  Does not touch the hardware. This function must be called prior to any
+ *  other function in the shared code. The ixgbe_hw structure should be
+ *  memset to 0 prior to calling this function.  The following fields in
+ *  hw structure should be filled in prior to calling this function:
+ *  hw_addr, back, device_id, vendor_id, subsystem_device_id,
+ *  subsystem_vendor_id, and revision_id
+ **/
+s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
 {
 	s32 status;
 
@@ -72,18 +73,17 @@
 		break;
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_set_mac_type - Sets MAC type
- * @hw: pointer to the HW structure
+/**
+ *  ixgbe_set_mac_type - Sets MAC type
+ *  @hw: pointer to the HW structure
  *
- * This function sets the mac type of the adapter based on the
- * vendor ID and device ID stored in the hw structure.
- */
-s32
-ixgbe_set_mac_type(struct ixgbe_hw *hw)
+ *  This function sets the mac type of the adapter based on the
+ *  vendor ID and device ID stored in the hw structure.
+ **/
+s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
 {
 	s32 ret_val = IXGBE_SUCCESS;
 
@@ -109,9 +109,9 @@
 		case IXGBE_DEV_ID_82599_KX4_MEZZ:
 		case IXGBE_DEV_ID_82599_XAUI_LOM:
 		case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
-		case IXGBE_DEV_ID_82599_KR:
 		case IXGBE_DEV_ID_82599_SFP:
-		case IXGBE_DEV_ID_82599_SFP_EM:
+		case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
+		case IXGBE_DEV_ID_82599_SFP_FCOE:
 		case IXGBE_DEV_ID_82599_CX4:
 		case IXGBE_DEV_ID_82599_T3_LOM:
 			hw->mac.type = ixgbe_mac_82599EB;
@@ -125,636 +125,625 @@
 	}
 
 	DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
-	    hw->mac.type, ret_val);
-
-	return (ret_val);
+	          hw->mac.type, ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_init_hw - Initialize the hardware
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_init_hw - Initialize the hardware
+ *  @hw: pointer to hardware structure
  *
- * Initialize the hardware by resetting and then starting the hardware
- */
-s32
-ixgbe_init_hw(struct ixgbe_hw *hw)
+ *  Initialize the hardware by resetting and then starting the hardware
+ **/
+s32 ixgbe_init_hw(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_reset_hw - Performs a hardware reset
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_reset_hw - Performs a hardware reset
+ *  @hw: pointer to hardware structure
  *
- * Resets the hardware by resetting the transmit and receive units, masks and
- * clears all interrupts, performs a PHY reset, and performs a MAC reset
- */
-s32
-ixgbe_reset_hw(struct ixgbe_hw *hw)
+ *  Resets the hardware by resetting the transmit and receive units, masks and
+ *  clears all interrupts, performs a PHY reset, and performs a MAC reset
+ **/
+s32 ixgbe_reset_hw(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_start_hw - Prepares hardware for Rx/Tx
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_start_hw - Prepares hardware for Rx/Tx
+ *  @hw: pointer to hardware structure
  *
- * Starts the hardware by filling the bus info structure and media type,
- * clears all on chip counters, initializes receive address registers,
- * multicast table, VLAN filter table, calls routine to setup link and
- * flow control settings, and leaves transmit and receive units disabled
- * and uninitialized.
- */
-s32
-ixgbe_start_hw(struct ixgbe_hw *hw)
+ *  Starts the hardware by filling the bus info structure and media type,
+ *  clears all on chip counters, initializes receive address registers,
+ *  multicast table, VLAN filter table, calls routine to setup link and
+ *  flow control settings, and leaves transmit and receive units disabled
+ *  and uninitialized.
+ **/
+s32 ixgbe_start_hw(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,
- * which is disabled by default in ixgbe_start_hw();
+/**
+ *  ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,
+ *  which is disabled by default in ixgbe_start_hw();
  *
- * @hw: pointer to hardware structure
+ *  @hw: pointer to hardware structure
  *
- * Enable relaxed ordering;
- */
-void
-ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw)
+ *   Enable relaxed ordering;
+ **/
+void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw)
 {
 	if (hw->mac.ops.enable_relaxed_ordering)
 		hw->mac.ops.enable_relaxed_ordering(hw);
 }
 
-/*
- * ixgbe_clear_hw_cntrs - Clear hardware counters
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_clear_hw_cntrs - Clear hardware counters
+ *  @hw: pointer to hardware structure
  *
- * Clears all hardware statistics counters by reading them from the hardware
- * Statistics counters are clear on read.
- */
-s32
-ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
+ *  Clears all hardware statistics counters by reading them from the hardware
+ *  Statistics counters are clear on read.
+ **/
+s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_get_media_type - Get media type
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_media_type - Get media type
+ *  @hw: pointer to hardware structure
  *
- * Returns the media type (fiber, copper, backplane)
- */
-enum ixgbe_media_type
-ixgbe_get_media_type(struct ixgbe_hw *hw)
+ *  Returns the media type (fiber, copper, backplane)
+ **/
+enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),
-	    ixgbe_media_type_unknown);
+	                       ixgbe_media_type_unknown);
 }
 
-/*
- * ixgbe_get_mac_addr - Get MAC address
- * @hw: pointer to hardware structure
- * @mac_addr: Adapter MAC address
+/**
+ *  ixgbe_get_mac_addr - Get MAC address
+ *  @hw: pointer to hardware structure
+ *  @mac_addr: Adapter MAC address
  *
- * Reads the adapter's MAC address from the first Receive Address Register
- * (RAR0) A reset of the adapter must have been performed prior to calling
- * this function in order for the MAC address to have been loaded from the
- * EEPROM into RAR0
- */
-s32
-ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
+ *  Reads the adapter's MAC address from the first Receive Address Register
+ *  (RAR0) A reset of the adapter must have been performed prior to calling
+ *  this function in order for the MAC address to have been loaded from the
+ *  EEPROM into RAR0
+ **/
+s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,
-	    (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
+	                       (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_get_san_mac_addr - Get SAN MAC address
- * @hw: pointer to hardware structure
- * @san_mac_addr: SAN MAC address
+/**
+ *  ixgbe_get_san_mac_addr - Get SAN MAC address
+ *  @hw: pointer to hardware structure
+ *  @san_mac_addr: SAN MAC address
  *
- * Reads the SAN MAC address from the EEPROM, if it's available.  This is
- * per-port, so set_lan_id() must be called before reading the addresses.
- */
-s32
-ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
+ *  Reads the SAN MAC address from the EEPROM, if it's available.  This is
+ *  per-port, so set_lan_id() must be called before reading the addresses.
+ **/
+s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr,
-	    (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
+	                       (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_set_san_mac_addr - Write a SAN MAC address
- * @hw: pointer to hardware structure
- * @san_mac_addr: SAN MAC address
+/**
+ *  ixgbe_set_san_mac_addr - Write a SAN MAC address
+ *  @hw: pointer to hardware structure
+ *  @san_mac_addr: SAN MAC address
  *
- * Writes A SAN MAC address to the EEPROM.
- */
-s32
-ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
+ *  Writes A SAN MAC address to the EEPROM.
+ **/
+s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr,
-	    (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
+	                       (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_get_device_caps - Get additional device capabilities
- * @hw: pointer to hardware structure
- * @device_caps: the EEPROM word for device capabilities
+/**
+ *  ixgbe_get_device_caps - Get additional device capabilities
+ *  @hw: pointer to hardware structure
+ *  @device_caps: the EEPROM word for device capabilities
  *
- * Reads the extra device capabilities from the EEPROM
- */
-s32
-ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
+ *  Reads the extra device capabilities from the EEPROM
+ **/
+s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.get_device_caps,
-	    (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
+	                       (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM
- * @hw: pointer to hardware structure
- * @wwnn_prefix: the alternative WWNN prefix
- * @wwpn_prefix: the alternative WWPN prefix
+/**
+ *  ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM
+ *  @hw: pointer to hardware structure
+ *  @wwnn_prefix: the alternative WWNN prefix
+ *  @wwpn_prefix: the alternative WWPN prefix
  *
- * This function will read the EEPROM from the alternative SAN MAC address
- * block to check the support for the alternative WWNN/WWPN prefix support.
- */
-s32
-ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, u16 *wwpn_prefix)
+ *  This function will read the EEPROM from the alternative SAN MAC address
+ *  block to check the support for the alternative WWNN/WWPN prefix support.
+ **/
+s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
+                         u16 *wwpn_prefix)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,
-	    (hw, wwnn_prefix, wwpn_prefix), IXGBE_NOT_IMPLEMENTED);
+	                       (hw, wwnn_prefix, wwpn_prefix),
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_get_fcoe_boot_status -  Get FCOE boot status from EEPROM
- * @hw: pointer to hardware structure
- * @bs: the fcoe boot status
+/**
+ *  ixgbe_get_fcoe_boot_status -  Get FCOE boot status from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @bs: the fcoe boot status
  *
- * This function will read the FCOE boot status from the iSCSI FCOE block
- */
-s32
-ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)
+ *  This function will read the FCOE boot status from the iSCSI FCOE block
+ **/
+s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status,
-	    (hw, bs), IXGBE_NOT_IMPLEMENTED);
+	                       (hw, bs),
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_get_bus_info - Set PCI bus info
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_bus_info - Set PCI bus info
+ *  @hw: pointer to hardware structure
  *
- * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
- */
-s32
-ixgbe_get_bus_info(struct ixgbe_hw *hw)
+ *  Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
+ **/
+s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_get_num_of_tx_queues - Get Tx queues
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_num_of_tx_queues - Get Tx queues
+ *  @hw: pointer to hardware structure
  *
- * Returns the number of transmit queues for the given adapter.
- */
-u32
-ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
+ *  Returns the number of transmit queues for the given adapter.
+ **/
+u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
 {
-	return (hw->mac.max_tx_queues);
+	return hw->mac.max_tx_queues;
 }
 
-/*
- * ixgbe_get_num_of_rx_queues - Get Rx queues
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_num_of_rx_queues - Get Rx queues
+ *  @hw: pointer to hardware structure
  *
- * Returns the number of receive queues for the given adapter.
- */
-u32
-ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
+ *  Returns the number of receive queues for the given adapter.
+ **/
+u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
 {
-	return (hw->mac.max_rx_queues);
+	return hw->mac.max_rx_queues;
 }
 
-/*
- * ixgbe_stop_adapter - Disable Rx/Tx units
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_stop_adapter - Disable Rx/Tx units
+ *  @hw: pointer to hardware structure
  *
- * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
- * disables transmit and receive units. The adapter_stopped flag is used by
- * the shared code and drivers to determine if the adapter is in a stopped
- * state and should not touch the hardware.
- */
-s32
-ixgbe_stop_adapter(struct ixgbe_hw *hw)
+ *  Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
+ *  disables transmit and receive units. The adapter_stopped flag is used by
+ *  the shared code and drivers to determine if the adapter is in a stopped
+ *  state and should not touch the hardware.
+ **/
+s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_read_pba_num - Reads part number from EEPROM
- * @hw: pointer to hardware structure
- * @pba_num: stores the part number from the EEPROM
+/**
+ *  ixgbe_read_pba_string - Reads part number string from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @pba_num: stores the part number string from the EEPROM
+ *  @pba_num_size: part number string buffer length
  *
- * Reads the part number from the EEPROM.
- */
-s32
-ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)
+ *  Reads the part number string from the EEPROM.
+ **/
+s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)
 {
-	return (ixgbe_read_pba_num_generic(hw, pba_num));
+	return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);
 }
 
-/*
- * ixgbe_identify_phy - Get PHY type
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_read_pba_length - Reads part number string length from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @pba_num_size: part number string buffer length
  *
- * Determines the physical layer module found on the current adapter.
- */
-s32
-ixgbe_identify_phy(struct ixgbe_hw *hw)
+ *  Reads the part number length from the EEPROM.
+ *  Returns expected buffer size in pba_num_size.
+ **/
+s32 ixgbe_read_pba_length(struct ixgbe_hw *hw, u32 *pba_num_size)
 {
+	return ixgbe_read_pba_length_generic(hw, pba_num_size);
+}
+
+/**
+ *  ixgbe_read_pba_num - Reads part number from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @pba_num: stores the part number from the EEPROM
+ *
+ *  Reads the part number from the EEPROM.
+ **/
+s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)
+{
+	return ixgbe_read_pba_num_generic(hw, pba_num);
+}
+
+/**
+ *  ixgbe_identify_phy - Get PHY type
+ *  @hw: pointer to hardware structure
+ *
+ *  Determines the physical layer module found on the current adapter.
+ **/
+s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
+{
 	s32 status = IXGBE_SUCCESS;
 
 	if (hw->phy.type == ixgbe_phy_unknown) {
-		status = ixgbe_call_func(hw,
-		    hw->phy.ops.identify,
-		    (hw),
-		    IXGBE_NOT_IMPLEMENTED);
+		status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),
+		                         IXGBE_NOT_IMPLEMENTED);
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_reset_phy - Perform a PHY reset
- * @hw: pointer to hardware structure
- */
-s32
-ixgbe_reset_phy(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_reset_phy - Perform a PHY reset
+ *  @hw: pointer to hardware structure
+ **/
+s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_SUCCESS;
 
 	if (hw->phy.type == ixgbe_phy_unknown) {
-		if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) {
+		if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS)
 			status = IXGBE_ERR_PHY;
-		}
 	}
 
 	if (status == IXGBE_SUCCESS) {
 		status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),
-		    IXGBE_NOT_IMPLEMENTED);
+		                         IXGBE_NOT_IMPLEMENTED);
 	}
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_get_phy_firmware_version -
- * @hw: pointer to hardware structure
- * @firmware_version: pointer to firmware version
- */
-s32
-ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)
+/**
+ *  ixgbe_get_phy_firmware_version -
+ *  @hw: pointer to hardware structure
+ *  @firmware_version: pointer to firmware version
+ **/
+s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)
 {
 	s32 status = IXGBE_SUCCESS;
 
 	status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
-	    (hw, firmware_version), IXGBE_NOT_IMPLEMENTED);
-	return (status);
+	                         (hw, firmware_version),
+	                         IXGBE_NOT_IMPLEMENTED);
+	return status;
 }
 
-/*
- * ixgbe_read_phy_reg - Read PHY register
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit address of PHY register to read
- * @phy_data: Pointer to read data from PHY register
+/**
+ *  ixgbe_read_phy_reg - Read PHY register
+ *  @hw: pointer to hardware structure
+ *  @reg_addr: 32 bit address of PHY register to read
+ *  @phy_data: Pointer to read data from PHY register
  *
- * Reads a value from a specified PHY register
- */
-s32
-ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
-	u16 *phy_data)
+ *  Reads a value from a specified PHY register
+ **/
+s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
+                       u16 *phy_data)
 {
 	if (hw->phy.id == 0)
 		(void) ixgbe_identify_phy(hw);
 
 	return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
-	    device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
+	                       device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_write_phy_reg - Write PHY register
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit PHY register to write
- * @phy_data: Data to write to the PHY register
+/**
+ *  ixgbe_write_phy_reg - Write PHY register
+ *  @hw: pointer to hardware structure
+ *  @reg_addr: 32 bit PHY register to write
+ *  @phy_data: Data to write to the PHY register
  *
- * Writes a value to specified PHY register
- */
+ *  Writes a value to specified PHY register
+ **/
 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
-    u16 phy_data)
+                        u16 phy_data)
 {
 	if (hw->phy.id == 0)
 		(void) ixgbe_identify_phy(hw);
 
 	return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
-	    device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
+	                       device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_setup_phy_link - Restart PHY autoneg
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_setup_phy_link - Restart PHY autoneg
+ *  @hw: pointer to hardware structure
  *
- * Restart autonegotiation and PHY and waits for completion.
- */
-s32
-ixgbe_setup_phy_link(struct ixgbe_hw *hw)
+ *  Restart autonegotiation and PHY and waits for completion.
+ **/
+s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_check_phy_link - Determine link and speed status
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_check_phy_link - Determine link and speed status
+ *  @hw: pointer to hardware structure
  *
- * Reads a PHY register to determine if link is up and the current speed for
- * the PHY.
- */
+ *  Reads a PHY register to determine if link is up and the current speed for
+ *  the PHY.
+ **/
 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
-    bool *link_up)
+                         bool *link_up)
 {
 	return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
-	    link_up), IXGBE_NOT_IMPLEMENTED);
+	                       link_up), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_setup_phy_link_speed - Set auto advertise
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
+/**
+ *  ixgbe_setup_phy_link_speed - Set auto advertise
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: TRUE if autonegotiation enabled
  *
- * Sets the auto advertised capabilities
- */
-s32
-ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
-    bool autoneg,
-    bool autoneg_wait_to_complete)
+ *  Sets the auto advertised capabilities
+ **/
+s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
+                               bool autoneg,
+                               bool autoneg_wait_to_complete)
 {
 	return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
-	    autoneg, autoneg_wait_to_complete),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       autoneg, autoneg_wait_to_complete),
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_check_link - Get link and speed status
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_check_link - Get link and speed status
+ *  @hw: pointer to hardware structure
  *
- * Reads the links register to determine if link is up and the current speed
- */
-s32
-ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
-    bool *link_up, bool link_up_wait_to_complete)
+ *  Reads the links register to determine if link is up and the current speed
+ **/
+s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
+                     bool *link_up, bool link_up_wait_to_complete)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
-	    link_up, link_up_wait_to_complete), IXGBE_NOT_IMPLEMENTED);
+	                       link_up, link_up_wait_to_complete),
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_disable_tx_laser - Disable Tx laser
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_disable_tx_laser - Disable Tx laser
+ *  @hw: pointer to hardware structure
  *
- * If the driver needs to disable the laser on SFI optics.
- */
-void
-ixgbe_disable_tx_laser(struct ixgbe_hw *hw)
+ *  If the driver needs to disable the laser on SFI optics.
+ **/
+void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)
 {
 	if (hw->mac.ops.disable_tx_laser)
 		hw->mac.ops.disable_tx_laser(hw);
 }
 
-/*
- * ixgbe_enable_tx_laser - Enable Tx laser
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_enable_tx_laser - Enable Tx laser
+ *  @hw: pointer to hardware structure
  *
- * If the driver needs to enable the laser on SFI optics.
- */
-void
-ixgbe_enable_tx_laser(struct ixgbe_hw *hw)
+ *  If the driver needs to enable the laser on SFI optics.
+ **/
+void ixgbe_enable_tx_laser(struct ixgbe_hw *hw)
 {
 	if (hw->mac.ops.enable_tx_laser)
 		hw->mac.ops.enable_tx_laser(hw);
 }
 
-/*
- * ixgbe_flap_tx_laser - flap Tx laser to start autotry process
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_flap_tx_laser - flap Tx laser to start autotry process
+ *  @hw: pointer to hardware structure
  *
- * When the driver changes the link speeds that it can support then
- * flap the tx laser to alert the link partner to start autotry
- * process on its end.
- */
-void
-ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
+ *  When the driver changes the link speeds that it can support then
+ *  flap the tx laser to alert the link partner to start autotry
+ *  process on its end.
+ **/
+void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
 {
 	if (hw->mac.ops.flap_tx_laser)
 		hw->mac.ops.flap_tx_laser(hw);
 }
 
-/*
- * ixgbe_setup_link - Set link speed
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
+/**
+ *  ixgbe_setup_link - Set link speed
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: TRUE if autonegotiation enabled
  *
- * Configures link settings.  Restarts the link.
- * Performs autonegotiation if needed.
- */
+ *  Configures link settings.  Restarts the link.
+ *  Performs autonegotiation if needed.
+ **/
 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
-    bool autoneg,
-    bool autoneg_wait_to_complete)
+                           bool autoneg,
+                           bool autoneg_wait_to_complete)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
-	    autoneg, autoneg_wait_to_complete),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       autoneg, autoneg_wait_to_complete),
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_get_link_capabilities - Returns link capabilities
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_link_capabilities - Returns link capabilities
+ *  @hw: pointer to hardware structure
  *
- * Determines the link capabilities of the current configuration.
- */
-s32
-ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
-    bool *autoneg)
+ *  Determines the link capabilities of the current configuration.
+ **/
+s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
+                                bool *autoneg)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
-	    speed, autoneg), IXGBE_NOT_IMPLEMENTED);
+	                       speed, autoneg), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_led_on - Turn on LEDs
- * @hw: pointer to hardware structure
- * @index: led number to turn on
+/**
+ *  ixgbe_led_on - Turn on LEDs
+ *  @hw: pointer to hardware structure
+ *  @index: led number to turn on
  *
- * Turns on the software controllable LEDs.
- */
-s32
-ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
+ *  Turns on the software controllable LEDs.
+ **/
+s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_led_off - Turn off LEDs
- * @hw: pointer to hardware structure
- * @index: led number to turn off
+/**
+ *  ixgbe_led_off - Turn off LEDs
+ *  @hw: pointer to hardware structure
+ *  @index: led number to turn off
  *
- * Turns off the software controllable LEDs.
- */
-s32
-ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
+ *  Turns off the software controllable LEDs.
+ **/
+s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_blink_led_start - Blink LEDs
- * @hw: pointer to hardware structure
- * @index: led number to blink
+/**
+ *  ixgbe_blink_led_start - Blink LEDs
+ *  @hw: pointer to hardware structure
+ *  @index: led number to blink
  *
- * Blink LED based on index.
- */
-s32
-ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
+ *  Blink LED based on index.
+ **/
+s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_blink_led_stop - Stop blinking LEDs
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_blink_led_stop - Stop blinking LEDs
+ *  @hw: pointer to hardware structure
  *
- * Stop blinking LED based on index.
- */
-s32
-ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
+ *  Stop blinking LED based on index.
+ **/
+s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_init_eeprom_params - Initialize EEPROM parameters
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_init_eeprom_params - Initialize EEPROM parameters
+ *  @hw: pointer to hardware structure
  *
- * Initializes the EEPROM parameters ixgbe_eeprom_info within the
- * ixgbe_hw struct in order to set up EEPROM access.
- */
-s32
-ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
+ *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
+ *  ixgbe_hw struct in order to set up EEPROM access.
+ **/
+s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
 
-/*
- * ixgbe_write_eeprom - Write word to EEPROM
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be written to
- * @data: 16 bit word to be written to the EEPROM
+/**
+ *  ixgbe_write_eeprom - Write word to EEPROM
+ *  @hw: pointer to hardware structure
+ *  @offset: offset within the EEPROM to be written to
+ *  @data: 16 bit word to be written to the EEPROM
  *
- * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
- * called after this function, the EEPROM will most likely contain an
- * invalid checksum.
- */
-s32
-ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
+ *  Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
+ *  called after this function, the EEPROM will most likely contain an
+ *  invalid checksum.
+ **/
+s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
 {
 	return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_read_eeprom - Read word from EEPROM
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be read
- * @data: read 16 bit value from EEPROM
+/**
+ *  ixgbe_read_eeprom - Read word from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @offset: offset within the EEPROM to be read
+ *  @data: read 16 bit value from EEPROM
  *
- * Reads 16 bit value from EEPROM
- */
-s32
-ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
+ *  Reads 16 bit value from EEPROM
+ **/
+s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
 {
 	return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
- * @hw: pointer to hardware structure
- * @checksum_val: calculated checksum
+/**
+ *  ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
+ *  @hw: pointer to hardware structure
+ *  @checksum_val: calculated checksum
  *
- * Performs checksum calculation and validates the EEPROM checksum
- */
-s32
-ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
+ *  Performs checksum calculation and validates the EEPROM checksum
+ **/
+s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
 {
 	return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,
-	    (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
+	                       (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
- * @hw: pointer to hardware structure
- */
-s32
-ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
+ *  @hw: pointer to hardware structure
+ **/
+s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_insert_mac_addr - Find a RAR for this mac address
- * @hw: pointer to hardware structure
- * @addr: Address to put into receive address register
- * @vmdq: VMDq pool to assign
+/**
+ *  ixgbe_insert_mac_addr - Find a RAR for this mac address
+ *  @hw: pointer to hardware structure
+ *  @addr: Address to put into receive address register
+ *  @vmdq: VMDq pool to assign
  *
- * Puts an ethernet address into a receive address register, or
- * finds the rar that it is aleady in; adds to the pool list
- */
-s32
-ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
+ *  Puts an ethernet address into a receive address register, or
+ *  finds the rar that it is aleady in; adds to the pool list
+ **/
+s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr,
-	    (hw, addr, vmdq), IXGBE_NOT_IMPLEMENTED);
+	                       (hw, addr, vmdq),
+			       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_set_rar - Set Rx address register
- * @hw: pointer to hardware structure
- * @index: Receive address register to write
- * @addr: Address to put into receive address register
- * @vmdq: VMDq "set"
- * @enable_addr: set flag that address is active
+/**
+ *  ixgbe_set_rar - Set Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: Receive address register to write
+ *  @addr: Address to put into receive address register
+ *  @vmdq: VMDq "set"
+ *  @enable_addr: set flag that address is active
  *
- * Puts an ethernet address into a receive address register.
- */
-s32
-ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
-    u32 enable_addr)
+ *  Puts an ethernet address into a receive address register.
+ **/
+s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
+                  u32 enable_addr)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,
 	    enable_addr), IXGBE_NOT_IMPLEMENTED);
@@ -757,344 +746,325 @@
     u32 enable_addr)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,
-	    enable_addr), IXGBE_NOT_IMPLEMENTED);
+	                       enable_addr), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_clear_rar - Clear Rx address register
- * @hw: pointer to hardware structure
- * @index: Receive address register to write
+/**
+ *  ixgbe_clear_rar - Clear Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: Receive address register to write
  *
- * Puts an ethernet address into a receive address register.
- */
-s32
-ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
+ *  Puts an ethernet address into a receive address register.
+ **/
+s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_set_vmdq - Associate a VMDq index with a receive address
- * @hw: pointer to hardware structure
- * @rar: receive address register index to associate with VMDq index
- * @vmdq: VMDq set or pool index
- */
-s32
-ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
+/**
+ *  ixgbe_set_vmdq - Associate a VMDq index with a receive address
+ *  @hw: pointer to hardware structure
+ *  @rar: receive address register index to associate with VMDq index
+ *  @vmdq: VMDq set or pool index
+ **/
+s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
- * @hw: pointer to hardware structure
- * @rar: receive address register index to disassociate with VMDq index
- * @vmdq: VMDq set or pool index
- */
-s32
-ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
+/**
+ *  ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
+ *  @hw: pointer to hardware structure
+ *  @rar: receive address register index to disassociate with VMDq index
+ *  @vmdq: VMDq set or pool index
+ **/
+s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_init_rx_addrs - Initializes receive address filters.
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_init_rx_addrs - Initializes receive address filters.
+ *  @hw: pointer to hardware structure
  *
- * Places the MAC address in receive address register 0 and clears the rest
- * of the receive address registers. Clears the multicast table. Assumes
- * the receiver is in reset when the routine is called.
- */
-s32
-ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
+ *  Places the MAC address in receive address register 0 and clears the rest
+ *  of the receive address registers. Clears the multicast table. Assumes
+ *  the receiver is in reset when the routine is called.
+ **/
+s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
- * @hw: pointer to hardware structure
- */
-u32
-ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
+ *  @hw: pointer to hardware structure
+ **/
+u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)
 {
-	return (hw->mac.num_rar_entries);
+	return hw->mac.num_rar_entries;
 }
 
-/*
- * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses
- * @hw: pointer to hardware structure
- * @addr_list: the list of new multicast addresses
- * @addr_count: number of addresses
- * @func: iterator function to walk the multicast address list
+/**
+ *  ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses
+ *  @hw: pointer to hardware structure
+ *  @addr_list: the list of new multicast addresses
+ *  @addr_count: number of addresses
+ *  @func: iterator function to walk the multicast address list
  *
- * The given list replaces any existing list. Clears the secondary addrs from
- * receive address registers. Uses unused receive address registers for the
- * first secondary addresses, and falls back to promiscuous mode as needed.
- */
-s32
-ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
-    u32 addr_count, ixgbe_mc_addr_itr func)
+ *  The given list replaces any existing list. Clears the secondary addrs from
+ *  receive address registers. Uses unused receive address registers for the
+ *  first secondary addresses, and falls back to promiscuous mode as needed.
+ **/
+s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
+                              u32 addr_count, ixgbe_mc_addr_itr func)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,
-	    addr_list, addr_count, func),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       addr_list, addr_count, func),
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
- * @hw: pointer to hardware structure
- * @mc_addr_list: the list of new multicast addresses
- * @mc_addr_count: number of addresses
- * @func: iterator function to walk the multicast address list
+/**
+ *  ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
+ *  @hw: pointer to hardware structure
+ *  @mc_addr_list: the list of new multicast addresses
+ *  @mc_addr_count: number of addresses
+ *  @func: iterator function to walk the multicast address list
  *
- * The given list replaces any existing list. Clears the MC addrs from receive
- * address registers and the multicast table. Uses unused receive address
- * registers for the first multicast addresses, and hashes the rest into the
- * multicast table.
- */
-s32
-ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
-    u32 mc_addr_count, ixgbe_mc_addr_itr func)
+ *  The given list replaces any existing list. Clears the MC addrs from receive
+ *  address registers and the multicast table. Uses unused receive address
+ *  registers for the first multicast addresses, and hashes the rest into the
+ *  multicast table.
+ **/
+s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
+                              u32 mc_addr_count, ixgbe_mc_addr_itr func)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
-	    mc_addr_list, mc_addr_count, func),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       mc_addr_list, mc_addr_count, func),
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_enable_mc - Enable multicast address in RAR
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_enable_mc - Enable multicast address in RAR
+ *  @hw: pointer to hardware structure
  *
- * Enables multicast address in RAR and the use of the multicast hash table.
- */
-s32
-ixgbe_enable_mc(struct ixgbe_hw *hw)
+ *  Enables multicast address in RAR and the use of the multicast hash table.
+ **/
+s32 ixgbe_enable_mc(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_disable_mc - Disable multicast address in RAR
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_disable_mc - Disable multicast address in RAR
+ *  @hw: pointer to hardware structure
  *
- * Disables multicast address in RAR and the use of the multicast hash table.
- */
-s32
-ixgbe_disable_mc(struct ixgbe_hw *hw)
+ *  Disables multicast address in RAR and the use of the multicast hash table.
+ **/
+s32 ixgbe_disable_mc(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_clear_vfta - Clear VLAN filter table
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_clear_vfta - Clear VLAN filter table
+ *  @hw: pointer to hardware structure
  *
- * Clears the VLAN filer table, and the VMDq index associated with the filter
- */
-s32
-ixgbe_clear_vfta(struct ixgbe_hw *hw)
+ *  Clears the VLAN filer table, and the VMDq index associated with the filter
+ **/
+s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_set_vfta - Set VLAN filter table
- * @hw: pointer to hardware structure
- * @vlan: VLAN id to write to VLAN filter
- * @vind: VMDq output index that maps queue to VLAN id in VFTA
- * @vlan_on: boolean flag to turn on/off VLAN in VFTA
+/**
+ *  ixgbe_set_vfta - Set VLAN filter table
+ *  @hw: pointer to hardware structure
+ *  @vlan: VLAN id to write to VLAN filter
+ *  @vind: VMDq output index that maps queue to VLAN id in VFTA
+ *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
  *
- * Turn on/off specified VLAN in the VLAN filter table.
- */
-s32
-ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
+ *  Turn on/off specified VLAN in the VLAN filter table.
+ **/
+s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
-	    vlan_on), IXGBE_NOT_IMPLEMENTED);
+	                       vlan_on), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_fc_enable - Enable flow control
- * @hw: pointer to hardware structure
- * @packetbuf_num: packet buffer number (0-7)
+/**
+ *  ixgbe_fc_enable - Enable flow control
+ *  @hw: pointer to hardware structure
+ *  @packetbuf_num: packet buffer number (0-7)
  *
- * Configures the flow control settings based on SW configuration.
- */
-s32
-ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
+ *  Configures the flow control settings based on SW configuration.
+ **/
+s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_read_analog_reg8 - Reads 8 bit analog register
- * @hw: pointer to hardware structure
- * @reg: analog register to read
- * @val: read value
+/**
+ *  ixgbe_read_analog_reg8 - Reads 8 bit analog register
+ *  @hw: pointer to hardware structure
+ *  @reg: analog register to read
+ *  @val: read value
  *
- * Performs write operation to analog register specified.
- */
-s32
-ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
+ *  Performs write operation to analog register specified.
+ **/
+s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
-	    val), IXGBE_NOT_IMPLEMENTED);
+	                       val), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_write_analog_reg8 - Writes 8 bit analog register
- * @hw: pointer to hardware structure
- * @reg: analog register to write
- * @val: value to write
+/**
+ *  ixgbe_write_analog_reg8 - Writes 8 bit analog register
+ *  @hw: pointer to hardware structure
+ *  @reg: analog register to write
+ *  @val: value to write
  *
- * Performs write operation to Atlas analog register specified.
- */
-s32
-ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
+ *  Performs write operation to Atlas analog register specified.
+ **/
+s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,
-	    val), IXGBE_NOT_IMPLEMENTED);
+	                       val), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
+ *  @hw: pointer to hardware structure
  *
- * Initializes the Unicast Table Arrays to zero on device load.  This
- * is part of the Rx init addr execution path.
- */
-s32
-ixgbe_init_uta_tables(struct ixgbe_hw *hw)
+ *  Initializes the Unicast Table Arrays to zero on device load.  This
+ *  is part of the Rx init addr execution path.
+ **/
+s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
-	    IXGBE_NOT_IMPLEMENTED);
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to read
- * @data: value read
+/**
+ *  ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: byte offset to read
+ *  @data: value read
  *
- * Performs byte read operation to SFP module's EEPROM over I2C interface.
- */
-s32
-ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
-    u8 *data)
+ *  Performs byte read operation to SFP module's EEPROM over I2C interface.
+ **/
+s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
+                        u8 *data)
 {
 	return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,
-	    dev_addr, data), IXGBE_NOT_IMPLEMENTED);
+	                       dev_addr, data), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to write
- * @data: value to write
+/**
+ *  ixgbe_write_i2c_byte - Writes 8 bit word over I2C
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: byte offset to write
+ *  @data: value to write
  *
- * Performs byte write operation to SFP module's EEPROM over I2C interface
- * at a specified device address.
- */
-s32
-ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
-    u8 data)
+ *  Performs byte write operation to SFP module's EEPROM over I2C interface
+ *  at a specified device address.
+ **/
+s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
+                         u8 data)
 {
-	return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte,
-	    (hw, byte_offset, dev_addr, data), IXGBE_NOT_IMPLEMENTED);
+	return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,
+	                       dev_addr, data), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
- * @hw: pointer to hardware structure
- * @byte_offset: EEPROM byte offset to write
- * @eeprom_data: value to write
+/**
+ *  ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: EEPROM byte offset to write
+ *  @eeprom_data: value to write
  *
- * Performs byte write operation to SFP module's EEPROM over I2C interface.
- */
-s32
-ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data)
+ *  Performs byte write operation to SFP module's EEPROM over I2C interface.
+ **/
+s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,
+                           u8 byte_offset, u8 eeprom_data)
 {
 	return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,
-	    (hw, byte_offset, eeprom_data), IXGBE_NOT_IMPLEMENTED);
+	                       (hw, byte_offset, eeprom_data),
+	                       IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
- * @hw: pointer to hardware structure
- * @byte_offset: EEPROM byte offset to read
- * @eeprom_data: value read
+/**
+ *  ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: EEPROM byte offset to read
+ *  @eeprom_data: value read
  *
- * Performs byte read operation to SFP module's EEPROM over I2C interface.
- */
-s32
-ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
+ *  Performs byte read operation to SFP module's EEPROM over I2C interface.
+ **/
+s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
 {
 	return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,
-	    (hw, byte_offset, eeprom_data), IXGBE_NOT_IMPLEMENTED);
+	                      (hw, byte_offset, eeprom_data),
+	                      IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_get_supported_physical_layer - Returns physical layer type
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_supported_physical_layer - Returns physical layer type
+ *  @hw: pointer to hardware structure
  *
- * Determines physical layer capabilities of the current configuration.
- */
-u32
-ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
+ *  Determines physical layer capabilities of the current configuration.
+ **/
+u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
-	    (hw), IXGBE_NOT_IMPLEMENTED);
+	                       (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
 }
 
-/*
- * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics
- * @hw: pointer to hardware structure
- * @regval: bitfield to write to the Rx DMA register
+/**
+ *  ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics
+ *  @hw: pointer to hardware structure
+ *  @regval: bitfield to write to the Rx DMA register
  *
- * Enables the Rx DMA unit of the device.
- */
-s32
-ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)
+ *  Enables the Rx DMA unit of the device.
+ **/
+s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
-	    (hw, regval), IXGBE_NOT_IMPLEMENTED);
+	                       (hw, regval), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
- * @hw: pointer to hardware structure
- * @mask: Mask to specify which semaphore to acquire
+/**
+ *  ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
+ *  @hw: pointer to hardware structure
+ *  @mask: Mask to specify which semaphore to acquire
  *
- * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
- * function (CSR, PHY0, PHY1, EEPROM, Flash)
- */
-s32
-ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
+ *  Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
+ *  function (CSR, PHY0, PHY1, EEPROM, Flash)
+ **/
+s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
 {
 	return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
-	    (hw, mask), IXGBE_NOT_IMPLEMENTED);
+	                       (hw, mask), IXGBE_NOT_IMPLEMENTED);
 }
 
-/*
- * ixgbe_release_swfw_semaphore - Release SWFW semaphore
- * @hw: pointer to hardware structure
- * @mask: Mask to specify which semaphore to release
+/**
+ *  ixgbe_release_swfw_semaphore - Release SWFW semaphore
+ *  @hw: pointer to hardware structure
+ *  @mask: Mask to specify which semaphore to release
  *
- * Releases the SWFW semaphore through SW_FW_SYNC register for the specified
- * function (CSR, PHY0, PHY1, EEPROM, Flash)
- */
-void
-ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
+ *  Releases the SWFW semaphore through SW_FW_SYNC register for the specified
+ *  function (CSR, PHY0, PHY1, EEPROM, Flash)
+ **/
+void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
 {
 	if (hw->mac.ops.release_swfw_sync)
 		hw->mac.ops.release_swfw_sync(hw, mask);
 }
+
--- old/usr/src/uts/common/io/ixgbe/ixgbe_api.h	Wed Sep  7 11:32:35 2011
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_api.h	Wed Sep  7 11:32:34 2011
@@ -1,38 +1,39 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at:
- *      http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When using or redistributing this file, you may do so under the
- * License only. No other modification of this header is permitted.
- *
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
+/******************************************************************************
 
-/*
- * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
- */
+  Copyright (c) 2001-2010, Intel Corporation 
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without 
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice, 
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright 
+      notice, this list of conditions and the following disclaimer in the 
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its 
+      contributors may be used to endorse or promote products derived from 
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
 
-/*
- * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
- */
+******************************************************************************/
 
-/* IntelVersion: 1.82 scm_061610_003709 */
+#ifndef _IXGBE_API_H_
+#define _IXGBE_API_H_
 
-#ifndef _IXGBE_API_H
-#define	_IXGBE_API_H
-
 #include "ixgbe_type.h"
 
 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw);
@@ -50,28 +51,33 @@
 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);
 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num);
+s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);
+s32 ixgbe_read_pba_length(struct ixgbe_hw *hw, u32 *pba_num_size);
 
 s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
 s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
-    u16 *phy_data);
+                       u16 *phy_data);
 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
-    u16 phy_data);
+                        u16 phy_data);
 
 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
-    ixgbe_link_speed *speed, bool *link_up);
-s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
-    bool autoneg, bool autoneg_wait_to_complete);
+                         ixgbe_link_speed *speed,
+                         bool *link_up);
+s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,
+                               ixgbe_link_speed speed,
+                               bool autoneg,
+                               bool autoneg_wait_to_complete);
 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw);
 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw);
 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw);
 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
-    bool autoneg, bool autoneg_wait_to_complete);
+                           bool autoneg, bool autoneg_wait_to_complete);
 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
-    bool *link_up, bool link_up_wait_to_complete);
+                     bool *link_up, bool link_up_wait_to_complete);
 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
-    bool *autoneg);
+                            bool *autoneg);
 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);
@@ -85,7 +91,7 @@
 
 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
-    u32 enable_addr);
+                  u32 enable_addr);
 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index);
 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
@@ -92,20 +98,21 @@
 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw);
 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw);
 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
-    u32 addr_count, ixgbe_mc_addr_itr func);
+                              u32 addr_count, ixgbe_mc_addr_itr func);
 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
-    u32 mc_addr_count, ixgbe_mc_addr_itr func);
+                              u32 mc_addr_count, ixgbe_mc_addr_itr func);
 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);
 s32 ixgbe_enable_mc(struct ixgbe_hw *hw);
 s32 ixgbe_disable_mc(struct ixgbe_hw *hw);
 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw);
-s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on);
+s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan,
+                   u32 vind, bool vlan_on);
 
 s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num);
 
 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);
 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw,
-    u16 *firmware_version);
+                                   u16 *firmware_version);
 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);
 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);
 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw);
@@ -116,40 +123,19 @@
 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
-    struct ixgbe_atr_input *input, u8 queue);
+                                          union ixgbe_atr_hash_dword input,
+					  union ixgbe_atr_hash_dword common,
+                                          u8 queue);
 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
-    struct ixgbe_atr_input *input, struct ixgbe_atr_input_masks *masks,
-    u16 soft_id, u8 queue);
-u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *input, u32 key);
-s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan_id);
-s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr);
-s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr);
-s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input, u32 src_addr_1,
-    u32 src_addr_2, u32 src_addr_3, u32 src_addr_4);
-s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input, u32 dst_addr_1,
-    u32 dst_addr_2, u32 dst_addr_3, u32 dst_addr_4);
-s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port);
-s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port);
-s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte);
-s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input, u8 vm_pool);
-s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type);
-s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan_id);
-s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input, u32 *src_addr);
-s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 *dst_addr);
-s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input, u32 *src_addr_1,
-    u32 *src_addr_2, u32 *src_addr_3, u32 *src_addr_4);
-s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input, u32 *dst_addr_1,
-    u32 *dst_addr_2, u32 *dst_addr_3, u32 *dst_addr_4);
-s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input, u16 *src_port);
-s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input, u16 *dst_port);
-s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
-    u16 *flex_byte);
-s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input, u8 *vm_pool);
-s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input, u8 *l4type);
+                                        union ixgbe_atr_input *input,
+                                        struct ixgbe_atr_input_masks *masks,
+                                        u16 soft_id,
+                                        u8 queue);
+u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *input, u32 key);
 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
-    u8 *data);
+                        u8 *data);
 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
-    u8 data);
+                         u8 data);
 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);
 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
@@ -157,7 +143,8 @@
 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
-    u16 *wwpn_prefix);
+                         u16 *wwpn_prefix);
 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);
 
-#endif /* _IXGBE_API_H */
+
+#endif /* _IXGBE_API_H_ */
--- old/usr/src/uts/common/io/ixgbe/ixgbe_common.c	Wed Sep  7 11:32:36 2011
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_common.c	Wed Sep  7 11:32:35 2011
@@ -1,34 +1,37 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
+/******************************************************************************
 
-/*
- * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
- */
+  Copyright (c) 2001-2010, Intel Corporation 
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without 
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice, 
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright 
+      notice, this list of conditions and the following disclaimer in the 
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its 
+      contributors may be used to endorse or promote products derived from 
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
 
-/*
- * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
- */
+******************************************************************************/
+/*$FreeBSD$*/
 
-/* IntelVersion: 1.238 scm_061610_003709 */
-
 #include "ixgbe_common.h"
 #include "ixgbe_phy.h"
 #include "ixgbe_api.h"
@@ -39,7 +42,7 @@
 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
-    u16 count);
+                                        u16 count);
 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
@@ -47,23 +50,23 @@
 
 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
-    u16 *san_mac_offset);
+                                        u16 *san_mac_offset);
 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw);
 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw);
 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw);
 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
-    u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
+			      u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
+
 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan);
 
-/*
- * ixgbe_init_ops_generic - Inits function ptrs
- * @hw: pointer to the hardware structure
+/**
+ *  ixgbe_init_ops_generic - Inits function ptrs
+ *  @hw: pointer to the hardware structure
  *
- * Initialize the function pointers.
- */
-s32
-ixgbe_init_ops_generic(struct ixgbe_hw *hw)
+ *  Initialize the function pointers.
+ **/
+s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 	struct ixgbe_mac_info *mac = &hw->mac;
@@ -80,7 +83,7 @@
 		eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
 	eeprom->ops.write = &ixgbe_write_eeprom_generic;
 	eeprom->ops.validate_checksum =
-	    &ixgbe_validate_eeprom_checksum_generic;
+	                              &ixgbe_validate_eeprom_checksum_generic;
 	eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
 	eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
 
@@ -128,20 +131,19 @@
 	mac->ops.setup_link = NULL;
 	mac->ops.check_link = NULL;
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
+ *  @hw: pointer to hardware structure
  *
- * Starts the hardware by filling the bus info structure and media type, clears
- * all on chip counters, initializes receive address registers, multicast
- * table, VLAN filter table, calls routine to set up link and flow control
- * settings, and leaves transmit and receive units disabled and uninitialized
- */
-s32
-ixgbe_start_hw_generic(struct ixgbe_hw *hw)
+ *  Starts the hardware by filling the bus info structure and media type, clears
+ *  all on chip counters, initializes receive address registers, multicast
+ *  table, VLAN filter table, calls routine to set up link and flow control
+ *  settings, and leaves transmit and receive units disabled and uninitialized
+ **/
+s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
 {
 	u32 ctrl_ext;
 
@@ -168,26 +170,64 @@
 	(void) ixgbe_setup_fc(hw, 0);
 
 	/* Clear adapter stopped flag */
-	hw->adapter_stopped = false;
+	hw->adapter_stopped = FALSE;
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_init_hw_generic - Generic hardware initialization
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_start_hw_gen2 - Init sequence for common device family
+ *  @hw: pointer to hw structure
  *
- * Initialize the hardware by resetting the hardware, filling the bus info
- * structure and media type, clears all on chip counters, initializes receive
- * address registers, multicast table, VLAN filter table, calls routine to set
- * up link and flow control settings, and leaves transmit and receive units
- * disabled and uninitialized
- */
-s32
-ixgbe_init_hw_generic(struct ixgbe_hw *hw)
+ * Performs the init sequence common to the second generation
+ * of 10 GbE devices.
+ * Devices in the second generation:
+ *     82599
+ *     X540
+ **/
+s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
 {
-	s32 status = IXGBE_SUCCESS;
+	u32 i;
+	u32 regval;
 
+	/* Clear the rate limiters */
+	for (i = 0; i < hw->mac.max_tx_queues; i++) {
+		IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
+		IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
+	}
+	IXGBE_WRITE_FLUSH(hw);
+
+	/* Disable relaxed ordering */
+	for (i = 0; i < hw->mac.max_tx_queues; i++) {
+		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
+		regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
+	}
+
+	for (i = 0; i < hw->mac.max_rx_queues; i++) {
+		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
+		regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
+					IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
+	}
+
+	return IXGBE_SUCCESS;
+}
+
+/**
+ *  ixgbe_init_hw_generic - Generic hardware initialization
+ *  @hw: pointer to hardware structure
+ *
+ *  Initialize the hardware by resetting the hardware, filling the bus info
+ *  structure and media type, clears all on chip counters, initializes receive
+ *  address registers, multicast table, VLAN filter table, calls routine to set
+ *  up link and flow control settings, and leaves transmit and receive units
+ *  disabled and uninitialized
+ **/
+s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
+{
+	s32 status;
+
 	DEBUGFUNC("ixgbe_init_hw_generic");
 
 	/* Reset the hardware */
@@ -198,18 +238,17 @@
 		status = hw->mac.ops.start_hw(hw);
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
+ *  @hw: pointer to hardware structure
  *
- * Clears all hardware statistics counters by reading them from the hardware
- * Statistics counters are clear on read.
- */
-s32
-ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
+ *  Clears all hardware statistics counters by reading them from the hardware
+ *  Statistics counters are clear on read.
+ **/
+s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
 {
 	u16 i = 0;
 
@@ -249,7 +288,6 @@
 	if (hw->mac.type >= ixgbe_mac_82599EB)
 		for (i = 0; i < 8; i++)
 			(void) IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
-
 	(void) IXGBE_READ_REG(hw, IXGBE_PRC64);
 	(void) IXGBE_READ_REG(hw, IXGBE_PRC127);
 	(void) IXGBE_READ_REG(hw, IXGBE_PRC255);
@@ -300,28 +338,201 @@
 		}
 	}
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_read_pba_num_generic - Reads part number from EEPROM
- * @hw: pointer to hardware structure
- * @pba_num: stores the part number from the EEPROM
+/**
+ *  ixgbe_read_pba_string_generic - Reads part number string from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @pba_num: stores the part number string from the EEPROM
+ *  @pba_num_size: part number string buffer length
  *
- * Reads the part number from the EEPROM.
- */
-s32
-ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
+ *  Reads the part number string from the EEPROM.
+ **/
+s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
+                                  u32 pba_num_size)
 {
 	s32 ret_val;
 	u16 data;
+	u16 pba_ptr;
+	u16 offset;
+	u16 length;
 
+	DEBUGFUNC("ixgbe_read_pba_string_generic");
+
+	if (pba_num == NULL) {
+		DEBUGOUT("PBA string buffer was null\n");
+		return IXGBE_ERR_INVALID_ARGUMENT;
+	}
+
+	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
+	if (ret_val) {
+		DEBUGOUT("NVM Read Error\n");
+		return ret_val;
+	}
+
+	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
+	if (ret_val) {
+		DEBUGOUT("NVM Read Error\n");
+		return ret_val;
+	}
+
+	/*
+	 * if data is not ptr guard the PBA must be in legacy format which
+	 * means pba_ptr is actually our second data word for the PBA number
+	 * and we can decode it into an ascii string
+	 */
+	if (data != IXGBE_PBANUM_PTR_GUARD) {
+		DEBUGOUT("NVM PBA number is not stored as string\n");
+
+		/* we will need 11 characters to store the PBA */
+		if (pba_num_size < 11) {
+			DEBUGOUT("PBA string buffer too small\n");
+			return IXGBE_ERR_NO_SPACE;
+		}
+
+		/* extract hex string from data and pba_ptr */
+		pba_num[0] = (data >> 12) & 0xF;
+		pba_num[1] = (data >> 8) & 0xF;
+		pba_num[2] = (data >> 4) & 0xF;
+		pba_num[3] = data & 0xF;
+		pba_num[4] = (pba_ptr >> 12) & 0xF;
+		pba_num[5] = (pba_ptr >> 8) & 0xF;
+		pba_num[6] = '-';
+		pba_num[7] = 0;
+		pba_num[8] = (pba_ptr >> 4) & 0xF;
+		pba_num[9] = pba_ptr & 0xF;
+
+		/* put a null character on the end of our string */
+		pba_num[10] = '\0';
+
+		/* switch all the data but the '-' to hex char */
+		for (offset = 0; offset < 10; offset++) {
+			if (pba_num[offset] < 0xA)
+				pba_num[offset] += '0';
+			else if (pba_num[offset] < 0x10)
+				pba_num[offset] += 'A' - 0xA;
+		}
+
+		return IXGBE_SUCCESS;
+	}
+
+	ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
+	if (ret_val) {
+		DEBUGOUT("NVM Read Error\n");
+		return ret_val;
+	}
+
+	if (length == 0xFFFF || length == 0) {
+		DEBUGOUT("NVM PBA number section invalid length\n");
+		return IXGBE_ERR_PBA_SECTION;
+	}
+
+	/* check if pba_num buffer is big enough */
+	if (pba_num_size  < (((u32)length * 2) - 1)) {
+		DEBUGOUT("PBA string buffer too small\n");
+		return IXGBE_ERR_NO_SPACE;
+	}
+
+	/* trim pba length from start of string */
+	pba_ptr++;
+	length--;
+
+	for (offset = 0; offset < length; offset++) {
+		ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
+		if (ret_val) {
+			DEBUGOUT("NVM Read Error\n");
+			return ret_val;
+		}
+		pba_num[offset * 2] = (u8)(data >> 8);
+		pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
+	}
+	pba_num[offset * 2] = '\0';
+
+	return IXGBE_SUCCESS;
+}
+
+/**
+ *  ixgbe_read_pba_length_generic - Reads part number length from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @pba_num_size: part number string buffer length
+ *
+ *  Reads the part number length from the EEPROM.
+ *  Returns expected buffer size in pba_num_size
+ **/
+s32 ixgbe_read_pba_length_generic(struct ixgbe_hw *hw, u32 *pba_num_size)
+{
+	s32 ret_val;
+	u16 data;
+	u16 pba_ptr;
+	u16 length;
+
+	DEBUGFUNC("ixgbe_read_pba_length_generic");
+
+	if (pba_num_size == NULL) {
+		DEBUGOUT("PBA buffer size was null\n");
+		return IXGBE_ERR_INVALID_ARGUMENT;
+	}
+
+	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
+	if (ret_val) {
+		DEBUGOUT("NVM Read Error\n");
+		return ret_val;
+	}
+
+	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
+	if (ret_val) {
+		DEBUGOUT("NVM Read Error\n");
+		return ret_val;
+	}
+
+	 /* if data is not ptr guard the PBA must be in legacy format */
+	if (data != IXGBE_PBANUM_PTR_GUARD) {
+		*pba_num_size = 11;
+		return IXGBE_SUCCESS;
+	}
+
+	ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
+	if (ret_val) {
+		DEBUGOUT("NVM Read Error\n");
+		return ret_val;
+	}
+
+	if (length == 0xFFFF || length == 0) {
+		DEBUGOUT("NVM PBA number section invalid length\n");
+		return IXGBE_ERR_PBA_SECTION;
+	}
+
+	/*
+	 * Convert from length in u16 values to u8 chars, add 1 for NULL,
+	 * and subtract 2 because length field is included in length.
+	 */
+	*pba_num_size = ((u32)length * 2) - 1;
+
+	return IXGBE_SUCCESS;
+}
+
+/**
+ *  ixgbe_read_pba_num_generic - Reads part number from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @pba_num: stores the part number from the EEPROM
+ *
+ *  Reads the part number from the EEPROM.
+ **/
+s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
+{
+	s32 ret_val;
+	u16 data;
+
 	DEBUGFUNC("ixgbe_read_pba_num_generic");
 
 	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
 	if (ret_val) {
 		DEBUGOUT("NVM Read Error\n");
-		return (ret_val);
+		return ret_val;
+	} else if (data == IXGBE_PBANUM_PTR_GUARD) {
+		DEBUGOUT("NVM Not supported\n");
+		return IXGBE_NOT_IMPLEMENTED;
 	}
 	*pba_num = (u32)(data << 16);
 
@@ -328,24 +539,23 @@
 	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
 	if (ret_val) {
 		DEBUGOUT("NVM Read Error\n");
-		return (ret_val);
+		return ret_val;
 	}
 	*pba_num |= data;
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_get_mac_addr_generic - Generic get MAC address
- * @hw: pointer to hardware structure
- * @mac_addr: Adapter MAC address
+/**
+ *  ixgbe_get_mac_addr_generic - Generic get MAC address
+ *  @hw: pointer to hardware structure
+ *  @mac_addr: Adapter MAC address
  *
- * Reads the adapter's MAC address from first Receive Address Register (RAR0)
- * A reset of the adapter must be performed prior to calling this function
- * in order for the MAC address to have been loaded from the EEPROM into RAR0
- */
-s32
-ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
+ *  Reads the adapter's MAC address from first Receive Address Register (RAR0)
+ *  A reset of the adapter must be performed prior to calling this function
+ *  in order for the MAC address to have been loaded from the EEPROM into RAR0
+ **/
+s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
 {
 	u32 rar_high;
 	u32 rar_low;
@@ -362,17 +572,16 @@
 	for (i = 0; i < 2; i++)
 		mac_addr[i+4] = (u8)(rar_high >> (i*8));
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_get_bus_info_generic - Generic set PCI bus info
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_bus_info_generic - Generic set PCI bus info
+ *  @hw: pointer to hardware structure
  *
- * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
- */
-s32
-ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
+ *  Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
+ **/
+s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 	u16 link_status;
@@ -416,19 +625,17 @@
 
 	mac->ops.set_lan_id(hw);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-
-/*
- * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
- * @hw: pointer to the HW structure
+/**
+ *  ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
+ *  @hw: pointer to the HW structure
  *
- * Determines the LAN function id by reading memory-mapped registers
- * and swaps the port value if requested.
- */
-void
-ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
+ *  Determines the LAN function id by reading memory-mapped registers
+ *  and swaps the port value if requested.
+ **/
+void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
 {
 	struct ixgbe_bus_info *bus = &hw->bus;
 	u32 reg;
@@ -445,17 +652,16 @@
 		bus->func ^= 0x1;
 }
 
-/*
- * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
+ *  @hw: pointer to hardware structure
  *
- * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
- * disables transmit and receive units. The adapter_stopped flag is used by
- * the shared code and drivers to determine if the adapter is in a stopped
- * state and should not touch the hardware.
- */
-s32
-ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
+ *  Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
+ *  disables transmit and receive units. The adapter_stopped flag is used by
+ *  the shared code and drivers to determine if the adapter is in a stopped
+ *  state and should not touch the hardware.
+ **/
+s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
 {
 	u32 number_of_queues;
 	u32 reg_val;
@@ -467,7 +673,7 @@
 	 * Set the adapter_stopped flag so other driver functions stop touching
 	 * the hardware
 	 */
-	hw->adapter_stopped = true;
+	hw->adapter_stopped = TRUE;
 
 	/* Disable the receive unit */
 	reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
@@ -498,16 +704,15 @@
 	 */
 	(void) ixgbe_disable_pcie_master(hw);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_led_on_generic - Turns on the software controllable LEDs.
- * @hw: pointer to hardware structure
- * @index: led number to turn on
- */
-s32
-ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
+/**
+ *  ixgbe_led_on_generic - Turns on the software controllable LEDs.
+ *  @hw: pointer to hardware structure
+ *  @index: led number to turn on
+ **/
+s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
 {
 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 
@@ -519,16 +724,15 @@
 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 	IXGBE_WRITE_FLUSH(hw);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_led_off_generic - Turns off the software controllable LEDs.
- * @hw: pointer to hardware structure
- * @index: led number to turn off
- */
-s32
-ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
+/**
+ *  ixgbe_led_off_generic - Turns off the software controllable LEDs.
+ *  @hw: pointer to hardware structure
+ *  @index: led number to turn off
+ **/
+s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
 {
 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 
@@ -540,18 +744,17 @@
 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 	IXGBE_WRITE_FLUSH(hw);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_init_eeprom_params_generic - Initialize EEPROM params
+ *  @hw: pointer to hardware structure
  *
- * Initializes the EEPROM parameters ixgbe_eeprom_info within the
- * ixgbe_hw struct in order to set up EEPROM access.
- */
-s32
-ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
+ *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
+ *  ixgbe_hw struct in order to set up EEPROM access.
+ **/
+s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 	u32 eec;
@@ -561,10 +764,8 @@
 
 	if (eeprom->type == ixgbe_eeprom_uninitialized) {
 		eeprom->type = ixgbe_eeprom_none;
-		/*
-		 * Set default semaphore delay to 10ms which is a well
-		 * tested value
-		 */
+		/* Set default semaphore delay to 10ms which is a well
+		 * tested value */
 		eeprom->semaphore_delay = 10;
 
 		/*
@@ -580,9 +781,9 @@
 			 * change if a future EEPROM is not SPI.
 			 */
 			eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
-			    IXGBE_EEC_SIZE_SHIFT);
+			                    IXGBE_EEC_SIZE_SHIFT);
 			eeprom->word_size = 1 << (eeprom_size +
-			    IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT);
+			                     IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT);
 		}
 
 		if (eec & IXGBE_EEC_ADDR_SIZE)
@@ -590,24 +791,23 @@
 		else
 			eeprom->address_bits = 8;
 		DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
-		    "%d\n", eeprom->type, eeprom->word_size,
-		    eeprom->address_bits);
+		          "%d\n", eeprom->type, eeprom->word_size,
+		          eeprom->address_bits);
 	}
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be written to
- * @data: 16 bit word to be written to the EEPROM
+/**
+ *  ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
+ *  @hw: pointer to hardware structure
+ *  @offset: offset within the EEPROM to be written to
+ *  @data: 16 bit word to be written to the EEPROM
  *
- * If ixgbe_eeprom_update_checksum is not called after this function, the
- * EEPROM will most likely contain an invalid checksum.
- */
-s32
-ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
+ *  If ixgbe_eeprom_update_checksum is not called after this function, the
+ *  EEPROM will most likely contain an invalid checksum.
+ **/
+s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
 {
 	s32 status;
 	u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
@@ -636,7 +836,7 @@
 
 		/*  Send the WRITE ENABLE command (8 bit opcode )  */
 		ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
-		    IXGBE_EEPROM_OPCODE_BITS);
+		                            IXGBE_EEPROM_OPCODE_BITS);
 
 		ixgbe_standby_eeprom(hw);
 
@@ -649,9 +849,9 @@
 
 		/* Send the Write command (8-bit opcode + addr) */
 		ixgbe_shift_out_eeprom_bits(hw, write_opcode,
-		    IXGBE_EEPROM_OPCODE_BITS);
+		                            IXGBE_EEPROM_OPCODE_BITS);
 		ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
-		    hw->eeprom.address_bits);
+		                            hw->eeprom.address_bits);
 
 		/* Send the data */
 		data = (data >> 8) | (data << 8);
@@ -663,20 +863,19 @@
 	}
 
 out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
- * @hw: pointer to hardware structure
- * @offset: offset within the EEPROM to be read
- * @data: read 16 bit value from EEPROM
+/**
+ *  ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
+ *  @hw: pointer to hardware structure
+ *  @offset: offset within the EEPROM to be read
+ *  @data: read 16 bit value from EEPROM
  *
- * Reads 16 bit value from EEPROM through bit-bang method
- */
-s32
-ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
-	u16 *data)
+ *  Reads 16 bit value from EEPROM through bit-bang method
+ **/
+s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
+                                       u16 *data)
 {
 	s32 status;
 	u16 word_in;
@@ -713,9 +912,9 @@
 
 		/* Send the READ command (opcode + addr) */
 		ixgbe_shift_out_eeprom_bits(hw, read_opcode,
-		    IXGBE_EEPROM_OPCODE_BITS);
+		                            IXGBE_EEPROM_OPCODE_BITS);
 		ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
-		    hw->eeprom.address_bits);
+		                            hw->eeprom.address_bits);
 
 		/* Read the data. */
 		word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
@@ -726,19 +925,18 @@
 	}
 
 out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_read_eerd_generic - Read EEPROM word using EERD
- * @hw: pointer to hardware structure
- * @offset: offset of  word in the EEPROM to read
- * @data: word read from the EEPROM
+/**
+ *  ixgbe_read_eerd_generic - Read EEPROM word using EERD
+ *  @hw: pointer to hardware structure
+ *  @offset: offset of  word in the EEPROM to read
+ *  @data: word read from the EEPROM
  *
- * Reads a 16 bit word from the EEPROM using the EERD register.
- */
-s32
-ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
+ *  Reads a 16 bit word from the EEPROM using the EERD register.
+ **/
+s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
 {
 	u32 eerd;
 	s32 status;
@@ -753,7 +951,7 @@
 	}
 
 	eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
-	    IXGBE_EEPROM_RW_REG_START;
+	       IXGBE_EEPROM_RW_REG_START;
 
 	IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
 	status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
@@ -760,25 +958,67 @@
 
 	if (status == IXGBE_SUCCESS)
 		*data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
-		    IXGBE_EEPROM_RW_REG_DATA);
+		         IXGBE_EEPROM_RW_REG_DATA);
 	else
 		DEBUGOUT("Eeprom read timed out\n");
 
 out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
- * @hw: pointer to hardware structure
- * @ee_reg: EEPROM flag for polling
+/**
+ *  ixgbe_write_eewr_generic - Write EEPROM word using EEWR
+ *  @hw: pointer to hardware structure
+ *  @offset: offset of  word in the EEPROM to write
+ *  @data: word write to the EEPROM
  *
- * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
- * read or write is done respectively.
- */
-s32
-ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
+ *  Write a 16 bit word to the EEPROM using the EEWR register.
+ **/
+s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
 {
+	u32 eewr;
+	s32 status;
+
+	DEBUGFUNC("ixgbe_write_eewr_generic");
+
+	hw->eeprom.ops.init_params(hw);
+
+	if (offset >= hw->eeprom.word_size) {
+		status = IXGBE_ERR_EEPROM;
+		goto out;
+	}
+
+	eewr = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) |
+	       (data << IXGBE_EEPROM_RW_REG_DATA) | IXGBE_EEPROM_RW_REG_START;
+
+	status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
+	if (status != IXGBE_SUCCESS) {
+		DEBUGOUT("Eeprom write EEWR timed out\n");
+		goto out;
+	}
+
+	IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
+
+	status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
+	if (status != IXGBE_SUCCESS) {
+		DEBUGOUT("Eeprom write EEWR timed out\n");
+		goto out;
+	}
+
+out:
+	return status;
+}
+
+/**
+ *  ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
+ *  @hw: pointer to hardware structure
+ *  @ee_reg: EEPROM flag for polling
+ *
+ *  Polls the status bit (bit 1) of the EERD or EEWR to determine when the
+ *  read or write is done respectively.
+ **/
+s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
+{
 	u32 i;
 	u32 reg;
 	s32 status = IXGBE_ERR_EEPROM;
@@ -797,18 +1037,17 @@
 		}
 		usec_delay(5);
 	}
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
+ *  @hw: pointer to hardware structure
  *
- * Prepares EEPROM for access using bit-bang method. This function should
- * be called before issuing a command to the EEPROM.
- */
-static s32
-ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
+ *  Prepares EEPROM for access using bit-bang method. This function should
+ *  be called before issuing a command to the EEPROM.
+ **/
+static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 eec;
@@ -842,27 +1081,26 @@
 			ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 			status = IXGBE_ERR_EEPROM;
 		}
-	}
 
-	/* Setup EEPROM for Read/Write */
-	if (status == IXGBE_SUCCESS) {
-		/* Clear CS and SK */
-		eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
-		IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
-		IXGBE_WRITE_FLUSH(hw);
-		usec_delay(1);
+		/* Setup EEPROM for Read/Write */
+		if (status == IXGBE_SUCCESS) {
+			/* Clear CS and SK */
+			eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
+			IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
+			IXGBE_WRITE_FLUSH(hw);
+			usec_delay(1);
+		}
 	}
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_get_eeprom_semaphore - Get hardware semaphore
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_eeprom_semaphore - Get hardware semaphore
+ *  @hw: pointer to hardware structure
  *
- * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
- */
-static s32
-ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
+ *  Sets the hardware semaphores so EEPROM access can occur for bit-bang method
+ **/
+static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_ERR_EEPROM;
 	u32 timeout = 2000;
@@ -871,6 +1109,7 @@
 
 	DEBUGFUNC("ixgbe_get_eeprom_semaphore");
 
+
 	/* Get SMBI software semaphore between device drivers first */
 	for (i = 0; i < timeout; i++) {
 		/*
@@ -911,26 +1150,25 @@
 		 */
 		if (i >= timeout) {
 			DEBUGOUT("SWESMBI Software EEPROM semaphore "
-			    "not granted.\n");
+			         "not granted.\n");
 			ixgbe_release_eeprom_semaphore(hw);
 			status = IXGBE_ERR_EEPROM;
 		}
 	} else {
 		DEBUGOUT("Software semaphore SMBI between device drivers "
-		    "not granted.\n");
+		         "not granted.\n");
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_release_eeprom_semaphore - Release hardware semaphore
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_release_eeprom_semaphore - Release hardware semaphore
+ *  @hw: pointer to hardware structure
  *
- * This function clears hardware semaphore bits.
- */
-static void
-ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
+ *  This function clears hardware semaphore bits.
+ **/
+static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
 {
 	u32 swsm;
 
@@ -944,12 +1182,11 @@
 	IXGBE_WRITE_FLUSH(hw);
 }
 
-/*
- * ixgbe_ready_eeprom - Polls for EEPROM ready
- * @hw: pointer to hardware structure
- */
-static s32
-ixgbe_ready_eeprom(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_ready_eeprom - Polls for EEPROM ready
+ *  @hw: pointer to hardware structure
+ **/
+static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_SUCCESS;
 	u16 i;
@@ -965,7 +1202,7 @@
 	 */
 	for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
 		ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
-		    IXGBE_EEPROM_OPCODE_BITS);
+		                            IXGBE_EEPROM_OPCODE_BITS);
 		spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
 		if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
 			break;
@@ -983,15 +1220,14 @@
 		status = IXGBE_ERR_EEPROM;
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
- * @hw: pointer to hardware structure
- */
-static void
-ixgbe_standby_eeprom(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
+ *  @hw: pointer to hardware structure
+ **/
+static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
 {
 	u32 eec;
 
@@ -1010,15 +1246,14 @@
 	usec_delay(1);
 }
 
-/*
- * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
- * @hw: pointer to hardware structure
- * @data: data to send to the EEPROM
- * @count: number of bits to shift out
- */
-static void
-ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
-    u16 count)
+/**
+ *  ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
+ *  @hw: pointer to hardware structure
+ *  @data: data to send to the EEPROM
+ *  @count: number of bits to shift out
+ **/
+static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
+                                        u16 count)
 {
 	u32 eec;
 	u32 mask;
@@ -1068,12 +1303,11 @@
 	IXGBE_WRITE_FLUSH(hw);
 }
 
-/*
- * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
- * @hw: pointer to hardware structure
- */
-static u16
-ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
+/**
+ *  ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
+ *  @hw: pointer to hardware structure
+ **/
+static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
 {
 	u32 eec;
 	u32 i;
@@ -1105,16 +1339,15 @@
 		ixgbe_lower_eeprom_clk(hw, &eec);
 	}
 
-	return (data);
+	return data;
 }
 
-/*
- * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
- * @hw: pointer to hardware structure
- * @eec: EEC register's current value
- */
-static void
-ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
+/**
+ *  ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
+ *  @hw: pointer to hardware structure
+ *  @eec: EEC register's current value
+ **/
+static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
 {
 	DEBUGFUNC("ixgbe_raise_eeprom_clk");
 
@@ -1128,13 +1361,12 @@
 	usec_delay(1);
 }
 
-/*
- * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
- * @hw: pointer to hardware structure
- * @eecd: EECD's current value
- */
-static void
-ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
+/**
+ *  ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
+ *  @hw: pointer to hardware structure
+ *  @eecd: EECD's current value
+ **/
+static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
 {
 	DEBUGFUNC("ixgbe_lower_eeprom_clk");
 
@@ -1148,12 +1380,11 @@
 	usec_delay(1);
 }
 
-/*
- * ixgbe_release_eeprom - Release EEPROM, release semaphores
- * @hw: pointer to hardware structure
- */
-static void
-ixgbe_release_eeprom(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_release_eeprom - Release EEPROM, release semaphores
+ *  @hw: pointer to hardware structure
+ **/
+static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
 {
 	u32 eec;
 
@@ -1179,12 +1410,11 @@
 	msec_delay(hw->eeprom.semaphore_delay);
 }
 
-/*
- * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
- * @hw: pointer to hardware structure
- */
-u16
-ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
+ *  @hw: pointer to hardware structure
+ **/
+u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
 {
 	u16 i;
 	u16 j;
@@ -1223,20 +1453,19 @@
 
 	checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 
-	return (checksum);
+	return checksum;
 }
 
-/*
- * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
- * @hw: pointer to hardware structure
- * @checksum_val: calculated checksum
+/**
+ *  ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
+ *  @hw: pointer to hardware structure
+ *  @checksum_val: calculated checksum
  *
- * Performs checksum calculation and validates the EEPROM checksum.  If the
- * caller does not need checksum_val, the value can be NULL.
- */
-s32
-ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
-    u16 *checksum_val)
+ *  Performs checksum calculation and validates the EEPROM checksum.  If the
+ *  caller does not need checksum_val, the value can be NULL.
+ **/
+s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
+                                           u16 *checksum_val)
 {
 	s32 status;
 	u16 checksum;
@@ -1270,15 +1499,14 @@
 		DEBUGOUT("EEPROM read failed\n");
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
- * @hw: pointer to hardware structure
- */
-s32
-ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
+ *  @hw: pointer to hardware structure
+ **/
+s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
 {
 	s32 status;
 	u16 checksum;
@@ -1295,22 +1523,21 @@
 	if (status == IXGBE_SUCCESS) {
 		checksum = hw->eeprom.ops.calc_checksum(hw);
 		status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
-		    checksum);
+		                              checksum);
 	} else {
 		DEBUGOUT("EEPROM read failed\n");
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_validate_mac_addr - Validate MAC address
- * @mac_addr: pointer to MAC address.
+/**
+ *  ixgbe_validate_mac_addr - Validate MAC address
+ *  @mac_addr: pointer to MAC address.
  *
- * Tests a MAC address to ensure it is a valid Individual Address
- */
-s32
-ixgbe_validate_mac_addr(u8 *mac_addr)
+ *  Tests a MAC address to ensure it is a valid Individual Address
+ **/
+s32 ixgbe_validate_mac_addr(u8 *mac_addr)
 {
 	s32 status = IXGBE_SUCCESS;
 
@@ -1326,26 +1553,25 @@
 		status = IXGBE_ERR_INVALID_MAC_ADDR;
 	/* Reject the zero address */
 	} else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
-	    mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
+	           mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
 		DEBUGOUT("MAC address is all zeros\n");
 		status = IXGBE_ERR_INVALID_MAC_ADDR;
 	}
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_set_rar_generic - Set Rx address register
- * @hw: pointer to hardware structure
- * @index: Receive address register to write
- * @addr: Address to put into receive address register
- * @vmdq: VMDq "set" or "pool" index
- * @enable_addr: set flag that address is active
+/**
+ *  ixgbe_set_rar_generic - Set Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: Receive address register to write
+ *  @addr: Address to put into receive address register
+ *  @vmdq: VMDq "set" or "pool" index
+ *  @enable_addr: set flag that address is active
  *
- * Puts an ethernet address into a receive address register.
- */
-s32
-ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
-    u32 enable_addr)
+ *  Puts an ethernet address into a receive address register.
+ **/
+s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
+                          u32 enable_addr)
 {
 	u32 rar_low, rar_high;
 	u32 rar_entries = hw->mac.num_rar_entries;
@@ -1352,49 +1578,49 @@
 
 	DEBUGFUNC("ixgbe_set_rar_generic");
 
+	/* Make sure we are using a valid rar index range */
+	if (index >= rar_entries) {
+		DEBUGOUT1("RAR index %d is out of range.\n", index);
+		return IXGBE_ERR_INVALID_ARGUMENT;
+	}
+
 	/* setup VMDq pool selection before this RAR gets enabled */
 	hw->mac.ops.set_vmdq(hw, index, vmdq);
 
-	/* Make sure we are using a valid rar index range */
-	if (index < rar_entries) {
-		/*
-		 * HW expects these in little endian so we reverse the byte
-		 * order from network order (big endian) to little endian
-		 */
-		rar_low = ((u32)addr[0] |
-		    ((u32)addr[1] << 8) |
-		    ((u32)addr[2] << 16) |
-		    ((u32)addr[3] << 24));
-		/*
-		 * Some parts put the VMDq setting in the extra RAH bits,
-		 * so save everything except the lower 16 bits that hold part
-		 * of the address and the address valid bit.
-		 */
-		rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
-		rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
-		rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
+	/*
+	 * HW expects these in little endian so we reverse the byte
+	 * order from network order (big endian) to little endian
+	 */
+	rar_low = ((u32)addr[0] |
+	           ((u32)addr[1] << 8) |
+	           ((u32)addr[2] << 16) |
+	           ((u32)addr[3] << 24));
+	/*
+	 * Some parts put the VMDq setting in the extra RAH bits,
+	 * so save everything except the lower 16 bits that hold part
+	 * of the address and the address valid bit.
+	 */
+	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
+	rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
+	rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
 
-		if (enable_addr != 0)
-			rar_high |= IXGBE_RAH_AV;
+	if (enable_addr != 0)
+		rar_high |= IXGBE_RAH_AV;
 
-		IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
-		IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
-	} else {
-		DEBUGOUT1("RAR index %d is out of range.\n", index);
-	}
+	IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
+	IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_clear_rar_generic - Remove Rx address register
- * @hw: pointer to hardware structure
- * @index: Receive address register to write
+/**
+ *  ixgbe_clear_rar_generic - Remove Rx address register
+ *  @hw: pointer to hardware structure
+ *  @index: Receive address register to write
  *
- * Clears an ethernet address from a receive address register.
- */
-s32
-ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
+ *  Clears an ethernet address from a receive address register.
+ **/
+s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
 {
 	u32 rar_high;
 	u32 rar_entries = hw->mac.num_rar_entries;
@@ -1402,37 +1628,37 @@
 	DEBUGFUNC("ixgbe_clear_rar_generic");
 
 	/* Make sure we are using a valid rar index range */
-	if (index < rar_entries) {
-		/*
-		 * Some parts put the VMDq setting in the extra RAH bits,
-		 * so save everything except the lower 16 bits that hold part
-		 * of the address and the address valid bit.
-		 */
-		rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
-		rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
-
-		IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
-		IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
-	} else {
+	if (index >= rar_entries) {
 		DEBUGOUT1("RAR index %d is out of range.\n", index);
+		return IXGBE_ERR_INVALID_ARGUMENT;
 	}
 
+	/*
+	 * Some parts put the VMDq setting in the extra RAH bits,
+	 * so save everything except the lower 16 bits that hold part
+	 * of the address and the address valid bit.
+	 */
+	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
+	rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
+
+	IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
+	IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
+
 	/* clear VMDq pool/queue selection for this RAR */
 	hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_init_rx_addrs_generic - Initializes receive address filters.
+ *  @hw: pointer to hardware structure
  *
- * Places the MAC address in receive address register 0 and clears the rest
- * of the receive address registers. Clears the multicast table. Assumes
- * the receiver is in reset when the routine is called.
- */
-s32
-ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
+ *  Places the MAC address in receive address register 0 and clears the rest
+ *  of the receive address registers. Clears the multicast table. Assumes
+ *  the receiver is in reset when the routine is called.
+ **/
+s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
 {
 	u32 i;
 	u32 rar_entries = hw->mac.num_rar_entries;
@@ -1450,20 +1676,23 @@
 		hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
 
 		DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
-		    hw->mac.addr[0], hw->mac.addr[1],
-		    hw->mac.addr[2]);
+		          hw->mac.addr[0], hw->mac.addr[1],
+		          hw->mac.addr[2]);
 		DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
-		    hw->mac.addr[4], hw->mac.addr[5]);
+		          hw->mac.addr[4], hw->mac.addr[5]);
 	} else {
 		/* Setup the receive address. */
 		DEBUGOUT("Overriding MAC Address in RAR[0]\n");
 		DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
-		    hw->mac.addr[0], hw->mac.addr[1],
-		    hw->mac.addr[2]);
+		          hw->mac.addr[0], hw->mac.addr[1],
+		          hw->mac.addr[2]);
 		DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
-		    hw->mac.addr[4], hw->mac.addr[5]);
+		          hw->mac.addr[4], hw->mac.addr[5]);
 
 		hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
+
+		/* clear VMDq pool/queue selection for RAR 0 */
+		hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
 	}
 	hw->addr_ctrl.overflow_promisc = 0;
 
@@ -1486,19 +1715,17 @@
 
 	(void) ixgbe_init_uta_tables(hw);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-
-/*
- * ixgbe_add_uc_addr - Adds a secondary unicast address.
- * @hw: pointer to hardware structure
- * @addr: new address
+/**
+ *  ixgbe_add_uc_addr - Adds a secondary unicast address.
+ *  @hw: pointer to hardware structure
+ *  @addr: new address
  *
- * Adds it to unused receive address register or goes into promiscuous mode.
- */
-void
-ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
+ *  Adds it to unused receive address register or goes into promiscuous mode.
+ **/
+void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
 {
 	u32 rar_entries = hw->mac.num_rar_entries;
 	u32 rar;
@@ -1506,7 +1733,7 @@
 	DEBUGFUNC("ixgbe_add_uc_addr");
 
 	DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
-	    addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+	          addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
 
 	/*
 	 * Place this address in the RAR if there is room,
@@ -1524,23 +1751,22 @@
 	DEBUGOUT("ixgbe_add_uc_addr Complete\n");
 }
 
-/*
- * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
- * @hw: pointer to hardware structure
- * @addr_list: the list of new addresses
- * @addr_count: number of addresses
- * @next: iterator function to walk the address list
+/**
+ *  ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
+ *  @hw: pointer to hardware structure
+ *  @addr_list: the list of new addresses
+ *  @addr_count: number of addresses
+ *  @next: iterator function to walk the address list
  *
- * The given list replaces any existing list.  Clears the secondary addrs from
- * receive address registers.  Uses unused receive address registers for the
- * first secondary addresses, and falls back to promiscuous mode as needed.
+ *  The given list replaces any existing list.  Clears the secondary addrs from
+ *  receive address registers.  Uses unused receive address registers for the
+ *  first secondary addresses, and falls back to promiscuous mode as needed.
  *
- * Drivers using secondary unicast addresses must set user_set_promisc when
- * manually putting the device into promiscuous mode.
- */
-s32
-ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
-    u32 addr_count, ixgbe_mc_addr_itr next)
+ *  Drivers using secondary unicast addresses must set user_set_promisc when
+ *  manually putting the device into promiscuous mode.
+ **/
+s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
+                                      u32 addr_count, ixgbe_mc_addr_itr next)
 {
 	u8 *addr;
 	u32 i;
@@ -1560,10 +1786,10 @@
 	hw->addr_ctrl.overflow_promisc = 0;
 
 	/* Zero out the other receive addresses */
-	DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use + 1);
+	DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
 	for (i = 0; i < uc_addr_in_use; i++) {
-		IXGBE_WRITE_REG(hw, IXGBE_RAL(i + 1), 0);
-		IXGBE_WRITE_REG(hw, IXGBE_RAH(i + 1), 0);
+		IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
+		IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
 	}
 
 	/* Add the new addresses */
@@ -1592,23 +1818,22 @@
 	}
 
 	DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_mta_vector - Determines bit-vector in multicast table to set
- * @hw: pointer to hardware structure
- * @mc_addr: the multicast address
+/**
+ *  ixgbe_mta_vector - Determines bit-vector in multicast table to set
+ *  @hw: pointer to hardware structure
+ *  @mc_addr: the multicast address
  *
- * Extracts the 12 bits, from a multicast address, to determine which
- * bit-vector to set in the multicast table. The hardware uses 12 bits, from
- * incoming rx multicast addresses, to determine the bit-vector to check in
- * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
- * by the MO field of the MCSTCTRL. The MO field is set during initialization
- * to mc_filter_type.
- */
-static s32
-ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
+ *  Extracts the 12 bits, from a multicast address, to determine which
+ *  bit-vector to set in the multicast table. The hardware uses 12 bits, from
+ *  incoming rx multicast addresses, to determine the bit-vector to check in
+ *  the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
+ *  by the MO field of the MCSTCTRL. The MO field is set during initialization
+ *  to mc_filter_type.
+ **/
+static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
 {
 	u32 vector = 0;
 
@@ -1635,18 +1860,17 @@
 
 	/* vector can only be 12-bits or boundary will be exceeded */
 	vector &= 0xFFF;
-	return (vector);
+	return vector;
 }
 
-/*
- * ixgbe_set_mta - Set bit-vector in multicast table
- * @hw: pointer to hardware structure
- * @hash_value: Multicast address hash value
+/**
+ *  ixgbe_set_mta - Set bit-vector in multicast table
+ *  @hw: pointer to hardware structure
+ *  @hash_value: Multicast address hash value
  *
- * Sets the bit-vector in the multicast table.
- */
-void
-ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
+ *  Sets the bit-vector in the multicast table.
+ **/
+void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
 {
 	u32 vector;
 	u32 vector_bit;
@@ -1673,21 +1897,20 @@
 	hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
 }
 
-/*
- * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
- * @hw: pointer to hardware structure
- * @mc_addr_list: the list of new multicast addresses
- * @mc_addr_count: number of addresses
- * @next: iterator function to walk the multicast address list
+/**
+ *  ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
+ *  @hw: pointer to hardware structure
+ *  @mc_addr_list: the list of new multicast addresses
+ *  @mc_addr_count: number of addresses
+ *  @next: iterator function to walk the multicast address list
  *
- * The given list replaces any existing list. Clears the MC addrs from receive
- * address registers and the multicast table. Uses unused receive address
- * registers for the first multicast addresses, and hashes the rest into the
- * multicast table.
- */
-s32
-ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
-    u32 mc_addr_count, ixgbe_mc_addr_itr next)
+ *  The given list replaces any existing list. Clears the MC addrs from receive
+ *  address registers and the multicast table. Uses unused receive address
+ *  registers for the first multicast addresses, and hashes the rest into the
+ *  multicast table.
+ **/
+s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
+                                      u32 mc_addr_count, ixgbe_mc_addr_itr next)
 {
 	u32 i;
 	u32 vmdq;
@@ -1703,7 +1926,7 @@
 
 	/* Clear mta_shadow */
 	DEBUGOUT(" Clearing MTA\n");
-	(void) memset(&hw->mac.mta_shadow, 0, sizeof (hw->mac.mta_shadow));
+	(void) memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
 
 	/* Update mta_shadow */
 	for (i = 0; i < mc_addr_count; i++) {
@@ -1714,24 +1937,23 @@
 	/* Enable mta */
 	for (i = 0; i < hw->mac.mcft_size; i++)
 		IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
-		    hw->mac.mta_shadow[i]);
+				      hw->mac.mta_shadow[i]);
 
 	if (hw->addr_ctrl.mta_in_use > 0)
 		IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
-		    IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
+		                IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
 
 	DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_enable_mc_generic - Enable multicast address in RAR
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_enable_mc_generic - Enable multicast address in RAR
+ *  @hw: pointer to hardware structure
  *
- * Enables multicast address in RAR and the use of the multicast hash table.
- */
-s32
-ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
+ *  Enables multicast address in RAR and the use of the multicast hash table.
+ **/
+s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
 
@@ -1739,19 +1961,18 @@
 
 	if (a->mta_in_use > 0)
 		IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
-		    hw->mac.mc_filter_type);
+		                hw->mac.mc_filter_type);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_disable_mc_generic - Disable multicast address in RAR
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_disable_mc_generic - Disable multicast address in RAR
+ *  @hw: pointer to hardware structure
  *
- * Disables multicast address in RAR and the use of the multicast hash table.
- */
-s32
-ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
+ *  Disables multicast address in RAR and the use of the multicast hash table.
+ **/
+s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
 
@@ -1760,23 +1981,23 @@
 	if (a->mta_in_use > 0)
 		IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_fc_enable_generic - Enable flow control
- * @hw: pointer to hardware structure
- * @packetbuf_num: packet buffer number (0-7)
+/**
+ *  ixgbe_fc_enable_generic - Enable flow control
+ *  @hw: pointer to hardware structure
+ *  @packetbuf_num: packet buffer number (0-7)
  *
- * Enable flow control according to the current settings.
- */
-s32
-ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
+ *  Enable flow control according to the current settings.
+ **/
+s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
 {
 	s32 ret_val = IXGBE_SUCCESS;
 	u32 mflcn_reg, fccfg_reg;
 	u32 reg;
 	u32 rx_pba_size;
+	u32 fcrtl, fcrth;
 
 	DEBUGFUNC("ixgbe_fc_enable_generic");
 
@@ -1843,40 +2064,21 @@
 	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
 	IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
 
-	reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
-	/* Thresholds are different for link flow control when in DCB mode */
-	if (reg & IXGBE_MTQC_RT_ENA) {
-		rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
+	rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
+	rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
 
-		/* Always disable XON for LFC when in DCB mode */
-		reg = (rx_pba_size >> 5) & 0xFFE0;
-		IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
+	fcrth = (rx_pba_size - hw->fc.high_water) << 10;
+	fcrtl = (rx_pba_size - hw->fc.low_water) << 10;
 
-		reg = (rx_pba_size >> 2) & 0xFFE0;
-		if (hw->fc.current_mode & ixgbe_fc_tx_pause)
-			reg |= IXGBE_FCRTH_FCEN;
-		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
-	} else {
-		/*
-		 * Set up and enable Rx high/low water mark thresholds,
-		 * enable XON.
-		 */
-		if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
-			if (hw->fc.send_xon) {
-				IXGBE_WRITE_REG(hw,
-				    IXGBE_FCRTL_82599(packetbuf_num),
-				    (hw->fc.low_water | IXGBE_FCRTL_XONE));
-			} else {
-				IXGBE_WRITE_REG(hw,
-				    IXGBE_FCRTL_82599(packetbuf_num),
-				    hw->fc.low_water);
-			}
-
-			IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
-			    (hw->fc.high_water | IXGBE_FCRTH_FCEN));
-		}
+	if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
+		fcrth |= IXGBE_FCRTH_FCEN;
+		if (hw->fc.send_xon)
+			fcrtl |= IXGBE_FCRTL_XONE;
 	}
 
+	IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
+	IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
+
 	/* Configure pause time (2 TCs per register) */
 	reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
 	if ((packetbuf_num & 1) == 0)
@@ -1888,18 +2090,17 @@
 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
 
 out:
-	return (ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_fc_autoneg - Configure flow control
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_fc_autoneg - Configure flow control
+ *  @hw: pointer to hardware structure
  *
- * Compares our advertised flow control capabilities to those advertised by
- * our link partner, and determines the proper flow control mode to use.
- */
-s32
-ixgbe_fc_autoneg(struct ixgbe_hw *hw)
+ *  Compares our advertised flow control capabilities to those advertised by
+ *  our link partner, and determines the proper flow control mode to use.
+ **/
+s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
 {
 	s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
 	ixgbe_link_speed speed;
@@ -1917,9 +2118,9 @@
 	 * - link is not up.
 	 *
 	 * Since we're being called from an LSC, link is already known to be up.
-	 * So use link_up_wait_to_complete=false.
+	 * So use link_up_wait_to_complete=FALSE.
 	 */
-	hw->mac.ops.check_link(hw, &speed, &link_up, false);
+	hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
 	if (!link_up) {
 		ret_val = IXGBE_ERR_FLOW_CONTROL;
 		goto out;
@@ -1949,24 +2150,23 @@
 
 out:
 	if (ret_val == IXGBE_SUCCESS) {
-		hw->fc.fc_was_autonegged = true;
+		hw->fc.fc_was_autonegged = TRUE;
 	} else {
-		hw->fc.fc_was_autonegged = false;
+		hw->fc.fc_was_autonegged = FALSE;
 		hw->fc.current_mode = hw->fc.requested_mode;
 	}
-	return (ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
- * @hw: pointer to hardware structure
- * @speed:
- * @link_up
+/**
+ *  ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
+ *  @hw: pointer to hardware structure
+ *  @speed:
+ *  @link_up
  *
- * Enable flow control according on 1 gig fiber.
- */
-static s32
-ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
+ *  Enable flow control according on 1 gig fiber.
+ **/
+static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
 {
 	u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
 	s32 ret_val;
@@ -1987,24 +2187,23 @@
 	pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
 	pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
 
-	ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
-	    pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
-	    IXGBE_PCS1GANA_ASM_PAUSE,
-	    IXGBE_PCS1GANA_SYM_PAUSE,
-	    IXGBE_PCS1GANA_ASM_PAUSE);
+	ret_val =  ixgbe_negotiate_fc(hw, pcs_anadv_reg,
+			       pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
+			       IXGBE_PCS1GANA_ASM_PAUSE,
+			       IXGBE_PCS1GANA_SYM_PAUSE,
+			       IXGBE_PCS1GANA_ASM_PAUSE);
 
 out:
-	return (ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
+ *  @hw: pointer to hardware structure
  *
- * Enable flow control according to IEEE clause 37.
- */
-static s32
-ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
+ *  Enable flow control according to IEEE clause 37.
+ **/
+static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
 {
 	u32 links2, anlp1_reg, autoc_reg, links;
 	s32 ret_val;
@@ -2016,7 +2215,7 @@
 	 */
 	links = IXGBE_READ_REG(hw, IXGBE_LINKS);
 	if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
-		hw->fc.fc_was_autonegged = false;
+		hw->fc.fc_was_autonegged = FALSE;
 		hw->fc.current_mode = hw->fc.requested_mode;
 		ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
 		goto out;
@@ -2025,7 +2224,7 @@
 	if (hw->mac.type == ixgbe_mac_82599EB) {
 		links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
 		if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
-			hw->fc.fc_was_autonegged = false;
+			hw->fc.fc_was_autonegged = FALSE;
 			hw->fc.current_mode = hw->fc.requested_mode;
 			ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
 			goto out;
@@ -2039,55 +2238,55 @@
 	anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
 
 	ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
-	    anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
-	    IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
+		anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
+		IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
 
 out:
-	return (ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
+ *  @hw: pointer to hardware structure
  *
- * Enable flow control according to IEEE clause 37.
- */
-static s32
-ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
+ *  Enable flow control according to IEEE clause 37.
+ **/
+static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
 {
 	u16 technology_ability_reg = 0;
 	u16 lp_technology_ability_reg = 0;
 
 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
-	    IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &technology_ability_reg);
+			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+			     &technology_ability_reg);
 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
-	    IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &lp_technology_ability_reg);
+			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+			     &lp_technology_ability_reg);
 
-	return (ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
-	    (u32)lp_technology_ability_reg,
-	    IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
-	    IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE));
+	return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
+				  (u32)lp_technology_ability_reg,
+				  IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
+				  IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
 }
 
-/*
- * ixgbe_negotiate_fc - Negotiate flow control
- * @hw: pointer to hardware structure
- * @adv_reg: flow control advertised settings
- * @lp_reg: link partner's flow control settings
- * @adv_sym: symmetric pause bit in advertisement
- * @adv_asm: asymmetric pause bit in advertisement
- * @lp_sym: symmetric pause bit in link partner advertisement
- * @lp_asm: asymmetric pause bit in link partner advertisement
+/**
+ *  ixgbe_negotiate_fc - Negotiate flow control
+ *  @hw: pointer to hardware structure
+ *  @adv_reg: flow control advertised settings
+ *  @lp_reg: link partner's flow control settings
+ *  @adv_sym: symmetric pause bit in advertisement
+ *  @adv_asm: asymmetric pause bit in advertisement
+ *  @lp_sym: symmetric pause bit in link partner advertisement
+ *  @lp_asm: asymmetric pause bit in link partner advertisement
  *
- * Find the intersection between advertised settings and link partner's
- * advertised settings
- */
-static s32
-ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
-    u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
+ *  Find the intersection between advertised settings and link partner's
+ *  advertised settings
+ **/
+static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
+			      u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
 {
-	if ((!(adv_reg)) || (!(lp_reg)))
-		return (IXGBE_ERR_FC_NOT_NEGOTIATED);
+	if ((!(adv_reg)) ||  (!(lp_reg)))
+		return IXGBE_ERR_FC_NOT_NEGOTIATED;
 
 	if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
 		/*
@@ -2105,11 +2304,11 @@
 			DEBUGOUT("Flow Control=RX PAUSE frames only\n");
 		}
 	} else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
-	    (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
+		   (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
 		hw->fc.current_mode = ixgbe_fc_tx_pause;
 		DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
 	} else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
-	    !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
+		   !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
 		hw->fc.current_mode = ixgbe_fc_rx_pause;
 		DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
 	} else {
@@ -2116,17 +2315,16 @@
 		hw->fc.current_mode = ixgbe_fc_none;
 		DEBUGOUT("Flow Control = NONE.\n");
 	}
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_setup_fc - Set up flow control
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_setup_fc - Set up flow control
+ *  @hw: pointer to hardware structure
  *
- * Called at init time to set up flow control.
- */
-s32
-ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
+ *  Called at init time to set up flow control.
+ **/
+s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
 {
 	s32 ret_val = IXGBE_SUCCESS;
 	u32 reg = 0, reg_bp = 0;
@@ -2137,7 +2335,7 @@
 	/* Validate the packetbuf configuration */
 	if (packetbuf_num < 0 || packetbuf_num > 7) {
 		DEBUGOUT1("Invalid packet buffer number [%d], expected range is"
-		    " 0-7\n", packetbuf_num);
+		          " 0-7\n", packetbuf_num);
 		ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 		goto out;
 	}
@@ -2174,6 +2372,7 @@
 	 * HW will be able to do fc autoneg once the cable is plugged in.  If
 	 * we link at 10G, the 1G advertisement is harmless and vice versa.
 	 */
+
 	switch (hw->phy.media_type) {
 	case ixgbe_media_type_fiber:
 	case ixgbe_media_type_backplane:
@@ -2183,7 +2382,7 @@
 
 	case ixgbe_media_type_copper:
 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg_cu);
+					IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg_cu);
 		break;
 
 	default:
@@ -2206,7 +2405,7 @@
 		reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
 		if (hw->phy.media_type == ixgbe_media_type_backplane)
 			reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
-			    IXGBE_AUTOC_ASM_PAUSE);
+				    IXGBE_AUTOC_ASM_PAUSE);
 		else if (hw->phy.media_type == ixgbe_media_type_copper)
 			reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
 		break;
@@ -2222,7 +2421,7 @@
 		reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
 		if (hw->phy.media_type == ixgbe_media_type_backplane)
 			reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
-			    IXGBE_AUTOC_ASM_PAUSE);
+				   IXGBE_AUTOC_ASM_PAUSE);
 		else if (hw->phy.media_type == ixgbe_media_type_copper)
 			reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
 		break;
@@ -2246,7 +2445,7 @@
 		reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
 		if (hw->phy.media_type == ixgbe_media_type_backplane)
 			reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
-			    IXGBE_AUTOC_ASM_PAUSE);
+				   IXGBE_AUTOC_ASM_PAUSE);
 		else if (hw->phy.media_type == ixgbe_media_type_copper)
 			reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
 		break;
@@ -2256,6 +2455,10 @@
 		goto out;
 	}
 
+	/*
+	 * Enable auto-negotiation between the MAC & PHY;
+	 * the MAC will advertise clause 37 flow control.
+	 */
 	IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
 	reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
 
@@ -2267,35 +2470,34 @@
 	DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
 
 	/*
-	 * AUTOC restart handles negotiation of 1G and 10G. There is
-	 * no need to set the PCS1GCTL register.
+	 * AUTOC restart handles negotiation of 1G and 10G on backplane
+	 * and copper. There is no need to set the PCS1GCTL register.
+	 *
 	 */
 	if (hw->phy.media_type == ixgbe_media_type_backplane) {
 		reg_bp |= IXGBE_AUTOC_AN_RESTART;
 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
 	} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
-	    (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
+		    (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
 		hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
+				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
 	}
 
 	DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
-
 out:
-	return (ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_disable_pcie_master - Disable PCI-express master access
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_disable_pcie_master - Disable PCI-express master access
+ *  @hw: pointer to hardware structure
  *
- * Disables PCI-Express master access and verifies there are no pending
- * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
- * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
- * is returned signifying master requests disabled.
- */
-s32
-ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
+ *  Disables PCI-Express master access and verifies there are no pending
+ *  requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
+ *  bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
+ *  is returned signifying master requests disabled.
+ **/
+s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
 {
 	u32 i;
 	u32 reg_val;
@@ -2324,7 +2526,7 @@
 
 	for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
 		if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
-			goto out;
+			goto check_device_status;
 		usec_delay(100);
 	}
 
@@ -2332,15 +2534,13 @@
 	status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 
 	/*
-	 * The GIO Master Disable bit didn't clear.  There are multiple reasons
-	 * for this listed in the datasheet 5.2.5.3.2 Master Disable, and they
-	 * all require a double reset to recover from.  Before proceeding, we
-	 * first wait a little more to try to ensure that, at a minimum, the
-	 * PCIe block has no transactions pending.
+	 * Before proceeding, make sure that the PCIe block does not have
+	 * transactions pending.
 	 */
+check_device_status:
 	for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
 		if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
-		    IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
+			IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
 			break;
 		usec_delay(100);
 	}
@@ -2347,6 +2547,8 @@
 
 	if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
 		DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
+	else
+		goto out;
 
 	/*
 	 * Two consecutive resets are required via CTRL.RST per datasheet
@@ -2356,22 +2558,22 @@
 	 * remaining completions from the PCIe bus to trickle in, and then reset
 	 * again to clear out any effects they may have had on our device.
 	 */
-	hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
+	 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 
 out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
- * @hw: pointer to hardware structure
- * @mask: Mask to specify which semaphore to acquire
+
+/**
+ *  ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
+ *  @hw: pointer to hardware structure
+ *  @mask: Mask to specify which semaphore to acquire
  *
- * Acquires the SWFW semaphore thought the GSSR register for the specified
- * function (CSR, PHY0, PHY1, EEPROM, Flash)
- */
-s32
-ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
+ *  Acquires the SWFW semaphore thought the GSSR register for the specified
+ *  function (CSR, PHY0, PHY1, EEPROM, Flash)
+ **/
+s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
 {
 	u32 gssr;
 	u32 swmask = mask;
@@ -2386,7 +2588,7 @@
 		 * SW_FW_SYNC/GSSR bits (not just EEPROM)
 		 */
 		if (ixgbe_get_eeprom_semaphore(hw))
-			return (IXGBE_ERR_SWFW_SYNC);
+			return IXGBE_ERR_SWFW_SYNC;
 
 		gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
 		if (!(gssr & (fwmask | swmask)))
@@ -2403,7 +2605,7 @@
 
 	if (!timeout) {
 		DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
-		return (IXGBE_ERR_SWFW_SYNC);
+		return IXGBE_ERR_SWFW_SYNC;
 	}
 
 	gssr |= swmask;
@@ -2410,19 +2612,18 @@
 	IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
 
 	ixgbe_release_eeprom_semaphore(hw);
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_release_swfw_sync - Release SWFW semaphore
- * @hw: pointer to hardware structure
- * @mask: Mask to specify which semaphore to release
+/**
+ *  ixgbe_release_swfw_sync - Release SWFW semaphore
+ *  @hw: pointer to hardware structure
+ *  @mask: Mask to specify which semaphore to release
  *
- * Releases the SWFW semaphore thought the GSSR register for the specified
- * function (CSR, PHY0, PHY1, EEPROM, Flash)
- */
-void
-ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
+ *  Releases the SWFW semaphore thought the GSSR register for the specified
+ *  function (CSR, PHY0, PHY1, EEPROM, Flash)
+ **/
+void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
 {
 	u32 gssr;
 	u32 swmask = mask;
@@ -2438,30 +2639,28 @@
 	ixgbe_release_eeprom_semaphore(hw);
 }
 
-/*
- * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
- * @hw: pointer to hardware structure
- * @regval: register value to write to RXCTRL
+/**
+ *  ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
+ *  @hw: pointer to hardware structure
+ *  @regval: register value to write to RXCTRL
  *
- * Enables the Rx DMA unit
- */
-s32
-ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
+ *  Enables the Rx DMA unit
+ **/
+s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
 {
 	DEBUGFUNC("ixgbe_enable_rx_dma_generic");
 
 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_blink_led_start_generic - Blink LED based on index.
- * @hw: pointer to hardware structure
- * @index: led number to blink
- */
-s32
-ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
+/**
+ *  ixgbe_blink_led_start_generic - Blink LED based on index.
+ *  @hw: pointer to hardware structure
+ *  @index: led number to blink
+ **/
+s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
 {
 	ixgbe_link_speed speed = 0;
 	bool link_up = 0;
@@ -2474,7 +2673,7 @@
 	 * Link must be up to auto-blink the LEDs;
 	 * Force it if link is down.
 	 */
-	hw->mac.ops.check_link(hw, &speed, &link_up, false);
+	hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
 
 	if (!link_up) {
 		autoc_reg |= IXGBE_AUTOC_AN_RESTART;
@@ -2488,16 +2687,15 @@
 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 	IXGBE_WRITE_FLUSH(hw);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
- * @hw: pointer to hardware structure
- * @index: led number to stop blinking
- */
-s32
-ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
+/**
+ *  ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
+ *  @hw: pointer to hardware structure
+ *  @index: led number to stop blinking
+ **/
+s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
 {
 	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
@@ -2504,6 +2702,7 @@
 
 	DEBUGFUNC("ixgbe_blink_led_stop_generic");
 
+
 	autoc_reg &= ~IXGBE_AUTOC_FLU;
 	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
@@ -2514,20 +2713,20 @@
 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 	IXGBE_WRITE_FLUSH(hw);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
- * @hw: pointer to hardware structure
- * @san_mac_offset: SAN MAC address offset
+/**
+ *  ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
+ *  @hw: pointer to hardware structure
+ *  @san_mac_offset: SAN MAC address offset
  *
- * This function will read the EEPROM location for the SAN MAC address
- * pointer, and returns the value at that location.  This is used in both
- * get and set mac_addr routines.
- */
-static s32
-ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, u16 *san_mac_offset)
+ *  This function will read the EEPROM location for the SAN MAC address
+ *  pointer, and returns the value at that location.  This is used in both
+ *  get and set mac_addr routines.
+ **/
+static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
+                                        u16 *san_mac_offset)
 {
 	DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
 
@@ -2537,21 +2736,20 @@
 	 */
 	hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
- * @hw: pointer to hardware structure
- * @san_mac_addr: SAN MAC address
+/**
+ *  ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
+ *  @hw: pointer to hardware structure
+ *  @san_mac_addr: SAN MAC address
  *
- * Reads the SAN MAC address from the EEPROM, if it's available.  This is
- * per-port, so set_lan_id() must be called before reading the addresses.
- * set_lan_id() is called by identify_sfp(), but this cannot be relied
- * upon for non-SFP connections, so we must call it here.
- */
-s32
-ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
+ *  Reads the SAN MAC address from the EEPROM, if it's available.  This is
+ *  per-port, so set_lan_id() must be called before reading the addresses.
+ *  set_lan_id() is called by identify_sfp(), but this cannot be relied
+ *  upon for non-SFP connections, so we must call it here.
+ **/
+s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
 {
 	u16 san_mac_data, san_mac_offset;
 	u8 i;
@@ -2579,7 +2777,7 @@
 	hw->mac.ops.set_lan_id(hw);
 	/* apply the port offset to the address offset */
 	(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
-	    (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
+	                 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
 	for (i = 0; i < 3; i++) {
 		hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
 		san_mac_addr[i * 2] = (u8)(san_mac_data);
@@ -2588,18 +2786,17 @@
 	}
 
 san_mac_addr_out:
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
- * @hw: pointer to hardware structure
- * @san_mac_addr: SAN MAC address
+/**
+ *  ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
+ *  @hw: pointer to hardware structure
+ *  @san_mac_addr: SAN MAC address
  *
- * Write a SAN MAC address to the EEPROM.
- */
-s32
-ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
+ *  Write a SAN MAC address to the EEPROM.
+ **/
+s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
 {
 	s32 status = IXGBE_SUCCESS;
 	u16 san_mac_data, san_mac_offset;
@@ -2619,7 +2816,7 @@
 	hw->mac.ops.set_lan_id(hw);
 	/* Apply the port offset to the address offset */
 	(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
-	    (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
+	                 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
 
 	for (i = 0; i < 3; i++) {
 		san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
@@ -2629,18 +2826,17 @@
 	}
 
 san_mac_addr_out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
+ *  @hw: pointer to hardware structure
  *
- * Read PCIe configuration space, and get the MSI-X vector count from
- * the capabilities table.
- */
-u32
-ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
+ *  Read PCIe configuration space, and get the MSI-X vector count from
+ *  the capabilities table.
+ **/
+u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
 {
 	u32 msix_count = 64;
 
@@ -2647,30 +2843,27 @@
 	DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
 	if (hw->mac.msix_vectors_from_pcie) {
 		msix_count = IXGBE_READ_PCIE_WORD(hw,
-		    IXGBE_PCIE_MSIX_82599_CAPS);
+		                                  IXGBE_PCIE_MSIX_82599_CAPS);
 		msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
 
-		/*
-		 * MSI-X count is zero-based in HW, so increment to give
-		 * proper value.
-		 */
+		/* MSI-X count is zero-based in HW, so increment to give
+		 * proper value */
 		msix_count++;
 	}
 
-	return (msix_count);
+	return msix_count;
 }
 
-/*
- * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
- * @hw: pointer to hardware structure
- * @addr: Address to put into receive address register
- * @vmdq: VMDq pool to assign
+/**
+ *  ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
+ *  @hw: pointer to hardware structure
+ *  @addr: Address to put into receive address register
+ *  @vmdq: VMDq pool to assign
  *
- * Puts an ethernet address into a receive address register, or
- * finds the rar that it is aleady in; adds to the pool list
- */
-s32
-ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
+ *  Puts an ethernet address into a receive address register, or
+ *  finds the rar that it is aleady in; adds to the pool list
+ **/
+s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
 {
 	static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
 	u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
@@ -2682,8 +2875,8 @@
 
 	/* swap bytes for HW little endian */
 	addr_low  = addr[0] | (addr[1] << 8)
-	    | (addr[2] << 16)
-	    | (addr[3] << 24);
+			    | (addr[2] << 16)
+			    | (addr[3] << 24);
 	addr_high = addr[4] | (addr[5] << 8);
 
 	/*
@@ -2695,8 +2888,8 @@
 	for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
 		rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 
-		if (((IXGBE_RAH_AV & rar_high) == 0) &&
-		    first_empty_rar == NO_EMPTY_RAR_FOUND) {
+		if (((IXGBE_RAH_AV & rar_high) == 0)
+		    && first_empty_rar == NO_EMPTY_RAR_FOUND) {
 			first_empty_rar = rar;
 		} else if ((rar_high & 0xFFFF) == addr_high) {
 			rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
@@ -2717,7 +2910,7 @@
 		(void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
 		hw->mac.rar_highwater++;
 	} else if (rar >= hw->mac.num_rar_entries) {
-		return (IXGBE_ERR_INVALID_MAC_ADDR);
+		return IXGBE_ERR_INVALID_MAC_ADDR;
 	}
 
 	/*
@@ -2727,17 +2920,16 @@
 	if (rar == 0)
 		(void) ixgbe_clear_vmdq(hw, rar, 0);
 
-	return (rar);
+	return rar;
 }
 
-/*
- * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
- * @hw: pointer to hardware struct
- * @rar: receive address register index to disassociate
- * @vmdq: VMDq pool index to remove from the rar
- */
-s32
-ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
+/**
+ *  ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
+ *  @hw: pointer to hardware struct
+ *  @rar: receive address register index to disassociate
+ *  @vmdq: VMDq pool index to remove from the rar
+ **/
+s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 {
 	u32 mpsar_lo, mpsar_hi;
 	u32 rar_entries = hw->mac.num_rar_entries;
@@ -2744,49 +2936,49 @@
 
 	DEBUGFUNC("ixgbe_clear_vmdq_generic");
 
-	if (rar < rar_entries) {
-		mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
-		mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
+	/* Make sure we are using a valid rar index range */
+	if (rar >= rar_entries) {
+		DEBUGOUT1("RAR index %d is out of range.\n", rar);
+		return IXGBE_ERR_INVALID_ARGUMENT;
+	}
 
-		if (!mpsar_lo && !mpsar_hi)
-			goto done;
+	mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
+	mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
 
-		if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
-			if (mpsar_lo) {
-				IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
-				mpsar_lo = 0;
-			}
-			if (mpsar_hi) {
-				IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
-				mpsar_hi = 0;
-			}
-		} else if (vmdq < 32) {
-			mpsar_lo &= ~(1 << vmdq);
-			IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
-		} else {
-			mpsar_hi &= ~(1 << (vmdq - 32));
-			IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
-		}
+	if (!mpsar_lo && !mpsar_hi)
+		goto done;
 
-		/* was that the last pool using this rar? */
-		if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
-			hw->mac.ops.clear_rar(hw, rar);
+	if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
+		if (mpsar_lo) {
+			IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
+			mpsar_lo = 0;
+		}
+		if (mpsar_hi) {
+			IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
+			mpsar_hi = 0;
+		}
+	} else if (vmdq < 32) {
+		mpsar_lo &= ~(1 << vmdq);
+		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
 	} else {
-		DEBUGOUT1("RAR index %d is out of range.\n", rar);
+		mpsar_hi &= ~(1 << (vmdq - 32));
+		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
 	}
 
+	/* was that the last pool using this rar? */
+	if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
+		hw->mac.ops.clear_rar(hw, rar);
 done:
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
- * @hw: pointer to hardware struct
- * @rar: receive address register index to associate with a VMDq index
- * @vmdq: VMDq pool index
- */
-s32
-ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
+/**
+ *  ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
+ *  @hw: pointer to hardware struct
+ *  @rar: receive address register index to associate with a VMDq index
+ *  @vmdq: VMDq pool index
+ **/
+s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 {
 	u32 mpsar;
 	u32 rar_entries = hw->mac.num_rar_entries;
@@ -2793,28 +2985,29 @@
 
 	DEBUGFUNC("ixgbe_set_vmdq_generic");
 
-	if (rar < rar_entries) {
-		if (vmdq < 32) {
-			mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
-			mpsar |= 1 << vmdq;
-			IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
-		} else {
-			mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
-			mpsar |= 1 << (vmdq - 32);
-			IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
-		}
-	} else {
+	/* Make sure we are using a valid rar index range */
+	if (rar >= rar_entries) {
 		DEBUGOUT1("RAR index %d is out of range.\n", rar);
+		return IXGBE_ERR_INVALID_ARGUMENT;
 	}
-	return (IXGBE_SUCCESS);
+
+	if (vmdq < 32) {
+		mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
+		mpsar |= 1 << vmdq;
+		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
+	} else {
+		mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
+		mpsar |= 1 << (vmdq - 32);
+		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
+	}
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
- * @hw: pointer to hardware structure
- */
-s32
-ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
+ *  @hw: pointer to hardware structure
+ **/
+s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
 {
 	int i;
 
@@ -2824,19 +3017,18 @@
 	for (i = 0; i < 128; i++)
 		IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
- * @hw: pointer to hardware structure
- * @vlan: VLAN id to write to VLAN filter
+/**
+ *  ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
+ *  @hw: pointer to hardware structure
+ *  @vlan: VLAN id to write to VLAN filter
  *
- * return the VLVF index where this VLAN id should be placed
+ *  return the VLVF index where this VLAN id should be placed
  *
- */
-s32
-ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
+ **/
+s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
 {
 	u32 bits = 0;
 	u32 first_empty_slot = 0;
@@ -2844,12 +3036,12 @@
 
 	/* short cut the special case */
 	if (vlan == 0)
-		return (0);
+		return 0;
 
 	/*
-	 * Search for the vlan id in the VLVF entries. Save off the first empty
-	 * slot found along the way
-	 */
+	  * Search for the vlan id in the VLVF entries. Save off the first empty
+	  * slot found along the way
+	  */
 	for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
 		bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
 		if (!bits && !(first_empty_slot))
@@ -2859,10 +3051,10 @@
 	}
 
 	/*
-	 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
-	 * in the VLVF. Else use the first empty VLVF register for this
-	 * vlan id.
-	 */
+	  * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
+	  * in the VLVF. Else use the first empty VLVF register for this
+	  * vlan id.
+	  */
 	if (regindex >= IXGBE_VLVF_ENTRIES) {
 		if (first_empty_slot)
 			regindex = first_empty_slot;
@@ -2872,20 +3064,20 @@
 		}
 	}
 
-	return (regindex);
+	return regindex;
 }
 
-/*
- * ixgbe_set_vfta_generic - Set VLAN filter table
- * @hw: pointer to hardware structure
- * @vlan: VLAN id to write to VLAN filter
- * @vind: VMDq output index that maps queue to VLAN id in VFVFB
- * @vlan_on: boolean flag to turn on/off VLAN in VFVF
+/**
+ *  ixgbe_set_vfta_generic - Set VLAN filter table
+ *  @hw: pointer to hardware structure
+ *  @vlan: VLAN id to write to VLAN filter
+ *  @vind: VMDq output index that maps queue to VLAN id in VFVFB
+ *  @vlan_on: boolean flag to turn on/off VLAN in VFVF
  *
- * Turn on/off specified VLAN in the VLAN filter table.
- */
-s32
-ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
+ *  Turn on/off specified VLAN in the VLAN filter table.
+ **/
+s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
+                           bool vlan_on)
 {
 	s32 regindex;
 	u32 bitindex;
@@ -2893,12 +3085,12 @@
 	u32 bits;
 	u32 vt;
 	u32 targetbit;
-	bool vfta_changed = false;
+	bool vfta_changed = FALSE;
 
 	DEBUGFUNC("ixgbe_set_vfta_generic");
 
 	if (vlan > 4095)
-		return (IXGBE_ERR_PARAM);
+		return IXGBE_ERR_PARAM;
 
 	/*
 	 * this is a 2 part operation - first the VFTA, then the
@@ -2906,8 +3098,7 @@
 	 * We don't write the VFTA until we know the VLVF part succeeded.
 	 */
 
-	/*
-	 * Part 1
+	/* Part 1
 	 * The VFTA is a bitstring made up of 128 32-bit registers
 	 * that enable the particular VLAN id, much like the MTA:
 	 *    bits[11-5]: which register
@@ -2921,24 +3112,22 @@
 	if (vlan_on) {
 		if (!(vfta & targetbit)) {
 			vfta |= targetbit;
-			vfta_changed = true;
+			vfta_changed = TRUE;
 		}
 	} else {
 		if ((vfta & targetbit)) {
 			vfta &= ~targetbit;
-			vfta_changed = true;
+			vfta_changed = TRUE;
 		}
 	}
 
-
-	/*
-	 * Part 2
+	/* Part 2
 	 * If VT Mode is set
-	 *  Either vlan_on
-	 *   make sure the vlan is in VLVF
-	 *   set the vind bit in the matching VLVFB
-	 *  Or !vlan_on
-	 *   clear the pool bit and possibly the vind
+	 *   Either vlan_on
+	 *     make sure the vlan is in VLVF
+	 *     set the vind bit in the matching VLVFB
+	 *   Or !vlan_on
+	 *     clear the pool bit and possibly the vind
 	 */
 	vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 	if (vt & IXGBE_VT_CTL_VT_ENABLE) {
@@ -2946,45 +3135,45 @@
 
 		vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
 		if (vlvf_index < 0)
-			return (vlvf_index);
+			return vlvf_index;
 
 		if (vlan_on) {
 			/* set the pool bit */
 			if (vind < 32) {
 				bits = IXGBE_READ_REG(hw,
-				    IXGBE_VLVFB(vlvf_index * 2));
+						IXGBE_VLVFB(vlvf_index*2));
 				bits |= (1 << vind);
 				IXGBE_WRITE_REG(hw,
-				    IXGBE_VLVFB(vlvf_index * 2),
-				    bits);
+						IXGBE_VLVFB(vlvf_index*2),
+						bits);
 			} else {
 				bits = IXGBE_READ_REG(hw,
-				    IXGBE_VLVFB((vlvf_index * 2) + 1));
-				bits |= (1 << (vind - 32));
+						IXGBE_VLVFB((vlvf_index*2)+1));
+				bits |= (1 << (vind-32));
 				IXGBE_WRITE_REG(hw,
-				    IXGBE_VLVFB((vlvf_index * 2) + 1),
-				    bits);
+						IXGBE_VLVFB((vlvf_index*2)+1),
+						bits);
 			}
 		} else {
 			/* clear the pool bit */
 			if (vind < 32) {
 				bits = IXGBE_READ_REG(hw,
-				    IXGBE_VLVFB(vlvf_index * 2));
+						IXGBE_VLVFB(vlvf_index*2));
 				bits &= ~(1 << vind);
 				IXGBE_WRITE_REG(hw,
-				    IXGBE_VLVFB(vlvf_index * 2),
-				    bits);
+						IXGBE_VLVFB(vlvf_index*2),
+						bits);
 				bits |= IXGBE_READ_REG(hw,
-				    IXGBE_VLVFB((vlvf_index * 2) + 1));
+						IXGBE_VLVFB((vlvf_index*2)+1));
 			} else {
 				bits = IXGBE_READ_REG(hw,
-				    IXGBE_VLVFB((vlvf_index * 2) + 1));
-				bits &= ~(1 << (vind - 32));
+						IXGBE_VLVFB((vlvf_index*2)+1));
+				bits &= ~(1 << (vind-32));
 				IXGBE_WRITE_REG(hw,
-				    IXGBE_VLVFB((vlvf_index * 2) + 1),
-				    bits);
+						IXGBE_VLVFB((vlvf_index*2)+1),
+						bits);
 				bits |= IXGBE_READ_REG(hw,
-				    IXGBE_VLVFB(vlvf_index * 2));
+						IXGBE_VLVFB(vlvf_index*2));
 			}
 		}
 
@@ -3005,34 +3194,31 @@
 		 */
 		if (bits) {
 			IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
-			    (IXGBE_VLVF_VIEN | vlan));
+					(IXGBE_VLVF_VIEN | vlan));
 			if (!vlan_on) {
-				/*
-				 * someone wants to clear the vfta entry
+				/* someone wants to clear the vfta entry
 				 * but some pools/VFs are still using it.
-				 * Ignore it.
-				 */
-				vfta_changed = false;
+				 * Ignore it. */
+				vfta_changed = FALSE;
 			}
-		} else {
-			IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
 		}
+		else
+			IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
 	}
 
 	if (vfta_changed)
 		IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_clear_vfta_generic - Clear VLAN filter table
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_clear_vfta_generic - Clear VLAN filter table
+ *  @hw: pointer to hardware structure
  *
- * Clears the VLAN filer table, and the VMDq index associated with the filter
- */
-s32
-ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
+ *  Clears the VLAN filer table, and the VMDq index associated with the filter
+ **/
+s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
 {
 	u32 offset;
 
@@ -3047,21 +3233,20 @@
 		IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
 	}
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_check_mac_link_generic - Determine link and speed status
- * @hw: pointer to hardware structure
- * @speed: pointer to link speed
- * @link_up: true when link is up
- * @link_up_wait_to_complete: bool used to wait for link up or not
+/**
+ *  ixgbe_check_mac_link_generic - Determine link and speed status
+ *  @hw: pointer to hardware structure
+ *  @speed: pointer to link speed
+ *  @link_up: TRUE when link is up
+ *  @link_up_wait_to_complete: bool used to wait for link up or not
  *
- * Reads the links register to determine if link is up and the current speed
- */
-s32
-ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
-    bool *link_up, bool link_up_wait_to_complete)
+ *  Reads the links register to determine if link is up and the current speed
+ **/
+s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
+                                 bool *link_up, bool link_up_wait_to_complete)
 {
 	u32 links_reg, links_orig;
 	u32 i;
@@ -3075,16 +3260,16 @@
 
 	if (links_orig != links_reg) {
 		DEBUGOUT2("LINKS changed from %08X to %08X\n",
-		    links_orig, links_reg);
+		          links_orig, links_reg);
 	}
 
 	if (link_up_wait_to_complete) {
 		for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 			if (links_reg & IXGBE_LINKS_UP) {
-				*link_up = true;
+				*link_up = TRUE;
 				break;
 			} else {
-				*link_up = false;
+				*link_up = FALSE;
 			}
 			msec_delay(100);
 			links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
@@ -3091,9 +3276,9 @@
 		}
 	} else {
 		if (links_reg & IXGBE_LINKS_UP)
-			*link_up = true;
+			*link_up = TRUE;
 		else
-			*link_up = false;
+			*link_up = FALSE;
 	}
 
 	if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
@@ -3100,36 +3285,35 @@
 	    IXGBE_LINKS_SPEED_10G_82599)
 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
 	else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
-	    IXGBE_LINKS_SPEED_1G_82599)
+	         IXGBE_LINKS_SPEED_1G_82599)
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
 	else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
-	    IXGBE_LINKS_SPEED_100_82599)
+	         IXGBE_LINKS_SPEED_100_82599)
 		*speed = IXGBE_LINK_SPEED_100_FULL;
 	else
 		*speed = IXGBE_LINK_SPEED_UNKNOWN;
 
 	/* if link is down, zero out the current_mode */
-	if (*link_up == false) {
+	if (*link_up == FALSE) {
 		hw->fc.current_mode = ixgbe_fc_none;
-		hw->fc.fc_was_autonegged = false;
+		hw->fc.fc_was_autonegged = FALSE;
 	}
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
- * the EEPROM
- * @hw: pointer to hardware structure
- * @wwnn_prefix: the alternative WWNN prefix
- * @wwpn_prefix: the alternative WWPN prefix
+/**
+ *  ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
+ *  the EEPROM
+ *  @hw: pointer to hardware structure
+ *  @wwnn_prefix: the alternative WWNN prefix
+ *  @wwpn_prefix: the alternative WWPN prefix
  *
- * This function will read the EEPROM from the alternative SAN MAC address
- * block to check the support for the alternative WWNN/WWPN prefix support.
- */
-s32
-ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
-    u16 *wwpn_prefix)
+ *  This function will read the EEPROM from the alternative SAN MAC address
+ *  block to check the support for the alternative WWNN/WWPN prefix support.
+ **/
+s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
+                                 u16 *wwpn_prefix)
 {
 	u16 offset, caps;
 	u16 alt_san_mac_blk_offset;
@@ -3142,7 +3326,7 @@
 
 	/* check if alternative SAN MAC is supported */
 	hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
-	    &alt_san_mac_blk_offset);
+	                    &alt_san_mac_blk_offset);
 
 	if ((alt_san_mac_blk_offset == 0) ||
 	    (alt_san_mac_blk_offset == 0xFFFF))
@@ -3162,18 +3346,17 @@
 	hw->eeprom.ops.read(hw, offset, wwpn_prefix);
 
 wwn_prefix_out:
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
- * @hw: pointer to hardware structure
- * @bs: the fcoe boot status
+/**
+ *  ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
+ *  @hw: pointer to hardware structure
+ *  @bs: the fcoe boot status
  *
- * This function will read the FCOE boot status from the iSCSI FCOE block
- */
-s32
-ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
+ *  This function will read the FCOE boot status from the iSCSI FCOE block
+ **/
+s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
 {
 	u16 offset, caps, flags;
 	s32 status;
@@ -3212,18 +3395,18 @@
 		*bs = ixgbe_fcoe_bootstatus_disabled;
 
 out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
- * control
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
+ *  control
+ *  @hw: pointer to hardware structure
  *
- * There are several phys that do not support autoneg flow control. This
- * function check the device id to see if the associated phy supports
- * autoneg flow control.
- */
+ *  There are several phys that do not support autoneg flow control. This
+ *  function check the device id to see if the associated phy supports
+ *  autoneg flow control.
+ **/
 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
 {
 
@@ -3231,8 +3414,117 @@
 
 	switch (hw->device_id) {
 	case IXGBE_DEV_ID_82599_T3_LOM:
-		return (IXGBE_SUCCESS);
+		return IXGBE_SUCCESS;
 	default:
-		return (IXGBE_ERR_FC_NOT_SUPPORTED);
+		return IXGBE_ERR_FC_NOT_SUPPORTED;
 	}
+}
+
+/**
+ *  ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
+ *  @hw: pointer to hardware structure
+ *  @enable: enable or disable switch for anti-spoofing
+ *  @pf: Physical Function pool - do not enable anti-spoofing for the PF
+ *
+ **/
+void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
+{
+	int j;
+	int pf_target_reg = pf >> 3;
+	int pf_target_shift = pf % 8;
+	u32 pfvfspoof = 0;
+
+	if (hw->mac.type == ixgbe_mac_82598EB)
+		return;
+
+	if (enable)
+		pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
+
+	/*
+	 * PFVFSPOOF register array is size 8 with 8 bits assigned to
+	 * MAC anti-spoof enables in each register array element.
+	 */
+	for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
+		IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
+
+	/* If not enabling anti-spoofing then done */
+	if (!enable)
+		return;
+
+	/*
+	 * The PF should be allowed to spoof so that it can support
+	 * emulation mode NICs.  Reset the bit assigned to the PF
+	 */
+	pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
+	pfvfspoof ^= (1 << pf_target_shift);
+	IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
+}
+
+/**
+ *  ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
+ *  @hw: pointer to hardware structure
+ *  @enable: enable or disable switch for VLAN anti-spoofing
+ *  @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
+ *
+ **/
+void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
+{
+	int vf_target_reg = vf >> 3;
+	int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
+	u32 pfvfspoof;
+
+	if (hw->mac.type == ixgbe_mac_82598EB)
+		return;
+
+	pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
+	if (enable)
+		pfvfspoof |= (1 << vf_target_shift);
+	else
+		pfvfspoof &= ~(1 << vf_target_shift);
+	IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
+}
+
+/**
+ *  ixgbe_get_device_caps_generic - Get additional device capabilities
+ *  @hw: pointer to hardware structure
+ *  @device_caps: the EEPROM word with the extra device capabilities
+ *
+ *  This function will read the EEPROM location for the device capabilities,
+ *  and return the word through device_caps.
+ **/
+s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
+{
+	DEBUGFUNC("ixgbe_get_device_caps_generic");
+
+	hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
+
+	return IXGBE_SUCCESS;
+}
+
+/**
+ *  ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
+ *  @hw: pointer to hardware structure
+ *
+ **/
+void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
+{
+	u32 regval;
+	u32 i;
+
+	DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
+
+	/* Enable relaxed ordering */
+	for (i = 0; i < hw->mac.max_tx_queues; i++) {
+		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
+		regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
+	}
+
+	for (i = 0; i < hw->mac.max_rx_queues; i++) {
+		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
+		regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
+		           IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
+	}
+
 }
--- old/usr/src/uts/common/io/ixgbe/ixgbe_common.h	Wed Sep  7 11:32:37 2011
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_common.h	Wed Sep  7 11:32:36 2011
@@ -1,46 +1,46 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at:
- *      http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When using or redistributing this file, you may do so under the
- * License only. No other modification of this header is permitted.
- *
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
+/******************************************************************************
 
-/*
- * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
- */
+  Copyright (c) 2001-2010, Intel Corporation 
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without 
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice, 
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright 
+      notice, this list of conditions and the following disclaimer in the 
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its 
+      contributors may be used to endorse or promote products derived from 
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
 
-/*
- * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
- */
+******************************************************************************/
+/*$FreeBSD$*/
 
-/* IntelVersion: 1.95 scm_061610_003709 */
+#ifndef _IXGBE_COMMON_H_
+#define _IXGBE_COMMON_H_
 
-#ifndef _IXGBE_COMMON_H
-#define	_IXGBE_COMMON_H
-
 #include "ixgbe_type.h"
-#ifndef IXGBE_WRITE_REG64
-#define	IXGBE_WRITE_REG64(hw, reg, value) \
-	do { \
+#define IXGBE_WRITE_REG64(hw, reg, value) \
+	{ \
 		IXGBE_WRITE_REG(hw, reg, (u32) value); \
 		IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \
-	} while (0)
-#endif /* IXGBE_WRITE_REG64 */
+	}
 
 u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
 
@@ -47,8 +47,12 @@
 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
+s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);
 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
+s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
+                                  u32 pba_num_size);
+s32 ixgbe_read_pba_length_generic(struct ixgbe_hw *hw, u32 *pba_num_size);
 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
@@ -60,23 +64,24 @@
 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
+s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
-    u16 *data);
+                                       u16 *data);
 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
-    u16 *checksum_val);
+                                           u16 *checksum_val);
 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
 
 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
-    u32 enable_addr);
+                          u32 enable_addr);
 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
-    u32 mc_addr_count,
-    ixgbe_mc_addr_itr func);
+                                      u32 mc_addr_count,
+                                      ixgbe_mc_addr_itr func);
 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
-    u32 addr_count, ixgbe_mc_addr_itr func);
+                                      u32 addr_count, ixgbe_mc_addr_itr func);
 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
@@ -101,14 +106,19 @@
 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
-    u32 vind, bool vlan_on);
+                         u32 vind, bool vlan_on);
 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
 
 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
-    ixgbe_link_speed *speed, bool *link_up, bool link_up_wait_to_complete);
+                               ixgbe_link_speed *speed,
+                               bool *link_up, bool link_up_wait_to_complete);
 
 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
-    u16 *wwpn_prefix);
-s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs);
+                                 u16 *wwpn_prefix);
 
-#endif /* _IXGBE_COMMON_H */
+s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs);
+void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf);
+void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
+s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
+void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw);
+#endif /* IXGBE_COMMON */
--- old/usr/src/uts/common/io/ixgbe/ixgbe_osdep.h	Wed Sep  7 11:32:37 2011
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_osdep.h	Wed Sep  7 11:32:37 2011
@@ -66,6 +66,8 @@
 
 #define	false		B_FALSE
 #define	true		B_TRUE
+#define	FALSE		B_FALSE
+#define	TRUE		B_TRUE
 
 #define	IXGBE_READ_PCIE_WORD 	ixgbe_read_pci_cfg
 #define	IXGBE_WRITE_PCIE_WORD 	ixgbe_write_pci_cfg
@@ -93,15 +95,10 @@
 #define	IXGBE_READ_REG_ARRAY(a, reg, index)	\
 	IXGBE_READ_REG(a, ((reg) + ((index) << 2)))
 
-#define	IXGBE_WRITE_REG64(hw, reg, value)	\
-	do {								\
-		IXGBE_WRITE_REG(hw, reg, (u32) value);			\
-		IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32));	\
-		_NOTE(CONSTCOND)					\
-	} while (0)
-
 #define	msec_delay_irq	msec_delay
 #define	IXGBE_HTONL	htonl
+#define	IXGBE_NTOHL	ntohl
+#define	IXGBE_NTOHS	ntohs
 
 #define	UNREFERENCED_PARAMETER(x)	_NOTE(ARGUNUSED(x))
 
--- old/usr/src/uts/common/io/ixgbe/ixgbe_phy.c	Wed Sep  7 11:32:38 2011
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_phy.c	Wed Sep  7 11:32:38 2011
@@ -1,35 +1,37 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at:
- *      http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When using or redistributing this file, you may do so under the
- * License only. No other modification of this header is permitted.
- *
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
+/******************************************************************************
 
-/*
- * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
- */
+  Copyright (c) 2001-2010, Intel Corporation 
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without 
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice, 
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright 
+      notice, this list of conditions and the following disclaimer in the 
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its 
+      contributors may be used to endorse or promote products derived from 
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
 
-/*
- * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
- */
+******************************************************************************/
+/*$FreeBSD$*/
 
-/* IntelVersion: 1.109 scm_061610_003709 */
-
 #include "ixgbe_api.h"
 #include "ixgbe_common.h"
 #include "ixgbe_phy.h"
@@ -47,14 +49,13 @@
 static bool ixgbe_get_i2c_data(u32 *i2cctl);
 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
 
-/*
- * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
- * @hw: pointer to the hardware structure
+/**
+ *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
+ *  @hw: pointer to the hardware structure
  *
- * Initialize the function pointers.
- */
-s32
-ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
+ *  Initialize the function pointers.
+ **/
+s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_phy_info *phy = &hw->phy;
 
@@ -77,18 +78,16 @@
 	phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic;
 	phy->sfp_type = ixgbe_sfp_type_unknown;
 	phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
-
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_identify_phy_generic - Get physical layer module
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_identify_phy_generic - Get physical layer module
+ *  @hw: pointer to hardware structure
  *
- * Determines the physical layer module found on the current adapter.
- */
-s32
-ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
+ *  Determines the physical layer module found on the current adapter.
+ **/
+s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 	u32 phy_addr;
@@ -102,22 +101,21 @@
 				hw->phy.addr = phy_addr;
 				(void) ixgbe_get_phy_id(hw);
 				hw->phy.type =
-				    ixgbe_get_phy_type_from_id(hw->phy.id);
+				        ixgbe_get_phy_type_from_id(hw->phy.id);
 
 				if (hw->phy.type == ixgbe_phy_unknown) {
 					hw->phy.ops.read_reg(hw,
-					    IXGBE_MDIO_PHY_EXT_ABILITY,
-					    IXGBE_MDIO_PMA_PMD_DEV_TYPE,
-					    &ext_ability);
+						  IXGBE_MDIO_PHY_EXT_ABILITY,
+					          IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+					          &ext_ability);
 					if (ext_ability &
-					    IXGBE_MDIO_PHY_10GBASET_ABILITY ||
-					    ext_ability &
-					    IXGBE_MDIO_PHY_1000BASET_ABILITY)
+					    (IXGBE_MDIO_PHY_10GBASET_ABILITY |
+					     IXGBE_MDIO_PHY_1000BASET_ABILITY))
 						hw->phy.type =
-						    ixgbe_phy_cu_unknown;
+						         ixgbe_phy_cu_unknown;
 					else
 						hw->phy.type =
-						    ixgbe_phy_generic;
+						         ixgbe_phy_generic;
 				}
 
 				status = IXGBE_SUCCESS;
@@ -124,6 +122,7 @@
 				break;
 			}
 		}
+		/* clear value if nothing found */
 		if (status != IXGBE_SUCCESS)
 			hw->phy.addr = 0;
 	} else {
@@ -130,39 +129,37 @@
 		status = IXGBE_SUCCESS;
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_validate_phy_addr - Determines phy address is valid
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_validate_phy_addr - Determines phy address is valid
+ *  @hw: pointer to hardware structure
  *
- */
-bool
-ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
+ **/
+bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 {
 	u16 phy_id = 0;
-	bool valid = false;
+	bool valid = FALSE;
 
 	DEBUGFUNC("ixgbe_validate_phy_addr");
 
 	hw->phy.addr = phy_addr;
 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
-	    IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
+	                     IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 
 	if (phy_id != 0xFFFF && phy_id != 0x0)
-		valid = true;
+		valid = TRUE;
 
-	return (valid);
+	return valid;
 }
 
-/*
- * ixgbe_get_phy_id - Get the phy type
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_phy_id - Get the phy type
+ *  @hw: pointer to hardware structure
  *
- */
-s32
-ixgbe_get_phy_id(struct ixgbe_hw *hw)
+ **/
+s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 {
 	u32 status;
 	u16 phy_id_high = 0;
@@ -171,28 +168,26 @@
 	DEBUGFUNC("ixgbe_get_phy_id");
 
 	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
-	    IXGBE_MDIO_PMA_PMD_DEV_TYPE,
-	    &phy_id_high);
+	                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+	                              &phy_id_high);
 
 	if (status == IXGBE_SUCCESS) {
 		hw->phy.id = (u32)(phy_id_high << 16);
 		status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
-		    IXGBE_MDIO_PMA_PMD_DEV_TYPE,
-		    &phy_id_low);
+		                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+		                              &phy_id_low);
 		hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 		hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 	}
-
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_get_phy_type_from_id - Get the phy type
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_phy_type_from_id - Get the phy type
+ *  @hw: pointer to hardware structure
  *
- */
-enum ixgbe_phy_type
-ixgbe_get_phy_type_from_id(u32 phy_id)
+ **/
+enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 {
 	enum ixgbe_phy_type phy_type;
 
@@ -217,16 +212,14 @@
 	}
 
 	DEBUGOUT1("phy type found is %d\n", phy_type);
-
-	return (phy_type);
+	return phy_type;
 }
 
-/*
- * ixgbe_reset_phy_generic - Performs a PHY reset
- * @hw: pointer to hardware structure
- */
-s32
-ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_reset_phy_generic - Performs a PHY reset
+ *  @hw: pointer to hardware structure
+ **/
+s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 {
 	u32 i;
 	u16 ctrl = 0;
@@ -240,11 +233,10 @@
 	if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 		goto out;
 
+	/* Don't reset PHY if it's shut down due to overtemp. */
 	if (!hw->phy.reset_if_overtemp &&
-	    (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) {
-		/* Don't reset PHY if it's shut down due to overtemp. */
+	    (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 		goto out;
-	}
 
 	/*
 	 * Perform soft PHY reset to the PHY_XS.
@@ -251,8 +243,8 @@
 	 * This will cause a soft reset to the PHY
 	 */
 	hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
-	    IXGBE_MDIO_PHY_XS_DEV_TYPE,
-	    IXGBE_MDIO_PHY_XS_RESET);
+	                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
+	                      IXGBE_MDIO_PHY_XS_RESET);
 
 	/*
 	 * Poll for reset bit to self-clear indicating reset is complete.
@@ -262,7 +254,7 @@
 	for (i = 0; i < 30; i++) {
 		msec_delay(100);
 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
-		    IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
+		                     IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 		if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 			usec_delay(2);
 			break;
@@ -275,18 +267,17 @@
 	}
 
 out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit address of PHY register to read
- * @phy_data: Pointer to read data from PHY register
- */
-s32
-ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
-    u32 device_type, u16 *phy_data)
+/**
+ *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
+ *  @hw: pointer to hardware structure
+ *  @reg_addr: 32 bit address of PHY register to read
+ *  @phy_data: Pointer to read data from PHY register
+ **/
+s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
+                               u32 device_type, u16 *phy_data)
 {
 	u32 command;
 	u32 i;
@@ -307,9 +298,9 @@
 	if (status == IXGBE_SUCCESS) {
 		/* Setup and write the address cycle command */
 		command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
-		    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
-		    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
-		    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
+		           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+		           (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+		           (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 
 		IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 
@@ -323,9 +314,8 @@
 
 			command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 
-			if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) {
+			if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 				break;
-			}
 		}
 
 		if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
@@ -339,9 +329,9 @@
 			 * command
 			 */
 			command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
-			    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
-			    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
-			    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
+			           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+			           (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+			           (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 
 			IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 
@@ -376,18 +366,18 @@
 		ixgbe_release_swfw_sync(hw, gssr);
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
- * @hw: pointer to hardware structure
- * @reg_addr: 32 bit PHY register to write
- * @device_type: 5 bit device type
- * @phy_data: Data to write to the PHY register
- */
+/**
+ *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
+ *  @hw: pointer to hardware structure
+ *  @reg_addr: 32 bit PHY register to write
+ *  @device_type: 5 bit device type
+ *  @phy_data: Data to write to the PHY register
+ **/
 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
-    u32 device_type, u16 phy_data)
+                                u32 device_type, u16 phy_data)
 {
 	u32 command;
 	u32 i;
@@ -405,16 +395,14 @@
 		status = IXGBE_ERR_SWFW_SYNC;
 
 	if (status == IXGBE_SUCCESS) {
-		/*
-		 * Put the data in the MDI single read and write data register
-		 */
+		/* Put the data in the MDI single read and write data register*/
 		IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 
 		/* Setup and write the address cycle command */
 		command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
-		    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
-		    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
-		    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
+		           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+		           (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+		           (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 
 		IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 
@@ -443,9 +431,9 @@
 			 * command
 			 */
 			command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
-			    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
-			    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
-			    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
+			           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+			           (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+			           (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 
 			IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 
@@ -472,23 +460,22 @@
 		ixgbe_release_swfw_sync(hw, gssr);
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_setup_phy_link_generic - Set and restart autoneg
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_setup_phy_link_generic - Set and restart autoneg
+ *  @hw: pointer to hardware structure
  *
- * Restart autonegotiation and PHY and waits for completion.
- */
-s32
-ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
+ *  Restart autonegotiation and PHY and waits for completion.
+ **/
+s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 time_out;
 	u32 max_time_out = 10;
 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
-	bool autoneg = false;
+	bool autoneg = FALSE;
 	ixgbe_link_speed speed;
 
 	DEBUGFUNC("ixgbe_setup_phy_link_generic");
@@ -498,8 +485,8 @@
 	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 		/* Set or unset auto-negotiation 10G advertisement */
 		hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    &autoneg_reg);
+		                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+	                             &autoneg_reg);
 
 		autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
@@ -506,16 +493,16 @@
 			autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 
 		hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    autoneg_reg);
+		                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                      autoneg_reg);
 	}
 
 	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 		/* Set or unset auto-negotiation 1G advertisement */
 		hw->phy.ops.read_reg(hw,
-		    IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    &autoneg_reg);
+		                     IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
+		                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                     &autoneg_reg);
 
 		autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
@@ -522,16 +509,16 @@
 			autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 
 		hw->phy.ops.write_reg(hw,
-		    IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    autoneg_reg);
+		                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
+		                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                      autoneg_reg);
 	}
 
 	if (speed & IXGBE_LINK_SPEED_100_FULL) {
 		/* Set or unset auto-negotiation 100M advertisement */
 		hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    &autoneg_reg);
+		                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                     &autoneg_reg);
 
 		autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
@@ -538,18 +525,18 @@
 			autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 
 		hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    autoneg_reg);
+		                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                      autoneg_reg);
 	}
 
 	/* Restart PHY autonegotiation and wait for completion */
 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
-	    IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
+	                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 
 	autoneg_reg |= IXGBE_MII_RESTART;
 
 	hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
-	    IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
+	                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 
 	/* Wait for autonegotiation to finish */
 	for (time_out = 0; time_out < max_time_out; time_out++) {
@@ -556,8 +543,8 @@
 		usec_delay(10);
 		/* Restart PHY autonegotiation and wait for completion */
 		status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    &autoneg_reg);
+		                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                              &autoneg_reg);
 
 		autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 		if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
@@ -570,20 +557,19 @@
 		DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
- * @hw: pointer to hardware structure
- * @speed: new link speed
- * @autoneg: true if autonegotiation enabled
- */
-s32
-ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed,
-    bool autoneg,
-    bool autoneg_wait_to_complete)
+/**
+ *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: TRUE if autonegotiation enabled
+ **/
+s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
+                                       ixgbe_link_speed speed,
+                                       bool autoneg,
+                                       bool autoneg_wait_to_complete)
 {
 	UNREFERENCED_PARAMETER(autoneg);
 	UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
@@ -596,13 +582,11 @@
 	 */
 	hw->phy.autoneg_advertised = 0;
 
-	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
+	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
-	}
 
-	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
+	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
-	}
 
 	if (speed & IXGBE_LINK_SPEED_100_FULL)
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
@@ -610,20 +594,20 @@
 	/* Setup link based on the new speed settings */
 	hw->phy.ops.setup_link(hw);
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
- * @hw: pointer to hardware structure
- * @speed: pointer to link speed
- * @autoneg: boolean auto-negotiation value
+/**
+ *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
+ *  @hw: pointer to hardware structure
+ *  @speed: pointer to link speed
+ *  @autoneg: boolean auto-negotiation value
  *
- * Determines the link capabilities by reading the AUTOC register.
- */
-s32
-ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
-    ixgbe_link_speed *speed, bool *autoneg)
+ *  Determines the link capabilities by reading the AUTOC register.
+ **/
+s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
+                                             ixgbe_link_speed *speed,
+                                             bool *autoneg)
 {
 	s32 status = IXGBE_ERR_LINK_SETUP;
 	u16 speed_ability;
@@ -631,10 +615,11 @@
 	DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 
 	*speed = 0;
-	*autoneg = true;
+	*autoneg = TRUE;
 
 	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
-	    IXGBE_MDIO_PMA_PMD_DEV_TYPE, &speed_ability);
+	                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
+	                              &speed_ability);
 
 	if (status == IXGBE_SUCCESS) {
 		if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
@@ -645,19 +630,18 @@
 			*speed |= IXGBE_LINK_SPEED_100_FULL;
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_check_phy_link_tnx - Determine link and speed status
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_check_phy_link_tnx - Determine link and speed status
+ *  @hw: pointer to hardware structure
  *
- * Reads the VS1 register to determine if link is up and the current speed for
- * the PHY.
- */
-s32
-ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
-    bool *link_up)
+ *  Reads the VS1 register to determine if link is up and the current speed for
+ *  the PHY.
+ **/
+s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
+                             bool *link_up)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 time_out;
@@ -669,7 +653,7 @@
 	DEBUGFUNC("ixgbe_check_phy_link_tnx");
 
 	/* Initialize speed and link to default case */
-	*link_up = false;
+	*link_up = FALSE;
 	*speed = IXGBE_LINK_SPEED_10GB_FULL;
 
 	/*
@@ -680,15 +664,15 @@
 	for (time_out = 0; time_out < max_time_out; time_out++) {
 		usec_delay(10);
 		status = hw->phy.ops.read_reg(hw,
-		    IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
-		    IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
-		    &phy_data);
+		                        IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
+		                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
+		                        &phy_data);
 		phy_link = phy_data &
-		    IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
+		           IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 		phy_speed = phy_data &
-		    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
+		            IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 		if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
-			*link_up = true;
+			*link_up = TRUE;
 			if (phy_speed ==
 			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 				*speed = IXGBE_LINK_SPEED_1GB_FULL;
@@ -696,23 +680,22 @@
 		}
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_setup_phy_link_tnx - Set and restart autoneg
- * @hw: pointer to hardware structure
+/**
+ *	ixgbe_setup_phy_link_tnx - Set and restart autoneg
+ *	@hw: pointer to hardware structure
  *
- * Restart autonegotiation and PHY and waits for completion.
- */
-s32
-ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
+ *	Restart autonegotiation and PHY and waits for completion.
+ **/
+s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 time_out;
 	u32 max_time_out = 10;
 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
-	bool autoneg = false;
+	bool autoneg = FALSE;
 	ixgbe_link_speed speed;
 
 	DEBUGFUNC("ixgbe_setup_phy_link_tnx");
@@ -722,8 +705,8 @@
 	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 		/* Set or unset auto-negotiation 10G advertisement */
 		hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    &autoneg_reg);
+		                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                     &autoneg_reg);
 
 		autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
@@ -730,15 +713,15 @@
 			autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 
 		hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    autoneg_reg);
+		                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                      autoneg_reg);
 	}
 
 	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 		/* Set or unset auto-negotiation 1G advertisement */
 		hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    &autoneg_reg);
+		                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                     &autoneg_reg);
 
 		autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
@@ -745,15 +728,15 @@
 			autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 
 		hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    autoneg_reg);
+		                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                      autoneg_reg);
 	}
 
 	if (speed & IXGBE_LINK_SPEED_100_FULL) {
 		/* Set or unset auto-negotiation 100M advertisement */
 		hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    &autoneg_reg);
+		                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                     &autoneg_reg);
 
 		autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
@@ -760,18 +743,18 @@
 			autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 
 		hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    autoneg_reg);
+		                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                      autoneg_reg);
 	}
 
 	/* Restart PHY autonegotiation and wait for completion */
 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
-	    IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
+	                     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 
 	autoneg_reg |= IXGBE_MII_RESTART;
 
 	hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
-	    IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
+	                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 
 	/* Wait for autonegotiation to finish */
 	for (time_out = 0; time_out < max_time_out; time_out++) {
@@ -778,8 +761,8 @@
 		usec_delay(10);
 		/* Restart PHY autonegotiation and wait for completion */
 		status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
-		    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
-		    &autoneg_reg);
+		                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
+		                              &autoneg_reg);
 
 		autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 		if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
@@ -792,16 +775,16 @@
 		DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
- * @hw: pointer to hardware structure
- * @firmware_version: pointer to the PHY Firmware Version
- */
-s32
-ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, u16 *firmware_version)
+/**
+ *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
+ *  @hw: pointer to hardware structure
+ *  @firmware_version: pointer to the PHY Firmware Version
+ **/
+s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
+                                       u16 *firmware_version)
 {
 	s32 status = IXGBE_SUCCESS;
 
@@ -808,19 +791,19 @@
 	DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
 
 	status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
-	    IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, firmware_version);
+	                              IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
+	                              firmware_version);
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
- * @hw: pointer to hardware structure
- * @firmware_version: pointer to the PHY Firmware Version
- */
-s32
-ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
-    u16 *firmware_version)
+/**
+ *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
+ *  @hw: pointer to hardware structure
+ *  @firmware_version: pointer to the PHY Firmware Version
+ **/
+s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
+                                       u16 *firmware_version)
 {
 	s32 status = IXGBE_SUCCESS;
 
@@ -827,20 +810,20 @@
 	DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
 
 	status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
-	    IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, firmware_version);
+	                              IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
+	                              firmware_version);
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_reset_phy_nl - Performs a PHY reset
- * @hw: pointer to hardware structure
- */
-s32
-ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
+/**
+ *  ixgbe_reset_phy_nl - Performs a PHY reset
+ *  @hw: pointer to hardware structure
+ **/
+s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 {
 	u16 phy_offset, control, eword, edata, block_crc;
-	bool end_data = false;
+	bool end_data = FALSE;
 	u16 list_offset, data_offset;
 	u16 phy_data = 0;
 	s32 ret_val = IXGBE_SUCCESS;
@@ -849,16 +832,16 @@
 	DEBUGFUNC("ixgbe_reset_phy_nl");
 
 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
-	    IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
+	                     IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 
 	/* reset the PHY and poll for completion */
 	hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
-	    IXGBE_MDIO_PHY_XS_DEV_TYPE,
-	    (phy_data | IXGBE_MDIO_PHY_XS_RESET));
+	                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
+	                      (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 
 	for (i = 0; i < 100; i++) {
 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
-		    IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
+		                     IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 		if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 			break;
 		msec_delay(10);
@@ -872,7 +855,7 @@
 
 	/* Get init offsets */
 	ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
-	    &data_offset);
+	                                              &data_offset);
 	if (ret_val != IXGBE_SUCCESS)
 		goto out;
 
@@ -884,7 +867,7 @@
 		 */
 		ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 		control = (eword & IXGBE_CONTROL_MASK_NL) >>
-		    IXGBE_CONTROL_SHIFT_NL;
+		           IXGBE_CONTROL_SHIFT_NL;
 		edata = eword & IXGBE_DATA_MASK_NL;
 		switch (control) {
 		case IXGBE_DELAY_NL:
@@ -895,13 +878,14 @@
 		case IXGBE_DATA_NL:
 			DEBUGOUT("DATA:  \n");
 			data_offset++;
-			hw->eeprom.ops.read(hw, data_offset++, &phy_offset);
+			hw->eeprom.ops.read(hw, data_offset++,
+			                    &phy_offset);
 			for (i = 0; i < edata; i++) {
 				hw->eeprom.ops.read(hw, data_offset, &eword);
 				hw->phy.ops.write_reg(hw, phy_offset,
-				    IXGBE_TWINAX_DEV, eword);
+				                      IXGBE_TWINAX_DEV, eword);
 				DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
-				    phy_offset);
+				          phy_offset);
 				data_offset++;
 				phy_offset++;
 			}
@@ -911,7 +895,7 @@
 			DEBUGOUT("CONTROL: \n");
 			if (edata == IXGBE_CONTROL_EOL_NL) {
 				DEBUGOUT("EOL\n");
-				end_data = true;
+				end_data = TRUE;
 			} else if (edata == IXGBE_CONTROL_SOL_NL) {
 				DEBUGOUT("SOL\n");
 			} else {
@@ -928,17 +912,16 @@
 	}
 
 out:
-	return (ret_val);
+	return ret_val;
 }
 
-/*
- * ixgbe_identify_sfp_module_generic - Identifies SFP module
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
+ *  @hw: pointer to hardware structure
  *
- * Searches for and identifies the SFP module and assigns appropriate PHY type.
- */
-s32
-ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
+ *  Searches for and identifies the SFP module and assigns appropriate PHY type.
+ **/
+s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 	u32 vendor_oui = 0;
@@ -960,17 +943,13 @@
 	}
 
 	status = hw->phy.ops.read_i2c_eeprom(hw,
-	    IXGBE_SFF_IDENTIFIER, &identifier);
+	                                     IXGBE_SFF_IDENTIFIER,
+	                                     &identifier);
 
-	if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) {
-		status = IXGBE_ERR_SFP_NOT_PRESENT;
-		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
-		if (hw->phy.type != ixgbe_phy_nl) {
-			hw->phy.id = 0;
-			hw->phy.type = ixgbe_phy_unknown;
-		}
-		goto out;
-	}
+	if (status == IXGBE_ERR_SWFW_SYNC ||
+	    status == IXGBE_ERR_I2C ||
+	    status == IXGBE_ERR_SFP_NOT_PRESENT)
+		goto err_read_i2c_eeprom;
 
 	/* LAN ID is needed for sfp_type determination */
 	hw->mac.ops.set_lan_id(hw);
@@ -979,28 +958,46 @@
 		hw->phy.type = ixgbe_phy_sfp_unsupported;
 		status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 	} else {
-		hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
-		    &comp_codes_1g);
-		hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
-		    &comp_codes_10g);
-		hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
-		    &cable_tech);
+		status = hw->phy.ops.read_i2c_eeprom(hw,
+		                                     IXGBE_SFF_1GBE_COMP_CODES,
+		                                     &comp_codes_1g);
 
-		/*
-		 * ID  Module
-		 * ============
-		 * 0    SFP_DA_CU
-		 * 1    SFP_SR
-		 * 2    SFP_LR
-		 * 3	SFP_DA_CORE0 - 82599-specific
-		 * 4	SFP_DA_CORE1 - 82599-specific
-		 * 5	SFP_SR/LR_CORE0 - 82599-specific
-		 * 6	SFP_SR/LR_CORE1 - 82599-specific
-		 * 7	SFP_act_lmt_DA_CORE0 - 82599-specific
-		 * 8	SFP_act_lmt_DA_CORE1 - 82599-specific
-		 * 9	SFP_1g_cu_CORE0 - 82599-specific
-		 * 10	SFP_1g_cu_CORE1 - 82599-specific
-		 */
+		if (status == IXGBE_ERR_SWFW_SYNC ||
+		    status == IXGBE_ERR_I2C ||
+		    status == IXGBE_ERR_SFP_NOT_PRESENT)
+			goto err_read_i2c_eeprom;
+
+		status = hw->phy.ops.read_i2c_eeprom(hw,
+		                                     IXGBE_SFF_10GBE_COMP_CODES,
+		                                     &comp_codes_10g);
+
+		if (status == IXGBE_ERR_SWFW_SYNC ||
+		    status == IXGBE_ERR_I2C ||
+		    status == IXGBE_ERR_SFP_NOT_PRESENT)
+			goto err_read_i2c_eeprom;
+		status = hw->phy.ops.read_i2c_eeprom(hw,
+		                                     IXGBE_SFF_CABLE_TECHNOLOGY,
+		                                     &cable_tech);
+
+		if (status == IXGBE_ERR_SWFW_SYNC ||
+		    status == IXGBE_ERR_I2C ||
+		    status == IXGBE_ERR_SFP_NOT_PRESENT)
+			goto err_read_i2c_eeprom;
+
+		 /* ID Module
+		  * =========
+		  * 0   SFP_DA_CU
+		  * 1   SFP_SR
+		  * 2   SFP_LR
+		  * 3   SFP_DA_CORE0 - 82599-specific
+		  * 4   SFP_DA_CORE1 - 82599-specific
+		  * 5   SFP_SR/LR_CORE0 - 82599-specific
+		  * 6   SFP_SR/LR_CORE1 - 82599-specific
+		  * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
+		  * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
+		  * 9   SFP_1g_cu_CORE0 - 82599-specific
+		  * 10  SFP_1g_cu_CORE1 - 82599-specific
+		  */
 		if (hw->mac.type == ixgbe_mac_82598EB) {
 			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 				hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
@@ -1014,40 +1011,42 @@
 			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
 				if (hw->bus.lan_id == 0)
 					hw->phy.sfp_type =
-					    ixgbe_sfp_type_da_cu_core0;
+					             ixgbe_sfp_type_da_cu_core0;
 				else
 					hw->phy.sfp_type =
-					    ixgbe_sfp_type_da_cu_core1;
+					             ixgbe_sfp_type_da_cu_core1;
 			} else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
 				hw->phy.ops.read_i2c_eeprom(
-				    hw, IXGBE_SFF_CABLE_SPEC_COMP, &cable_spec);
+						hw, IXGBE_SFF_CABLE_SPEC_COMP,
+						&cable_spec);
 				if (cable_spec &
 				    IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
 					if (hw->bus.lan_id == 0)
-					hw->phy.sfp_type =
-					    ixgbe_sfp_type_da_act_lmt_core0;
+						hw->phy.sfp_type =
+						ixgbe_sfp_type_da_act_lmt_core0;
 					else
+						hw->phy.sfp_type =
+						ixgbe_sfp_type_da_act_lmt_core1;
+				} else {
 					hw->phy.sfp_type =
-					    ixgbe_sfp_type_da_act_lmt_core1;
-				} else
-					hw->phy.sfp_type =
-					    ixgbe_sfp_type_unknown;
+					                ixgbe_sfp_type_unknown;
+				}
 			} else if (comp_codes_10g &
-			    (IXGBE_SFF_10GBASESR_CAPABLE |
-			    IXGBE_SFF_10GBASELR_CAPABLE)) {
+				   (IXGBE_SFF_10GBASESR_CAPABLE |
+				    IXGBE_SFF_10GBASELR_CAPABLE)) {
 				if (hw->bus.lan_id == 0)
 					hw->phy.sfp_type =
-					    ixgbe_sfp_type_srlr_core0;
+					              ixgbe_sfp_type_srlr_core0;
 				else
 					hw->phy.sfp_type =
-					    ixgbe_sfp_type_srlr_core1;
+					              ixgbe_sfp_type_srlr_core1;
 			} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
 				if (hw->bus.lan_id == 0)
 					hw->phy.sfp_type =
-					    ixgbe_sfp_type_1g_cu_core0;
+						ixgbe_sfp_type_1g_cu_core0;
 				else
 					hw->phy.sfp_type =
-					    ixgbe_sfp_type_1g_cu_core1;
+						ixgbe_sfp_type_1g_cu_core1;
 			} else {
 				hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 			}
@@ -1054,37 +1053,56 @@
 		}
 
 		if (hw->phy.sfp_type != stored_sfp_type)
-			hw->phy.sfp_setup_needed = true;
+			hw->phy.sfp_setup_needed = TRUE;
 
 		/* Determine if the SFP+ PHY is dual speed or not. */
-		hw->phy.multispeed_fiber = false;
+		hw->phy.multispeed_fiber = FALSE;
 		if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
-		    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
-		    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
-		    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
-			hw->phy.multispeed_fiber = true;
+		   (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
+		   ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
+		   (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
+			hw->phy.multispeed_fiber = TRUE;
 
 		/* Determine PHY vendor */
 		if (hw->phy.type != ixgbe_phy_nl) {
 			hw->phy.id = identifier;
-			hw->phy.ops.read_i2c_eeprom(hw,
-			    IXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]);
-			hw->phy.ops.read_i2c_eeprom(hw,
-			    IXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]);
-			hw->phy.ops.read_i2c_eeprom(hw,
-			    IXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]);
+			status = hw->phy.ops.read_i2c_eeprom(hw,
+			                            IXGBE_SFF_VENDOR_OUI_BYTE0,
+			                            &oui_bytes[0]);
 
+			if (status == IXGBE_ERR_SWFW_SYNC ||
+			    status == IXGBE_ERR_I2C ||
+			    status == IXGBE_ERR_SFP_NOT_PRESENT)
+				goto err_read_i2c_eeprom;
+
+			status = hw->phy.ops.read_i2c_eeprom(hw,
+			                            IXGBE_SFF_VENDOR_OUI_BYTE1,
+			                            &oui_bytes[1]);
+
+			if (status == IXGBE_ERR_SWFW_SYNC ||
+			    status == IXGBE_ERR_I2C ||
+			    status == IXGBE_ERR_SFP_NOT_PRESENT)
+				goto err_read_i2c_eeprom;
+
+			status = hw->phy.ops.read_i2c_eeprom(hw,
+			                            IXGBE_SFF_VENDOR_OUI_BYTE2,
+			                            &oui_bytes[2]);
+
+			if (status == IXGBE_ERR_SWFW_SYNC ||
+			    status == IXGBE_ERR_I2C ||
+			    status == IXGBE_ERR_SFP_NOT_PRESENT)
+				goto err_read_i2c_eeprom;
+
 			vendor_oui =
-			    ((oui_bytes[0] <<
-			    IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
-			    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
-			    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
+			  ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
+			   (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
+			   (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
 
 			switch (vendor_oui) {
 			case IXGBE_SFF_VENDOR_OUI_TYCO:
 				if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 					hw->phy.type =
-					    ixgbe_phy_sfp_passive_tyco;
+					            ixgbe_phy_sfp_passive_tyco;
 				break;
 			case IXGBE_SFF_VENDOR_OUI_FTL:
 				if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
@@ -1101,10 +1119,10 @@
 			default:
 				if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 					hw->phy.type =
-					    ixgbe_phy_sfp_passive_unknown;
+					         ixgbe_phy_sfp_passive_unknown;
 				else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
 					hw->phy.type =
-					    ixgbe_phy_sfp_active_unknown;
+						ixgbe_phy_sfp_active_unknown;
 				else
 					hw->phy.type = ixgbe_phy_sfp_unknown;
 				break;
@@ -1118,10 +1136,10 @@
 			goto out;
 		}
 
-		/* Verify supporteed 1G SFP modules */
+		/* Verify supported 1G SFP modules */
 		if (comp_codes_10g == 0 &&
 		    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
-		    hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
+		      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
 			hw->phy.type = ixgbe_phy_sfp_unsupported;
 			status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 			goto out;
@@ -1136,7 +1154,7 @@
 		(void) ixgbe_get_device_caps(hw, &enforce_sfp);
 		if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
 		    !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
-		    (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
+		      (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
 			/* Make sure we're a supported PHY type */
 			if (hw->phy.type == ixgbe_phy_sfp_intel) {
 				status = IXGBE_SUCCESS;
@@ -1151,21 +1169,29 @@
 	}
 
 out:
-	return (status);
+	return status;
+
+err_read_i2c_eeprom:
+	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
+	if (hw->phy.type != ixgbe_phy_nl) {
+		hw->phy.id = 0;
+		hw->phy.type = ixgbe_phy_unknown;
+	}
+	return IXGBE_ERR_SFP_NOT_PRESENT;
 }
 
-
-/*
- * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
- * @hw: pointer to hardware structure
- * @list_offset: offset to the SFP ID list
- * @data_offset: offset to the SFP data block
+/**
+ *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
+ *  @hw: pointer to hardware structure
+ *  @list_offset: offset to the SFP ID list
+ *  @data_offset: offset to the SFP data block
  *
- * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
- * so it returns the offsets to the phy init sequence block.
- */
+ *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
+ *  so it returns the offsets to the phy init sequence block.
+ **/
 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
-    u16 *list_offset, u16 *data_offset)
+                                        u16 *list_offset,
+                                        u16 *data_offset)
 {
 	u16 sfp_id;
 	u16 sfp_type = hw->phy.sfp_type;
@@ -1173,14 +1199,14 @@
 	DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
 
 	if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
-		return (IXGBE_ERR_SFP_NOT_SUPPORTED);
+		return IXGBE_ERR_SFP_NOT_SUPPORTED;
 
 	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
-		return (IXGBE_ERR_SFP_NOT_PRESENT);
+		return IXGBE_ERR_SFP_NOT_PRESENT;
 
 	if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
 	    (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
-		return (IXGBE_ERR_SFP_NOT_SUPPORTED);
+		return IXGBE_ERR_SFP_NOT_SUPPORTED;
 
 	/*
 	 * Limiting active cables and 1G Phys must be initialized as
@@ -1190,7 +1216,7 @@
 	    sfp_type == ixgbe_sfp_type_1g_cu_core0)
 		sfp_type = ixgbe_sfp_type_srlr_core0;
 	else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
-	    sfp_type == ixgbe_sfp_type_1g_cu_core1)
+		 sfp_type == ixgbe_sfp_type_1g_cu_core1)
 		sfp_type = ixgbe_sfp_type_srlr_core1;
 
 	/* Read offset to PHY init contents */
@@ -1197,7 +1223,7 @@
 	hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
 
 	if ((!*list_offset) || (*list_offset == 0xFFFF))
-		return (IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT);
+		return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
 
 	/* Shift offset to first ID word */
 	(*list_offset)++;
@@ -1214,7 +1240,7 @@
 			hw->eeprom.ops.read(hw, *list_offset, data_offset);
 			if ((!*data_offset) || (*data_offset == 0xFFFF)) {
 				DEBUGOUT("SFP+ module not supported\n");
-				return (IXGBE_ERR_SFP_NOT_SUPPORTED);
+				return IXGBE_ERR_SFP_NOT_SUPPORTED;
 			} else {
 				break;
 			}
@@ -1221,65 +1247,65 @@
 		} else {
 			(*list_offset) += 2;
 			if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
-				return (IXGBE_ERR_PHY);
+				return IXGBE_ERR_PHY;
 		}
 	}
 
 	if (sfp_id == IXGBE_PHY_INIT_END_NL) {
 		DEBUGOUT("No matching SFP+ module found\n");
-		return (IXGBE_ERR_SFP_NOT_SUPPORTED);
+		return IXGBE_ERR_SFP_NOT_SUPPORTED;
 	}
 
-	return (IXGBE_SUCCESS);
+	return IXGBE_SUCCESS;
 }
 
-/*
- * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
- * @hw: pointer to hardware structure
- * @byte_offset: EEPROM byte offset to read
- * @eeprom_data: value read
+/**
+ *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: EEPROM byte offset to read
+ *  @eeprom_data: value read
  *
- * Performs byte read operation to SFP module's EEPROM over I2C interface.
- */
-s32
-ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
-    u8 *eeprom_data)
+ *  Performs byte read operation to SFP module's EEPROM over I2C interface.
+ **/
+s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
+                                  u8 *eeprom_data)
 {
 	DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
 
-	return (hw->phy.ops.read_i2c_byte(hw, byte_offset,
-	    IXGBE_I2C_EEPROM_DEV_ADDR, eeprom_data));
+	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
+	                                 IXGBE_I2C_EEPROM_DEV_ADDR,
+	                                 eeprom_data);
 }
 
-/*
- * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
- * @hw: pointer to hardware structure
- * @byte_offset: EEPROM byte offset to write
- * @eeprom_data: value to write
+/**
+ *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: EEPROM byte offset to write
+ *  @eeprom_data: value to write
  *
- * Performs byte write operation to SFP module's EEPROM over I2C interface.
- */
+ *  Performs byte write operation to SFP module's EEPROM over I2C interface.
+ **/
 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
-    u8 eeprom_data)
+                                   u8 eeprom_data)
 {
 	DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
 
-	return (hw->phy.ops.write_i2c_byte(hw, byte_offset,
-	    IXGBE_I2C_EEPROM_DEV_ADDR, eeprom_data));
+	return hw->phy.ops.write_i2c_byte(hw, byte_offset,
+	                                  IXGBE_I2C_EEPROM_DEV_ADDR,
+	                                  eeprom_data);
 }
 
-/*
- * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to read
- * @data: value read
+/**
+ *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: byte offset to read
+ *  @data: value read
  *
- * Performs byte read operation to SFP module's EEPROM over I2C interface at
- * a specified deivce address.
- */
-s32
-ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
-    u8 dev_addr, u8 *data)
+ *  Performs byte read operation to SFP module's EEPROM over I2C interface at
+ *  a specified deivce address.
+ **/
+s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
+                                u8 dev_addr, u8 *data)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 max_retry = 10;
@@ -1350,26 +1376,26 @@
 			DEBUGOUT("I2C byte read error - Retrying.\n");
 		else
 			DEBUGOUT("I2C byte read error.\n");
+
 	} while (retry < max_retry);
 
 	ixgbe_release_swfw_sync(hw, swfw_mask);
 
 read_byte_out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
- * @hw: pointer to hardware structure
- * @byte_offset: byte offset to write
- * @data: value to write
+/**
+ *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
+ *  @hw: pointer to hardware structure
+ *  @byte_offset: byte offset to write
+ *  @data: value to write
  *
- * Performs byte write operation to SFP module's EEPROM over I2C interface at
- * a specified device address.
- */
-s32
-ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
-    u8 dev_addr, u8 data)
+ *  Performs byte write operation to SFP module's EEPROM over I2C interface at
+ *  a specified device address.
+ **/
+s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
+                                 u8 dev_addr, u8 data)
 {
 	s32 status = IXGBE_SUCCESS;
 	u32 max_retry = 1;
@@ -1430,17 +1456,16 @@
 	ixgbe_release_swfw_sync(hw, swfw_mask);
 
 write_byte_out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_i2c_start - Sets I2C start condition
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_i2c_start - Sets I2C start condition
+ *  @hw: pointer to hardware structure
  *
- * Sets I2C start condition (High -> Low on SDA while SCL is High)
- */
-static void
-ixgbe_i2c_start(struct ixgbe_hw *hw)
+ *  Sets I2C start condition (High -> Low on SDA while SCL is High)
+ **/
+static void ixgbe_i2c_start(struct ixgbe_hw *hw)
 {
 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
 
@@ -1462,16 +1487,16 @@
 
 	/* Minimum low period of clock is 4.7 us */
 	usec_delay(IXGBE_I2C_T_LOW);
+
 }
 
-/*
- * ixgbe_i2c_stop - Sets I2C stop condition
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_i2c_stop - Sets I2C stop condition
+ *  @hw: pointer to hardware structure
  *
- * Sets I2C stop condition (Low -> High on SDA while SCL is High)
- */
-static void
-ixgbe_i2c_stop(struct ixgbe_hw *hw)
+ *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
+ **/
+static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
 {
 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
 
@@ -1486,19 +1511,18 @@
 
 	(void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
 
-	/* bus free time between stop and start (4.7us) */
+	/* bus free time between stop and start (4.7us)*/
 	usec_delay(IXGBE_I2C_T_BUF);
 }
 
-/*
- * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
- * @hw: pointer to hardware structure
- * @data: data byte to clock in
+/**
+ *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
+ *  @hw: pointer to hardware structure
+ *  @data: data byte to clock in
  *
- * Clocks in one byte data via I2C data/clock
- */
-static s32
-ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
+ *  Clocks in one byte data via I2C data/clock
+ **/
+static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
 {
 	s32 status = IXGBE_SUCCESS;
 	s32 i;
@@ -1508,24 +1532,23 @@
 
 	for (i = 7; i >= 0; i--) {
 		status = ixgbe_clock_in_i2c_bit(hw, &bit);
-		*data |= bit<<i;
+		*data |= bit << i;
 
 		if (status != IXGBE_SUCCESS)
 			break;
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
- * @hw: pointer to hardware structure
- * @data: data byte clocked out
+/**
+ *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
+ *  @hw: pointer to hardware structure
+ *  @data: data byte clocked out
  *
- * Clocks out one byte data via I2C data/clock
- */
-static s32
-ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
+ *  Clocks out one byte data via I2C data/clock
+ **/
+static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
 {
 	s32 status = IXGBE_SUCCESS;
 	s32 i;
@@ -1547,17 +1570,16 @@
 	i2cctl |= IXGBE_I2C_DATA_OUT;
 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_get_i2c_ack - Polls for I2C ACK
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_get_i2c_ack - Polls for I2C ACK
+ *  @hw: pointer to hardware structure
  *
- * Clocks in/out one bit via I2C data/clock
- */
-static s32
-ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
+ *  Clocks in/out one bit via I2C data/clock
+ **/
+static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
 {
 	s32 status;
 	u32 i = 0;
@@ -1575,10 +1597,8 @@
 	/* Minimum high period of clock is 4us */
 	usec_delay(IXGBE_I2C_T_HIGH);
 
-	/*
-	 * Poll for ACK.  Note that ACK in I2C spec is
-	 * transition from 1 to 0
-	 */
+	/* Poll for ACK.  Note that ACK in I2C spec is
+	 * transition from 1 to 0 */
 	for (i = 0; i < timeout; i++) {
 		i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
 		ack = ixgbe_get_i2c_data(&i2cctl);
@@ -1599,18 +1619,17 @@
 	usec_delay(IXGBE_I2C_T_LOW);
 
 out:
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
- * @hw: pointer to hardware structure
- * @data: read data value
+/**
+ *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
+ *  @hw: pointer to hardware structure
+ *  @data: read data value
  *
- * Clocks in one bit via I2C data/clock
- */
-static s32
-ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
+ *  Clocks in one bit via I2C data/clock
+ **/
+static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
 {
 	s32 status;
 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
@@ -1630,18 +1649,17 @@
 	/* Minimum low period of clock is 4.7 us */
 	usec_delay(IXGBE_I2C_T_LOW);
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
- * @hw: pointer to hardware structure
- * @data: data value to write
+/**
+ *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
+ *  @hw: pointer to hardware structure
+ *  @data: data value to write
  *
- * Clocks out one bit via I2C data/clock
- */
-static s32
-ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
+ *  Clocks out one bit via I2C data/clock
+ **/
+static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
 {
 	s32 status;
 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
@@ -1657,8 +1675,7 @@
 
 		ixgbe_lower_i2c_clk(hw, &i2cctl);
 
-		/*
-		 * Minimum low period of clock is 4.7 us.
+		/* Minimum low period of clock is 4.7 us.
 		 * This also takes care of the data hold time.
 		 */
 		usec_delay(IXGBE_I2C_T_LOW);
@@ -1667,18 +1684,16 @@
 		DEBUGOUT1("I2C data was not set to %X\n", data);
 	}
 
-	return (status);
+	return status;
 }
-
-/*
- * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
- * @hw: pointer to hardware structure
- * @i2cctl: Current value of I2CCTL register
+/**
+ *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
+ *  @hw: pointer to hardware structure
+ *  @i2cctl: Current value of I2CCTL register
  *
- * Raises the I2C clock line '0'->'1'
- */
-static s32
-ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
+ *  Raises the I2C clock line '0'->'1'
+ **/
+static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
 {
 	s32 status = IXGBE_SUCCESS;
 
@@ -1691,19 +1706,19 @@
 	/* SCL rise time (1000ns) */
 	usec_delay(IXGBE_I2C_T_RISE);
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
- * @hw: pointer to hardware structure
- * @i2cctl: Current value of I2CCTL register
+/**
+ *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
+ *  @hw: pointer to hardware structure
+ *  @i2cctl: Current value of I2CCTL register
  *
- * Lowers the I2C clock line '1'->'0'
- */
-static void
-ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
+ *  Lowers the I2C clock line '1'->'0'
+ **/
+static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
 {
+
 	DEBUGFUNC("ixgbe_lower_i2c_clk");
 
 	*i2cctl &= ~IXGBE_I2C_CLK_OUT;
@@ -1714,16 +1729,15 @@
 	usec_delay(IXGBE_I2C_T_FALL);
 }
 
-/*
- * ixgbe_set_i2c_data - Sets the I2C data bit
- * @hw: pointer to hardware structure
- * @i2cctl: Current value of I2CCTL register
- * @data: I2C data value (0 or 1) to set
+/**
+ *  ixgbe_set_i2c_data - Sets the I2C data bit
+ *  @hw: pointer to hardware structure
+ *  @i2cctl: Current value of I2CCTL register
+ *  @data: I2C data value (0 or 1) to set
  *
- * Sets the I2C data bit
- */
-static s32
-ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
+ *  Sets the I2C data bit
+ **/
+static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
 {
 	s32 status = IXGBE_SUCCESS;
 
@@ -1746,18 +1760,17 @@
 		DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
 	}
 
-	return (status);
+	return status;
 }
 
-/*
- * ixgbe_get_i2c_data - Reads the I2C SDA data bit
- * @hw: pointer to hardware structure
- * @i2cctl: Current value of I2CCTL register
+/**
+ *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
+ *  @hw: pointer to hardware structure
+ *  @i2cctl: Current value of I2CCTL register
  *
- * Returns the I2C data bit value
- */
-static bool
-ixgbe_get_i2c_data(u32 *i2cctl)
+ *  Returns the I2C data bit value
+ **/
+static bool ixgbe_get_i2c_data(u32 *i2cctl)
 {
 	bool data;
 
@@ -1768,18 +1781,17 @@
 	else
 		data = 0;
 
-	return (data);
+	return data;
 }
 
-/*
- * ixgbe_i2c_bus_clear - Clears the I2C bus
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_i2c_bus_clear - Clears the I2C bus
+ *  @hw: pointer to hardware structure
  *
- * Clears the I2C bus by sending nine clock pulses.
- * Used when data line is stuck low.
- */
-void
-ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
+ *  Clears the I2C bus by sending nine clock pulses.
+ *  Used when data line is stuck low.
+ **/
+void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
 {
 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
 	u32 i;
@@ -1798,7 +1810,7 @@
 
 		ixgbe_lower_i2c_clk(hw, &i2cctl);
 
-		/* Min low period of clock is 4.7us */
+		/* Min low period of clock is 4.7us*/
 		usec_delay(IXGBE_I2C_T_LOW);
 	}
 
@@ -1808,14 +1820,13 @@
 	ixgbe_i2c_stop(hw);
 }
 
-/*
- * ixgbe_tn_check_overtemp - Checks if an overtemp occured.
- * @hw: pointer to hardware structure
+/**
+ *  ixgbe_tn_check_overtemp - Checks if an overtemp occured.
+ *  @hw: pointer to hardware structure
  *
- * Checks if the LASI temp alarm status was triggered due to overtemp
- */
-s32
-ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
+ *  Checks if the LASI temp alarm status was triggered due to overtemp
+ **/
+s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_SUCCESS;
 	u16 phy_data = 0;
@@ -1827,7 +1838,7 @@
 
 	/* Check that the LASI temp alarm status was triggered */
 	hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
-	    IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
+			     IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
 
 	if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
 		goto out;
@@ -1834,5 +1845,5 @@
 
 	status = IXGBE_ERR_OVERTEMP;
 out:
-	return (status);
+	return status;
 }
--- old/usr/src/uts/common/io/ixgbe/ixgbe_phy.h	Wed Sep  7 11:32:39 2011
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_phy.h	Wed Sep  7 11:32:38 2011
@@ -1,98 +1,99 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at:
- *      http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When using or redistributing this file, you may do so under the
- * License only. No other modification of this header is permitted.
- *
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
+/******************************************************************************
 
-/*
- * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
- */
+  Copyright (c) 2001-2010, Intel Corporation 
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without 
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice, 
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright 
+      notice, this list of conditions and the following disclaimer in the 
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its 
+      contributors may be used to endorse or promote products derived from 
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
 
-/*
- * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
- */
+******************************************************************************/
+/*$FreeBSD$*/
 
-/* IntelVersion: 1.43 scm_061610_003709 */
+#ifndef _IXGBE_PHY_H_
+#define _IXGBE_PHY_H_
 
-#ifndef _IXGBE_PHY_H
-#define	_IXGBE_PHY_H
-
 #include "ixgbe_type.h"
+#define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0
 
-#define	IXGBE_I2C_EEPROM_DEV_ADDR	0xA0
-
 /* EEPROM byte offsets */
-#define	IXGBE_SFF_IDENTIFIER		0x0
-#define	IXGBE_SFF_IDENTIFIER_SFP	0x3
-#define	IXGBE_SFF_VENDOR_OUI_BYTE0	0x25
-#define	IXGBE_SFF_VENDOR_OUI_BYTE1	0x26
-#define	IXGBE_SFF_VENDOR_OUI_BYTE2	0x27
-#define	IXGBE_SFF_1GBE_COMP_CODES	0x6
-#define	IXGBE_SFF_10GBE_COMP_CODES	0x3
-#define	IXGBE_SFF_CABLE_TECHNOLOGY	0x8
-#define	IXGBE_SFF_CABLE_SPEC_COMP	0x3C
+#define IXGBE_SFF_IDENTIFIER         0x0
+#define IXGBE_SFF_IDENTIFIER_SFP     0x3
+#define IXGBE_SFF_VENDOR_OUI_BYTE0   0x25
+#define IXGBE_SFF_VENDOR_OUI_BYTE1   0x26
+#define IXGBE_SFF_VENDOR_OUI_BYTE2   0x27
+#define IXGBE_SFF_1GBE_COMP_CODES    0x6
+#define IXGBE_SFF_10GBE_COMP_CODES   0x3
+#define IXGBE_SFF_CABLE_TECHNOLOGY   0x8
+#define IXGBE_SFF_CABLE_SPEC_COMP    0x3C
 
 /* Bitmasks */
-#define	IXGBE_SFF_DA_PASSIVE_CABLE	0x4
-#define	IXGBE_SFF_DA_ACTIVE_CABLE	0x8
-#define	IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING	0x4
-#define	IXGBE_SFF_1GBASESX_CAPABLE	0x1
-#define	IXGBE_SFF_1GBASELX_CAPABLE	0x2
-#define	IXGBE_SFF_1GBASET_CAPABLE	0x8
-#define	IXGBE_SFF_10GBASESR_CAPABLE	0x10
-#define	IXGBE_SFF_10GBASELR_CAPABLE	0x20
-#define	IXGBE_I2C_EEPROM_READ_MASK	0x100
-#define	IXGBE_I2C_EEPROM_STATUS_MASK	0x3
-#define	IXGBE_I2C_EEPROM_STATUS_NO_OPERATION	0x0
-#define	IXGBE_I2C_EEPROM_STATUS_PASS	0x1
-#define	IXGBE_I2C_EEPROM_STATUS_FAIL	0x2
-#define	IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS	0x3
+#define IXGBE_SFF_DA_PASSIVE_CABLE           0x4
+#define IXGBE_SFF_DA_ACTIVE_CABLE            0x8
+#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING    0x4
+#define IXGBE_SFF_1GBASESX_CAPABLE           0x1
+#define IXGBE_SFF_1GBASELX_CAPABLE           0x2
+#define IXGBE_SFF_1GBASET_CAPABLE            0x8
+#define IXGBE_SFF_10GBASESR_CAPABLE          0x10
+#define IXGBE_SFF_10GBASELR_CAPABLE          0x20
+#define IXGBE_I2C_EEPROM_READ_MASK           0x100
+#define IXGBE_I2C_EEPROM_STATUS_MASK         0x3
+#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
+#define IXGBE_I2C_EEPROM_STATUS_PASS         0x1
+#define IXGBE_I2C_EEPROM_STATUS_FAIL         0x2
+#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS  0x3
 
 /* Flow control defines */
-#define	IXGBE_TAF_SYM_PAUSE	0x400
-#define	IXGBE_TAF_ASM_PAUSE	0x800
+#define IXGBE_TAF_SYM_PAUSE                  0x400
+#define IXGBE_TAF_ASM_PAUSE                  0x800
 
 /* Bit-shift macros */
-#define	IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT	24
-#define	IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT	16
-#define	IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT	8
+#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT    24
+#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT    16
+#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT    8
 
 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
-#define	IXGBE_SFF_VENDOR_OUI_TYCO	0x00407600
-#define	IXGBE_SFF_VENDOR_OUI_FTL	0x00906500
-#define	IXGBE_SFF_VENDOR_OUI_AVAGO	0x00176A00
-#define	IXGBE_SFF_VENDOR_OUI_INTEL	0x001B2100
+#define IXGBE_SFF_VENDOR_OUI_TYCO     0x00407600
+#define IXGBE_SFF_VENDOR_OUI_FTL      0x00906500
+#define IXGBE_SFF_VENDOR_OUI_AVAGO    0x00176A00
+#define IXGBE_SFF_VENDOR_OUI_INTEL    0x001B2100
 
 /* I2C SDA and SCL timing parameters for standard mode */
-#define	IXGBE_I2C_T_HD_STA	4
-#define	IXGBE_I2C_T_LOW		5
-#define	IXGBE_I2C_T_HIGH	4
-#define	IXGBE_I2C_T_SU_STA	5
-#define	IXGBE_I2C_T_HD_DATA	5
-#define	IXGBE_I2C_T_SU_DATA	1
-#define	IXGBE_I2C_T_RISE	1
-#define	IXGBE_I2C_T_FALL	1
-#define	IXGBE_I2C_T_SU_STO	4
-#define	IXGBE_I2C_T_BUF		5
+#define IXGBE_I2C_T_HD_STA  4
+#define IXGBE_I2C_T_LOW     5
+#define IXGBE_I2C_T_HIGH    4
+#define IXGBE_I2C_T_SU_STA  5
+#define IXGBE_I2C_T_HD_DATA 5
+#define IXGBE_I2C_T_SU_DATA 1
+#define IXGBE_I2C_T_RISE    1
+#define IXGBE_I2C_T_FALL    1
+#define IXGBE_I2C_T_SU_STO  4
+#define IXGBE_I2C_T_BUF     5
 
-#define	IXGBE_TN_LASI_STATUS_REG	0x9005
-#define	IXGBE_TN_LASI_STATUS_TEMP_ALARM	0x0008
+#define IXGBE_TN_LASI_STATUS_REG        0x9005
+#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
 
 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
@@ -101,36 +102,40 @@
 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
-    u32 device_type, u16 *phy_data);
+                               u32 device_type, u16 *phy_data);
 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
-    u32 device_type, u16 phy_data);
+                                u32 device_type, u16 phy_data);
 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
-    ixgbe_link_speed speed, bool autoneg, bool autoneg_wait_to_complete);
+                                       ixgbe_link_speed speed,
+                                       bool autoneg,
+                                       bool autoneg_wait_to_complete);
 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
-    ixgbe_link_speed *speed, bool *autoneg);
+                                             ixgbe_link_speed *speed,
+                                             bool *autoneg);
 
 /* PHY specific */
 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
-    ixgbe_link_speed *speed, bool *link_up);
+                             ixgbe_link_speed *speed,
+                             bool *link_up);
 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
-    u16 *firmware_version);
+                                       u16 *firmware_version);
 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
-    u16 *firmware_version);
+                                       u16 *firmware_version);
 
 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
-    u16 *list_offset, u16 *data_offset);
+                                        u16 *list_offset,
+                                        u16 *data_offset);
 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
-    u8 dev_addr, u8 *data);
+                                u8 dev_addr, u8 *data);
 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
-    u8 dev_addr, u8 data);
+                                 u8 dev_addr, u8 data);
 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
-    u8 *eeprom_data);
+                                  u8 *eeprom_data);
 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
-    u8 eeprom_data);
-
-#endif /* _IXGBE_PHY_H */
+                                   u8 eeprom_data);
+#endif /* _IXGBE_PHY_H_ */
--- old/usr/src/uts/common/io/ixgbe/ixgbe_type.h	Wed Sep  7 11:32:39 2011
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_type.h	Wed Sep  7 11:32:39 2011
@@ -1,173 +1,177 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License (the "License").
- * You may not use this file except in compliance with the License.
- *
- * You can obtain a copy of the license at:
- *      http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When using or redistributing this file, you may do so under the
- * License only. No other modification of this header is permitted.
- *
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
+/******************************************************************************
 
-/*
- * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
- */
+  Copyright (c) 2001-2010, Intel Corporation 
+  All rights reserved.
+  
+  Redistribution and use in source and binary forms, with or without 
+  modification, are permitted provided that the following conditions are met:
+  
+   1. Redistributions of source code must retain the above copyright notice, 
+      this list of conditions and the following disclaimer.
+  
+   2. Redistributions in binary form must reproduce the above copyright 
+      notice, this list of conditions and the following disclaimer in the 
+      documentation and/or other materials provided with the distribution.
+  
+   3. Neither the name of the Intel Corporation nor the names of its 
+      contributors may be used to endorse or promote products derived from 
+      this software without specific prior written permission.
+  
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+  POSSIBILITY OF SUCH DAMAGE.
 
-/*
- * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
- */
+******************************************************************************/
 
-/* IntelVersion: 1.397 scm_061610_003709 */
+#ifndef _IXGBE_TYPE_H_
+#define _IXGBE_TYPE_H_
 
-#ifndef _IXGBE_TYPE_H
-#define	_IXGBE_TYPE_H
-
 #include "ixgbe_osdep.h"
 
+
 /* Vendor ID */
-#define	IXGBE_INTEL_VENDOR_ID   0x8086
+#define IXGBE_INTEL_VENDOR_ID   0x8086
 
 /* Device IDs */
-#define	IXGBE_DEV_ID_82598			0x10B6
-#define	IXGBE_DEV_ID_82598_BX			0x1508
-#define	IXGBE_DEV_ID_82598AF_DUAL_PORT		0x10C6
-#define	IXGBE_DEV_ID_82598AF_SINGLE_PORT	0x10C7
-#define	IXGBE_DEV_ID_82598AT			0x10C8
-#define	IXGBE_DEV_ID_82598AT2			0x150B
-#define	IXGBE_DEV_ID_82598EB_SFP_LOM		0x10DB
-#define	IXGBE_DEV_ID_82598EB_CX4		0x10DD
-#define	IXGBE_DEV_ID_82598_CX4_DUAL_PORT	0x10EC
-#define	IXGBE_DEV_ID_82598_DA_DUAL_PORT		0x10F1
-#define	IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM	0x10E1
-#define	IXGBE_DEV_ID_82598EB_XF_LR		0x10F4
-#define	IXGBE_DEV_ID_82599_KX4			0x10F7
-#define	IXGBE_DEV_ID_82599_KX4_MEZZ		0x1514
-#define	IXGBE_DEV_ID_82599_KR			0x1517
-#define	IXGBE_DEV_ID_82599_COMBO_BACKPLANE	0x10F8
-#define	IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ	0x000C
-#define	IXGBE_DEV_ID_82599_CX4			0x10F9
-#define	IXGBE_DEV_ID_82599_SFP			0x10FB
-#define	IXGBE_DEV_ID_82599_SFP_EM		0x1507
-#define	IXGBE_DEV_ID_82599_XAUI_LOM		0x10FC
-#define	IXGBE_DEV_ID_82599_T3_LOM		0x151C
+#define IXGBE_DEV_ID_82598               0x10B6
+#define IXGBE_DEV_ID_82598_BX            0x1508
+#define IXGBE_DEV_ID_82598AF_DUAL_PORT   0x10C6
+#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
+#define IXGBE_DEV_ID_82598AT             0x10C8
+#define IXGBE_DEV_ID_82598AT2            0x150B
+#define IXGBE_DEV_ID_82598EB_SFP_LOM     0x10DB
+#define IXGBE_DEV_ID_82598EB_CX4         0x10DD
+#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
+#define IXGBE_DEV_ID_82598_DA_DUAL_PORT  0x10F1
+#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM      0x10E1
+#define IXGBE_DEV_ID_82598EB_XF_LR       0x10F4
+#define IXGBE_DEV_ID_82599_KX4  0x10F7
+#define IXGBE_DEV_ID_82599_KX4_MEZZ      0x1514
+#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE      0x10F8
+#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ       0x000C
+#define IXGBE_DEV_ID_82599_CX4  0x10F9
+#define IXGBE_DEV_ID_82599_SFP  0x10FB
+#define IXGBE_SUBDEV_ID_82599_SFP        0x11A9
+#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE       0x152A
+#define IXGBE_DEV_ID_82599_SFP_FCOE      0x1529
+#define IXGBE_DEV_ID_82599_XAUI_LOM      0x10FC
+#define IXGBE_DEV_ID_82599_T3_LOM        0x151C
+#define IXGBE_DEV_ID_82599_VF   0x10ED
 
 /* General Registers */
-#define	IXGBE_CTRL	0x00000
-#define	IXGBE_STATUS	0x00008
-#define	IXGBE_CTRL_EXT	0x00018
-#define	IXGBE_ESDP	0x00020
-#define	IXGBE_EODSDP	0x00028
-#define	IXGBE_I2CCTL	0x00028
-#define	IXGBE_LEDCTL	0x00200
-#define	IXGBE_FRTIMER	0x00048
-#define	IXGBE_TCPTIMER	0x0004C
-#define	IXGBE_CORESPARE	0x00600
-#define	IXGBE_EXVET	0x05078
+#define IXGBE_CTRL      0x00000
+#define IXGBE_STATUS    0x00008
+#define IXGBE_CTRL_EXT  0x00018
+#define IXGBE_ESDP      0x00020
+#define IXGBE_EODSDP    0x00028
+#define IXGBE_I2CCTL    0x00028
+#define IXGBE_LEDCTL    0x00200
+#define IXGBE_FRTIMER   0x00048
+#define IXGBE_TCPTIMER  0x0004C
+#define IXGBE_CORESPARE 0x00600
+#define IXGBE_EXVET     0x05078
 
 /* NVM Registers */
-#define	IXGBE_EEC	0x10010
-#define	IXGBE_EERD	0x10014
-#define	IXGBE_EEWR	0x10018
-#define	IXGBE_FLA	0x1001C
-#define	IXGBE_EEMNGCTL	0x10110
-#define	IXGBE_EEMNGDATA	0x10114
-#define	IXGBE_FLMNGCTL	0x10118
-#define	IXGBE_FLMNGDATA	0x1011C
-#define	IXGBE_FLMNGCNT	0x10120
-#define	IXGBE_FLOP	0x1013C
-#define	IXGBE_GRC	0x10200
+#define IXGBE_EEC       0x10010
+#define IXGBE_EERD      0x10014
+#define IXGBE_EEWR      0x10018
+#define IXGBE_FLA       0x1001C
+#define IXGBE_EEMNGCTL  0x10110
+#define IXGBE_EEMNGDATA 0x10114
+#define IXGBE_FLMNGCTL  0x10118
+#define IXGBE_FLMNGDATA 0x1011C
+#define IXGBE_FLMNGCNT  0x10120
+#define IXGBE_FLOP      0x1013C
+#define IXGBE_GRC       0x10200
 
 /* General Receive Control */
-#define	IXGBE_GRC_MNG	0x00000001 /* Manageability Enable */
-#define	IXGBE_GRC_APME	0x00000002 /* APM enabled in EEPROM */
+#define IXGBE_GRC_MNG   0x00000001 /* Manageability Enable */
+#define IXGBE_GRC_APME  0x00000002 /* APM enabled in EEPROM */
 
-#define	IXGBE_VPDDIAG0	0x10204
-#define	IXGBE_VPDDIAG1	0x10208
+#define IXGBE_VPDDIAG0  0x10204
+#define IXGBE_VPDDIAG1  0x10208
 
 /* I2CCTL Bit Masks */
-#define	IXGBE_I2C_CLK_IN	0x00000001
-#define	IXGBE_I2C_CLK_OUT	0x00000002
-#define	IXGBE_I2C_DATA_IN	0x00000004
-#define	IXGBE_I2C_DATA_OUT	0x00000008
+#define IXGBE_I2C_CLK_IN        0x00000001
+#define IXGBE_I2C_CLK_OUT       0x00000002
+#define IXGBE_I2C_DATA_IN       0x00000004
+#define IXGBE_I2C_DATA_OUT      0x00000008
 
 /* Interrupt Registers */
-#define	IXGBE_EICR	0x00800
-#define	IXGBE_EICS	0x00808
-#define	IXGBE_EIMS	0x00880
-#define	IXGBE_EIMC	0x00888
-#define	IXGBE_EIAC	0x00810
-#define	IXGBE_EIAM	0x00890
-#define	IXGBE_EICS_EX(_i)	(0x00A90 + (_i) * 4)
-#define	IXGBE_EIMS_EX(_i)	(0x00AA0 + (_i) * 4)
-#define	IXGBE_EIMC_EX(_i)	(0x00AB0 + (_i) * 4)
-#define	IXGBE_EIAM_EX(_i)	(0x00AD0 + (_i) * 4)
+#define IXGBE_EICR      0x00800
+#define IXGBE_EICS      0x00808
+#define IXGBE_EIMS      0x00880
+#define IXGBE_EIMC      0x00888
+#define IXGBE_EIAC      0x00810
+#define IXGBE_EIAM      0x00890
+#define IXGBE_EICS_EX(_i)       (0x00A90 + (_i) * 4)
+#define IXGBE_EIMS_EX(_i)       (0x00AA0 + (_i) * 4)
+#define IXGBE_EIMC_EX(_i)       (0x00AB0 + (_i) * 4)
+#define IXGBE_EIAM_EX(_i)       (0x00AD0 + (_i) * 4)
 /* 82599 EITR is only 12 bits, with the lower 3 always zero */
 /*
  * 82598 EITR is 16 bits but set the limits based on the max
  * supported by all ixgbe hardware
  */
-#define	IXGBE_MAX_INT_RATE	488281
-#define	IXGBE_MIN_INT_RATE	956
-#define	IXGBE_MAX_EITR		0x00000FF8
-#define	IXGBE_MIN_EITR		8
-#define	IXGBE_EITR(_i)	(((_i) <= 23) ? \
-	(0x00820 + ((_i) * 4)) : (0x012300 + (((_i) - 24) * 4)))
-#define	IXGBE_EITR_ITR_INT_MASK	0x00000FF8
-#define	IXGBE_EITR_LLI_MOD	0x00008000
-#define	IXGBE_EITR_CNT_WDIS	0x80000000
-#define	IXGBE_IVAR(_i)	(0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
-#define	IXGBE_IVAR_MISC	0x00A00 /* misc MSI-X interrupt causes */
-#define	IXGBE_EITRSEL	0x00894
-#define	IXGBE_MSIXT	0x00000 /* MSI-X Table. 0x0000 - 0x01C */
-#define	IXGBE_MSIXPBA	0x02000 /* MSI-X Pending bit array */
-#define	IXGBE_PBACL(_i)	(((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
-#define	IXGBE_GPIE	0x00898
+#define IXGBE_MAX_INT_RATE      488281
+#define IXGBE_MIN_INT_RATE      956
+#define IXGBE_MAX_EITR          0x00000FF8
+#define IXGBE_MIN_EITR          8
+#define IXGBE_EITR(_i)  (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
+                         (0x012300 + (((_i) - 24) * 4)))
+#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
+#define IXGBE_EITR_LLI_MOD      0x00008000
+#define IXGBE_EITR_CNT_WDIS     0x80000000
+#define IXGBE_IVAR(_i)  (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
+#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
+#define IXGBE_EITRSEL   0x00894
+#define IXGBE_MSIXT     0x00000 /* MSI-X Table. 0x0000 - 0x01C */
+#define IXGBE_MSIXPBA   0x02000 /* MSI-X Pending bit array */
+#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
+#define IXGBE_GPIE      0x00898
 
 /* Flow Control Registers */
-#define	IXGBE_FCADBUL	0x03210
-#define	IXGBE_FCADBUH	0x03214
-#define	IXGBE_FCAMACL	0x04328
-#define	IXGBE_FCAMACH	0x0432C
-#define	IXGBE_FCRTH_82599(_i)	(0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_FCRTL_82599(_i)	(0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_PFCTOP    0x03008
-#define	IXGBE_FCTTV(_i)	(0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
-#define	IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
-#define	IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
-#define	IXGBE_FCRTV	0x032A0
-#define	IXGBE_FCCFG	0x03D00
-#define	IXGBE_TFCS	0x0CE00
+#define IXGBE_FCADBUL   0x03210
+#define IXGBE_FCADBUH   0x03214
+#define IXGBE_FCAMACL   0x04328
+#define IXGBE_FCAMACH   0x0432C
+#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_PFCTOP    0x03008
+#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
+#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
+#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
+#define IXGBE_FCRTV     0x032A0
+#define IXGBE_FCCFG     0x03D00
+#define IXGBE_TFCS      0x0CE00
 
 /* Receive DMA Registers */
-#define	IXGBE_RDBAL(_i)		(((_i) < 64) ? \
-	(0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40)))
-#define	IXGBE_RDBAH(_i)		(((_i) < 64) ? \
-	(0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40)))
-#define	IXGBE_RDLEN(_i)		(((_i) < 64) ? \
-	(0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40)))
-#define	IXGBE_RDH(_i)		(((_i) < 64) ? \
-	(0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40)))
-#define	IXGBE_RDT(_i)		(((_i) < 64) ? \
-	(0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40)))
-#define	IXGBE_RXDCTL(_i)	(((_i) < 64) ? \
-	(0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40)))
-#define	IXGBE_RSCCTL(_i)	(((_i) < 64) ? \
-	(0x0102C + ((_i) * 0x40)) : (0x0D02C + ((_i - 64) * 0x40)))
-#define	IXGBE_RSCDBU	0x03028
-#define	IXGBE_RDDCC	0x02F20
-#define	IXGBE_RXMEMWRAP	0x03190
-#define	IXGBE_STARCTRL	0x03024
+#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
+                         (0x0D000 + ((_i - 64) * 0x40)))
+#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
+                         (0x0D004 + ((_i - 64) * 0x40)))
+#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
+                         (0x0D008 + ((_i - 64) * 0x40)))
+#define IXGBE_RDH(_i)   (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
+                         (0x0D010 + ((_i - 64) * 0x40)))
+#define IXGBE_RDT(_i)   (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
+                         (0x0D018 + ((_i - 64) * 0x40)))
+#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
+                          (0x0D028 + ((_i - 64) * 0x40)))
+#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
+                          (0x0D02C + ((_i - 64) * 0x40)))
+#define IXGBE_RSCDBU     0x03028
+#define IXGBE_RDDCC      0x02F20
+#define IXGBE_RXMEMWRAP  0x03190
+#define IXGBE_STARCTRL   0x03024
 /*
  * Split and Replication Receive Control Registers
  * 00-15 : 0x02100 + n*4
@@ -174,9 +178,9 @@
  * 16-64 : 0x01014 + n*0x40
  * 64-127: 0x0D014 + (n-64)*0x40
  */
-#define	IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
-	(((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
-	(0x0D014 + ((_i - 64) * 0x40))))
+#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
+                          (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
+                          (0x0D014 + ((_i - 64) * 0x40))))
 /*
  * Rx DCA Control Register:
  * 00-15 : 0x02200 + n*4
@@ -183,1187 +187,1212 @@
  * 16-64 : 0x0100C + n*0x40
  * 64-127: 0x0D00C + (n-64)*0x40
  */
-#define	IXGBE_DCA_RXCTRL(_i)    (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
-	(((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
-	(0x0D00C + ((_i - 64) * 0x40))))
-#define	IXGBE_RDRXCTL    0x02F00
-#define	IXGBE_RDRXCTL_RSC_PUSH	0x80
-/* 8 of these 0x03C00 - 0x03C1C */
-#define	IXGBE_RXPBSIZE(_i)	(0x03C00 + ((_i) * 4))
-#define	IXGBE_RXCTRL	0x03000
-#define	IXGBE_DROPEN    0x03D04
-#define	IXGBE_RXPBSIZE_SHIFT 10
+#define IXGBE_DCA_RXCTRL(_i)    (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
+                                 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
+                                 (0x0D00C + ((_i - 64) * 0x40))))
+#define IXGBE_RDRXCTL           0x02F00
+#define IXGBE_RDRXCTL_RSC_PUSH  0x80
+#define IXGBE_RXPBSIZE(_i)      (0x03C00 + ((_i) * 4))
+                                             /* 8 of these 0x03C00 - 0x03C1C */
+#define IXGBE_RXCTRL    0x03000
+#define IXGBE_DROPEN    0x03D04
+#define IXGBE_RXPBSIZE_SHIFT 10
 
 /* Receive Registers */
-#define	IXGBE_RXCSUM    0x05000
-#define	IXGBE_RFCTL	0x05008
-#define	IXGBE_DRECCCTL	0x02F08
-#define	IXGBE_DRECCCTL_DISABLE	0
+#define IXGBE_RXCSUM    0x05000
+#define IXGBE_RFCTL     0x05008
+#define IXGBE_DRECCCTL  0x02F08
+#define IXGBE_DRECCCTL_DISABLE 0
+
 /* Multicast Table Array - 128 entries */
-#define	IXGBE_MTA(_i)   (0x05200 + ((_i) * 4))
-#define	IXGBE_RAL(_i)   (((_i) <= 15) ? \
-	(0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8)))
-#define	IXGBE_RAH(_i)   (((_i) <= 15) ? \
-	(0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8)))
-#define	IXGBE_MPSAR_LO(_i)	(0x0A600 + ((_i) * 8))
-#define	IXGBE_MPSAR_HI(_i)	(0x0A604 + ((_i) * 8))
+#define IXGBE_MTA(_i)   (0x05200 + ((_i) * 4))
+#define IXGBE_RAL(_i)   (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
+                         (0x0A200 + ((_i) * 8)))
+#define IXGBE_RAH(_i)   (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
+                         (0x0A204 + ((_i) * 8)))
+#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
+#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
 /* Packet split receive type */
-#define	IXGBE_PSRTYPE(_i)    (((_i) <= 15) ? \
-	(0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4)))
+#define IXGBE_PSRTYPE(_i)    (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
+                              (0x0EA00 + ((_i) * 4)))
 /* array of 4096 1-bit vlan filters */
-#define	IXGBE_VFTA(_i)  (0x0A000 + ((_i) * 4))
-/* array of 4096 4-bit vlan vmdq indices */
-#define	IXGBE_VFTAVIND(_j, _i)  (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
-#define	IXGBE_FCTRL	0x05080
-#define	IXGBE_VLNCTRL	0x05088
-#define	IXGBE_MCSTCTRL	0x05090
-#define	IXGBE_MRQC	0x05818
-#define	IXGBE_SAQF(_i)	(0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
-#define	IXGBE_DAQF(_i)	(0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
-#define	IXGBE_SDPQF(_i)	(0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
-#define	IXGBE_FTQF(_i)	(0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
-#define	IXGBE_ETQF(_i)	(0x05128 + ((_i) * 4)) /* EType Queue Filter */
-#define	IXGBE_ETQS(_i)	(0x0EC00 + ((_i) * 4)) /* EType Queue Select */
-#define	IXGBE_SYNQF	0x0EC30 /* SYN Packet Queue Filter */
-#define	IXGBE_RQTC	0x0EC70
-#define	IXGBE_MTQC	0x08120
-#define	IXGBE_VLVF(_i)	(0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */
-#define	IXGBE_VLVFB(_i)	(0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */
-#define	IXGBE_VMVIR(_i)	(0x08000 + ((_i) * 4))  /* 64 of these (0-63) */
-#define	IXGBE_VT_CTL	0x051B0
-#define	IXGBE_VFRE(_i)	(0x051E0 + ((_i) * 4))
-#define	IXGBE_VFTE(_i)	(0x08110 + ((_i) * 4))
-#define	IXGBE_QDE	0x2F04
-#define	IXGBE_VMOLR(_i)	(0x0F000 + ((_i) * 4)) /* 64 total */
-#define	IXGBE_UTA(_i)	(0x0F400 + ((_i) * 4))
-#define	IXGBE_VMRCTL(_i)	(0x0F600 + ((_i) * 4))
-#define	IXGBE_VMRVLAN(_i)	(0x0F610 + ((_i) * 4))
-#define	IXGBE_VMRVM(_i)		(0x0F630 + ((_i) * 4))
-#define	IXGBE_L34T_IMIR(_i)	(0x0E800 + ((_i) * 4))
-				/* 128 of these (0-127) */
-#define	IXGBE_LLITHRESH	0x0EC90
-#define	IXGBE_IMIR(_i)	(0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
-#define	IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
-#define	IXGBE_IMIRVP	0x05AC0
-#define	IXGBE_VMD_CTL	0x0581C
-#define	IXGBE_RETA(_i)	(0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
-#define	IXGBE_RSSRK(_i)	(0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
+#define IXGBE_VFTA(_i)  (0x0A000 + ((_i) * 4))
+/*array of 4096 4-bit vlan vmdq indices */
+#define IXGBE_VFTAVIND(_j, _i)  (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
+#define IXGBE_FCTRL     0x05080
+#define IXGBE_VLNCTRL   0x05088
+#define IXGBE_MCSTCTRL  0x05090
+#define IXGBE_MRQC      0x05818
+#define IXGBE_SAQF(_i)  (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
+#define IXGBE_DAQF(_i)  (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
+#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
+#define IXGBE_FTQF(_i)  (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
+#define IXGBE_ETQF(_i)  (0x05128 + ((_i) * 4)) /* EType Queue Filter */
+#define IXGBE_ETQS(_i)  (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
+#define IXGBE_SYNQF     0x0EC30 /* SYN Packet Queue Filter */
+#define IXGBE_RQTC      0x0EC70
+#define IXGBE_MTQC      0x08120
+#define IXGBE_VLVF(_i)  (0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */
+#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */
+#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))  /* 64 of these (0-63) */
+#define IXGBE_VT_CTL    0x051B0
+#define IXGBE_VFRE(_i)  (0x051E0 + ((_i) * 4))
+#define IXGBE_VFTE(_i)  (0x08110 + ((_i) * 4))
+#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
+#define IXGBE_QDE       0x2F04
+#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
+#define IXGBE_UTA(_i)   (0x0F400 + ((_i) * 4))
+#define IXGBE_VMRCTL(_i)        (0x0F600 + ((_i) * 4))
+#define IXGBE_VMRVLAN(_i)       (0x0F610 + ((_i) * 4))
+#define IXGBE_VMRVM(_i)         (0x0F630 + ((_i) * 4))
+#define IXGBE_L34T_IMIR(_i)      (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
+#define IXGBE_LLITHRESH 0x0EC90
+#define IXGBE_IMIR(_i)  (0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
+#define IXGBE_IMIREXT(_i)       (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
+#define IXGBE_IMIRVP    0x05AC0
+#define IXGBE_VMD_CTL   0x0581C
+#define IXGBE_RETA(_i)  (0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
+#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
 
 /* Flow Director registers */
-#define	IXGBE_FDIRCTRL	0x0EE00
-#define	IXGBE_FDIRHKEY	0x0EE68
-#define	IXGBE_FDIRSKEY	0x0EE6C
-#define	IXGBE_FDIRDIP4M	0x0EE3C
-#define	IXGBE_FDIRSIP4M	0x0EE40
-#define	IXGBE_FDIRTCPM	0x0EE44
-#define	IXGBE_FDIRUDPM	0x0EE48
-#define	IXGBE_FDIRIP6M	0x0EE74
-#define	IXGBE_FDIRM	0x0EE70
+#define IXGBE_FDIRCTRL  0x0EE00
+#define IXGBE_FDIRHKEY  0x0EE68
+#define IXGBE_FDIRSKEY  0x0EE6C
+#define IXGBE_FDIRDIP4M 0x0EE3C
+#define IXGBE_FDIRSIP4M 0x0EE40
+#define IXGBE_FDIRTCPM  0x0EE44
+#define IXGBE_FDIRUDPM  0x0EE48
+#define IXGBE_FDIRIP6M  0x0EE74
+#define IXGBE_FDIRM     0x0EE70
 
 /* Flow Director Stats registers */
-#define	IXGBE_FDIRFREE	0x0EE38
-#define	IXGBE_FDIRLEN	0x0EE4C
-#define	IXGBE_FDIRUSTAT	0x0EE50
-#define	IXGBE_FDIRFSTAT	0x0EE54
-#define	IXGBE_FDIRMATCH	0x0EE58
-#define	IXGBE_FDIRMISS	0x0EE5C
+#define IXGBE_FDIRFREE  0x0EE38
+#define IXGBE_FDIRLEN   0x0EE4C
+#define IXGBE_FDIRUSTAT 0x0EE50
+#define IXGBE_FDIRFSTAT 0x0EE54
+#define IXGBE_FDIRMATCH 0x0EE58
+#define IXGBE_FDIRMISS  0x0EE5C
 
 /* Flow Director Programming registers */
-#define	IXGBE_FDIRSIPv6(_i)	(0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
-#define	IXGBE_FDIRIPSA	0x0EE18
-#define	IXGBE_FDIRIPDA	0x0EE1C
-#define	IXGBE_FDIRPORT	0x0EE20
-#define	IXGBE_FDIRVLAN	0x0EE24
-#define	IXGBE_FDIRHASH	0x0EE28
-#define	IXGBE_FDIRCMD	0x0EE2C
+#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
+#define IXGBE_FDIRIPSA      0x0EE18
+#define IXGBE_FDIRIPDA      0x0EE1C
+#define IXGBE_FDIRPORT      0x0EE20
+#define IXGBE_FDIRVLAN      0x0EE24
+#define IXGBE_FDIRHASH      0x0EE28
+#define IXGBE_FDIRCMD       0x0EE2C
 
 /* Transmit DMA registers */
-#define	IXGBE_TDBAL(_i)	(0x06000 + ((_i) * 0x40)) /* 32 of these (0-31) */
-#define	IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
-#define	IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
-#define	IXGBE_TDH(_i)	(0x06010 + ((_i) * 0x40))
-#define	IXGBE_TDT(_i)	(0x06018 + ((_i) * 0x40))
-#define	IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
-#define	IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
-#define	IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
-#define	IXGBE_DTXCTL	0x07E00
+#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
+#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
+#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
+#define IXGBE_TDH(_i)   (0x06010 + ((_i) * 0x40))
+#define IXGBE_TDT(_i)   (0x06018 + ((_i) * 0x40))
+#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
+#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
+#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
+#define IXGBE_DTXCTL    0x07E00
 
-#define	IXGBE_DMATXCTL		0x04A80
-#define	IXGBE_PFDTXGSWC		0x08220
-#define	IXGBE_DTXMXSZRQ		0x08100
-#define	IXGBE_DTXTCPFLGL	0x04A88
-#define	IXGBE_DTXTCPFLGH	0x04A8C
-#define	IXGBE_LBDRPEN		0x0CA00
-#define	IXGBE_TXPBTHRESH(_i)	(0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
+#define IXGBE_DMATXCTL          0x04A80
+#define IXGBE_PFVFSPOOF(_i)     (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
+#define IXGBE_PFDTXGSWC         0x08220
+#define IXGBE_DTXMXSZRQ         0x08100
+#define IXGBE_DTXTCPFLGL        0x04A88
+#define IXGBE_DTXTCPFLGH        0x04A8C
+#define IXGBE_LBDRPEN           0x0CA00
+#define IXGBE_TXPBTHRESH(_i)    (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
 
-#define	IXGBE_DMATXCTL_TE	0x1 /* Transmit Enable */
-#define	IXGBE_DMATXCTL_NS	0x2 /* No Snoop LSO hdr buffer */
-#define	IXGBE_DMATXCTL_GDV	0x8 /* Global Double VLAN */
-#define	IXGBE_DMATXCTL_VT_SHIFT	16  /* VLAN EtherType */
+#define IXGBE_DMATXCTL_TE       0x1 /* Transmit Enable */
+#define IXGBE_DMATXCTL_NS       0x2 /* No Snoop LSO hdr buffer */
+#define IXGBE_DMATXCTL_GDV      0x8 /* Global Double VLAN */
+#define IXGBE_DMATXCTL_VT_SHIFT 16  /* VLAN EtherType */
 
-#define	IXGBE_PFDTXGSWC_VT_LBEN	0x1 /* Local L2 VT switch enable */
-#define	IXGBE_DCA_TXCTRL(_i)	(0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
+#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
+
+/* Anti-spoofing defines */
+#define IXGBE_SPOOF_MACAS_MASK          0xFF
+#define IXGBE_SPOOF_VLANAS_MASK         0xFF00
+#define IXGBE_SPOOF_VLANAS_SHIFT        8
+#define IXGBE_PFVFSPOOF_REG_COUNT       8
+#define IXGBE_DCA_TXCTRL(_i)    (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
 /* Tx DCA Control register : 128 of these (0-127) */
-#define	IXGBE_DCA_TXCTRL_82599(_i)	(0x0600C + ((_i) * 0x40))
-#define	IXGBE_TIPG		0x0CB00
-#define	IXGBE_TXPBSIZE(_i)	(0x0CC00 + ((_i) *0x04)) /* 8 of these */
-#define	IXGBE_MNGTXMAP		0x0CD10
-#define	IXGBE_TIPG_FIBER_DEFAULT	3
-#define	IXGBE_TXPBSIZE_SHIFT		10
+#define IXGBE_DCA_TXCTRL_82599(_i)  (0x0600C + ((_i) * 0x40))
+#define IXGBE_TIPG      0x0CB00
+#define IXGBE_TXPBSIZE(_i)      (0x0CC00 + ((_i) * 4)) /* 8 of these */
+#define IXGBE_MNGTXMAP  0x0CD10
+#define IXGBE_TIPG_FIBER_DEFAULT 3
+#define IXGBE_TXPBSIZE_SHIFT    10
 
 /* Wake up registers */
-#define	IXGBE_WUC	0x05800
-#define	IXGBE_WUFC	0x05808
-#define	IXGBE_WUS	0x05810
-#define	IXGBE_IPAV	0x05838
-#define	IXGBE_IP4AT	0x05840 /* IPv4 table 0x5840-0x5858 */
-#define	IXGBE_IP6AT	0x05880 /* IPv6 table 0x5880-0x588F */
-#define	IXGBE_WUPL	0x05900
-#define	IXGBE_WUPM	0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
-#define	IXGBE_FHFT(_n)	(0x09000 + (_n * 0x100)) /* Flex host filter table */
-/* Ext Flexible Host Filter Table */
-#define	IXGBE_FHFT_EXT(_n)	(0x09800 + (_n * 0x100))
-#define	IXGBE_FLEXIBLE_FILTER_COUNT_MAX		4
-#define	IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX	2
+#define IXGBE_WUC       0x05800
+#define IXGBE_WUFC      0x05808
+#define IXGBE_WUS       0x05810
+#define IXGBE_IPAV      0x05838
+#define IXGBE_IP4AT     0x05840 /* IPv4 table 0x5840-0x5858 */
+#define IXGBE_IP6AT     0x05880 /* IPv6 table 0x5880-0x588F */
 
+#define IXGBE_WUPL      0x05900
+#define IXGBE_WUPM      0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
+#define IXGBE_FHFT(_n)     (0x09000 + (_n * 0x100)) /* Flex host filter table */
+#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
+                                                     * Filter Table */
+
+#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX         4
+#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
+
 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
-#define	IXGBE_FLEXIBLE_FILTER_SIZE_MAX	128
-#define	IXGBE_FHFT_LENGTH_OFFSET	0xFC  /* Length byte in FHFT */
-#define	IXGBE_FHFT_LENGTH_MASK		0x0FF /* Length in lower byte */
+#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX  128
+#define IXGBE_FHFT_LENGTH_OFFSET        0xFC  /* Length byte in FHFT */
+#define IXGBE_FHFT_LENGTH_MASK          0x0FF /* Length in lower byte */
 
 /* Definitions for power management and wakeup registers */
 /* Wake Up Control */
-#define	IXGBE_WUC_PME_EN	0x00000002 /* PME Enable */
-#define	IXGBE_WUC_PME_STATUS	0x00000004 /* PME Status */
-#define	IXGBE_WUC_WKEN		0x00000010 /* Enable PE_WAKE_N pin assertion */
+#define IXGBE_WUC_PME_EN     0x00000002 /* PME Enable */
+#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
+#define IXGBE_WUC_WKEN       0x00000010 /* Enable PE_WAKE_N pin assertion  */
 
 /* Wake Up Filter Control */
-#define	IXGBE_WUFC_LNKC	0x00000001 /* Link Status Change Wakeup Enable */
-#define	IXGBE_WUFC_MAG	0x00000002 /* Magic Packet Wakeup Enable */
-#define	IXGBE_WUFC_EX	0x00000004 /* Directed Exact Wakeup Enable */
-#define	IXGBE_WUFC_MC	0x00000008 /* Directed Multicast Wakeup Enable */
-#define	IXGBE_WUFC_BC	0x00000010 /* Broadcast Wakeup Enable */
-#define	IXGBE_WUFC_ARP	0x00000020 /* ARP Request Packet Wakeup Enable */
-#define	IXGBE_WUFC_IPV4	0x00000040 /* Directed IPv4 Packet Wakeup Enable */
-#define	IXGBE_WUFC_IPV6	0x00000080 /* Directed IPv6 Packet Wakeup Enable */
-#define	IXGBE_WUFC_MNG	0x00000100 /* Directed Mgmt Packet Wakeup Enable */
+#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
+#define IXGBE_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
+#define IXGBE_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
+#define IXGBE_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
+#define IXGBE_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
+#define IXGBE_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
+#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
+#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
+#define IXGBE_WUFC_MNG  0x00000100 /* Directed Mgmt Packet Wakeup Enable */
 
-#define	IXGBE_WUFC_IGNORE_TCO	0x00008000 /* Ignore WakeOn TCO packets */
-#define	IXGBE_WUFC_FLX0		0x00010000 /* Flexible Filter 0 Enable */
-#define	IXGBE_WUFC_FLX1		0x00020000 /* Flexible Filter 1 Enable */
-#define	IXGBE_WUFC_FLX2		0x00040000 /* Flexible Filter 2 Enable */
-#define	IXGBE_WUFC_FLX3		0x00080000 /* Flexible Filter 3 Enable */
-#define	IXGBE_WUFC_FLX4		0x00100000 /* Flexible Filter 4 Enable */
-#define	IXGBE_WUFC_FLX5		0x00200000 /* Flexible Filter 5 Enable */
-#define	IXGBE_WUFC_FLX_FILTERS	0x000F0000 /* Mask for 4 flex filters */
-#define	IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
-#define	IXGBE_WUFC_ALL_FILTERS	0x003F00FF /* Mask for all wakeup filters */
-#define	IXGBE_WUFC_FLX_OFFSET	16 /* Offset to the Flexible Filters bits */
+#define IXGBE_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
+#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
+#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
+#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
+#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
+#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
+#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
+#define IXGBE_WUFC_FLX_FILTERS     0x000F0000 /* Mask for 4 flex filters */
+#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
+#define IXGBE_WUFC_ALL_FILTERS     0x003F00FF /* Mask for all wakeup filters */
+#define IXGBE_WUFC_FLX_OFFSET      16 /* Offset to the Flexible Filters bits */
 
 /* Wake Up Status */
-#define	IXGBE_WUS_LNKC	IXGBE_WUFC_LNKC
-#define	IXGBE_WUS_MAG	IXGBE_WUFC_MAG
-#define	IXGBE_WUS_EX	IXGBE_WUFC_EX
-#define	IXGBE_WUS_MC	IXGBE_WUFC_MC
-#define	IXGBE_WUS_BC	IXGBE_WUFC_BC
-#define	IXGBE_WUS_ARP	IXGBE_WUFC_ARP
-#define	IXGBE_WUS_IPV4	IXGBE_WUFC_IPV4
-#define	IXGBE_WUS_IPV6	IXGBE_WUFC_IPV6
-#define	IXGBE_WUS_MNG	IXGBE_WUFC_MNG
-#define	IXGBE_WUS_FLX0	IXGBE_WUFC_FLX0
-#define	IXGBE_WUS_FLX1	IXGBE_WUFC_FLX1
-#define	IXGBE_WUS_FLX2	IXGBE_WUFC_FLX2
-#define	IXGBE_WUS_FLX3	IXGBE_WUFC_FLX3
-#define	IXGBE_WUS_FLX4	IXGBE_WUFC_FLX4
-#define	IXGBE_WUS_FLX5	IXGBE_WUFC_FLX5
-#define	IXGBE_WUS_FLX_FILTERS	IXGBE_WUFC_FLX_FILTERS
+#define IXGBE_WUS_LNKC  IXGBE_WUFC_LNKC
+#define IXGBE_WUS_MAG   IXGBE_WUFC_MAG
+#define IXGBE_WUS_EX    IXGBE_WUFC_EX
+#define IXGBE_WUS_MC    IXGBE_WUFC_MC
+#define IXGBE_WUS_BC    IXGBE_WUFC_BC
+#define IXGBE_WUS_ARP   IXGBE_WUFC_ARP
+#define IXGBE_WUS_IPV4  IXGBE_WUFC_IPV4
+#define IXGBE_WUS_IPV6  IXGBE_WUFC_IPV6
+#define IXGBE_WUS_MNG   IXGBE_WUFC_MNG
+#define IXGBE_WUS_FLX0  IXGBE_WUFC_FLX0
+#define IXGBE_WUS_FLX1  IXGBE_WUFC_FLX1
+#define IXGBE_WUS_FLX2  IXGBE_WUFC_FLX2
+#define IXGBE_WUS_FLX3  IXGBE_WUFC_FLX3
+#define IXGBE_WUS_FLX4  IXGBE_WUFC_FLX4
+#define IXGBE_WUS_FLX5  IXGBE_WUFC_FLX5
+#define IXGBE_WUS_FLX_FILTERS  IXGBE_WUFC_FLX_FILTERS
 
 /* Wake Up Packet Length */
-#define	IXGBE_WUPL_LENGTH_MASK	0xFFFF
+#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
 
 /* DCB registers */
-#define	IXGBE_RMCS	0x03D00
-#define	IXGBE_DPMCS	0x07F40
-#define	IXGBE_PDPMCS	0x0CD00
-#define	IXGBE_RUPPBMR	0x050A0
-#define	IXGBE_RT2CR(_i)	(0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_RT2SR(_i)	(0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_TDTQ2TCCR(_i)	(0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
-#define	IXGBE_TDTQ2TCSR(_i)	(0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
-#define	IXGBE_TDPT2TCCR(_i)	(0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_TDPT2TCSR(_i)	(0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RMCS      0x03D00
+#define IXGBE_DPMCS     0x07F40
+#define IXGBE_PDPMCS    0x0CD00
+#define IXGBE_RUPPBMR   0x050A0
+#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_TDTQ2TCCR(_i)     (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
+#define IXGBE_TDTQ2TCSR(_i)     (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
+#define IXGBE_TDPT2TCCR(_i)     (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_TDPT2TCSR(_i)     (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 
+
 /* Security Control Registers */
-#define	IXGBE_SECTXCTRL		0x08800
-#define	IXGBE_SECTXSTAT		0x08804
-#define	IXGBE_SECTXBUFFAF	0x08808
-#define	IXGBE_SECTXMINIFG	0x08810
-#define	IXGBE_SECTXSTAT		0x08804
-#define	IXGBE_SECRXCTRL		0x08D00
-#define	IXGBE_SECRXSTAT		0x08D04
+#define IXGBE_SECTXCTRL         0x08800
+#define IXGBE_SECTXSTAT         0x08804
+#define IXGBE_SECTXBUFFAF       0x08808
+#define IXGBE_SECTXMINIFG       0x08810
+#define IXGBE_SECTXSTAT         0x08804
+#define IXGBE_SECRXCTRL         0x08D00
+#define IXGBE_SECRXSTAT         0x08D04
 
 /* Security Bit Fields and Masks */
-#define	IXGBE_SECTXCTRL_SECTX_DIS	0x00000001
-#define	IXGBE_SECTXCTRL_TX_DIS		0x00000002
-#define	IXGBE_SECTXCTRL_STORE_FORWARD	0x00000004
+#define IXGBE_SECTXCTRL_SECTX_DIS       0x00000001
+#define IXGBE_SECTXCTRL_TX_DIS          0x00000002
+#define IXGBE_SECTXCTRL_STORE_FORWARD   0x00000004
 
-#define	IXGBE_SECTXSTAT_SECTX_RDY	0x00000001
-#define	IXGBE_SECTXSTAT_ECC_TXERR	0x00000002
+#define IXGBE_SECTXSTAT_SECTX_RDY       0x00000001
+#define IXGBE_SECTXSTAT_ECC_TXERR       0x00000002
 
-#define	IXGBE_SECRXCTRL_SECRX_DIS	0x00000001
-#define	IXGBE_SECRXCTRL_RX_DIS		0x00000002
+#define IXGBE_SECRXCTRL_SECRX_DIS       0x00000001
+#define IXGBE_SECRXCTRL_RX_DIS          0x00000002
 
-#define	IXGBE_SECRXSTAT_SECRX_RDY	0x00000001
-#define	IXGBE_SECRXSTAT_ECC_RXERR	0x00000002
+#define IXGBE_SECRXSTAT_SECRX_RDY       0x00000001
+#define IXGBE_SECRXSTAT_ECC_RXERR       0x00000002
 
 /* LinkSec (MacSec) Registers */
-#define	IXGBE_LSECTXCAP		0x08A00
-#define	IXGBE_LSECRXCAP		0x08F00
-#define	IXGBE_LSECTXCTRL	0x08A04
-#define	IXGBE_LSECTXSCL		0x08A08 /* SCI Low */
-#define	IXGBE_LSECTXSCH		0x08A0C /* SCI High */
-#define	IXGBE_LSECTXSA		0x08A10
-#define	IXGBE_LSECTXPN0		0x08A14
-#define	IXGBE_LSECTXPN1		0x08A18
-#define	IXGBE_LSECTXKEY0(_n)	(0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
-#define	IXGBE_LSECTXKEY1(_n)	(0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
-#define	IXGBE_LSECRXCTRL	0x08F04
-#define	IXGBE_LSECRXSCL		0x08F08
-#define	IXGBE_LSECRXSCH		0x08F0C
-#define	IXGBE_LSECRXSA(_i)	(0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
-#define	IXGBE_LSECRXPN(_i)	(0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
-#define	IXGBE_LSECRXKEY(_n, _m)	(0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
-#define	IXGBE_LSECTXUT		0x08A3C /* OutPktsUntagged */
-#define	IXGBE_LSECTXPKTE	0x08A40 /* OutPktsEncrypted */
-#define	IXGBE_LSECTXPKTP	0x08A44 /* OutPktsProtected */
-#define	IXGBE_LSECTXOCTE	0x08A48 /* OutOctetsEncrypted */
-#define	IXGBE_LSECTXOCTP	0x08A4C /* OutOctetsProtected */
-#define	IXGBE_LSECRXUT		0x08F40 /* InPktsUntagged/InPktsNoTag */
-#define	IXGBE_LSECRXOCTD	0x08F44 /* InOctetsDecrypted */
-#define	IXGBE_LSECRXOCTV	0x08F48 /* InOctetsValidated */
-#define	IXGBE_LSECRXBAD		0x08F4C /* InPktsBadTag */
-#define	IXGBE_LSECRXNOSCI	0x08F50 /* InPktsNoSci */
-#define	IXGBE_LSECRXUNSCI	0x08F54 /* InPktsUnknownSci */
-#define	IXGBE_LSECRXUNCH	0x08F58 /* InPktsUnchecked */
-#define	IXGBE_LSECRXDELAY	0x08F5C /* InPktsDelayed */
-#define	IXGBE_LSECRXLATE	0x08F60 /* InPktsLate */
-#define	IXGBE_LSECRXOK(_n)	(0x08F64 + (0x04 * (_n))) /* InPktsOk */
-#define	IXGBE_LSECRXINV(_n)	(0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
-#define	IXGBE_LSECRXNV(_n)	(0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
-#define	IXGBE_LSECRXUNSA	0x08F7C /* InPktsUnusedSa */
-#define	IXGBE_LSECRXNUSA	0x08F80 /* InPktsNotUsingSa */
+#define IXGBE_LSECTXCAP         0x08A00
+#define IXGBE_LSECRXCAP         0x08F00
+#define IXGBE_LSECTXCTRL        0x08A04
+#define IXGBE_LSECTXSCL         0x08A08 /* SCI Low */
+#define IXGBE_LSECTXSCH         0x08A0C /* SCI High */
+#define IXGBE_LSECTXSA          0x08A10
+#define IXGBE_LSECTXPN0         0x08A14
+#define IXGBE_LSECTXPN1         0x08A18
+#define IXGBE_LSECTXKEY0(_n)    (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
+#define IXGBE_LSECTXKEY1(_n)    (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
+#define IXGBE_LSECRXCTRL        0x08F04
+#define IXGBE_LSECRXSCL         0x08F08
+#define IXGBE_LSECRXSCH         0x08F0C
+#define IXGBE_LSECRXSA(_i)      (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
+#define IXGBE_LSECRXPN(_i)      (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
+#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
+#define IXGBE_LSECTXUT          0x08A3C /* OutPktsUntagged */
+#define IXGBE_LSECTXPKTE        0x08A40 /* OutPktsEncrypted */
+#define IXGBE_LSECTXPKTP        0x08A44 /* OutPktsProtected */
+#define IXGBE_LSECTXOCTE        0x08A48 /* OutOctetsEncrypted */
+#define IXGBE_LSECTXOCTP        0x08A4C /* OutOctetsProtected */
+#define IXGBE_LSECRXUT          0x08F40 /* InPktsUntagged/InPktsNoTag */
+#define IXGBE_LSECRXOCTD        0x08F44 /* InOctetsDecrypted */
+#define IXGBE_LSECRXOCTV        0x08F48 /* InOctetsValidated */
+#define IXGBE_LSECRXBAD         0x08F4C /* InPktsBadTag */
+#define IXGBE_LSECRXNOSCI       0x08F50 /* InPktsNoSci */
+#define IXGBE_LSECRXUNSCI       0x08F54 /* InPktsUnknownSci */
+#define IXGBE_LSECRXUNCH        0x08F58 /* InPktsUnchecked */
+#define IXGBE_LSECRXDELAY       0x08F5C /* InPktsDelayed */
+#define IXGBE_LSECRXLATE        0x08F60 /* InPktsLate */
+#define IXGBE_LSECRXOK(_n)      (0x08F64 + (0x04 * (_n))) /* InPktsOk */
+#define IXGBE_LSECRXINV(_n)     (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
+#define IXGBE_LSECRXNV(_n)      (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
+#define IXGBE_LSECRXUNSA        0x08F7C /* InPktsUnusedSa */
+#define IXGBE_LSECRXNUSA        0x08F80 /* InPktsNotUsingSa */
 
 /* LinkSec (MacSec) Bit Fields and Masks */
-#define	IXGBE_LSECTXCAP_SUM_MASK	0x00FF0000
-#define	IXGBE_LSECTXCAP_SUM_SHIFT	16
-#define	IXGBE_LSECRXCAP_SUM_MASK	0x00FF0000
-#define	IXGBE_LSECRXCAP_SUM_SHIFT	16
+#define IXGBE_LSECTXCAP_SUM_MASK        0x00FF0000
+#define IXGBE_LSECTXCAP_SUM_SHIFT       16
+#define IXGBE_LSECRXCAP_SUM_MASK        0x00FF0000
+#define IXGBE_LSECRXCAP_SUM_SHIFT       16
 
-#define	IXGBE_LSECTXCTRL_EN_MASK	0x00000003
-#define	IXGBE_LSECTXCTRL_DISABLE	0x0
-#define	IXGBE_LSECTXCTRL_AUTH		0x1
-#define	IXGBE_LSECTXCTRL_AUTH_ENCRYPT	0x2
-#define	IXGBE_LSECTXCTRL_AISCI		0x00000020
-#define	IXGBE_LSECTXCTRL_PNTHRSH_MASK	0xFFFFFF00
-#define	IXGBE_LSECTXCTRL_RSV_MASK	0x000000D8
+#define IXGBE_LSECTXCTRL_EN_MASK        0x00000003
+#define IXGBE_LSECTXCTRL_DISABLE        0x0
+#define IXGBE_LSECTXCTRL_AUTH           0x1
+#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT   0x2
+#define IXGBE_LSECTXCTRL_AISCI          0x00000020
+#define IXGBE_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
+#define IXGBE_LSECTXCTRL_RSV_MASK       0x000000D8
 
-#define	IXGBE_LSECRXCTRL_EN_MASK	0x0000000C
-#define	IXGBE_LSECRXCTRL_EN_SHIFT	2
-#define	IXGBE_LSECRXCTRL_DISABLE	0x0
-#define	IXGBE_LSECRXCTRL_CHECK		0x1
-#define	IXGBE_LSECRXCTRL_STRICT		0x2
-#define	IXGBE_LSECRXCTRL_DROP		0x3
-#define	IXGBE_LSECRXCTRL_PLSH		0x00000040
-#define	IXGBE_LSECRXCTRL_RP		0x00000080
-#define	IXGBE_LSECRXCTRL_RSV_MASK	0xFFFFFF33
+#define IXGBE_LSECRXCTRL_EN_MASK        0x0000000C
+#define IXGBE_LSECRXCTRL_EN_SHIFT       2
+#define IXGBE_LSECRXCTRL_DISABLE        0x0
+#define IXGBE_LSECRXCTRL_CHECK          0x1
+#define IXGBE_LSECRXCTRL_STRICT         0x2
+#define IXGBE_LSECRXCTRL_DROP           0x3
+#define IXGBE_LSECRXCTRL_PLSH           0x00000040
+#define IXGBE_LSECRXCTRL_RP             0x00000080
+#define IXGBE_LSECRXCTRL_RSV_MASK       0xFFFFFF33
 
 /* IpSec Registers */
-#define	IXGBE_IPSTXIDX		0x08900
-#define	IXGBE_IPSTXSALT		0x08904
-#define	IXGBE_IPSTXKEY(_i)	(0x08908 + (4 * (_i))) /* 4 of these (0-3) */
-#define	IXGBE_IPSRXIDX		0x08E00
-#define	IXGBE_IPSRXIPADDR(_i)	(0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
-#define	IXGBE_IPSRXSPI		0x08E14
-#define	IXGBE_IPSRXIPIDX	0x08E18
-#define	IXGBE_IPSRXKEY(_i)	(0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
-#define	IXGBE_IPSRXSALT		0x08E2C
-#define	IXGBE_IPSRXMOD		0x08E30
+#define IXGBE_IPSTXIDX          0x08900
+#define IXGBE_IPSTXSALT         0x08904
+#define IXGBE_IPSTXKEY(_i)      (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
+#define IXGBE_IPSRXIDX          0x08E00
+#define IXGBE_IPSRXIPADDR(_i)   (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
+#define IXGBE_IPSRXSPI          0x08E14
+#define IXGBE_IPSRXIPIDX        0x08E18
+#define IXGBE_IPSRXKEY(_i)      (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
+#define IXGBE_IPSRXSALT         0x08E2C
+#define IXGBE_IPSRXMOD          0x08E30
 
-#define	IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE	0x4
+#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE    0x4
 
 /* DCB registers */
-#define	IXGBE_RTRPCS		0x02430
-#define	IXGBE_RTTDCS		0x04900
-#define	IXGBE_RTTDCS_ARBDIS	0x00000040 /* DCB arbiter disable */
-#define	IXGBE_RTTPCS		0x0CD00
-#define	IXGBE_RTRUP2TC		0x03020
-#define	IXGBE_RTTUP2TC		0x0C800
-#define	IXGBE_RTRPT4C(_i)	(0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_RTRPT4S(_i)	(0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_RTTDT2C(_i)	(0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_RTTDT2S(_i)	(0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_RTTPT2C(_i)	(0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_RTTPT2S(_i)	(0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_RTTDQSEL		0x04904
-#define	IXGBE_RTTDT1C		0x04908
-#define	IXGBE_RTTDT1S		0x0490C
-#define	IXGBE_RTTDTECC		0x04990
-#define	IXGBE_RTTDTECC_NO_BCN	0x00000100
+#define IXGBE_RTRPCS      0x02430
+#define IXGBE_RTTDCS      0x04900
+#define IXGBE_RTTDCS_ARBDIS     0x00000040 /* DCB arbiter disable */
+#define IXGBE_RTTPCS      0x0CD00
+#define IXGBE_RTRUP2TC    0x03020
+#define IXGBE_RTTUP2TC    0x0C800
+#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_RTTDQSEL    0x04904
+#define IXGBE_RTTDT1C     0x04908
+#define IXGBE_RTTDT1S     0x0490C
+#define IXGBE_RTTDTECC    0x04990
+#define IXGBE_RTTDTECC_NO_BCN   0x00000100
 
-#define	IXGBE_RTTBCNRC		0x04984
+#define IXGBE_RTTBCNRC    0x04984
+#define IXGBE_RTTBCNRC_RS_ENA           0x80000000
+#define IXGBE_RTTBCNRC_RF_DEC_MASK      0x00003FFF
+#define IXGBE_RTTBCNRC_RF_INT_SHIFT     14
+#define IXGBE_RTTBCNRC_RF_INT_MASK \
+	(IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
 
+/* BCN (for DCB) Registers */
+#define IXGBE_RTTBCNRM    0x04980
+#define IXGBE_RTTBCNRS    0x04988
+#define IXGBE_RTTBCNCR    0x08B00
+#define IXGBE_RTTBCNACH   0x08B04
+#define IXGBE_RTTBCNACL   0x08B08
+#define IXGBE_RTTBCNTG    0x04A90
+#define IXGBE_RTTBCNIDX   0x08B0C
+#define IXGBE_RTTBCNCP    0x08B10
+#define IXGBE_RTFRTIMER   0x08B14
+#define IXGBE_RTTBCNRTT   0x05150
+#define IXGBE_RTTBCNRD    0x0498C
+
 /* FCoE DMA Context Registers */
-#define	IXGBE_FCPTRL	0x02410 /* FC User Desc. PTR Low */
-#define	IXGBE_FCPTRH	0x02414 /* FC USer Desc. PTR High */
-#define	IXGBE_FCBUFF	0x02418 /* FC Buffer Control */
-#define	IXGBE_FCDMARW	0x02420 /* FC Receive DMA RW */
-#define	IXGBE_FCINVST0	0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
-#define	IXGBE_FCINVST(_i)	(IXGBE_FCINVST0 + ((_i) * 4))
-#define	IXGBE_FCBUFF_VALID	(1 << 0)   /* DMA Context Valid */
-#define	IXGBE_FCBUFF_BUFFSIZE	(3 << 3)   /* User Buffer Size */
-#define	IXGBE_FCBUFF_WRCONTX	(1 << 7)   /* 0: Initiator, 1: Target */
-#define	IXGBE_FCBUFF_BUFFCNT	0x0000ff00 /* Number of User Buffers */
-#define	IXGBE_FCBUFF_OFFSET	0xffff0000 /* User Buffer Offset */
-#define	IXGBE_FCBUFF_BUFFSIZE_SHIFT	3
-#define	IXGBE_FCBUFF_BUFFCNT_SHIFT	8
-#define	IXGBE_FCBUFF_OFFSET_SHIFT	16
-#define	IXGBE_FCDMARW_WE	(1 << 14)   /* Write enable */
-#define	IXGBE_FCDMARW_RE	(1 << 15)   /* Read enable */
-#define	IXGBE_FCDMARW_FCOESEL	0x000001ff  /* FC X_ID: 11 bits */
-#define	IXGBE_FCDMARW_LASTSIZE	0xffff0000  /* Last User Buffer Size */
-#define	IXGBE_FCDMARW_LASTSIZE_SHIFT	16
+#define IXGBE_FCPTRL    0x02410 /* FC User Desc. PTR Low */
+#define IXGBE_FCPTRH    0x02414 /* FC USer Desc. PTR High */
+#define IXGBE_FCBUFF    0x02418 /* FC Buffer Control */
+#define IXGBE_FCDMARW   0x02420 /* FC Receive DMA RW */
+#define IXGBE_FCINVST0  0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
+#define IXGBE_FCINVST(_i)       (IXGBE_FCINVST0 + ((_i) * 4))
+#define IXGBE_FCBUFF_VALID      (1 << 0)   /* DMA Context Valid */
+#define IXGBE_FCBUFF_BUFFSIZE   (3 << 3)   /* User Buffer Size */
+#define IXGBE_FCBUFF_WRCONTX    (1 << 7)   /* 0: Initiator, 1: Target */
+#define IXGBE_FCBUFF_BUFFCNT    0x0000ff00 /* Number of User Buffers */
+#define IXGBE_FCBUFF_OFFSET     0xffff0000 /* User Buffer Offset */
+#define IXGBE_FCBUFF_BUFFSIZE_SHIFT  3
+#define IXGBE_FCBUFF_BUFFCNT_SHIFT   8
+#define IXGBE_FCBUFF_OFFSET_SHIFT    16
+#define IXGBE_FCDMARW_WE        (1 << 14)   /* Write enable */
+#define IXGBE_FCDMARW_RE        (1 << 15)   /* Read enable */
+#define IXGBE_FCDMARW_FCOESEL   0x000001ff  /* FC X_ID: 11 bits */
+#define IXGBE_FCDMARW_LASTSIZE  0xffff0000  /* Last User Buffer Size */
+#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
 /* FCoE SOF/EOF */
-#define	IXGBE_TEOFF	0x04A94 /* Tx FC EOF */
-#define	IXGBE_TSOFF	0x04A98 /* Tx FC SOF */
-#define	IXGBE_REOFF	0x05158 /* Rx FC EOF */
-#define	IXGBE_RSOFF	0x051F8 /* Rx FC SOF */
+#define IXGBE_TEOFF     0x04A94 /* Tx FC EOF */
+#define IXGBE_TSOFF     0x04A98 /* Tx FC SOF */
+#define IXGBE_REOFF     0x05158 /* Rx FC EOF */
+#define IXGBE_RSOFF     0x051F8 /* Rx FC SOF */
 /* FCoE Filter Context Registers */
-#define	IXGBE_FCFLT	0x05108 /* FC FLT Context */
-#define	IXGBE_FCFLTRW	0x05110 /* FC Filter RW Control */
-#define	IXGBE_FCPARAM	0x051d8 /* FC Offset Parameter */
-#define	IXGBE_FCFLT_VALID	(1 << 0)   /* Filter Context Valid */
-#define	IXGBE_FCFLT_FIRST	(1 << 1)   /* Filter First */
-#define	IXGBE_FCFLT_SEQID	0x00ff0000 /* Sequence ID */
-#define	IXGBE_FCFLT_SEQCNT	0xff000000 /* Sequence Count */
-#define	IXGBE_FCFLTRW_RVALDT	(1 << 13)  /* Fast Re-Validation */
-#define	IXGBE_FCFLTRW_WE	(1 << 14)  /* Write Enable */
-#define	IXGBE_FCFLTRW_RE	(1 << 15)  /* Read Enable */
+#define IXGBE_FCFLT     0x05108 /* FC FLT Context */
+#define IXGBE_FCFLTRW   0x05110 /* FC Filter RW Control */
+#define IXGBE_FCPARAM   0x051d8 /* FC Offset Parameter */
+#define IXGBE_FCFLT_VALID       (1 << 0)   /* Filter Context Valid */
+#define IXGBE_FCFLT_FIRST       (1 << 1)   /* Filter First */
+#define IXGBE_FCFLT_SEQID       0x00ff0000 /* Sequence ID */
+#define IXGBE_FCFLT_SEQCNT      0xff000000 /* Sequence Count */
+#define IXGBE_FCFLTRW_RVALDT    (1 << 13)  /* Fast Re-Validation */
+#define IXGBE_FCFLTRW_WE        (1 << 14)  /* Write Enable */
+#define IXGBE_FCFLTRW_RE        (1 << 15)  /* Read Enable */
 /* FCoE Receive Control */
-#define	IXGBE_FCRXCTRL		0x05100 /* FC Receive Control */
-#define	IXGBE_FCRXCTRL_FCOELLI	(1 << 0)   /* Low latency interrupt */
-#define	IXGBE_FCRXCTRL_SAVBAD	(1 << 1)   /* Save Bad Frames */
-#define	IXGBE_FCRXCTRL_FRSTRDH	(1 << 2)   /* EN 1st Read Header */
-#define	IXGBE_FCRXCTRL_LASTSEQH	(1 << 3)   /* EN Last Header in Seq */
-#define	IXGBE_FCRXCTRL_ALLH	(1 << 4)   /* EN All Headers */
-#define	IXGBE_FCRXCTRL_FRSTSEQH	(1 << 5)   /* EN 1st Seq. Header */
-#define	IXGBE_FCRXCTRL_ICRC	(1 << 6)   /* Ignore Bad FC CRC */
-#define	IXGBE_FCRXCTRL_FCCRCBO	(1 << 7)   /* FC CRC Byte Ordering */
-#define	IXGBE_FCRXCTRL_FCOEVER	0x00000f00 /* FCoE Version: 4 bits */
-#define	IXGBE_FCRXCTRL_FCOEVER_SHIFT	8
+#define IXGBE_FCRXCTRL  0x05100 /* FC Receive Control */
+#define IXGBE_FCRXCTRL_FCOELLI  (1 << 0)   /* Low latency interrupt */
+#define IXGBE_FCRXCTRL_SAVBAD   (1 << 1)   /* Save Bad Frames */
+#define IXGBE_FCRXCTRL_FRSTRDH  (1 << 2)   /* EN 1st Read Header */
+#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3)   /* EN Last Header in Seq */
+#define IXGBE_FCRXCTRL_ALLH     (1 << 4)   /* EN All Headers */
+#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5)   /* EN 1st Seq. Header */
+#define IXGBE_FCRXCTRL_ICRC     (1 << 6)   /* Ignore Bad FC CRC */
+#define IXGBE_FCRXCTRL_FCCRCBO  (1 << 7)   /* FC CRC Byte Ordering */
+#define IXGBE_FCRXCTRL_FCOEVER  0x00000f00 /* FCoE Version: 4 bits */
+#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
 /* FCoE Redirection */
-#define	IXGBE_FCRECTL		0x0ED00 /* FC Redirection Control */
-#define	IXGBE_FCRETA0		0x0ED10 /* FC Redirection Table 0 */
-#define	IXGBE_FCRETA(_i)	(IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
-#define	IXGBE_FCRECTL_ENA	0x1	/* FCoE Redir Table Enable */
-#define	IXGBE_FCRETA_SIZE	8	/* Max entries in FCRETA */
-#define	IXGBE_FCRETA_ENTRY_MASK	0x0000007f /* 7 bits for the queue index */
+#define IXGBE_FCRECTL   0x0ED00 /* FC Redirection Control */
+#define IXGBE_FCRETA0   0x0ED10 /* FC Redirection Table 0 */
+#define IXGBE_FCRETA(_i)        (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
+#define IXGBE_FCRECTL_ENA       0x1        /* FCoE Redir Table Enable */
+#define IXGBE_FCRETA_SIZE       8          /* Max entries in FCRETA */
+#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
 
 /* Stats registers */
-#define	IXGBE_CRCERRS	0x04000
-#define	IXGBE_ILLERRC	0x04004
-#define	IXGBE_ERRBC	0x04008
-#define	IXGBE_MSPDC	0x04010
-#define	IXGBE_MPC(_i)	(0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC */
-#define	IXGBE_MLFC	0x04034
-#define	IXGBE_MRFC	0x04038
-#define	IXGBE_RLEC	0x04040
-#define	IXGBE_LXONTXC	0x03F60
-#define	IXGBE_LXONRXC	0x0CF60
-#define	IXGBE_LXOFFTXC	0x03F68
-#define	IXGBE_LXOFFRXC	0x0CF68
-#define	IXGBE_LXONRXCNT	0x041A4
-#define	IXGBE_LXOFFRXCNT	0x041A8
-#define	IXGBE_PXONRXCNT(_i)	(0x04140 + ((_i) * 4)) /* 8 of these */
-#define	IXGBE_PXOFFRXCNT(_i)	(0x04160 + ((_i) * 4)) /* 8 of these */
-#define	IXGBE_PXON2OFFCNT(_i)	(0x03240 + ((_i) * 4)) /* 8 of these */
-#define	IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C */
-#define	IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C */
-#define	IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C */
-#define	IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C */
-#define	IXGBE_PRC64	0x0405C
-#define	IXGBE_PRC127	0x04060
-#define	IXGBE_PRC255	0x04064
-#define	IXGBE_PRC511	0x04068
-#define	IXGBE_PRC1023	0x0406C
-#define	IXGBE_PRC1522	0x04070
-#define	IXGBE_GPRC	0x04074
-#define	IXGBE_BPRC	0x04078
-#define	IXGBE_MPRC	0x0407C
-#define	IXGBE_GPTC	0x04080
-#define	IXGBE_GORCL	0x04088
-#define	IXGBE_GORCH	0x0408C
-#define	IXGBE_GOTCL	0x04090
-#define	IXGBE_GOTCH	0x04094
-#define	IXGBE_RNBC(_i)	(0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC */
-#define	IXGBE_RUC	0x040A4
-#define	IXGBE_RFC	0x040A8
-#define	IXGBE_ROC	0x040AC
-#define	IXGBE_RJC	0x040B0
-#define	IXGBE_MNGPRC	0x040B4
-#define	IXGBE_MNGPDC	0x040B8
-#define	IXGBE_MNGPTC	0x0CF90
-#define	IXGBE_TORL	0x040C0
-#define	IXGBE_TORH	0x040C4
-#define	IXGBE_TPR	0x040D0
-#define	IXGBE_TPT	0x040D4
-#define	IXGBE_PTC64	0x040D8
-#define	IXGBE_PTC127	0x040DC
-#define	IXGBE_PTC255	0x040E0
-#define	IXGBE_PTC511	0x040E4
-#define	IXGBE_PTC1023	0x040E8
-#define	IXGBE_PTC1522	0x040EC
-#define	IXGBE_MPTC	0x040F0
-#define	IXGBE_BPTC	0x040F4
-#define	IXGBE_XEC	0x04120
-#define	IXGBE_SSVPC	0x08780
+#define IXGBE_CRCERRS   0x04000
+#define IXGBE_ILLERRC   0x04004
+#define IXGBE_ERRBC     0x04008
+#define IXGBE_MSPDC     0x04010
+#define IXGBE_MPC(_i)   (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
+#define IXGBE_MLFC      0x04034
+#define IXGBE_MRFC      0x04038
+#define IXGBE_RLEC      0x04040
+#define IXGBE_LXONTXC   0x03F60
+#define IXGBE_LXONRXC   0x0CF60
+#define IXGBE_LXOFFTXC  0x03F68
+#define IXGBE_LXOFFRXC  0x0CF68
+#define IXGBE_LXONRXCNT 0x041A4
+#define IXGBE_LXOFFRXCNT 0x041A8
+#define IXGBE_PXONRXCNT(_i)     (0x04140 + ((_i) * 4)) /* 8 of these */
+#define IXGBE_PXOFFRXCNT(_i)    (0x04160 + ((_i) * 4)) /* 8 of these */
+#define IXGBE_PXON2OFFCNT(_i)   (0x03240 + ((_i) * 4)) /* 8 of these */
+#define IXGBE_PXONTXC(_i)       (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
+#define IXGBE_PXONRXC(_i)       (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
+#define IXGBE_PXOFFTXC(_i)      (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
+#define IXGBE_PXOFFRXC(_i)      (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
+#define IXGBE_PRC64     0x0405C
+#define IXGBE_PRC127    0x04060
+#define IXGBE_PRC255    0x04064
+#define IXGBE_PRC511    0x04068
+#define IXGBE_PRC1023   0x0406C
+#define IXGBE_PRC1522   0x04070
+#define IXGBE_GPRC      0x04074
+#define IXGBE_BPRC      0x04078
+#define IXGBE_MPRC      0x0407C
+#define IXGBE_GPTC      0x04080
+#define IXGBE_GORCL     0x04088
+#define IXGBE_GORCH     0x0408C
+#define IXGBE_GOTCL     0x04090
+#define IXGBE_GOTCH     0x04094
+#define IXGBE_RNBC(_i)  (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
+#define IXGBE_RUC       0x040A4
+#define IXGBE_RFC       0x040A8
+#define IXGBE_ROC       0x040AC
+#define IXGBE_RJC       0x040B0
+#define IXGBE_MNGPRC    0x040B4
+#define IXGBE_MNGPDC    0x040B8
+#define IXGBE_MNGPTC    0x0CF90
+#define IXGBE_TORL      0x040C0
+#define IXGBE_TORH      0x040C4
+#define IXGBE_TPR       0x040D0
+#define IXGBE_TPT       0x040D4
+#define IXGBE_PTC64     0x040D8
+#define IXGBE_PTC127    0x040DC
+#define IXGBE_PTC255    0x040E0
+#define IXGBE_PTC511    0x040E4
+#define IXGBE_PTC1023   0x040E8
+#define IXGBE_PTC1522   0x040EC
+#define IXGBE_MPTC      0x040F0
+#define IXGBE_BPTC      0x040F4
+#define IXGBE_XEC       0x04120
+#define IXGBE_SSVPC     0x08780
 
-#define	IXGBE_RQSMR(_i)	(0x02300 + ((_i) * 4))
-#define	IXGBE_TQSMR(_i)	(((_i) <= 7) ? \
-	(0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4)))
-#define	IXGBE_TQSM(_i)	(0x08600 + ((_i) * 4))
+#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
+#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
+                         (0x08600 + ((_i) * 4)))
+#define IXGBE_TQSM(_i)  (0x08600 + ((_i) * 4))
 
-#define	IXGBE_QPRC(_i)	(0x01030 + ((_i) * 0x40)) /* 16 of these */
-#define	IXGBE_QPTC(_i)	(0x06030 + ((_i) * 0x40)) /* 16 of these */
-#define	IXGBE_QBRC(_i)	(0x01034 + ((_i) * 0x40)) /* 16 of these */
-#define	IXGBE_QBTC(_i)	(0x06034 + ((_i) * 0x40)) /* 16 of these */
-#define	IXGBE_QBRC_L(_i)	(0x01034 + ((_i) * 0x40)) /* 16 of these */
-#define	IXGBE_QBRC_H(_i)	(0x01038 + ((_i) * 0x40)) /* 16 of these */
-#define	IXGBE_QPRDC(_i)	(0x01430 + ((_i) * 0x40)) /* 16 of these */
-#define	IXGBE_QBTC_L(_i)	(0x08700 + ((_i) * 0x8)) /* 16 of these */
-#define	IXGBE_QBTC_H(_i)	(0x08704 + ((_i) * 0x8)) /* 16 of these */
-#define	IXGBE_FCCRC	0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
-#define	IXGBE_FCOERPDC	0x0241C /* FCoE Rx Packets Dropped Count */
-#define	IXGBE_FCLAST	0x02424 /* FCoE Last Error Count */
-#define	IXGBE_FCOEPRC	0x02428 /* Number of FCoE Packets Received */
-#define	IXGBE_FCOEDWRC	0x0242C /* Number of FCoE DWords Received */
-#define	IXGBE_FCOEPTC	0x08784 /* Number of FCoE Packets Transmitted */
-#define	IXGBE_FCOEDWTC	0x08788 /* Number of FCoE DWords Transmitted */
-#define	IXGBE_FCCRC_CNT_MASK	0x0000FFFF /* CRC_CNT: bit 0 - 15 */
-#define	IXGBE_FCLAST_CNT_MASK	0x0000FFFF /* Last_CNT: bit 0 - 15 */
+#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
+#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
+#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
+#define IXGBE_FCCRC     0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
+#define IXGBE_FCOERPDC  0x0241C /* FCoE Rx Packets Dropped Count */
+#define IXGBE_FCLAST    0x02424 /* FCoE Last Error Count */
+#define IXGBE_FCOEPRC   0x02428 /* Number of FCoE Packets Received */
+#define IXGBE_FCOEDWRC  0x0242C /* Number of FCoE DWords Received */
+#define IXGBE_FCOEPTC   0x08784 /* Number of FCoE Packets Transmitted */
+#define IXGBE_FCOEDWTC  0x08788 /* Number of FCoE DWords Transmitted */
+#define IXGBE_FCCRC_CNT_MASK    0x0000FFFF /* CRC_CNT: bit 0 - 15 */
+#define IXGBE_FCLAST_CNT_MASK   0x0000FFFF /* Last_CNT: bit 0 - 15 */
 
 /* Management */
-#define	IXGBE_MAVTV(_i)	(0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_MFUTP(_i)	(0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_MANC	0x05820
-#define	IXGBE_MFVAL	0x05824
-#define	IXGBE_MANC2H	0x05860
-#define	IXGBE_MDEF(_i)	(0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_MIPAF	0x058B0
-#define	IXGBE_MMAL(_i)	(0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
-#define	IXGBE_MMAH(_i)	(0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
-#define	IXGBE_FTFT	0x09400 /* 0x9400-0x97FC */
-#define	IXGBE_METF(_i)	(0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
-#define	IXGBE_MDEF_EXT(_i)	(0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
-#define	IXGBE_LSWFW	0x15014
+#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_MANC      0x05820
+#define IXGBE_MFVAL     0x05824
+#define IXGBE_MANC2H    0x05860
+#define IXGBE_MDEF(_i)  (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_MIPAF     0x058B0
+#define IXGBE_MMAL(_i)  (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
+#define IXGBE_MMAH(_i)  (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
+#define IXGBE_FTFT      0x09400 /* 0x9400-0x97FC */
+#define IXGBE_METF(_i)  (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
+#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
+#define IXGBE_LSWFW     0x15014
 
 /* ARC Subsystem registers */
-#define	IXGBE_HICR	0x15F00
-#define	IXGBE_FWSTS	0x15F0C
-#define	IXGBE_HSMC0R	0x15F04
-#define	IXGBE_HSMC1R	0x15F08
-#define	IXGBE_SWSR	0x15F10
-#define	IXGBE_HFDR	0x15FE8
-#define	IXGBE_FLEX_MNG	0x15800 /* 0x15800 - 0x15EFC */
+#define IXGBE_HICR      0x15F00
+#define IXGBE_FWSTS     0x15F0C
+#define IXGBE_HSMC0R    0x15F04
+#define IXGBE_HSMC1R    0x15F08
+#define IXGBE_SWSR      0x15F10
+#define IXGBE_HFDR      0x15FE8
+#define IXGBE_FLEX_MNG  0x15800 /* 0x15800 - 0x15EFC */
 
 /* PCI-E registers */
-#define	IXGBE_GCR	0x11000
-#define	IXGBE_GTV	0x11004
-#define	IXGBE_FUNCTAG	0x11008
-#define	IXGBE_GLT	0x1100C
-#define	IXGBE_GSCL_1	0x11010
-#define	IXGBE_GSCL_2	0x11014
-#define	IXGBE_GSCL_3	0x11018
-#define	IXGBE_GSCL_4	0x1101C
-#define	IXGBE_GSCN_0	0x11020
-#define	IXGBE_GSCN_1	0x11024
-#define	IXGBE_GSCN_2	0x11028
-#define	IXGBE_GSCN_3	0x1102C
-#define	IXGBE_FACTPS	0x10150
-#define	IXGBE_PCIEANACTL 0x11040
-#define	IXGBE_SWSM	0x10140
-#define	IXGBE_FWSM	0x10148
-#define	IXGBE_GSSR	0x10160
-#define	IXGBE_MREVID	0x11064
-#define	IXGBE_DCA_ID	0x11070
-#define	IXGBE_DCA_CTRL	0x11074
-#define	IXGBE_SWFW_SYNC	IXGBE_GSSR
+#define IXGBE_GCR       0x11000
+#define IXGBE_GTV       0x11004
+#define IXGBE_FUNCTAG   0x11008
+#define IXGBE_GLT       0x1100C
+#define IXGBE_GSCL_1    0x11010
+#define IXGBE_GSCL_2    0x11014
+#define IXGBE_GSCL_3    0x11018
+#define IXGBE_GSCL_4    0x1101C
+#define IXGBE_GSCN_0    0x11020
+#define IXGBE_GSCN_1    0x11024
+#define IXGBE_GSCN_2    0x11028
+#define IXGBE_GSCN_3    0x1102C
+#define IXGBE_FACTPS    0x10150
+#define IXGBE_PCIEANACTL  0x11040
+#define IXGBE_SWSM      0x10140
+#define IXGBE_FWSM      0x10148
+#define IXGBE_GSSR      0x10160
+#define IXGBE_MREVID    0x11064
+#define IXGBE_DCA_ID    0x11070
+#define IXGBE_DCA_CTRL  0x11074
+#define IXGBE_SWFW_SYNC IXGBE_GSSR
 
 /* PCI-E registers 82599-Specific */
-#define	IXGBE_GCR_EXT		0x11050
-#define	IXGBE_GSCL_5_82599	0x11030
-#define	IXGBE_GSCL_6_82599	0x11034
-#define	IXGBE_GSCL_7_82599	0x11038
-#define	IXGBE_GSCL_8_82599	0x1103C
-#define	IXGBE_PHYADR_82599	0x11040
-#define	IXGBE_PHYDAT_82599	0x11044
-#define	IXGBE_PHYCTL_82599	0x11048
-#define	IXGBE_PBACLR_82599	0x11068
-#define	IXGBE_CIAA_82599	0x11088
-#define	IXGBE_CIAD_82599	0x1108C
-#define	IXGBE_INTRPT_CSR_82599	0x110B0
-#define	IXGBE_INTRPT_MASK_82599	0x110B8
-#define	IXGBE_CDQ_MBR_82599	0x110B4
-#define	IXGBE_MISC_REG_82599	0x110F0
-#define	IXGBE_ECC_CTRL_0_82599	0x11100
-#define	IXGBE_ECC_CTRL_1_82599	0x11104
-#define	IXGBE_ECC_STATUS_82599	0x110E0
-#define	IXGBE_BAR_CTRL_82599	0x110F4
+#define IXGBE_GCR_EXT           0x11050
+#define IXGBE_GSCL_5_82599      0x11030
+#define IXGBE_GSCL_6_82599      0x11034
+#define IXGBE_GSCL_7_82599      0x11038
+#define IXGBE_GSCL_8_82599      0x1103C
+#define IXGBE_PHYADR_82599      0x11040
+#define IXGBE_PHYDAT_82599      0x11044
+#define IXGBE_PHYCTL_82599      0x11048
+#define IXGBE_PBACLR_82599      0x11068
+#define IXGBE_CIAA_82599        0x11088
+#define IXGBE_CIAD_82599        0x1108C
+#define IXGBE_INTRPT_CSR_82599  0x110B0
+#define IXGBE_INTRPT_MASK_82599 0x110B8
+#define IXGBE_CDQ_MBR_82599     0x110B4
+#define IXGBE_MISC_REG_82599    0x110F0
+#define IXGBE_ECC_CTRL_0_82599  0x11100
+#define IXGBE_ECC_CTRL_1_82599  0x11104
+#define IXGBE_ECC_STATUS_82599  0x110E0
+#define IXGBE_BAR_CTRL_82599    0x110F4
 
 /* PCI Express Control */
-#define	IXGBE_GCR_CMPL_TMOUT_MASK	0x0000F000
-#define	IXGBE_GCR_CMPL_TMOUT_10ms	0x00001000
-#define	IXGBE_GCR_CMPL_TMOUT_RESEND	0x00010000
-#define	IXGBE_GCR_CAP_VER2		0x00040000
+#define IXGBE_GCR_CMPL_TMOUT_MASK       0x0000F000
+#define IXGBE_GCR_CMPL_TMOUT_10ms       0x00001000
+#define IXGBE_GCR_CMPL_TMOUT_RESEND     0x00010000
+#define IXGBE_GCR_CAP_VER2              0x00040000
 
-#define	IXGBE_GCR_EXT_MSIX_EN		0x80000000
-#define	IXGBE_GCR_EXT_VT_MODE_16	0x00000001
-#define	IXGBE_GCR_EXT_VT_MODE_32	0x00000002
-#define	IXGBE_GCR_EXT_VT_MODE_64	0x00000003
-#define	IXGBE_GCR_EXT_SRIOV		(IXGBE_GCR_EXT_MSIX_EN | \
-					IXGBE_GCR_EXT_VT_MODE_64)
+#define IXGBE_GCR_EXT_MSIX_EN           0x80000000
+#define IXGBE_GCR_EXT_VT_MODE_16        0x00000001
+#define IXGBE_GCR_EXT_VT_MODE_32        0x00000002
+#define IXGBE_GCR_EXT_VT_MODE_64        0x00000003
+#define IXGBE_GCR_EXT_SRIOV             (IXGBE_GCR_EXT_MSIX_EN | \
+                                         IXGBE_GCR_EXT_VT_MODE_64)
 /* Time Sync Registers */
-#define	IXGBE_TSYNCRXCTL	0x05188 /* Rx Time Sync Control register - RW */
-#define	IXGBE_TSYNCTXCTL	0x08C00 /* Tx Time Sync Control register - RW */
-#define	IXGBE_RXSTMPL	0x051E8 /* Rx timestamp Low - RO */
-#define	IXGBE_RXSTMPH	0x051A4 /* Rx timestamp High - RO */
-#define	IXGBE_RXSATRL	0x051A0 /* Rx timestamp attribute low - RO */
-#define	IXGBE_RXSATRH	0x051A8 /* Rx timestamp attribute high - RO */
-#define	IXGBE_RXMTRL	0x05120 /* RX message type register low - RW */
-#define	IXGBE_TXSTMPL	0x08C04 /* Tx timestamp value Low - RO */
-#define	IXGBE_TXSTMPH	0x08C08 /* Tx timestamp value High - RO */
-#define	IXGBE_SYSTIML	0x08C0C /* System time register Low - RO */
-#define	IXGBE_SYSTIMH	0x08C10 /* System time register High - RO */
-#define	IXGBE_TIMINCA	0x08C14 /* Increment attributes register - RW */
-#define	IXGBE_RXUDP	0x08C1C /* Time Sync Rx UDP Port - RW */
+#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
+#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
+#define IXGBE_RXSTMPL    0x051E8 /* Rx timestamp Low - RO */
+#define IXGBE_RXSTMPH    0x051A4 /* Rx timestamp High - RO */
+#define IXGBE_RXSATRL    0x051A0 /* Rx timestamp attribute low - RO */
+#define IXGBE_RXSATRH    0x051A8 /* Rx timestamp attribute high - RO */
+#define IXGBE_RXMTRL     0x05120 /* RX message type register low - RW */
+#define IXGBE_TXSTMPL    0x08C04 /* Tx timestamp value Low - RO */
+#define IXGBE_TXSTMPH    0x08C08 /* Tx timestamp value High - RO */
+#define IXGBE_SYSTIML    0x08C0C /* System time register Low - RO */
+#define IXGBE_SYSTIMH    0x08C10 /* System time register High - RO */
+#define IXGBE_TIMINCA    0x08C14 /* Increment attributes register - RW */
+#define IXGBE_RXUDP      0x08C1C /* Time Sync Rx UDP Port - RW */
 
 /* Diagnostic Registers */
-#define	IXGBE_RDSTATCTL		0x02C20
-#define	IXGBE_RDSTAT(_i)	(0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
-#define	IXGBE_RDHMPN		0x02F08
-#define	IXGBE_RIC_DW(_i)	(0x02F10 + ((_i) * 4))
-#define	IXGBE_RDPROBE		0x02F20
-#define	IXGBE_RDMAM		0x02F30
-#define	IXGBE_RDMAD		0x02F34
-#define	IXGBE_TDSTATCTL		0x07C20
-#define	IXGBE_TDSTAT(_i)	(0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
-#define	IXGBE_TDHMPN		0x07F08
-#define	IXGBE_TDHMPN2		0x082FC
-#define	IXGBE_TXDESCIC		0x082CC
-#define	IXGBE_TIC_DW(_i)	(0x07F10 + ((_i) * 4))
-#define	IXGBE_TIC_DW2(_i)	(0x082B0 + ((_i) * 4))
-#define	IXGBE_TDPROBE		0x07F20
-#define	IXGBE_TXBUFCTRL		0x0C600
-#define	IXGBE_TXBUFDATA0	0x0C610
-#define	IXGBE_TXBUFDATA1	0x0C614
-#define	IXGBE_TXBUFDATA2	0x0C618
-#define	IXGBE_TXBUFDATA3	0x0C61C
-#define	IXGBE_RXBUFCTRL		0x03600
-#define	IXGBE_RXBUFDATA0	0x03610
-#define	IXGBE_RXBUFDATA1	0x03614
-#define	IXGBE_RXBUFDATA2	0x03618
-#define	IXGBE_RXBUFDATA3	0x0361C
-#define	IXGBE_PCIE_DIAG(_i)	(0x11090 + ((_i) * 4)) /* 8 of these */
-#define	IXGBE_RFVAL		0x050A4
-#define	IXGBE_MDFTC1		0x042B8
-#define	IXGBE_MDFTC2		0x042C0
-#define	IXGBE_MDFTFIFO1		0x042C4
-#define	IXGBE_MDFTFIFO2		0x042C8
-#define	IXGBE_MDFTS		0x042CC
-#define	IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C */
-#define	IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C */
-#define	IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C */
-#define	IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C */
-#define	IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C */
-#define	IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C */
-#define	IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C */
-#define	IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C */
-#define	IXGBE_PCIEECCCTL	0x1106C
-#define	IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C */
-#define	IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C */
-#define	IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C */
-#define	IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C */
-#define	IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C */
-#define	IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C */
-#define	IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C */
-#define	IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C */
-#define	IXGBE_PCIEECCCTL0	0x11100
-#define	IXGBE_PCIEECCCTL1	0x11104
-#define	IXGBE_RXDBUECC		0x03F70
-#define	IXGBE_TXDBUECC		0x0CF70
-#define	IXGBE_RXDBUEST		0x03F74
-#define	IXGBE_TXDBUEST		0x0CF74
-#define	IXGBE_PBTXECC		0x0C300
-#define	IXGBE_PBRXECC		0x03300
-#define	IXGBE_GHECCR		0x110B0
+#define IXGBE_RDSTATCTL   0x02C20
+#define IXGBE_RDSTAT(_i)  (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
+#define IXGBE_RDHMPN      0x02F08
+#define IXGBE_RIC_DW(_i)  (0x02F10 + ((_i) * 4))
+#define IXGBE_RDPROBE     0x02F20
+#define IXGBE_RDMAM       0x02F30
+#define IXGBE_RDMAD       0x02F34
+#define IXGBE_TDSTATCTL   0x07C20
+#define IXGBE_TDSTAT(_i)  (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
+#define IXGBE_TDHMPN      0x07F08
+#define IXGBE_TDHMPN2     0x082FC
+#define IXGBE_TXDESCIC    0x082CC
+#define IXGBE_TIC_DW(_i)  (0x07F10 + ((_i) * 4))
+#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
+#define IXGBE_TDPROBE     0x07F20
+#define IXGBE_TXBUFCTRL   0x0C600
+#define IXGBE_TXBUFDATA0  0x0C610
+#define IXGBE_TXBUFDATA1  0x0C614
+#define IXGBE_TXBUFDATA2  0x0C618
+#define IXGBE_TXBUFDATA3  0x0C61C
+#define IXGBE_RXBUFCTRL   0x03600
+#define IXGBE_RXBUFDATA0  0x03610
+#define IXGBE_RXBUFDATA1  0x03614
+#define IXGBE_RXBUFDATA2  0x03618
+#define IXGBE_RXBUFDATA3  0x0361C
+#define IXGBE_PCIE_DIAG(_i)     (0x11090 + ((_i) * 4)) /* 8 of these */
+#define IXGBE_RFVAL     0x050A4
+#define IXGBE_MDFTC1    0x042B8
+#define IXGBE_MDFTC2    0x042C0
+#define IXGBE_MDFTFIFO1 0x042C4
+#define IXGBE_MDFTFIFO2 0x042C8
+#define IXGBE_MDFTS     0x042CC
+#define IXGBE_RXDATAWRPTR(_i)   (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
+#define IXGBE_RXDESCWRPTR(_i)   (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
+#define IXGBE_RXDATARDPTR(_i)   (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
+#define IXGBE_RXDESCRDPTR(_i)   (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
+#define IXGBE_TXDATAWRPTR(_i)   (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
+#define IXGBE_TXDESCWRPTR(_i)   (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
+#define IXGBE_TXDATARDPTR(_i)   (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
+#define IXGBE_TXDESCRDPTR(_i)   (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
+#define IXGBE_PCIEECCCTL 0x1106C
+#define IXGBE_RXWRPTR(_i)       (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
+#define IXGBE_RXUSED(_i)        (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
+#define IXGBE_RXRDPTR(_i)       (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
+#define IXGBE_RXRDWRPTR(_i)     (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
+#define IXGBE_TXWRPTR(_i)       (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
+#define IXGBE_TXUSED(_i)        (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
+#define IXGBE_TXRDPTR(_i)       (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
+#define IXGBE_TXRDWRPTR(_i)     (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
+#define IXGBE_PCIEECCCTL0 0x11100
+#define IXGBE_PCIEECCCTL1 0x11104
+#define IXGBE_RXDBUECC  0x03F70
+#define IXGBE_TXDBUECC  0x0CF70
+#define IXGBE_RXDBUEST 0x03F74
+#define IXGBE_TXDBUEST 0x0CF74
+#define IXGBE_PBTXECC   0x0C300
+#define IXGBE_PBRXECC   0x03300
+#define IXGBE_GHECCR    0x110B0
 
 /* MAC Registers */
-#define	IXGBE_PCS1GCFIG		0x04200
-#define	IXGBE_PCS1GLCTL		0x04208
-#define	IXGBE_PCS1GLSTA		0x0420C
-#define	IXGBE_PCS1GDBG0		0x04210
-#define	IXGBE_PCS1GDBG1		0x04214
-#define	IXGBE_PCS1GANA		0x04218
-#define	IXGBE_PCS1GANLP		0x0421C
-#define	IXGBE_PCS1GANNP		0x04220
-#define	IXGBE_PCS1GANLPNP	0x04224
-#define	IXGBE_HLREG0		0x04240
-#define	IXGBE_HLREG1		0x04244
-#define	IXGBE_PAP		0x04248
-#define	IXGBE_MACA		0x0424C
-#define	IXGBE_APAE		0x04250
-#define	IXGBE_ARD		0x04254
-#define	IXGBE_AIS		0x04258
-#define	IXGBE_MSCA		0x0425C
-#define	IXGBE_MSRWD		0x04260
-#define	IXGBE_MLADD		0x04264
-#define	IXGBE_MHADD		0x04268
-#define	IXGBE_MAXFRS		0x04268
-#define	IXGBE_TREG		0x0426C
-#define	IXGBE_PCSS1		0x04288
-#define	IXGBE_PCSS2		0x0428C
-#define	IXGBE_XPCSS		0x04290
-#define	IXGBE_MFLCN		0x04294
-#define	IXGBE_SERDESC		0x04298
-#define	IXGBE_MACS		0x0429C
-#define	IXGBE_AUTOC		0x042A0
-#define	IXGBE_LINKS		0x042A4
-#define	IXGBE_LINKS2		0x04324
-#define	IXGBE_AUTOC2		0x042A8
-#define	IXGBE_AUTOC3		0x042AC
-#define	IXGBE_ANLP1		0x042B0
-#define	IXGBE_ANLP2		0x042B4
-#define	IXGBE_ATLASCTL		0x04800
-#define	IXGBE_MMNGC		0x042D0
-#define	IXGBE_ANLPNP1		0x042D4
-#define	IXGBE_ANLPNP2		0x042D8
-#define	IXGBE_KRPCSFC		0x042E0
-#define	IXGBE_KRPCSS		0x042E4
-#define	IXGBE_FECS1		0x042E8
-#define	IXGBE_FECS2		0x042EC
-#define	IXGBE_SMADARCTL		0x14F10
-#define	IXGBE_MPVC		0x04318
-#define	IXGBE_SGMIIC		0x04314
+#define IXGBE_PCS1GCFIG 0x04200
+#define IXGBE_PCS1GLCTL 0x04208
+#define IXGBE_PCS1GLSTA 0x0420C
+#define IXGBE_PCS1GDBG0 0x04210
+#define IXGBE_PCS1GDBG1 0x04214
+#define IXGBE_PCS1GANA  0x04218
+#define IXGBE_PCS1GANLP 0x0421C
+#define IXGBE_PCS1GANNP 0x04220
+#define IXGBE_PCS1GANLPNP 0x04224
+#define IXGBE_HLREG0    0x04240
+#define IXGBE_HLREG1    0x04244
+#define IXGBE_PAP       0x04248
+#define IXGBE_MACA      0x0424C
+#define IXGBE_APAE      0x04250
+#define IXGBE_ARD       0x04254
+#define IXGBE_AIS       0x04258
+#define IXGBE_MSCA      0x0425C
+#define IXGBE_MSRWD     0x04260
+#define IXGBE_MLADD     0x04264
+#define IXGBE_MHADD     0x04268
+#define IXGBE_MAXFRS    0x04268
+#define IXGBE_TREG      0x0426C
+#define IXGBE_PCSS1     0x04288
+#define IXGBE_PCSS2     0x0428C
+#define IXGBE_XPCSS     0x04290
+#define IXGBE_MFLCN     0x04294
+#define IXGBE_SERDESC   0x04298
+#define IXGBE_MACS      0x0429C
+#define IXGBE_AUTOC     0x042A0
+#define IXGBE_LINKS     0x042A4
+#define IXGBE_LINKS2    0x04324
+#define IXGBE_AUTOC2    0x042A8
+#define IXGBE_AUTOC3    0x042AC
+#define IXGBE_ANLP1     0x042B0
+#define IXGBE_ANLP2     0x042B4
+#define IXGBE_ATLASCTL  0x04800
+#define IXGBE_MMNGC     0x042D0
+#define IXGBE_ANLPNP1   0x042D4
+#define IXGBE_ANLPNP2   0x042D8
+#define IXGBE_KRPCSFC   0x042E0
+#define IXGBE_KRPCSS    0x042E4
+#define IXGBE_FECS1     0x042E8
+#define IXGBE_FECS2     0x042EC
+#define IXGBE_SMADARCTL 0x14F10
+#define IXGBE_MPVC      0x04318
+#define IXGBE_SGMIIC    0x04314
 
 /* Copper Pond 2 link timeout */
-#define	IXGBE_VALIDATE_LINK_READY_TIMEOUT	50
+#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
 
 /* Omer CORECTL */
-#define	IXGBE_CORECTL		0x014F00
+#define IXGBE_CORECTL           0x014F00
 /* BARCTRL */
-#define	IXGBE_BARCTRL		0x110F4
-#define	IXGBE_BARCTRL_FLSIZE	0x0700
-#define	IXGBE_BARCTRL_FLSIZE_SHIFT	8
-#define	IXGBE_BARCTRL_CSRSIZE	0x2000
+#define IXGBE_BARCTRL               0x110F4
+#define IXGBE_BARCTRL_FLSIZE        0x0700
+#define IXGBE_BARCTRL_FLSIZE_SHIFT  8
+#define IXGBE_BARCTRL_CSRSIZE       0x2000
 
 /* RSCCTL Bit Masks */
-#define	IXGBE_RSCCTL_RSCEN	0x01
-#define	IXGBE_RSCCTL_MAXDESC_1	0x00
-#define	IXGBE_RSCCTL_MAXDESC_4	0x04
-#define	IXGBE_RSCCTL_MAXDESC_8	0x08
-#define	IXGBE_RSCCTL_MAXDESC_16	0x0C
+#define IXGBE_RSCCTL_RSCEN          0x01
+#define IXGBE_RSCCTL_MAXDESC_1      0x00
+#define IXGBE_RSCCTL_MAXDESC_4      0x04
+#define IXGBE_RSCCTL_MAXDESC_8      0x08
+#define IXGBE_RSCCTL_MAXDESC_16     0x0C
 
 /* RSCDBU Bit Masks */
-#define	IXGBE_RSCDBU_RSCSMALDIS_MASK	0x0000007F
-#define	IXGBE_RSCDBU_RSCACKDIS		0x00000080
+#define IXGBE_RSCDBU_RSCSMALDIS_MASK    0x0000007F
+#define IXGBE_RSCDBU_RSCACKDIS          0x00000080
 
 /* RDRXCTL Bit Masks */
-#define	IXGBE_RDRXCTL_RDMTS_1_2	0x00000000 /* Rx Desc Min Threshold Size */
-#define	IXGBE_RDRXCTL_CRCSTRIP	0x00000002 /* CRC Strip */
-#define	IXGBE_RDRXCTL_MVMEN	0x00000020
-#define	IXGBE_RDRXCTL_DMAIDONE	0x00000008 /* DMA init cycle done */
-#define	IXGBE_RDRXCTL_AGGDIS	0x00010000 /* Aggregation disable */
-#define	IXGBE_RDRXCTL_RSCFRSTSIZE	0x003E0000 /* RSC First packet size */
-#define	IXGBE_RDRXCTL_RSCLLIDIS	0x00800000 /* Disable RSC compl on LLI */
-#define	IXGBE_RDRXCTL_RSCACKC	0x02000000 /* must set 1 when RSC enabled */
-#define	IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */
+#define IXGBE_RDRXCTL_RDMTS_1_2     0x00000000 /* Rx Desc Min Threshold Size */
+#define IXGBE_RDRXCTL_CRCSTRIP      0x00000002 /* CRC Strip */
+#define IXGBE_RDRXCTL_MVMEN         0x00000020
+#define IXGBE_RDRXCTL_DMAIDONE      0x00000008 /* DMA init cycle done */
+#define IXGBE_RDRXCTL_AGGDIS        0x00010000 /* Aggregation disable */
+#define IXGBE_RDRXCTL_RSCFRSTSIZE   0x003E0000 /* RSC First packet size */
+#define IXGBE_RDRXCTL_RSCLLIDIS     0x00800000 /* Disable RSC compl on LLI */
+#define IXGBE_RDRXCTL_RSCACKC       0x02000000 /* must set 1 when RSC enabled */
+#define IXGBE_RDRXCTL_FCOE_WRFIX    0x04000000 /* must set 1 when RSC enabled */
 
 /* RQTC Bit Masks and Shifts */
-#define	IXGBE_RQTC_SHIFT_TC(_i)	((_i) * 4)
-#define	IXGBE_RQTC_TC0_MASK	(0x7 << 0)
-#define	IXGBE_RQTC_TC1_MASK	(0x7 << 4)
-#define	IXGBE_RQTC_TC2_MASK	(0x7 << 8)
-#define	IXGBE_RQTC_TC3_MASK	(0x7 << 12)
-#define	IXGBE_RQTC_TC4_MASK	(0x7 << 16)
-#define	IXGBE_RQTC_TC5_MASK	(0x7 << 20)
-#define	IXGBE_RQTC_TC6_MASK	(0x7 << 24)
-#define	IXGBE_RQTC_TC7_MASK	(0x7 << 28)
+#define IXGBE_RQTC_SHIFT_TC(_i)     ((_i) * 4)
+#define IXGBE_RQTC_TC0_MASK         (0x7 << 0)
+#define IXGBE_RQTC_TC1_MASK         (0x7 << 4)
+#define IXGBE_RQTC_TC2_MASK         (0x7 << 8)
+#define IXGBE_RQTC_TC3_MASK         (0x7 << 12)
+#define IXGBE_RQTC_TC4_MASK         (0x7 << 16)
+#define IXGBE_RQTC_TC5_MASK         (0x7 << 20)
+#define IXGBE_RQTC_TC6_MASK         (0x7 << 24)
+#define IXGBE_RQTC_TC7_MASK         (0x7 << 28)
 
 /* PSRTYPE.RQPL Bit masks and shift */
-#define	IXGBE_PSRTYPE_RQPL_MASK		0x7
-#define	IXGBE_PSRTYPE_RQPL_SHIFT	29
+#define IXGBE_PSRTYPE_RQPL_MASK     0x7
+#define IXGBE_PSRTYPE_RQPL_SHIFT    29
 
 /* CTRL Bit Masks */
-#define	IXGBE_CTRL_GIO_DIS	0x00000004 /* Global IO Master Disable bit */
-#define	IXGBE_CTRL_LNK_RST	0x00000008 /* Link Reset. Resets everything. */
-#define	IXGBE_CTRL_RST		0x04000000 /* Reset (SW) */
+#define IXGBE_CTRL_GIO_DIS      0x00000004 /* Global IO Master Disable bit */
+#define IXGBE_CTRL_LNK_RST      0x00000008 /* Link Reset. Resets everything. */
+#define IXGBE_CTRL_RST          0x04000000 /* Reset (SW) */
 
 /* FACTPS */
-#define	IXGBE_FACTPS_LFS	0x40000000 /* LAN Function Select */
+#define IXGBE_FACTPS_LFS        0x40000000 /* LAN Function Select */
 
 /* MHADD Bit Masks */
-#define	IXGBE_MHADD_MFS_MASK	0xFFFF0000
-#define	IXGBE_MHADD_MFS_SHIFT	16
+#define IXGBE_MHADD_MFS_MASK    0xFFFF0000
+#define IXGBE_MHADD_MFS_SHIFT   16
 
 /* Extended Device Control */
-#define	IXGBE_CTRL_EXT_PFRSTD	0x00004000 /* Physical Function Reset Done */
-#define	IXGBE_CTRL_EXT_NS_DIS	0x00010000 /* No Snoop disable */
-#define	IXGBE_CTRL_EXT_RO_DIS	0x00020000 /* Relaxed Ordering disable */
-#define	IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
+#define IXGBE_CTRL_EXT_PFRSTD   0x00004000 /* Physical Function Reset Done */
+#define IXGBE_CTRL_EXT_NS_DIS   0x00010000 /* No Snoop disable */
+#define IXGBE_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
+#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
 
 /* Direct Cache Access (DCA) definitions */
-#define	IXGBE_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
-#define	IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
+#define IXGBE_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
+#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
 
-#define	IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
-#define	IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
+#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
+#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
 
-#define	IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
-#define	IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
-#define	IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
-#define	IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
-#define	IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
-#define	IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
-#define	IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
-#define	IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */
-#define	IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */
+#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
+#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599  0xFF000000 /* Rx CPUID Mask */
+#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
+#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
+#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
+#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
+#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
+#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */
+#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */
 
-#define	IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
-#define	IXGBE_DCA_TXCTRL_CPUID_MASK_82599  0xFF000000 /* Tx CPUID Mask */
-#define	IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
-#define	IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
-#define	IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
-#define	IXGBE_DCA_MAX_QUEUES_82598   16 /* DCA regs only on 16 queues */
+#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
+#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599  0xFF000000 /* Tx CPUID Mask */
+#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
+#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
+#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
+#define IXGBE_DCA_MAX_QUEUES_82598   16 /* DCA regs only on 16 queues */
 
 /* MSCA Bit Masks */
-#define	IXGBE_MSCA_NP_ADDR_MASK		0x0000FFFF
-					/* MDI Address (new protocol) */
-#define	IXGBE_MSCA_NP_ADDR_SHIFT	0
-#define	IXGBE_MSCA_DEV_TYPE_MASK	0x001F0000
-					/* Device Type (new protocol) */
-#define	IXGBE_MSCA_DEV_TYPE_SHIFT	16 /* Register Address (old protocol */
-#define	IXGBE_MSCA_PHY_ADDR_MASK	0x03E00000 /* PHY Address mask */
-#define	IXGBE_MSCA_PHY_ADDR_SHIFT	21 /* PHY Address shift */
-#define	IXGBE_MSCA_OP_CODE_MASK		0x0C000000 /* OP CODE mask */
-#define	IXGBE_MSCA_OP_CODE_SHIFT	26 /* OP CODE shift */
-#define	IXGBE_MSCA_ADDR_CYCLE		0x00000000 /* OP CODE 00 (addr cycle) */
-#define	IXGBE_MSCA_WRITE		0x04000000 /* OP CODE 01 (write) */
-#define	IXGBE_MSCA_READ			0x08000000 /* OP CODE 10 (read) */
-#define	IXGBE_MSCA_READ_AUTOINC		0x0C000000
-					/* OP CODE 11 (read, auto inc) */
-#define	IXGBE_MSCA_ST_CODE_MASK		0x30000000 /* ST Code mask */
-#define	IXGBE_MSCA_ST_CODE_SHIFT	28 /* ST Code shift */
-#define	IXGBE_MSCA_NEW_PROTOCOL		0x00000000
-					/* ST CODE 00 (new protocol) */
-#define	IXGBE_MSCA_OLD_PROTOCOL		0x10000000
-					/* ST CODE 01 (old protocol) */
-#define	IXGBE_MSCA_MDI_COMMAND		0x40000000 /* Initiate MDI command */
-#define	IXGBE_MSCA_MDI_IN_PROG_EN	0x80000000 /* MDI in progress enable */
+#define IXGBE_MSCA_NP_ADDR_MASK      0x0000FFFF /* MDI Address (new protocol) */
+#define IXGBE_MSCA_NP_ADDR_SHIFT     0
+#define IXGBE_MSCA_DEV_TYPE_MASK     0x001F0000 /* Device Type (new protocol) */
+#define IXGBE_MSCA_DEV_TYPE_SHIFT    16 /* Register Address (old protocol */
+#define IXGBE_MSCA_PHY_ADDR_MASK     0x03E00000 /* PHY Address mask */
+#define IXGBE_MSCA_PHY_ADDR_SHIFT    21 /* PHY Address shift*/
+#define IXGBE_MSCA_OP_CODE_MASK      0x0C000000 /* OP CODE mask */
+#define IXGBE_MSCA_OP_CODE_SHIFT     26 /* OP CODE shift */
+#define IXGBE_MSCA_ADDR_CYCLE        0x00000000 /* OP CODE 00 (addr cycle) */
+#define IXGBE_MSCA_WRITE             0x04000000 /* OP CODE 01 (write) */
+#define IXGBE_MSCA_READ              0x0C000000 /* OP CODE 11 (read) */
+#define IXGBE_MSCA_READ_AUTOINC      0x08000000 /* OP CODE 10 (read, auto inc)*/
+#define IXGBE_MSCA_ST_CODE_MASK      0x30000000 /* ST Code mask */
+#define IXGBE_MSCA_ST_CODE_SHIFT     28 /* ST Code shift */
+#define IXGBE_MSCA_NEW_PROTOCOL      0x00000000 /* ST CODE 00 (new protocol) */
+#define IXGBE_MSCA_OLD_PROTOCOL      0x10000000 /* ST CODE 01 (old protocol) */
+#define IXGBE_MSCA_MDI_COMMAND       0x40000000 /* Initiate MDI command */
+#define IXGBE_MSCA_MDI_IN_PROG_EN    0x80000000 /* MDI in progress enable */
 
 /* MSRWD bit masks */
-#define	IXGBE_MSRWD_WRITE_DATA_MASK	0x0000FFFF
-#define	IXGBE_MSRWD_WRITE_DATA_SHIFT	0
-#define	IXGBE_MSRWD_READ_DATA_MASK	0xFFFF0000
-#define	IXGBE_MSRWD_READ_DATA_SHIFT	16
+#define IXGBE_MSRWD_WRITE_DATA_MASK     0x0000FFFF
+#define IXGBE_MSRWD_WRITE_DATA_SHIFT    0
+#define IXGBE_MSRWD_READ_DATA_MASK      0xFFFF0000
+#define IXGBE_MSRWD_READ_DATA_SHIFT     16
 
 /* Atlas registers */
-#define	IXGBE_ATLAS_PDN_LPBK		0x24
-#define	IXGBE_ATLAS_PDN_10G		0xB
-#define	IXGBE_ATLAS_PDN_1G		0xC
-#define	IXGBE_ATLAS_PDN_AN		0xD
+#define IXGBE_ATLAS_PDN_LPBK    0x24
+#define IXGBE_ATLAS_PDN_10G     0xB
+#define IXGBE_ATLAS_PDN_1G      0xC
+#define IXGBE_ATLAS_PDN_AN      0xD
 
 /* Atlas bit masks */
-#define	IXGBE_ATLASCTL_WRITE_CMD	0x00010000
-#define	IXGBE_ATLAS_PDN_TX_REG_EN	0x10
-#define	IXGBE_ATLAS_PDN_TX_10G_QL_ALL	0xF0
-#define	IXGBE_ATLAS_PDN_TX_1G_QL_ALL	0xF0
-#define	IXGBE_ATLAS_PDN_TX_AN_QL_ALL	0xF0
+#define IXGBE_ATLASCTL_WRITE_CMD        0x00010000
+#define IXGBE_ATLAS_PDN_TX_REG_EN       0x10
+#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL   0xF0
+#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL    0xF0
+#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL    0xF0
 
 /* Omer bit masks */
-#define	IXGBE_CORECTL_WRITE_CMD		0x00010000
+#define IXGBE_CORECTL_WRITE_CMD         0x00010000
 
 /* Device Type definitions for new protocol MDIO commands */
-#define	IXGBE_MDIO_PMA_PMD_DEV_TYPE		0x1
-#define	IXGBE_MDIO_PCS_DEV_TYPE			0x3
-#define	IXGBE_MDIO_PHY_XS_DEV_TYPE		0x4
-#define	IXGBE_MDIO_AUTO_NEG_DEV_TYPE		0x7
-#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE	0x1E   /* Device 30 */
-#define	IXGBE_TWINAX_DEV			1
+#define IXGBE_MDIO_PMA_PMD_DEV_TYPE               0x1
+#define IXGBE_MDIO_PCS_DEV_TYPE                   0x3
+#define IXGBE_MDIO_PHY_XS_DEV_TYPE                0x4
+#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE              0x7
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE     0x1E   /* Device 30 */
+#define IXGBE_TWINAX_DEV                          1
 
-#define	IXGBE_MDIO_COMMAND_TIMEOUT	100 /* PHY Timeout for 1 GB mode */
+#define IXGBE_MDIO_COMMAND_TIMEOUT     100 /* PHY Timeout for 1 GB mode */
 
-#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL	0x0    /* VS1 Control Reg */
-#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS	0x1    /* VS1 Status Reg */
-#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
-#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
-#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED	0x0018
-#define	IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED	0x0010
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL      0x0    /* VS1 Control Reg */
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS       0x1    /* VS1 Status Reg */
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS  0x0008 /* 1 = Link Up */
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED    0x0018
+#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED     0x0010
 
-#define	IXGBE_MDIO_AUTO_NEG_CONTROL	0x0 /* AUTO_NEG Control Reg */
-#define	IXGBE_MDIO_AUTO_NEG_STATUS	0x1 /* AUTO_NEG Status Reg */
-#define	IXGBE_MDIO_AUTO_NEG_ADVT	0x10 /* AUTO_NEG Advt Reg */
-#define	IXGBE_MDIO_AUTO_NEG_LP		0x13 /* AUTO_NEG LP Status Reg */
-#define	IXGBE_MDIO_PHY_XS_CONTROL	0x0 /* PHY_XS Control Reg */
-#define	IXGBE_MDIO_PHY_XS_RESET		0x8000 /* PHY_XS Reset */
-#define	IXGBE_MDIO_PHY_ID_HIGH		0x2 /* PHY ID High Reg */
-#define	IXGBE_MDIO_PHY_ID_LOW		0x3 /* PHY ID Low Reg */
-#define	IXGBE_MDIO_PHY_SPEED_ABILITY	0x4 /* Speed Ability Reg */
-#define	IXGBE_MDIO_PHY_SPEED_10G	0x0001 /* 10G capable */
-#define	IXGBE_MDIO_PHY_SPEED_1G		0x0010 /* 1G capable */
-#define	IXGBE_MDIO_PHY_SPEED_100M	0x0020 /* 100M capable */
-#define	IXGBE_MDIO_PHY_EXT_ABILITY	0xB /* Ext Ability Reg */
-#define	IXGBE_MDIO_PHY_10GBASET_ABILITY	0x0004 /* 10GBaseT capable */
-#define	IXGBE_MDIO_PHY_1000BASET_ABILITY	0x0020 /* 1000BaseT capable */
-#define	IXGBE_MDIO_PHY_100BASETX_ABILITY	0x0080 /* 100BaseTX capable */
-#define	IXGBE_MDIO_PHY_SET_LOW_POWER_MODE	0x0800 /* Set low power mode */
+#define IXGBE_MDIO_AUTO_NEG_CONTROL    0x0 /* AUTO_NEG Control Reg */
+#define IXGBE_MDIO_AUTO_NEG_STATUS     0x1 /* AUTO_NEG Status Reg */
+#define IXGBE_MDIO_AUTO_NEG_ADVT       0x10 /* AUTO_NEG Advt Reg */
+#define IXGBE_MDIO_AUTO_NEG_LP         0x13 /* AUTO_NEG LP Status Reg */
+#define IXGBE_MDIO_PHY_XS_CONTROL      0x0 /* PHY_XS Control Reg */
+#define IXGBE_MDIO_PHY_XS_RESET        0x8000 /* PHY_XS Reset */
+#define IXGBE_MDIO_PHY_ID_HIGH         0x2 /* PHY ID High Reg*/
+#define IXGBE_MDIO_PHY_ID_LOW          0x3 /* PHY ID Low Reg*/
+#define IXGBE_MDIO_PHY_SPEED_ABILITY   0x4 /* Speed Ability Reg */
+#define IXGBE_MDIO_PHY_SPEED_10G       0x0001 /* 10G capable */
+#define IXGBE_MDIO_PHY_SPEED_1G        0x0010 /* 1G capable */
+#define IXGBE_MDIO_PHY_SPEED_100M      0x0020 /* 100M capable */
+#define IXGBE_MDIO_PHY_EXT_ABILITY        0xB /* Ext Ability Reg */
+#define IXGBE_MDIO_PHY_10GBASET_ABILITY   0x0004 /* 10GBaseT capable */
+#define IXGBE_MDIO_PHY_1000BASET_ABILITY  0x0020 /* 1000BaseT capable */
+#define IXGBE_MDIO_PHY_100BASETX_ABILITY  0x0080 /* 100BaseTX capable */
+#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */
 
-#define	IXGBE_MDIO_PMA_PMD_CONTROL_ADDR	0x0000 /* PMA/PMD Control Reg */
+#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR     0x0000 /* PMA/PMD Control Reg */
+#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR     0xC30A /* PHY_XS SDA/SCL Addr Reg */
+#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA     0xC30B /* PHY_XS SDA/SCL Data Reg */
+#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT     0xC30C /* PHY_XS SDA/SCL Status Reg */
 
-#define	IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR	0xC30A	/* PHY_XS SDA/SCL Addr Reg */
-#define	IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA	0xC30B	/* PHY_XS SDA/SCL Data Reg */
-#define	IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT	0xC30C	/* PHY_XS SDA/SCL Status Reg */
-
 /* MII clause 22/28 definitions */
-#define	IXGBE_MDIO_PHY_LOW_POWER_MODE	0x0800
+#define IXGBE_MDIO_PHY_LOW_POWER_MODE  0x0800
 
-#define	IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG	0x20   /* 10G Control Reg */
-#define	IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
-#define	IXGBE_MII_AUTONEG_XNP_TX_REG		0x17   /* 1G XNP Transmit */
-#define	IXGBE_MII_AUTONEG_ADVERTISE_REG		0x10   /* 100M Advertisement */
-#define	IXGBE_MII_10GBASE_T_ADVERTISE		0x1000 /* full duplex, bit:12 */
-#define	IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX	0x4000 /* full duplex, bit:14 */
-#define	IXGBE_MII_1GBASE_T_ADVERTISE		0x8000 /* full duplex, bit:15 */
-#define	IXGBE_MII_100BASE_T_ADVERTISE		0x0100 /* full duplex, bit:8 */
-#define	IXGBE_MII_RESTART		0x200
-#define	IXGBE_MII_AUTONEG_COMPLETE	0x20
-#define	IXGBE_MII_AUTONEG_LINK_UP	0x04
-#define	IXGBE_MII_AUTONEG_REG		0x0
+#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG     0x20   /* 10G Control Reg */
+#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
+#define IXGBE_MII_AUTONEG_XNP_TX_REG             0x17   /* 1G XNP Transmit */
+#define IXGBE_MII_AUTONEG_ADVERTISE_REG          0x10   /* 100M Advertisement */
+#define IXGBE_MII_10GBASE_T_ADVERTISE            0x1000 /* full duplex, bit:12*/
+#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX      0x4000 /* full duplex, bit:14*/
+#define IXGBE_MII_1GBASE_T_ADVERTISE             0x8000 /* full duplex, bit:15*/
+#define IXGBE_MII_100BASE_T_ADVERTISE            0x0100 /* full duplex, bit:8 */
+#define IXGBE_MII_RESTART                        0x200
+#define IXGBE_MII_AUTONEG_COMPLETE               0x20
+#define IXGBE_MII_AUTONEG_LINK_UP                0x04
+#define IXGBE_MII_AUTONEG_REG                    0x0
 
-#define	IXGBE_PHY_REVISION_MASK		0xFFFFFFF0
-#define	IXGBE_MAX_PHY_ADDR		32
+#define IXGBE_PHY_REVISION_MASK        0xFFFFFFF0
+#define IXGBE_MAX_PHY_ADDR             32
 
-/* PHY IDs */
-#define	TN1010_PHY_ID		0x00A19410
-#define	TNX_FW_REV		0xB
-#define	AQ1002_PHY_ID		0x03A1B420
-#define	AQ_FW_REV		0x20
-#define	QT2022_PHY_ID		0x0043A400
-#define	ATH_PHY_ID		0x03429050
+/* PHY IDs*/
+#define TN1010_PHY_ID    0x00A19410
+#define TNX_FW_REV       0xB
+#define AQ1002_PHY_ID    0x03A1B420
+#define AQ_FW_REV        0x20
+#define QT2022_PHY_ID    0x0043A400
+#define ATH_PHY_ID       0x03429050
 
 /* PHY Types */
-#define	IXGBE_M88E1145_E_PHY_ID	0x01410CD0
+#define IXGBE_M88E1145_E_PHY_ID  0x01410CD0
 
 /* Special PHY Init Routine */
-#define	IXGBE_PHY_INIT_OFFSET_NL	0x002B
-#define	IXGBE_PHY_INIT_END_NL		0xFFFF
-#define	IXGBE_CONTROL_MASK_NL		0xF000
-#define	IXGBE_DATA_MASK_NL		0x0FFF
-#define	IXGBE_CONTROL_SHIFT_NL		12
-#define	IXGBE_DELAY_NL			0
-#define	IXGBE_DATA_NL			1
-#define	IXGBE_CONTROL_NL		0x000F
-#define	IXGBE_CONTROL_EOL_NL		0x0FFF
-#define	IXGBE_CONTROL_SOL_NL		0x0000
+#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
+#define IXGBE_PHY_INIT_END_NL    0xFFFF
+#define IXGBE_CONTROL_MASK_NL    0xF000
+#define IXGBE_DATA_MASK_NL       0x0FFF
+#define IXGBE_CONTROL_SHIFT_NL   12
+#define IXGBE_DELAY_NL           0
+#define IXGBE_DATA_NL            1
+#define IXGBE_CONTROL_NL         0x000F
+#define IXGBE_CONTROL_EOL_NL     0x0FFF
+#define IXGBE_CONTROL_SOL_NL     0x0000
 
 /* General purpose Interrupt Enable */
-#define	IXGBE_SDP0_GPIEN	0x00000001 /* SDP0 */
-#define	IXGBE_SDP1_GPIEN	0x00000002 /* SDP1 */
-#define	IXGBE_SDP2_GPIEN	0x00000004 /* SDP2 */
-#define	IXGBE_GPIE_MSIX_MODE	0x00000010 /* MSI-X mode */
-#define	IXGBE_GPIE_OCD		0x00000020 /* Other Clear Disable */
-#define	IXGBE_GPIE_EIMEN	0x00000040 /* Immediate Interrupt Enable */
-#define	IXGBE_GPIE_EIAME	0x40000000
-#define	IXGBE_GPIE_PBA_SUPPORT	0x80000000
-#define	IXGBE_GPIE_RSC_DELAY_SHIFT	11
-#define	IXGBE_GPIE_VTMODE_MASK	0x0000C000 /* VT Mode Mask */
-#define	IXGBE_GPIE_VTMODE_16	0x00004000 /* 16 VFs 8 queues per VF */
-#define	IXGBE_GPIE_VTMODE_32	0x00008000 /* 32 VFs 4 queues per VF */
-#define	IXGBE_GPIE_VTMODE_64	0x0000C000 /* 64 VFs 2 queues per VF */
+#define IXGBE_SDP0_GPIEN         0x00000001 /* SDP0 */
+#define IXGBE_SDP1_GPIEN         0x00000002 /* SDP1 */
+#define IXGBE_SDP2_GPIEN         0x00000004 /* SDP2 */
+#define IXGBE_GPIE_MSIX_MODE     0x00000010 /* MSI-X mode */
+#define IXGBE_GPIE_OCD           0x00000020 /* Other Clear Disable */
+#define IXGBE_GPIE_EIMEN         0x00000040 /* Immediate Interrupt Enable */
+#define IXGBE_GPIE_EIAME         0x40000000
+#define IXGBE_GPIE_PBA_SUPPORT   0x80000000
+#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
+#define IXGBE_GPIE_VTMODE_MASK   0x0000C000 /* VT Mode Mask */
+#define IXGBE_GPIE_VTMODE_16     0x00004000 /* 16 VFs 8 queues per VF */
+#define IXGBE_GPIE_VTMODE_32     0x00008000 /* 32 VFs 4 queues per VF */
+#define IXGBE_GPIE_VTMODE_64     0x0000C000 /* 64 VFs 2 queues per VF */
 
 /* Transmit Flow Control status */
-#define	IXGBE_TFCS_TXOFF	0x00000001
-#define	IXGBE_TFCS_TXOFF0	0x00000100
-#define	IXGBE_TFCS_TXOFF1	0x00000200
-#define	IXGBE_TFCS_TXOFF2	0x00000400
-#define	IXGBE_TFCS_TXOFF3	0x00000800
-#define	IXGBE_TFCS_TXOFF4	0x00001000
-#define	IXGBE_TFCS_TXOFF5	0x00002000
-#define	IXGBE_TFCS_TXOFF6	0x00004000
-#define	IXGBE_TFCS_TXOFF7	0x00008000
+#define IXGBE_TFCS_TXOFF         0x00000001
+#define IXGBE_TFCS_TXOFF0        0x00000100
+#define IXGBE_TFCS_TXOFF1        0x00000200
+#define IXGBE_TFCS_TXOFF2        0x00000400
+#define IXGBE_TFCS_TXOFF3        0x00000800
+#define IXGBE_TFCS_TXOFF4        0x00001000
+#define IXGBE_TFCS_TXOFF5        0x00002000
+#define IXGBE_TFCS_TXOFF6        0x00004000
+#define IXGBE_TFCS_TXOFF7        0x00008000
 
 /* TCP Timer */
-#define	IXGBE_TCPTIMER_KS		0x00000100
-#define	IXGBE_TCPTIMER_COUNT_ENABLE	0x00000200
-#define	IXGBE_TCPTIMER_COUNT_FINISH	0x00000400
-#define	IXGBE_TCPTIMER_LOOP		0x00000800
-#define	IXGBE_TCPTIMER_DURATION_MASK	0x000000FF
+#define IXGBE_TCPTIMER_KS            0x00000100
+#define IXGBE_TCPTIMER_COUNT_ENABLE  0x00000200
+#define IXGBE_TCPTIMER_COUNT_FINISH  0x00000400
+#define IXGBE_TCPTIMER_LOOP          0x00000800
+#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
 
 /* HLREG0 Bit Masks */
-#define	IXGBE_HLREG0_TXCRCEN		0x00000001   /* bit  0 */
-#define	IXGBE_HLREG0_RXCRCSTRP		0x00000002   /* bit  1 */
-#define	IXGBE_HLREG0_JUMBOEN		0x00000004   /* bit  2 */
-#define	IXGBE_HLREG0_TXPADEN		0x00000400   /* bit 10 */
-#define	IXGBE_HLREG0_TXPAUSEEN		0x00001000   /* bit 12 */
-#define	IXGBE_HLREG0_RXPAUSEEN		0x00004000   /* bit 14 */
-#define	IXGBE_HLREG0_LPBK		0x00008000   /* bit 15 */
-#define	IXGBE_HLREG0_MDCSPD		0x00010000   /* bit 16 */
-#define	IXGBE_HLREG0_CONTMDC		0x00020000   /* bit 17 */
-#define	IXGBE_HLREG0_CTRLFLTR		0x00040000   /* bit 18 */
-#define	IXGBE_HLREG0_PREPEND		0x00F00000   /* bits 20-23 */
-#define	IXGBE_HLREG0_PRIPAUSEEN		0x01000000   /* bit 24 */
-#define	IXGBE_HLREG0_RXPAUSERECDA	0x06000000   /* bits 25-26 */
-#define	IXGBE_HLREG0_RXLNGTHERREN	0x08000000   /* bit 27 */
-#define	IXGBE_HLREG0_RXPADSTRIPEN	0x10000000   /* bit 28 */
+#define IXGBE_HLREG0_TXCRCEN      0x00000001   /* bit  0 */
+#define IXGBE_HLREG0_RXCRCSTRP    0x00000002   /* bit  1 */
+#define IXGBE_HLREG0_JUMBOEN      0x00000004   /* bit  2 */
+#define IXGBE_HLREG0_TXPADEN      0x00000400   /* bit 10 */
+#define IXGBE_HLREG0_TXPAUSEEN    0x00001000   /* bit 12 */
+#define IXGBE_HLREG0_RXPAUSEEN    0x00004000   /* bit 14 */
+#define IXGBE_HLREG0_LPBK         0x00008000   /* bit 15 */
+#define IXGBE_HLREG0_MDCSPD       0x00010000   /* bit 16 */
+#define IXGBE_HLREG0_CONTMDC      0x00020000   /* bit 17 */
+#define IXGBE_HLREG0_CTRLFLTR     0x00040000   /* bit 18 */
+#define IXGBE_HLREG0_PREPEND      0x00F00000   /* bits 20-23 */
+#define IXGBE_HLREG0_PRIPAUSEEN   0x01000000   /* bit 24 */
+#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000   /* bits 25-26 */
+#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000   /* bit 27 */
+#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000   /* bit 28 */
 
 /* VMD_CTL bitmasks */
-#define	IXGBE_VMD_CTL_VMDQ_EN		0x00000001
-#define	IXGBE_VMD_CTL_VMDQ_FILTER	0x00000002
+#define IXGBE_VMD_CTL_VMDQ_EN     0x00000001
+#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
 
 /* VT_CTL bitmasks */
-#define	IXGBE_VT_CTL_DIS_DEFPL	0x20000000 /* disable default pool */
-#define	IXGBE_VT_CTL_REPLEN	0x40000000 /* replication enabled */
-#define	IXGBE_VT_CTL_VT_ENABLE	0x00000001  /* Enable VT Mode */
-#define	IXGBE_VT_CTL_POOL_SHIFT	7
-#define	IXGBE_VT_CTL_POOL_MASK	(0x3F << IXGBE_VT_CTL_POOL_SHIFT)
+#define IXGBE_VT_CTL_DIS_DEFPL  0x20000000 /* disable default pool */
+#define IXGBE_VT_CTL_REPLEN     0x40000000 /* replication enabled */
+#define IXGBE_VT_CTL_VT_ENABLE  0x00000001  /* Enable VT Mode */
+#define IXGBE_VT_CTL_POOL_SHIFT 7
+#define IXGBE_VT_CTL_POOL_MASK  (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
 
 /* VMOLR bitmasks */
-#define	IXGBE_VMOLR_AUPE	0x01000000 /* accept untagged packets */
-#define	IXGBE_VMOLR_ROMPE	0x02000000 /* accept packets in MTA tbl */
-#define	IXGBE_VMOLR_ROPE	0x04000000 /* accept packets in UC tbl */
-#define	IXGBE_VMOLR_BAM		0x08000000 /* accept broadcast packets */
-#define	IXGBE_VMOLR_MPE		0x10000000 /* multicast promiscuous */
+#define IXGBE_VMOLR_AUPE        0x01000000 /* accept untagged packets */
+#define IXGBE_VMOLR_ROMPE       0x02000000 /* accept packets in MTA tbl */
+#define IXGBE_VMOLR_ROPE        0x04000000 /* accept packets in UC tbl */
+#define IXGBE_VMOLR_BAM         0x08000000 /* accept broadcast packets */
+#define IXGBE_VMOLR_MPE         0x10000000 /* multicast promiscuous */
 
 /* VFRE bitmask */
-#define	IXGBE_VFRE_ENABLE_ALL	0xFFFFFFFF
+#define IXGBE_VFRE_ENABLE_ALL   0xFFFFFFFF
 
-#define	IXGBE_VF_INIT_TIMEOUT	200 /* Number of retries to clear RSTI */
+#define IXGBE_VF_INIT_TIMEOUT   200 /* Number of retries to clear RSTI */
 
 /* RDHMPN and TDHMPN bitmasks */
-#define	IXGBE_RDHMPN_RDICADDR		0x007FF800
-#define	IXGBE_RDHMPN_RDICRDREQ		0x00800000
-#define	IXGBE_RDHMPN_RDICADDR_SHIFT	11
-#define	IXGBE_TDHMPN_TDICADDR		0x003FF800
-#define	IXGBE_TDHMPN_TDICRDREQ		0x00800000
-#define	IXGBE_TDHMPN_TDICADDR_SHIFT	11
+#define IXGBE_RDHMPN_RDICADDR       0x007FF800
+#define IXGBE_RDHMPN_RDICRDREQ      0x00800000
+#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
+#define IXGBE_TDHMPN_TDICADDR       0x003FF800
+#define IXGBE_TDHMPN_TDICRDREQ      0x00800000
+#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
 
-#define	IXGBE_RDMAM_MEM_SEL_SHIFT	13
-#define	IXGBE_RDMAM_DWORD_SHIFT		9
-#define	IXGBE_RDMAM_DESC_COMP_FIFO	1
-#define	IXGBE_RDMAM_DFC_CMD_FIFO	2
-#define	IXGBE_RDMAM_RSC_HEADER_ADDR	3
-#define	IXGBE_RDMAM_TCN_STATUS_RAM	4
-#define	IXGBE_RDMAM_WB_COLL_FIFO	5
-#define	IXGBE_RDMAM_QSC_CNT_RAM		6
-#define	IXGBE_RDMAM_QSC_FCOE_RAM	7
-#define	IXGBE_RDMAM_QSC_QUEUE_CNT	8
-#define	IXGBE_RDMAM_QSC_QUEUE_RAM	0xA
-#define	IXGBE_RDMAM_QSC_RSC_RAM		0xB
-#define	IXGBE_RDMAM_DESC_COM_FIFO_RANGE	135
-#define	IXGBE_RDMAM_DESC_COM_FIFO_COUNT	4
-#define	IXGBE_RDMAM_DFC_CMD_FIFO_RANGE	48
-#define	IXGBE_RDMAM_DFC_CMD_FIFO_COUNT	7
-#define	IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE	32
-#define	IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT	4
-#define	IXGBE_RDMAM_TCN_STATUS_RAM_RANGE	256
-#define	IXGBE_RDMAM_TCN_STATUS_RAM_COUNT	9
-#define	IXGBE_RDMAM_WB_COLL_FIFO_RANGE	8
-#define	IXGBE_RDMAM_WB_COLL_FIFO_COUNT	4
-#define	IXGBE_RDMAM_QSC_CNT_RAM_RANGE	64
-#define	IXGBE_RDMAM_QSC_CNT_RAM_COUNT	4
-#define	IXGBE_RDMAM_QSC_FCOE_RAM_RANGE	512
-#define	IXGBE_RDMAM_QSC_FCOE_RAM_COUNT	5
-#define	IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE	32
-#define	IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT	4
-#define	IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE	128
-#define	IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT	8
-#define	IXGBE_RDMAM_QSC_RSC_RAM_RANGE	32
-#define	IXGBE_RDMAM_QSC_RSC_RAM_COUNT	8
+#define IXGBE_RDMAM_MEM_SEL_SHIFT   13
+#define IXGBE_RDMAM_DWORD_SHIFT     9
+#define IXGBE_RDMAM_DESC_COMP_FIFO  1
+#define IXGBE_RDMAM_DFC_CMD_FIFO    2
+#define IXGBE_RDMAM_RSC_HEADER_ADDR 3
+#define IXGBE_RDMAM_TCN_STATUS_RAM  4
+#define IXGBE_RDMAM_WB_COLL_FIFO    5
+#define IXGBE_RDMAM_QSC_CNT_RAM     6
+#define IXGBE_RDMAM_QSC_FCOE_RAM    7
+#define IXGBE_RDMAM_QSC_QUEUE_CNT   8
+#define IXGBE_RDMAM_QSC_QUEUE_RAM   0xA
+#define IXGBE_RDMAM_QSC_RSC_RAM     0xB
+#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE     135
+#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT     4
+#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE      48
+#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT      7
+#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE   32
+#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT   4
+#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE    256
+#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT    9
+#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE      8
+#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT      4
+#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE       64
+#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT       4
+#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE      512
+#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT      5
+#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE     32
+#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT     4
+#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE     128
+#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT     8
+#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE       32
+#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT       8
 
-#define	IXGBE_TXDESCIC_READY		0x80000000
+#define IXGBE_TXDESCIC_READY        0x80000000
 
 /* Receive Checksum Control */
-#define	IXGBE_RXCSUM_IPPCSE	0x00001000   /* IP payload checksum enable */
-#define	IXGBE_RXCSUM_PCSD	0x00002000   /* packet checksum disabled */
+#define IXGBE_RXCSUM_IPPCSE     0x00001000   /* IP payload checksum enable */
+#define IXGBE_RXCSUM_PCSD       0x00002000   /* packet checksum disabled */
 
 /* FCRTL Bit Masks */
-#define	IXGBE_FCRTL_XONE	0x80000000  /* XON enable */
-#define	IXGBE_FCRTH_FCEN	0x80000000  /* Packet buffer fc enable */
+#define IXGBE_FCRTL_XONE        0x80000000  /* XON enable */
+#define IXGBE_FCRTH_FCEN        0x80000000  /* Packet buffer fc enable */
 
-/* PAP bit masks */
-#define	IXGBE_PAP_TXPAUSECNT_MASK	0x0000FFFF /* Pause counter mask */
+/* PAP bit masks*/
+#define IXGBE_PAP_TXPAUSECNT_MASK   0x0000FFFF /* Pause counter mask */
 
 /* RMCS Bit Masks */
-#define	IXGBE_RMCS_RRM		0x00000002 /* Receive Recycle Mode enable */
+#define IXGBE_RMCS_RRM          0x00000002 /* Receive Recycle Mode enable */
 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
-#define	IXGBE_RMCS_RAC		0x00000004
-#define	IXGBE_RMCS_DFP		IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
-#define	IXGBE_RMCS_TFCE_802_3X	0x00000008 /* Tx Priority FC ena */
-#define	IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
-#define	IXGBE_RMCS_ARBDIS	0x00000040 /* Arbitration disable bit */
+#define IXGBE_RMCS_RAC          0x00000004
+#define IXGBE_RMCS_DFP          IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
+#define IXGBE_RMCS_TFCE_802_3X         0x00000008 /* Tx Priority FC ena */
+#define IXGBE_RMCS_TFCE_PRIORITY       0x00000010 /* Tx Priority FC ena */
+#define IXGBE_RMCS_ARBDIS       0x00000040 /* Arbitration disable bit */
 
 /* FCCFG Bit Masks */
-#define	IXGBE_FCCFG_TFCE_802_3X		0x00000008 /* Tx link FC enable */
-#define	IXGBE_FCCFG_TFCE_PRIORITY	0x00000010 /* Tx priority FC enable */
+#define IXGBE_FCCFG_TFCE_802_3X         0x00000008 /* Tx link FC enable */
+#define IXGBE_FCCFG_TFCE_PRIORITY       0x00000010 /* Tx priority FC enable */
 
 /* Interrupt register bitmasks */
 
 /* Extended Interrupt Cause Read */
-#define	IXGBE_EICR_RTX_QUEUE	0x0000FFFF /* RTx Queue Interrupt */
-#define	IXGBE_EICR_FLOW_DIR	0x00010000 /* FDir Exception */
-#define	IXGBE_EICR_RX_MISS	0x00020000 /* Packet Buffer Overrun */
-#define	IXGBE_EICR_PCI		0x00040000 /* PCI Exception */
-#define	IXGBE_EICR_MAILBOX	0x00080000 /* VF to PF Mailbox Interrupt */
-#define	IXGBE_EICR_LSC		0x00100000 /* Link Status Change */
-#define	IXGBE_EICR_LINKSEC	0x00200000 /* PN Threshold */
-#define	IXGBE_EICR_MNG		0x00400000 /* Manageability Event Interrupt */
-#define	IXGBE_EICR_GPI_SDP0	0x01000000 /* Gen Purpose Interrupt on SDP0 */
-#define	IXGBE_EICR_GPI_SDP1	0x02000000 /* Gen Purpose Interrupt on SDP1 */
-#define	IXGBE_EICR_GPI_SDP2	0x04000000 /* Gen Purpose Interrupt on SDP2 */
-#define	IXGBE_EICR_ECC		0x10000000 /* ECC Error */
-#define	IXGBE_EICR_PBUR		0x10000000 /* Packet Buffer Handler Error */
-#define	IXGBE_EICR_DHER		0x20000000 /* Descriptor Handler Error */
-#define	IXGBE_EICR_TCP_TIMER	0x40000000 /* TCP Timer */
-#define	IXGBE_EICR_OTHER	0x80000000 /* Interrupt Cause Active */
+#define IXGBE_EICR_RTX_QUEUE    0x0000FFFF /* RTx Queue Interrupt */
+#define IXGBE_EICR_FLOW_DIR     0x00010000 /* FDir Exception */
+#define IXGBE_EICR_RX_MISS      0x00020000 /* Packet Buffer Overrun */
+#define IXGBE_EICR_PCI          0x00040000 /* PCI Exception */
+#define IXGBE_EICR_MAILBOX      0x00080000 /* VF to PF Mailbox Interrupt */
+#define IXGBE_EICR_LSC          0x00100000 /* Link Status Change */
+#define IXGBE_EICR_LINKSEC      0x00200000 /* PN Threshold */
+#define IXGBE_EICR_MNG          0x00400000 /* Manageability Event Interrupt */
+#define IXGBE_EICR_GPI_SDP0     0x01000000 /* Gen Purpose Interrupt on SDP0 */
+#define IXGBE_EICR_GPI_SDP1     0x02000000 /* Gen Purpose Interrupt on SDP1 */
+#define IXGBE_EICR_GPI_SDP2     0x04000000 /* Gen Purpose Interrupt on SDP2 */
+#define IXGBE_EICR_ECC          0x10000000 /* ECC Error */
+#define IXGBE_EICR_PBUR         0x10000000 /* Packet Buffer Handler Error */
+#define IXGBE_EICR_DHER         0x20000000 /* Descriptor Handler Error */
+#define IXGBE_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
+#define IXGBE_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
 
 /* Extended Interrupt Cause Set */
-#define	IXGBE_EICS_RTX_QUEUE	IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
-#define	IXGBE_EICS_FLOW_DIR	IXGBE_EICR_FLOW_DIR  /* FDir Exception */
-#define	IXGBE_EICS_RX_MISS	IXGBE_EICR_RX_MISS   /* Pkt Buffer Overrun */
-#define	IXGBE_EICS_PCI		IXGBE_EICR_PCI /* PCI Exception */
-#define	IXGBE_EICS_MAILBOX	IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
-#define	IXGBE_EICS_LSC		IXGBE_EICR_LSC /* Link Status Change */
-#define	IXGBE_EICS_MNG		IXGBE_EICR_MNG /* MNG Event Interrupt */
-#define	IXGBE_EICS_GPI_SDP0	IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
-#define	IXGBE_EICS_GPI_SDP1	IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
-#define	IXGBE_EICS_GPI_SDP2	IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
-#define	IXGBE_EICS_ECC		IXGBE_EICR_ECC	/* ECC Error */
-#define	IXGBE_EICS_PBUR		IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
-#define	IXGBE_EICS_DHER		IXGBE_EICR_DHER /* Desc Handler Error */
-#define	IXGBE_EICS_TCP_TIMER	IXGBE_EICR_TCP_TIMER /* TCP Timer */
-#define	IXGBE_EICS_OTHER	IXGBE_EICR_OTHER /* INT Cause Active */
+#define IXGBE_EICS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
+#define IXGBE_EICS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
+#define IXGBE_EICS_RX_MISS      IXGBE_EICR_RX_MISS   /* Pkt Buffer Overrun */
+#define IXGBE_EICS_PCI          IXGBE_EICR_PCI       /* PCI Exception */
+#define IXGBE_EICS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
+#define IXGBE_EICS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
+#define IXGBE_EICS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
+#define IXGBE_EICS_GPI_SDP0     IXGBE_EICR_GPI_SDP0  /* SDP0 Gen Purpose Int */
+#define IXGBE_EICS_GPI_SDP1     IXGBE_EICR_GPI_SDP1  /* SDP1 Gen Purpose Int */
+#define IXGBE_EICS_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
+#define IXGBE_EICS_ECC          IXGBE_EICR_ECC       /* ECC Error */
+#define IXGBE_EICS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
+#define IXGBE_EICS_DHER         IXGBE_EICR_DHER      /* Desc Handler Error */
+#define IXGBE_EICS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
+#define IXGBE_EICS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
 
 /* Extended Interrupt Mask Set */
-#define	IXGBE_EIMS_RTX_QUEUE	IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
-#define	IXGBE_EIMS_FLOW_DIR	IXGBE_EICR_FLOW_DIR  /* FDir Exception */
-#define	IXGBE_EIMS_RX_MISS	IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
-#define	IXGBE_EIMS_PCI		IXGBE_EICR_PCI	/* PCI Exception */
-#define	IXGBE_EIMS_MAILBOX	IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
-#define	IXGBE_EIMS_LSC		IXGBE_EICR_LSC /* Link Status Change */
-#define	IXGBE_EIMS_MNG		IXGBE_EICR_MNG /* MNG Event Interrupt */
-#define	IXGBE_EIMS_GPI_SDP0	IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
-#define	IXGBE_EIMS_GPI_SDP1	IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
-#define	IXGBE_EIMS_GPI_SDP2	IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
-#define	IXGBE_EIMS_ECC		IXGBE_EICR_ECC	/* ECC Error */
-#define	IXGBE_EIMS_PBUR		IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
-#define	IXGBE_EIMS_DHER		IXGBE_EICR_DHER /* Descr Handler Error */
-#define	IXGBE_EIMS_TCP_TIMER	IXGBE_EICR_TCP_TIMER /* TCP Timer */
-#define	IXGBE_EIMS_OTHER	IXGBE_EICR_OTHER /* INT Cause Active */
+#define IXGBE_EIMS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
+#define IXGBE_EIMS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
+#define IXGBE_EIMS_RX_MISS      IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
+#define IXGBE_EIMS_PCI          IXGBE_EICR_PCI       /* PCI Exception */
+#define IXGBE_EIMS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
+#define IXGBE_EIMS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
+#define IXGBE_EIMS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
+#define IXGBE_EIMS_GPI_SDP0     IXGBE_EICR_GPI_SDP0  /* SDP0 Gen Purpose Int */
+#define IXGBE_EIMS_GPI_SDP1     IXGBE_EICR_GPI_SDP1  /* SDP1 Gen Purpose Int */
+#define IXGBE_EIMS_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
+#define IXGBE_EIMS_ECC          IXGBE_EICR_ECC       /* ECC Error */
+#define IXGBE_EIMS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
+#define IXGBE_EIMS_DHER         IXGBE_EICR_DHER      /* Descr Handler Error */
+#define IXGBE_EIMS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
+#define IXGBE_EIMS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
 
 /* Extended Interrupt Mask Clear */
-#define	IXGBE_EIMC_RTX_QUEUE	IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
-#define	IXGBE_EIMC_FLOW_DIR	IXGBE_EICR_FLOW_DIR  /* FDir Exception */
-#define	IXGBE_EIMC_RX_MISS	IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
-#define	IXGBE_EIMC_PCI		IXGBE_EICR_PCI	/* PCI Exception */
-#define	IXGBE_EIMC_MAILBOX	IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
-#define	IXGBE_EIMC_LSC		IXGBE_EICR_LSC /* Link Status Change */
-#define	IXGBE_EIMC_MNG		IXGBE_EICR_MNG /* MNG Event Interrupt */
-#define	IXGBE_EIMC_GPI_SDP0	IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
-#define	IXGBE_EIMC_GPI_SDP1	IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
-#define	IXGBE_EIMC_GPI_SDP2	IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
-#define	IXGBE_EIMC_ECC		IXGBE_EICR_ECC	/* ECC Error */
-#define	IXGBE_EIMC_PBUR		IXGBE_EICR_PBUR /* Pkt Buf Handler Error */
-#define	IXGBE_EIMC_DHER		IXGBE_EICR_DHER /* Desc Handler Error */
-#define	IXGBE_EIMC_TCP_TIMER	IXGBE_EICR_TCP_TIMER /* TCP Timer */
-#define	IXGBE_EIMC_OTHER	IXGBE_EICR_OTHER /* INT Cause Active */
+#define IXGBE_EIMC_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
+#define IXGBE_EIMC_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
+#define IXGBE_EIMC_RX_MISS      IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
+#define IXGBE_EIMC_PCI          IXGBE_EICR_PCI       /* PCI Exception */
+#define IXGBE_EIMC_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
+#define IXGBE_EIMC_LSC          IXGBE_EICR_LSC       /* Link Status Change */
+#define IXGBE_EIMC_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
+#define IXGBE_EIMC_GPI_SDP0     IXGBE_EICR_GPI_SDP0  /* SDP0 Gen Purpose Int */
+#define IXGBE_EIMC_GPI_SDP1     IXGBE_EICR_GPI_SDP1  /* SDP1 Gen Purpose Int */
+#define IXGBE_EIMC_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
+#define IXGBE_EIMC_ECC          IXGBE_EICR_ECC       /* ECC Error */
+#define IXGBE_EIMC_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
+#define IXGBE_EIMC_DHER         IXGBE_EICR_DHER      /* Desc Handler Err */
+#define IXGBE_EIMC_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
+#define IXGBE_EIMC_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
 
-#define	IXGBE_EIMS_ENABLE_MASK ( \
-	IXGBE_EIMS_RTX_QUEUE | IXGBE_EIMS_LSC | \
-	IXGBE_EIMS_TCP_TIMER | IXGBE_EIMS_OTHER)
+#define IXGBE_EIMS_ENABLE_MASK ( \
+                                IXGBE_EIMS_RTX_QUEUE       | \
+                                IXGBE_EIMS_LSC             | \
+                                IXGBE_EIMS_TCP_TIMER       | \
+                                IXGBE_EIMS_OTHER)
 
 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
-#define	IXGBE_IMIR_PORT_IM_EN	0x00010000  /* TCP port enable */
-#define	IXGBE_IMIR_PORT_BP	0x00020000  /* TCP port check bypass */
-#define	IXGBE_IMIREXT_SIZE_BP	0x00001000  /* Packet size bypass */
-#define	IXGBE_IMIREXT_CTRL_URG	0x00002000  /* Check URG bit in header */
-#define	IXGBE_IMIREXT_CTRL_ACK	0x00004000  /* Check ACK bit in header */
-#define	IXGBE_IMIREXT_CTRL_PSH	0x00008000  /* Check PSH bit in header */
-#define	IXGBE_IMIREXT_CTRL_RST	0x00010000  /* Check RST bit in header */
-#define	IXGBE_IMIREXT_CTRL_SYN	0x00020000  /* Check SYN bit in header */
-#define	IXGBE_IMIREXT_CTRL_FIN	0x00040000  /* Check FIN bit in header */
-#define	IXGBE_IMIREXT_CTRL_BP	0x00080000  /* Bypass check of control bits */
-#define	IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
-#define	IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
-#define	IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
-#define	IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
-#define	IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
-#define	IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
-#define	IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
-#define	IXGBE_IMIR_CTRL_BP_82599  0x00080000 /* Bypass check of control bits */
-#define	IXGBE_IMIR_LLI_EN_82599   0x00100000 /* Enables low latency Int */
-#define	IXGBE_IMIR_RX_QUEUE_MASK_82599  0x0000007F /* Rx Queue Mask */
-#define	IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
-#define	IXGBE_IMIRVP_PRIORITY_MASK	0x00000007 /* VLAN priority mask */
-#define	IXGBE_IMIRVP_PRIORITY_EN	0x00000008 /* VLAN priority enable */
+#define IXGBE_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
+#define IXGBE_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
+#define IXGBE_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
+#define IXGBE_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
+#define IXGBE_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
+#define IXGBE_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
+#define IXGBE_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
+#define IXGBE_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
+#define IXGBE_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
+#define IXGBE_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of control bits */
+#define IXGBE_IMIR_SIZE_BP_82599  0x00001000 /* Packet size bypass */
+#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
+#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
+#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
+#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
+#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
+#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
+#define IXGBE_IMIR_CTRL_BP_82599  0x00080000 /* Bypass check of control bits */
+#define IXGBE_IMIR_LLI_EN_82599   0x00100000 /* Enables low latency Int */
+#define IXGBE_IMIR_RX_QUEUE_MASK_82599  0x0000007F /* Rx Queue Mask */
+#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
+#define IXGBE_IMIRVP_PRIORITY_MASK      0x00000007 /* VLAN priority mask */
+#define IXGBE_IMIRVP_PRIORITY_EN        0x00000008 /* VLAN priority enable */
 
-#define	IXGBE_MAX_FTQF_FILTERS		128
-#define	IXGBE_FTQF_PROTOCOL_MASK	0x00000003
-#define	IXGBE_FTQF_PROTOCOL_TCP		0x00000000
-#define	IXGBE_FTQF_PROTOCOL_UDP		0x00000001
-#define	IXGBE_FTQF_PROTOCOL_SCTP	2
-#define	IXGBE_FTQF_PRIORITY_MASK	0x00000007
-#define	IXGBE_FTQF_PRIORITY_SHIFT	2
-#define	IXGBE_FTQF_POOL_MASK		0x0000003F
-#define	IXGBE_FTQF_POOL_SHIFT		8
-#define	IXGBE_FTQF_5TUPLE_MASK_MASK	0x0000001F
-#define	IXGBE_FTQF_5TUPLE_MASK_SHIFT	25
-#define	IXGBE_FTQF_SOURCE_ADDR_MASK	0x1E
-#define	IXGBE_FTQF_DEST_ADDR_MASK	0x1D
-#define	IXGBE_FTQF_SOURCE_PORT_MASK	0x1B
-#define	IXGBE_FTQF_DEST_PORT_MASK	0x17
-#define	IXGBE_FTQF_PROTOCOL_COMP_MASK	0x0F
-#define	IXGBE_FTQF_POOL_MASK_EN		0x40000000
-#define	IXGBE_FTQF_QUEUE_ENABLE		0x80000000
+#define IXGBE_MAX_FTQF_FILTERS          128
+#define IXGBE_FTQF_PROTOCOL_MASK        0x00000003
+#define IXGBE_FTQF_PROTOCOL_TCP         0x00000000
+#define IXGBE_FTQF_PROTOCOL_UDP         0x00000001
+#define IXGBE_FTQF_PROTOCOL_SCTP        2
+#define IXGBE_FTQF_PRIORITY_MASK        0x00000007
+#define IXGBE_FTQF_PRIORITY_SHIFT       2
+#define IXGBE_FTQF_POOL_MASK            0x0000003F
+#define IXGBE_FTQF_POOL_SHIFT           8
+#define IXGBE_FTQF_5TUPLE_MASK_MASK     0x0000001F
+#define IXGBE_FTQF_5TUPLE_MASK_SHIFT    25
+#define IXGBE_FTQF_SOURCE_ADDR_MASK     0x1E
+#define IXGBE_FTQF_DEST_ADDR_MASK       0x1D
+#define IXGBE_FTQF_SOURCE_PORT_MASK     0x1B
+#define IXGBE_FTQF_DEST_PORT_MASK       0x17
+#define IXGBE_FTQF_PROTOCOL_COMP_MASK   0x0F
+#define IXGBE_FTQF_POOL_MASK_EN         0x40000000
+#define IXGBE_FTQF_QUEUE_ENABLE         0x80000000
 
 /* Interrupt clear mask */
-#define	IXGBE_IRQ_CLEAR_MASK	0xFFFFFFFF
+#define IXGBE_IRQ_CLEAR_MASK    0xFFFFFFFF
 
 /* Interrupt Vector Allocation Registers */
-#define	IXGBE_IVAR_REG_NUM	25
-#define	IXGBE_IVAR_REG_NUM_82599	64
-#define	IXGBE_IVAR_TXRX_ENTRY	96
-#define	IXGBE_IVAR_RX_ENTRY	64
-#define	IXGBE_IVAR_RX_QUEUE(_i)	(0 + (_i))
-#define	IXGBE_IVAR_TX_QUEUE(_i)	(64 + (_i))
-#define	IXGBE_IVAR_TX_ENTRY	32
+#define IXGBE_IVAR_REG_NUM      25
+#define IXGBE_IVAR_REG_NUM_82599           64
+#define IXGBE_IVAR_TXRX_ENTRY   96
+#define IXGBE_IVAR_RX_ENTRY     64
+#define IXGBE_IVAR_RX_QUEUE(_i)    (0 + (_i))
+#define IXGBE_IVAR_TX_QUEUE(_i)    (64 + (_i))
+#define IXGBE_IVAR_TX_ENTRY     32
 
-#define	IXGBE_IVAR_TCP_TIMER_INDEX	96 /* 0 based index */
-#define	IXGBE_IVAR_OTHER_CAUSES_INDEX	97 /* 0 based index */
+#define IXGBE_IVAR_TCP_TIMER_INDEX       96 /* 0 based index */
+#define IXGBE_IVAR_OTHER_CAUSES_INDEX    97 /* 0 based index */
 
-#define	IXGBE_MSIX_VECTOR(_i)	(0 + (_i))
+#define IXGBE_MSIX_VECTOR(_i)   (0 + (_i))
 
-#define	IXGBE_IVAR_ALLOC_VAL	0x80 /* Interrupt Allocation valid */
+#define IXGBE_IVAR_ALLOC_VAL    0x80 /* Interrupt Allocation valid */
 
 /* ETYPE Queue Filter/Select Bit Masks */
-#define	IXGBE_MAX_ETQF_FILTERS	8
-#define	IXGBE_ETQF_FCOE		0x08000000 /* bit 27 */
-#define	IXGBE_ETQF_BCN		0x10000000 /* bit 28 */
-#define	IXGBE_ETQF_1588		0x40000000 /* bit 30 */
-#define	IXGBE_ETQF_FILTER_EN	0x80000000 /* bit 31 */
-#define	IXGBE_ETQF_POOL_ENABLE	(1 << 26) /* bit 26 */
+#define IXGBE_MAX_ETQF_FILTERS  8
+#define IXGBE_ETQF_FCOE         0x08000000 /* bit 27 */
+#define IXGBE_ETQF_BCN          0x10000000 /* bit 28 */
+#define IXGBE_ETQF_1588         0x40000000 /* bit 30 */
+#define IXGBE_ETQF_FILTER_EN    0x80000000 /* bit 31 */
+#define IXGBE_ETQF_POOL_ENABLE   (1 << 26) /* bit 26 */
 
-#define	IXGBE_ETQS_RX_QUEUE	0x007F0000 /* bits 22:16 */
-#define	IXGBE_ETQS_RX_QUEUE_SHIFT	16
-#define	IXGBE_ETQS_LLI		0x20000000 /* bit 29 */
-#define	IXGBE_ETQS_QUEUE_EN	0x80000000 /* bit 31 */
+#define IXGBE_ETQS_RX_QUEUE     0x007F0000 /* bits 22:16 */
+#define IXGBE_ETQS_RX_QUEUE_SHIFT       16
+#define IXGBE_ETQS_LLI          0x20000000 /* bit 29 */
+#define IXGBE_ETQS_QUEUE_EN     0x80000000 /* bit 31 */
 
 /*
  * ETQF filter list: one static filter per filter consumer. This is
@@ -1376,764 +1405,722 @@
  *    1588 (0x88f7):         Filter 3
  *    FIP  (0x8914):         Filter 4
  */
-#define	IXGBE_ETQF_FILTER_EAPOL	0
-#define	IXGBE_ETQF_FILTER_FCOE	2
-#define	IXGBE_ETQF_FILTER_1588	3
-#define	IXGBE_ETQF_FILTER_FIP	4
-
+#define IXGBE_ETQF_FILTER_EAPOL          0
+#define IXGBE_ETQF_FILTER_FCOE           2
+#define IXGBE_ETQF_FILTER_1588           3
+#define IXGBE_ETQF_FILTER_FIP            4
 /* VLAN Control Bit Masks */
-#define	IXGBE_VLNCTRL_VET	0x0000FFFF  /* bits 0-15 */
-#define	IXGBE_VLNCTRL_CFI	0x10000000  /* bit 28 */
-#define	IXGBE_VLNCTRL_CFIEN	0x20000000  /* bit 29 */
-#define	IXGBE_VLNCTRL_VFE	0x40000000  /* bit 30 */
-#define	IXGBE_VLNCTRL_VME	0x80000000  /* bit 31 */
+#define IXGBE_VLNCTRL_VET       0x0000FFFF  /* bits 0-15 */
+#define IXGBE_VLNCTRL_CFI       0x10000000  /* bit 28 */
+#define IXGBE_VLNCTRL_CFIEN     0x20000000  /* bit 29 */
+#define IXGBE_VLNCTRL_VFE       0x40000000  /* bit 30 */
+#define IXGBE_VLNCTRL_VME       0x80000000  /* bit 31 */
 
 /* VLAN pool filtering masks */
-#define	IXGBE_VLVF_VIEN		0x80000000  /* filter is valid */
-#define	IXGBE_VLVF_ENTRIES	64
-#define	IXGBE_VLVF_VLANID_MASK	0x00000FFF
+#define IXGBE_VLVF_VIEN         0x80000000  /* filter is valid */
+#define IXGBE_VLVF_ENTRIES      64
+#define IXGBE_VLVF_VLANID_MASK  0x00000FFF
 /* Per VF Port VLAN insertion rules */
-#define	IXGBE_VMVIR_VLANA_DEFAULT	0x40000000 /* Always use default VLAN */
-#define	IXGBE_VMVIR_VLANA_NEVER		0x80000000 /* Never insert VLAN tag */
+#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
+#define IXGBE_VMVIR_VLANA_NEVER   0x80000000 /* Never insert VLAN tag */
 
+#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.1q protocol */
 
-#define	IXGBE_ETHERNET_IEEE_VLAN_TYPE	0x8100  /* 802.1q protocol */
-
 /* STATUS Bit Masks */
-#define	IXGBE_STATUS_LAN_ID	0x0000000C /* LAN ID */
-#define	IXGBE_STATUS_LAN_ID_SHIFT	2  /* LAN ID Shift */
-#define	IXGBE_STATUS_GIO	0x00080000 /* GIO Master Enable Status */
+#define IXGBE_STATUS_LAN_ID         0x0000000C /* LAN ID */
+#define IXGBE_STATUS_LAN_ID_SHIFT   2          /* LAN ID Shift*/
+#define IXGBE_STATUS_GIO            0x00080000 /* GIO Master Enable Status */
 
-#define	IXGBE_STATUS_LAN_ID_0	0x00000000 /* LAN ID 0 */
-#define	IXGBE_STATUS_LAN_ID_1	0x00000004 /* LAN ID 1 */
+#define IXGBE_STATUS_LAN_ID_0   0x00000000 /* LAN ID 0 */
+#define IXGBE_STATUS_LAN_ID_1   0x00000004 /* LAN ID 1 */
 
 /* ESDP Bit Masks */
-#define	IXGBE_ESDP_SDP0		0x00000001 /* SDP0 Data Value */
-#define	IXGBE_ESDP_SDP1		0x00000002 /* SDP1 Data Value */
-#define	IXGBE_ESDP_SDP2		0x00000004 /* SDP2 Data Value */
-#define	IXGBE_ESDP_SDP3		0x00000008 /* SDP3 Data Value */
-#define	IXGBE_ESDP_SDP4		0x00000010 /* SDP4 Data Value */
-#define	IXGBE_ESDP_SDP5		0x00000020 /* SDP5 Data Value */
-#define	IXGBE_ESDP_SDP6		0x00000040 /* SDP6 Data Value */
-#define	IXGBE_ESDP_SDP4_DIR	0x00000004 /* SDP4 IO direction */
-#define	IXGBE_ESDP_SDP5_DIR	0x00002000 /* SDP5 IO direction */
+#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
+#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
+#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
+#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
+#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
+#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
+#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
+#define IXGBE_ESDP_SDP4_DIR     0x00000004 /* SDP4 IO direction */
+#define IXGBE_ESDP_SDP5_DIR     0x00002000 /* SDP5 IO direction */
 
 /* LEDCTL Bit Masks */
-#define	IXGBE_LED_IVRT_BASE	0x00000040
-#define	IXGBE_LED_BLINK_BASE	0x00000080
-#define	IXGBE_LED_MODE_MASK_BASE	0x0000000F
-#define	IXGBE_LED_OFFSET(_base, _i)	(_base << (8 * (_i)))
-#define	IXGBE_LED_MODE_SHIFT(_i)	(8*(_i))
-#define	IXGBE_LED_IVRT(_i)	IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
-#define	IXGBE_LED_BLINK(_i)	IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
-#define	IXGBE_LED_MODE_MASK(_i)	IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
+#define IXGBE_LED_IVRT_BASE      0x00000040
+#define IXGBE_LED_BLINK_BASE     0x00000080
+#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
+#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
+#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
+#define IXGBE_LED_IVRT(_i)       IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
+#define IXGBE_LED_BLINK(_i)      IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
+#define IXGBE_LED_MODE_MASK(_i)  IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
 
 /* LED modes */
-#define	IXGBE_LED_LINK_UP	0x0
-#define	IXGBE_LED_LINK_10G	0x1
-#define	IXGBE_LED_MAC		0x2
-#define	IXGBE_LED_FILTER	0x3
-#define	IXGBE_LED_LINK_ACTIVE	0x4
-#define	IXGBE_LED_LINK_1G	0x5
-#define	IXGBE_LED_ON		0xE
-#define	IXGBE_LED_OFF		0xF
+#define IXGBE_LED_LINK_UP       0x0
+#define IXGBE_LED_LINK_10G      0x1
+#define IXGBE_LED_MAC           0x2
+#define IXGBE_LED_FILTER        0x3
+#define IXGBE_LED_LINK_ACTIVE   0x4
+#define IXGBE_LED_LINK_1G       0x5
+#define IXGBE_LED_ON            0xE
+#define IXGBE_LED_OFF           0xF
 
 /* AUTOC Bit Masks */
-#define	IXGBE_AUTOC_KX4_KX_SUPP_MASK	0xC0000000
-#define	IXGBE_AUTOC_KX4_SUPP	0x80000000
-#define	IXGBE_AUTOC_KX_SUPP	0x40000000
-#define	IXGBE_AUTOC_PAUSE	0x30000000
-#define	IXGBE_AUTOC_ASM_PAUSE	0x20000000
-#define	IXGBE_AUTOC_SYM_PAUSE	0x10000000
-#define	IXGBE_AUTOC_RF		0x08000000
-#define	IXGBE_AUTOC_PD_TMR	0x06000000
-#define	IXGBE_AUTOC_AN_RX_LOOSE	0x01000000
-#define	IXGBE_AUTOC_AN_RX_DRIFT	0x00800000
-#define	IXGBE_AUTOC_AN_RX_ALIGN	0x007C0000
-#define	IXGBE_AUTOC_FECA	0x00040000
-#define	IXGBE_AUTOC_FECR	0x00020000
-#define	IXGBE_AUTOC_KR_SUPP	0x00010000
-#define	IXGBE_AUTOC_AN_RESTART	0x00001000
-#define	IXGBE_AUTOC_FLU		0x00000001
-#define	IXGBE_AUTOC_LMS_SHIFT	13
-#define	IXGBE_AUTOC_LMS_10G_SERIAL	(0x3 << IXGBE_AUTOC_LMS_SHIFT)
-#define	IXGBE_AUTOC_LMS_KX4_KX_KR	(0x4 << IXGBE_AUTOC_LMS_SHIFT)
-#define	IXGBE_AUTOC_LMS_SGMII_1G_100M	(0x5 << IXGBE_AUTOC_LMS_SHIFT)
-#define	IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN	(0x6 << IXGBE_AUTOC_LMS_SHIFT)
-#define	IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII	(0x7 << IXGBE_AUTOC_LMS_SHIFT)
-#define	IXGBE_AUTOC_LMS_MASK		(0x7 << IXGBE_AUTOC_LMS_SHIFT)
-#define	IXGBE_AUTOC_LMS_1G_LINK_NO_AN	(0x0 << IXGBE_AUTOC_LMS_SHIFT)
-#define	IXGBE_AUTOC_LMS_10G_LINK_NO_AN	(0x1 << IXGBE_AUTOC_LMS_SHIFT)
-#define	IXGBE_AUTOC_LMS_1G_AN		(0x2 << IXGBE_AUTOC_LMS_SHIFT)
-#define	IXGBE_AUTOC_LMS_KX4_AN		(0x4 << IXGBE_AUTOC_LMS_SHIFT)
-#define	IXGBE_AUTOC_LMS_KX4_AN_1G_AN	(0x6 << IXGBE_AUTOC_LMS_SHIFT)
-#define	IXGBE_AUTOC_LMS_ATTACH_TYPE	(0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
+#define IXGBE_AUTOC_KX4_SUPP    0x80000000
+#define IXGBE_AUTOC_KX_SUPP     0x40000000
+#define IXGBE_AUTOC_PAUSE       0x30000000
+#define IXGBE_AUTOC_ASM_PAUSE   0x20000000
+#define IXGBE_AUTOC_SYM_PAUSE   0x10000000
+#define IXGBE_AUTOC_RF          0x08000000
+#define IXGBE_AUTOC_PD_TMR      0x06000000
+#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
+#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
+#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
+#define IXGBE_AUTOC_FECA        0x00040000
+#define IXGBE_AUTOC_FECR        0x00020000
+#define IXGBE_AUTOC_KR_SUPP     0x00010000
+#define IXGBE_AUTOC_AN_RESTART  0x00001000
+#define IXGBE_AUTOC_FLU         0x00000001
+#define IXGBE_AUTOC_LMS_SHIFT   13
+#define IXGBE_AUTOC_LMS_10G_SERIAL      (0x3 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_KX4_KX_KR       (0x4 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_SGMII_1G_100M   (0x5 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_MASK            (0x7 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN   (0x0 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN  (0x1 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_1G_AN           (0x2 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_KX4_AN          (0x4 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN    (0x6 << IXGBE_AUTOC_LMS_SHIFT)
+#define IXGBE_AUTOC_LMS_ATTACH_TYPE     (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
 
-#define	IXGBE_AUTOC_1G_PMA_PMD_MASK	0x00000200
-#define	IXGBE_AUTOC_1G_PMA_PMD_SHIFT	9
-#define	IXGBE_AUTOC_10G_PMA_PMD_MASK	0x00000180
-#define	IXGBE_AUTOC_10G_PMA_PMD_SHIFT	7
-#define	IXGBE_AUTOC_10G_XAUI		(0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
-#define	IXGBE_AUTOC_10G_KX4		(0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
-#define	IXGBE_AUTOC_10G_CX4		(0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
-#define	IXGBE_AUTOC_1G_BX		(0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
-#define	IXGBE_AUTOC_1G_KX		(0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
-#define	IXGBE_AUTOC_1G_SFI		(0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
-#define	IXGBE_AUTOC_1G_KX_BX		(0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_1G_PMA_PMD_MASK    0x00000200
+#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT   9
+#define IXGBE_AUTOC_10G_PMA_PMD_MASK   0x00000180
+#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT  7
+#define IXGBE_AUTOC_10G_XAUI   (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_10G_KX4    (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_10G_CX4    (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_1G_BX      (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_1G_KX      (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_1G_SFI     (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC_1G_KX_BX   (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
 
-#define	IXGBE_AUTOC2_UPPER_MASK	0xFFFF0000
-#define	IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK	0x00030000
-#define	IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT	16
-#define	IXGBE_AUTOC2_10G_KR	(0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
-#define	IXGBE_AUTOC2_10G_XFI	(0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
-#define	IXGBE_AUTOC2_10G_SFI	(0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC2_UPPER_MASK  0xFFFF0000
+#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK  0x00030000
+#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
+#define IXGBE_AUTOC2_10G_KR  (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
+#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
 
+
 /* LINKS Bit Masks */
-#define	IXGBE_LINKS_KX_AN_COMP	0x80000000
-#define	IXGBE_LINKS_UP		0x40000000
-#define	IXGBE_LINKS_SPEED	0x20000000
-#define	IXGBE_LINKS_MODE	0x18000000
-#define	IXGBE_LINKS_RX_MODE	0x06000000
-#define	IXGBE_LINKS_TX_MODE	0x01800000
-#define	IXGBE_LINKS_XGXS_EN	0x00400000
-#define	IXGBE_LINKS_SGMII_EN	0x02000000
-#define	IXGBE_LINKS_PCS_1G_EN	0x00200000
-#define	IXGBE_LINKS_1G_AN_EN	0x00100000
-#define	IXGBE_LINKS_KX_AN_IDLE	0x00080000
-#define	IXGBE_LINKS_1G_SYNC	0x00040000
-#define	IXGBE_LINKS_10G_ALIGN	0x00020000
-#define	IXGBE_LINKS_10G_LANE_SYNC 0x00017000
-#define	IXGBE_LINKS_TL_FAULT	0x00001000
-#define	IXGBE_LINKS_SIGNAL	0x00000F00
+#define IXGBE_LINKS_KX_AN_COMP  0x80000000
+#define IXGBE_LINKS_UP          0x40000000
+#define IXGBE_LINKS_SPEED       0x20000000
+#define IXGBE_LINKS_MODE        0x18000000
+#define IXGBE_LINKS_RX_MODE     0x06000000
+#define IXGBE_LINKS_TX_MODE     0x01800000
+#define IXGBE_LINKS_XGXS_EN     0x00400000
+#define IXGBE_LINKS_SGMII_EN    0x02000000
+#define IXGBE_LINKS_PCS_1G_EN   0x00200000
+#define IXGBE_LINKS_1G_AN_EN    0x00100000
+#define IXGBE_LINKS_KX_AN_IDLE  0x00080000
+#define IXGBE_LINKS_1G_SYNC     0x00040000
+#define IXGBE_LINKS_10G_ALIGN   0x00020000
+#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
+#define IXGBE_LINKS_TL_FAULT    0x00001000
+#define IXGBE_LINKS_SIGNAL      0x00000F00
 
-#define	IXGBE_LINKS_SPEED_82599		0x30000000
-#define	IXGBE_LINKS_SPEED_10G_82599	0x30000000
-#define	IXGBE_LINKS_SPEED_1G_82599	0x20000000
-#define	IXGBE_LINKS_SPEED_100_82599	0x10000000
-#define	IXGBE_LINK_UP_TIME		90 /* 9.0 Seconds */
-#define	IXGBE_AUTO_NEG_TIME		45 /* 4.5 Seconds */
+#define IXGBE_LINKS_SPEED_82599     0x30000000
+#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
+#define IXGBE_LINKS_SPEED_1G_82599  0x20000000
+#define IXGBE_LINKS_SPEED_100_82599 0x10000000
+#define IXGBE_LINK_UP_TIME      90 /* 9.0 Seconds */
+#define IXGBE_AUTO_NEG_TIME     45 /* 4.5 Seconds */
 
-#define	IXGBE_LINKS2_AN_SUPPORTED	0x00000040
+#define IXGBE_LINKS2_AN_SUPPORTED   0x00000040
 
 /* PCS1GLSTA Bit Masks */
-#define	IXGBE_PCS1GLSTA_LINK_OK		1
-#define	IXGBE_PCS1GLSTA_SYNK_OK		0x10
-#define	IXGBE_PCS1GLSTA_AN_COMPLETE	0x10000
-#define	IXGBE_PCS1GLSTA_AN_PAGE_RX	0x20000
-#define	IXGBE_PCS1GLSTA_AN_TIMED_OUT	0x40000
-#define	IXGBE_PCS1GLSTA_AN_REMOTE_FAULT	0x80000
-#define	IXGBE_PCS1GLSTA_AN_ERROR_RWS	0x100000
+#define IXGBE_PCS1GLSTA_LINK_OK         1
+#define IXGBE_PCS1GLSTA_SYNK_OK         0x10
+#define IXGBE_PCS1GLSTA_AN_COMPLETE     0x10000
+#define IXGBE_PCS1GLSTA_AN_PAGE_RX      0x20000
+#define IXGBE_PCS1GLSTA_AN_TIMED_OUT    0x40000
+#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
+#define IXGBE_PCS1GLSTA_AN_ERROR_RWS    0x100000
 
-#define	IXGBE_PCS1GANA_SYM_PAUSE	0x80
-#define	IXGBE_PCS1GANA_ASM_PAUSE	0x100
+#define IXGBE_PCS1GANA_SYM_PAUSE        0x80
+#define IXGBE_PCS1GANA_ASM_PAUSE        0x100
 
 /* PCS1GLCTL Bit Masks */
-#define	IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
-#define	IXGBE_PCS1GLCTL_FLV_LINK_UP	1
-#define	IXGBE_PCS1GLCTL_FORCE_LINK	0x20
-#define	IXGBE_PCS1GLCTL_LOW_LINK_LATCH	0x40
-#define	IXGBE_PCS1GLCTL_AN_ENABLE	0x10000
-#define	IXGBE_PCS1GLCTL_AN_RESTART	0x20000
+#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN  0x00040000 /* PCS 1G autoneg to en */
+#define IXGBE_PCS1GLCTL_FLV_LINK_UP     1
+#define IXGBE_PCS1GLCTL_FORCE_LINK      0x20
+#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH  0x40
+#define IXGBE_PCS1GLCTL_AN_ENABLE       0x10000
+#define IXGBE_PCS1GLCTL_AN_RESTART      0x20000
 
 /* ANLP1 Bit Masks */
-#define	IXGBE_ANLP1_PAUSE		0x0C00
-#define	IXGBE_ANLP1_SYM_PAUSE		0x0400
-#define	IXGBE_ANLP1_ASM_PAUSE		0x0800
+#define IXGBE_ANLP1_PAUSE               0x0C00
+#define IXGBE_ANLP1_SYM_PAUSE           0x0400
+#define IXGBE_ANLP1_ASM_PAUSE           0x0800
+#define IXGBE_ANLP1_AN_STATE_MASK       0x000f0000
 
 /* SW Semaphore Register bitmasks */
-#define	IXGBE_SWSM_SMBI		0x00000001 /* Driver Semaphore bit */
-#define	IXGBE_SWSM_SWESMBI	0x00000002 /* FW Semaphore bit */
-#define	IXGBE_SWSM_WMNG		0x00000004 /* Wake MNG Clock */
-#define	IXGBE_SWFW_REGSMP	0x80000000 /* Register Semaphore bit 31 */
+#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
+#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
+#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
+#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
 
 /* SW_FW_SYNC/GSSR definitions */
-#define	IXGBE_GSSR_EEP_SM	0x0001
-#define	IXGBE_GSSR_PHY0_SM	0x0002
-#define	IXGBE_GSSR_PHY1_SM	0x0004
-#define	IXGBE_GSSR_MAC_CSR_SM	0x0008
-#define	IXGBE_GSSR_FLASH_SM	0x0010
+#define IXGBE_GSSR_EEP_SM     0x0001
+#define IXGBE_GSSR_PHY0_SM    0x0002
+#define IXGBE_GSSR_PHY1_SM    0x0004
+#define IXGBE_GSSR_MAC_CSR_SM 0x0008
+#define IXGBE_GSSR_FLASH_SM   0x0010
 
 /* EEC Register */
-#define	IXGBE_EEC_SK		0x00000001 /* EEPROM Clock */
-#define	IXGBE_EEC_CS		0x00000002 /* EEPROM Chip Select */
-#define	IXGBE_EEC_DI		0x00000004 /* EEPROM Data In */
-#define	IXGBE_EEC_DO		0x00000008 /* EEPROM Data Out */
-#define	IXGBE_EEC_FWE_MASK	0x00000030 /* FLASH Write Enable */
-#define	IXGBE_EEC_FWE_DIS	0x00000010 /* Disable FLASH writes */
-#define	IXGBE_EEC_FWE_EN	0x00000020 /* Enable FLASH writes */
-#define	IXGBE_EEC_FWE_SHIFT 4
-#define	IXGBE_EEC_REQ		0x00000040 /* EEPROM Access Request */
-#define	IXGBE_EEC_GNT		0x00000080 /* EEPROM Access Grant */
-#define	IXGBE_EEC_PRES		0x00000100 /* EEPROM Present */
-#define	IXGBE_EEC_ARD		0x00000200 /* EEPROM Auto Read Done */
-#define	IXGBE_EEC_FLUP		0x00800000 /* Flash update command */
-#define	IXGBE_EEC_FLUDONE	0x04000000 /* Flash update done */
+#define IXGBE_EEC_SK        0x00000001 /* EEPROM Clock */
+#define IXGBE_EEC_CS        0x00000002 /* EEPROM Chip Select */
+#define IXGBE_EEC_DI        0x00000004 /* EEPROM Data In */
+#define IXGBE_EEC_DO        0x00000008 /* EEPROM Data Out */
+#define IXGBE_EEC_FWE_MASK  0x00000030 /* FLASH Write Enable */
+#define IXGBE_EEC_FWE_DIS   0x00000010 /* Disable FLASH writes */
+#define IXGBE_EEC_FWE_EN    0x00000020 /* Enable FLASH writes */
+#define IXGBE_EEC_FWE_SHIFT 4
+#define IXGBE_EEC_REQ       0x00000040 /* EEPROM Access Request */
+#define IXGBE_EEC_GNT       0x00000080 /* EEPROM Access Grant */
+#define IXGBE_EEC_PRES      0x00000100 /* EEPROM Present */
+#define IXGBE_EEC_ARD       0x00000200 /* EEPROM Auto Read Done */
+#define IXGBE_EEC_FLUP      0x00800000 /* Flash update command */
+#define IXGBE_EEC_SEC1VAL   0x02000000 /* Sector 1 Valid */
+#define IXGBE_EEC_FLUDONE   0x04000000 /* Flash update done */
 /* EEPROM Addressing bits based on type (0-small, 1-large) */
-#define	IXGBE_EEC_ADDR_SIZE	0x00000400
-#define	IXGBE_EEC_SIZE		0x00007800 /* EEPROM Size */
+#define IXGBE_EEC_ADDR_SIZE 0x00000400
+#define IXGBE_EEC_SIZE      0x00007800 /* EEPROM Size */
 
-#define	IXGBE_EEC_SIZE_SHIFT			11
-#define	IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT	6
-#define	IXGBE_EEPROM_OPCODE_BITS		8
+#define IXGBE_EEC_SIZE_SHIFT               11
+#define IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT  6
+#define IXGBE_EEPROM_OPCODE_BITS           8
 
+/* Part Number String Length */
+#define IXGBE_PBANUM_LENGTH 11
+
 /* Checksum and EEPROM pointers */
-#define	IXGBE_EEPROM_CHECKSUM	0x3F
-#define	IXGBE_EEPROM_SUM	0xBABA
-#define	IXGBE_PCIE_ANALOG_PTR	0x03
-#define	IXGBE_ATLAS0_CONFIG_PTR 0x04
-#define	IXGBE_PHY_PTR		0x04
-#define	IXGBE_ATLAS1_CONFIG_PTR 0x05
-#define	IXGBE_OPTION_ROM_PTR	0x05
-#define	IXGBE_PCIE_GENERAL_PTR  0x06
-#define	IXGBE_PCIE_CONFIG0_PTR  0x07
-#define	IXGBE_PCIE_CONFIG1_PTR  0x08
-#define	IXGBE_CORE0_PTR		0x09
-#define	IXGBE_CORE1_PTR		0x0A
-#define	IXGBE_MAC0_PTR		0x0B
-#define	IXGBE_MAC1_PTR		0x0C
-#define	IXGBE_CSR0_CONFIG_PTR	0x0D
-#define	IXGBE_CSR1_CONFIG_PTR	0x0E
-#define	IXGBE_FW_PTR		0x0F
-#define	IXGBE_PBANUM0_PTR	0x15
-#define	IXGBE_PBANUM1_PTR	0x16
-#define	IXGBE_SAN_MAC_ADDR_PTR	0x28
-#define	IXGBE_DEVICE_CAPS	0x2C
-#define	IXGBE_SERIAL_NUMBER_MAC_ADDR	0x11
-#define	IXGBE_PCIE_MSIX_82599_CAPS	0x72
-#define	IXGBE_PCIE_MSIX_82598_CAPS	0x62
+#define IXGBE_PBANUM_PTR_GUARD  0xFAFA
+#define IXGBE_EEPROM_CHECKSUM   0x3F
+#define IXGBE_EEPROM_SUM        0xBABA
+#define IXGBE_PCIE_ANALOG_PTR   0x03
+#define IXGBE_ATLAS0_CONFIG_PTR 0x04
+#define IXGBE_PHY_PTR           0x04
+#define IXGBE_ATLAS1_CONFIG_PTR 0x05
+#define IXGBE_OPTION_ROM_PTR    0x05
+#define IXGBE_PCIE_GENERAL_PTR  0x06
+#define IXGBE_PCIE_CONFIG0_PTR  0x07
+#define IXGBE_PCIE_CONFIG1_PTR  0x08
+#define IXGBE_CORE0_PTR         0x09
+#define IXGBE_CORE1_PTR         0x0A
+#define IXGBE_MAC0_PTR          0x0B
+#define IXGBE_MAC1_PTR          0x0C
+#define IXGBE_CSR0_CONFIG_PTR   0x0D
+#define IXGBE_CSR1_CONFIG_PTR   0x0E
+#define IXGBE_FW_PTR            0x0F
+#define IXGBE_PBANUM0_PTR       0x15
+#define IXGBE_PBANUM1_PTR       0x16
+#define IXGBE_SAN_MAC_ADDR_PTR  0x28
+#define IXGBE_DEVICE_CAPS       0x2C
+#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
+#define IXGBE_PCIE_MSIX_82599_CAPS  0x72
+#define IXGBE_PCIE_MSIX_82598_CAPS  0x62
 
 /* MSI-X capability fields masks */
-#define	IXGBE_PCIE_MSIX_TBL_SZ_MASK	0x7FF
+#define IXGBE_PCIE_MSIX_TBL_SZ_MASK     0x7FF
 
 /* Legacy EEPROM word offsets */
-#define	IXGBE_ISCSI_BOOT_CAPS		0x0033
-#define	IXGBE_ISCSI_SETUP_PORT_0	0x0030
-#define	IXGBE_ISCSI_SETUP_PORT_1	0x0034
+#define IXGBE_ISCSI_BOOT_CAPS           0x0033
+#define IXGBE_ISCSI_SETUP_PORT_0        0x0030
+#define IXGBE_ISCSI_SETUP_PORT_1        0x0034
 
 /* EEPROM Commands - SPI */
-#define	IXGBE_EEPROM_MAX_RETRY_SPI	5000 /* Max wait 5ms for RDY signal */
-#define	IXGBE_EEPROM_STATUS_RDY_SPI	0x01
-#define	IXGBE_EEPROM_READ_OPCODE_SPI	0x03  /* EEPROM read opcode */
-#define	IXGBE_EEPROM_WRITE_OPCODE_SPI	0x02  /* EEPROM write opcode */
-#define	IXGBE_EEPROM_A8_OPCODE_SPI	0x08  /* opcode bit-3 = addr bit-8 */
-#define	IXGBE_EEPROM_WREN_OPCODE_SPI	0x06  /* EEPROM set Write Ena latch */
+#define IXGBE_EEPROM_MAX_RETRY_SPI      5000 /* Max wait 5ms for RDY signal */
+#define IXGBE_EEPROM_STATUS_RDY_SPI     0x01
+#define IXGBE_EEPROM_READ_OPCODE_SPI    0x03  /* EEPROM read opcode */
+#define IXGBE_EEPROM_WRITE_OPCODE_SPI   0x02  /* EEPROM write opcode */
+#define IXGBE_EEPROM_A8_OPCODE_SPI      0x08  /* opcode bit-3 = addr bit-8 */
+#define IXGBE_EEPROM_WREN_OPCODE_SPI    0x06  /* EEPROM set Write Ena latch */
 /* EEPROM reset Write Enable latch */
-#define	IXGBE_EEPROM_WRDI_OPCODE_SPI	0x04
-#define	IXGBE_EEPROM_RDSR_OPCODE_SPI	0x05  /* EEPROM read Status reg */
-#define	IXGBE_EEPROM_WRSR_OPCODE_SPI	0x01  /* EEPROM write Status reg */
-#define	IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */
-#define	IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8  /* EEPROM ERASE 64KB */
-#define	IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB  /* EEPROM ERASE 256B */
+#define IXGBE_EEPROM_WRDI_OPCODE_SPI    0x04
+#define IXGBE_EEPROM_RDSR_OPCODE_SPI    0x05  /* EEPROM read Status reg */
+#define IXGBE_EEPROM_WRSR_OPCODE_SPI    0x01  /* EEPROM write Status reg */
+#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */
+#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI  0xD8  /* EEPROM ERASE 64KB */
+#define IXGBE_EEPROM_ERASE256_OPCODE_SPI  0xDB  /* EEPROM ERASE 256B */
 
 /* EEPROM Read Register */
-#define	IXGBE_EEPROM_RW_REG_DATA	16 /* data offset in EEPROM read reg */
-#define	IXGBE_EEPROM_RW_REG_DONE	2 /* Offset to READ done bit */
-#define	IXGBE_EEPROM_RW_REG_START	1 /* First bit to start operation */
-#define	IXGBE_EEPROM_RW_ADDR_SHIFT	2 /* Shift to the address bits */
-#define	IXGBE_NVM_POLL_WRITE	1 /* Flag for polling for write complete */
-#define	IXGBE_NVM_POLL_READ	0 /* Flag for polling for read complete */
+#define IXGBE_EEPROM_RW_REG_DATA   16 /* data offset in EEPROM read reg */
+#define IXGBE_EEPROM_RW_REG_DONE   2  /* Offset to READ done bit */
+#define IXGBE_EEPROM_RW_REG_START  1  /* First bit to start operation */
+#define IXGBE_EEPROM_RW_ADDR_SHIFT 2  /* Shift to the address bits */
+#define IXGBE_NVM_POLL_WRITE       1  /* Flag for polling for write complete */
+#define IXGBE_NVM_POLL_READ        0  /* Flag for polling for read complete */
 
-#define	IXGBE_ETH_LENGTH_OF_ADDRESS   6
+#define IXGBE_ETH_LENGTH_OF_ADDRESS   6
 
 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
-#define	IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
+#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
 #endif
 
-#ifndef IXGBE_EERD_EEWR_ATTEMPTS
-/*
- * Number of 5 microseconds we wait for EERD read and
- * EERW write to complete
- */
-#define	IXGBE_EERD_EEWR_ATTEMPTS 100000
-#endif
+/* Number of 5 microseconds we wait for EERD read and
+ * EERW write to complete */
+#define IXGBE_EERD_EEWR_ATTEMPTS 100000
 
-#ifndef	IXGBE_FLUDONE_ATTEMPTS
 /* # attempts we wait for flush update to complete */
-#define	IXGBE_FLUDONE_ATTEMPTS 20000
-#endif
+#define IXGBE_FLUDONE_ATTEMPTS 20000
 
-#define	IXGBE_PCIE_CTRL2		0x5	/* PCIe Control 2 Offset */
-#define	IXGBE_PCIE_CTRL2_DUMMY_ENABLE	0x8	/* Dummy Function Enable */
-#define	IXGBE_PCIE_CTRL2_LAN_DISABLE	0x2	/* LAN PCI Disable */
-#define	IXGBE_PCIE_CTRL2_DISABLE_SELECT	0x1	/* LAN Disable Select */
+#define IXGBE_PCIE_CTRL2                 0x5   /* PCIe Control 2 Offset */
+#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE    0x8   /* Dummy Function Enable */
+#define IXGBE_PCIE_CTRL2_LAN_DISABLE     0x2   /* LAN PCI Disable */
+#define IXGBE_PCIE_CTRL2_DISABLE_SELECT  0x1   /* LAN Disable Select */
 
-#define	IXGBE_SAN_MAC_ADDR_PORT0_OFFSET	0x0
-#define	IXGBE_SAN_MAC_ADDR_PORT1_OFFSET	0x3
-#define	IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP	0x1
-#define	IXGBE_DEVICE_CAPS_FCOE_OFFLOADS	0x2
-#define	IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR	0x4
-#define	IXGBE_FW_PATCH_VERSION_4	0x7
-#define	IXGBE_FCOE_IBA_CAPS_BLK_PTR	0x33 /* iSCSI/FCOE block */
-#define	IXGBE_FCOE_IBA_CAPS_FCOE	0x20 /* FCOE flags */
-#define	IXGBE_ISCSI_FCOE_BLK_PTR	0x17 /* iSCSI/FCOE block */
-#define	IXGBE_ISCSI_FCOE_FLAGS_OFFSET	0x0  /* FCOE flags */
-#define	IXGBE_ISCSI_FCOE_FLAGS_ENABLE	0x1  /* FCOE flags enable bit */
-#define	IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR	0x27 /* Alt. SAN MAC block */
-#define	IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET  0x0 /* Alt. SAN MAC capability */
-#define	IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
-#define	IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
-#define	IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET  0x7 /* Alt. WWNN prefix offset */
-#define	IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET  0x8 /* Alt. WWPN prefix offset */
-#define	IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC  0x0 /* Alt. SAN MAC exists */
-#define	IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN  0x1 /* Alt. WWN base exists */
+#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET  0x0
+#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET  0x3
+#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP  0x1
+#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS  0x2
+#define IXGBE_FW_LESM_PARAMETERS_PTR     0x2
+#define IXGBE_FW_LESM_STATE_1            0x1
+#define IXGBE_FW_LESM_STATE_ENABLED      0x8000 /* LESM Enable bit */
+#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR   0x4
+#define IXGBE_FW_PATCH_VERSION_4         0x7
+#define IXGBE_FCOE_IBA_CAPS_BLK_PTR         0x33 /* iSCSI/FCOE block */
+#define IXGBE_FCOE_IBA_CAPS_FCOE            0x20 /* FCOE flags */
+#define IXGBE_ISCSI_FCOE_BLK_PTR            0x17 /* iSCSI/FCOE block */
+#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET       0x0  /* FCOE flags */
+#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE       0x1  /* FCOE flags enable bit */
+#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR      0x27 /* Alt. SAN MAC block */
+#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET  0x0  /* Alt. SAN MAC capability */
+#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1  /* Alt. SAN MAC 0 offset */
+#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4  /* Alt. SAN MAC 1 offset */
+#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET  0x7  /* Alt. WWNN prefix offset */
+#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET  0x8  /* Alt. WWPN prefix offset */
+#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC  0x0  /* Alt. SAN MAC exists */
+#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN  0x1  /* Alt. WWN base exists */
 
 /* PCI Bus Info */
-#define	IXGBE_PCI_DEVICE_STATUS		0xAA
-#define	IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING	0x0020
-#define	IXGBE_PCI_LINK_STATUS		0xB2
-#define	IXGBE_PCI_DEVICE_CONTROL2	0xC8
-#define	IXGBE_PCI_LINK_WIDTH		0x3F0
-#define	IXGBE_PCI_LINK_WIDTH_1		0x10
-#define	IXGBE_PCI_LINK_WIDTH_2		0x20
-#define	IXGBE_PCI_LINK_WIDTH_4		0x40
-#define	IXGBE_PCI_LINK_WIDTH_8		0x80
-#define	IXGBE_PCI_LINK_SPEED		0xF
-#define	IXGBE_PCI_LINK_SPEED_2500	0x1
-#define	IXGBE_PCI_LINK_SPEED_5000	0x2
-#define	IXGBE_PCI_HEADER_TYPE_REGISTER  0x0E
-#define	IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
-#define	IXGBE_PCI_DEVICE_CONTROL2_16ms	0x0005
+#define IXGBE_PCI_DEVICE_STATUS   0xAA
+#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING   0x0020
+#define IXGBE_PCI_LINK_STATUS     0xB2
+#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
+#define IXGBE_PCI_LINK_WIDTH      0x3F0
+#define IXGBE_PCI_LINK_WIDTH_1    0x10
+#define IXGBE_PCI_LINK_WIDTH_2    0x20
+#define IXGBE_PCI_LINK_WIDTH_4    0x40
+#define IXGBE_PCI_LINK_WIDTH_8    0x80
+#define IXGBE_PCI_LINK_SPEED      0xF
+#define IXGBE_PCI_LINK_SPEED_2500 0x1
+#define IXGBE_PCI_LINK_SPEED_5000 0x2
+#define IXGBE_PCI_HEADER_TYPE_REGISTER  0x0E
+#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
+#define IXGBE_PCI_DEVICE_CONTROL2_16ms  0x0005
 
 /* Number of 100 microseconds we wait for PCI Express master disable */
-#define	IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
+#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
 
-/* Check whether address is multicast. This is little-endian specific check. */
-#define	IXGBE_IS_MULTICAST(Address) \
-	(bool)(((u8 *)(Address))[0] & ((u8)0x01))
+/* Check whether address is multicast.  This is little-endian specific check.*/
+#define IXGBE_IS_MULTICAST(Address) \
+                (bool)(((u8 *)(Address))[0] & ((u8)0x01))
 
 /* Check whether an address is broadcast. */
-#define	IXGBE_IS_BROADCAST(Address)		\
-	((((u8 *)(Address))[0] == ((u8)0xff)) && \
-	(((u8 *)(Address))[1] == ((u8)0xff)))
+#define IXGBE_IS_BROADCAST(Address)                      \
+                ((((u8 *)(Address))[0] == ((u8)0xff)) && \
+                (((u8 *)(Address))[1] == ((u8)0xff)))
 
 /* RAH */
-#define	IXGBE_RAH_VIND_MASK		0x003C0000
-#define	IXGBE_RAH_VIND_SHIFT		18
-#define	IXGBE_RAH_AV			0x80000000
-#define	IXGBE_CLEAR_VMDQ_ALL		0xFFFFFFFF
+#define IXGBE_RAH_VIND_MASK     0x003C0000
+#define IXGBE_RAH_VIND_SHIFT    18
+#define IXGBE_RAH_AV            0x80000000
+#define IXGBE_CLEAR_VMDQ_ALL    0xFFFFFFFF
 
 /* Header split receive */
-#define	IXGBE_RFCTL_ISCSI_DIS		0x00000001
-#define	IXGBE_RFCTL_ISCSI_DWC_MASK	0x0000003E
-#define	IXGBE_RFCTL_ISCSI_DWC_SHIFT	1
-#define	IXGBE_RFCTL_NFSW_DIS		0x00000040
-#define	IXGBE_RFCTL_NFSR_DIS		0x00000080
-#define	IXGBE_RFCTL_NFS_VER_MASK	0x00000300
-#define	IXGBE_RFCTL_NFS_VER_SHIFT	8
-#define	IXGBE_RFCTL_NFS_VER_2		0
-#define	IXGBE_RFCTL_NFS_VER_3		1
-#define	IXGBE_RFCTL_NFS_VER_4		2
-#define	IXGBE_RFCTL_IPV6_DIS		0x00000400
-#define	IXGBE_RFCTL_IPV6_XSUM_DIS	0x00000800
-#define	IXGBE_RFCTL_IPFRSP_DIS		0x00004000
-#define	IXGBE_RFCTL_IPV6_EX_DIS		0x00010000
-#define	IXGBE_RFCTL_NEW_IPV6_EXT_DIS	0x00020000
+#define IXGBE_RFCTL_ISCSI_DIS       0x00000001
+#define IXGBE_RFCTL_ISCSI_DWC_MASK  0x0000003E
+#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
+#define IXGBE_RFCTL_NFSW_DIS        0x00000040
+#define IXGBE_RFCTL_NFSR_DIS        0x00000080
+#define IXGBE_RFCTL_NFS_VER_MASK    0x00000300
+#define IXGBE_RFCTL_NFS_VER_SHIFT   8
+#define IXGBE_RFCTL_NFS_VER_2       0
+#define IXGBE_RFCTL_NFS_VER_3       1
+#define IXGBE_RFCTL_NFS_VER_4       2
+#define IXGBE_RFCTL_IPV6_DIS        0x00000400
+#define IXGBE_RFCTL_IPV6_XSUM_DIS   0x00000800
+#define IXGBE_RFCTL_IPFRSP_DIS      0x00004000
+#define IXGBE_RFCTL_IPV6_EX_DIS     0x00010000
+#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
 
 /* Transmit Config masks */
-#define	IXGBE_TXDCTL_ENABLE	0x02000000 /* Enable specific Tx Queue */
-#define	IXGBE_TXDCTL_SWFLSH	0x04000000 /* Tx Desc. write-back flushing */
-#define	IXGBE_TXDCTL_WTHRESH_SHIFT	16 /* shift to WTHRESH bits */
+#define IXGBE_TXDCTL_ENABLE     0x02000000 /* Enable specific Tx Queue */
+#define IXGBE_TXDCTL_SWFLSH     0x04000000 /* Tx Desc. write-back flushing */
+#define IXGBE_TXDCTL_WTHRESH_SHIFT      16 /* shift to WTHRESH bits */
 /* Enable short packet padding to 64 bytes */
-#define	IXGBE_TX_PAD_ENABLE	0x00000400
-#define	IXGBE_JUMBO_FRAME_ENABLE 0x00000004  /* Allow jumbo frames */
+#define IXGBE_TX_PAD_ENABLE     0x00000400
+#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004  /* Allow jumbo frames */
 /* This allows for 16K packets + 4k for vlan */
-#define	IXGBE_MAX_FRAME_SZ	0x40040000
+#define IXGBE_MAX_FRAME_SZ      0x40040000
 
-#define	IXGBE_TDWBAL_HEAD_WB_ENABLE	0x1 /* Tx head write-back enable */
-#define	IXGBE_TDWBAL_SEQNUM_WB_ENABLE	0x2 /* Tx seq# write-back enable */
+#define IXGBE_TDWBAL_HEAD_WB_ENABLE   0x1      /* Tx head write-back enable */
+#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2      /* Tx seq# write-back enable */
 
 /* Receive Config masks */
-#define	IXGBE_RXCTRL_RXEN	0x00000001  /* Enable Receiver */
-#define	IXGBE_RXCTRL_DMBYPS	0x00000002  /* Descriptor Monitor Bypass */
-#define	IXGBE_RXDCTL_ENABLE	0x02000000  /* Enable specific Rx Queue */
-#define	IXGBE_RXDCTL_VME	0x40000000  /* VLAN mode enable */
+#define IXGBE_RXCTRL_RXEN       0x00000001  /* Enable Receiver */
+#define IXGBE_RXCTRL_DMBYPS     0x00000002  /* Descriptor Monitor Bypass */
+#define IXGBE_RXDCTL_ENABLE     0x02000000  /* Enable specific Rx Queue */
+#define IXGBE_RXDCTL_VME        0x40000000  /* VLAN mode enable */
 
-#define	IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
-#define	IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena	*/
-#define	IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
-#define	IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
-#define	IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
-#define	IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
+#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
+#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
+#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
+#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
+#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
+#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
 /* Receive Priority Flow Control Enable */
-#define	IXGBE_FCTRL_RPFCE 0x00004000
-#define	IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
-#define	IXGBE_MFLCN_PMCF	0x00000001 /* Pass MAC Control Frames */
-#define	IXGBE_MFLCN_DPF		0x00000002 /* Discard Pause Frame */
-#define	IXGBE_MFLCN_RPFCE	0x00000004 /* Receive Priority FC Enable */
-#define	IXGBE_MFLCN_RFCE	0x00000008 /* Receive FC Enable */
+#define IXGBE_FCTRL_RPFCE 0x00004000
+#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
+#define IXGBE_MFLCN_PMCF        0x00000001 /* Pass MAC Control Frames */
+#define IXGBE_MFLCN_DPF         0x00000002 /* Discard Pause Frame */
+#define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */
+#define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */
 
 /* Multiple Receive Queue Control */
-#define	IXGBE_MRQC_RSSEN		0x00000001  /* RSS Enable */
-#define	IXGBE_MRQC_MRQE_MASK		0xF /* Bits 3:0 */
-#define	IXGBE_MRQC_RT8TCEN		0x00000002 /* 8 TC no RSS */
-#define	IXGBE_MRQC_RT4TCEN		0x00000003 /* 4 TC no RSS */
-#define	IXGBE_MRQC_RTRSS8TCEN		0x00000004 /* 8 TC w/ RSS */
-#define	IXGBE_MRQC_RTRSS4TCEN		0x00000005 /* 4 TC w/ RSS */
-#define	IXGBE_MRQC_VMDQEN		0x00000008 /* VMDq2 64 pools no RSS */
-#define	IXGBE_MRQC_VMDQRSS32EN		0x0000000A /* VMDq2 32 pools w/ RSS */
-#define	IXGBE_MRQC_VMDQRSS64EN		0x0000000B /* VMDq2 64 pools w/ RSS */
-#define	IXGBE_MRQC_VMDQRT8TCEN		0x0000000C /* VMDq2/RT 16 pool 8 TC */
-#define	IXGBE_MRQC_VMDQRT4TCEN		0x0000000D /* VMDq2/RT 32 pool 4 TC */
-#define	IXGBE_MRQC_RSS_FIELD_MASK	0xFFFF0000
-#define	IXGBE_MRQC_RSS_FIELD_IPV4_TCP	0x00010000
-#define	IXGBE_MRQC_RSS_FIELD_IPV4	0x00020000
-#define	IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
-#define	IXGBE_MRQC_RSS_FIELD_IPV6_EX	0x00080000
-#define	IXGBE_MRQC_RSS_FIELD_IPV6	0x00100000
-#define	IXGBE_MRQC_RSS_FIELD_IPV6_TCP	0x00200000
-#define	IXGBE_MRQC_RSS_FIELD_IPV4_UDP	0x00400000
-#define	IXGBE_MRQC_RSS_FIELD_IPV6_UDP	0x00800000
-#define	IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
-#define	IXGBE_MRQC_L3L4TXSWEN		0x00008000
+#define IXGBE_MRQC_RSSEN                 0x00000001  /* RSS Enable */
+#define IXGBE_MRQC_MRQE_MASK                    0xF /* Bits 3:0 */
+#define IXGBE_MRQC_RT8TCEN               0x00000002 /* 8 TC no RSS */
+#define IXGBE_MRQC_RT4TCEN               0x00000003 /* 4 TC no RSS */
+#define IXGBE_MRQC_RTRSS8TCEN            0x00000004 /* 8 TC w/ RSS */
+#define IXGBE_MRQC_RTRSS4TCEN            0x00000005 /* 4 TC w/ RSS */
+#define IXGBE_MRQC_VMDQEN                0x00000008 /* VMDq2 64 pools no RSS */
+#define IXGBE_MRQC_VMDQRSS32EN           0x0000000A /* VMDq2 32 pools w/ RSS */
+#define IXGBE_MRQC_VMDQRSS64EN           0x0000000B /* VMDq2 64 pools w/ RSS */
+#define IXGBE_MRQC_VMDQRT8TCEN           0x0000000C /* VMDq2/RT 16 pool 8 TC */
+#define IXGBE_MRQC_VMDQRT4TCEN           0x0000000D /* VMDq2/RT 32 pool 4 TC */
+#define IXGBE_MRQC_RSS_FIELD_MASK        0xFFFF0000
+#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP    0x00010000
+#define IXGBE_MRQC_RSS_FIELD_IPV4        0x00020000
+#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
+#define IXGBE_MRQC_RSS_FIELD_IPV6_EX     0x00080000
+#define IXGBE_MRQC_RSS_FIELD_IPV6        0x00100000
+#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP    0x00200000
+#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP    0x00400000
+#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP    0x00800000
+#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
+#define IXGBE_MRQC_L3L4TXSWEN            0x00008000
 
 /* Queue Drop Enable */
-#define	IXGBE_QDE_ENABLE	0x00000001
-#define	IXGBE_QDE_IDX_MASK	0x00007F00
-#define	IXGBE_QDE_IDX_SHIFT	8
+#define IXGBE_QDE_ENABLE     0x00000001
+#define IXGBE_QDE_IDX_MASK   0x00007F00
+#define IXGBE_QDE_IDX_SHIFT           8
 
-#define	IXGBE_TXD_POPTS_IXSM	0x01	/* Insert IP checksum */
-#define	IXGBE_TXD_POPTS_TXSM	0x02	/* Insert TCP/UDP checksum */
-#define	IXGBE_TXD_CMD_EOP	0x01000000 /* End of Packet */
-#define	IXGBE_TXD_CMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
-#define	IXGBE_TXD_CMD_IC	0x04000000 /* Insert Checksum */
-#define	IXGBE_TXD_CMD_RS	0x08000000 /* Report Status */
-#define	IXGBE_TXD_CMD_DEXT	0x20000000
-				/* Descriptor extension (0 = legacy) */
-#define	IXGBE_TXD_CMD_VLE	0x40000000 /* Add VLAN tag */
-#define	IXGBE_TXD_STAT_DD	0x00000001 /* Descriptor Done */
+#define IXGBE_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
+#define IXGBE_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
+#define IXGBE_TXD_CMD_EOP    0x01000000 /* End of Packet */
+#define IXGBE_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
+#define IXGBE_TXD_CMD_IC     0x04000000 /* Insert Checksum */
+#define IXGBE_TXD_CMD_RS     0x08000000 /* Report Status */
+#define IXGBE_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
+#define IXGBE_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
+#define IXGBE_TXD_STAT_DD    0x00000001 /* Descriptor Done */
 
-#define	IXGBE_RXDADV_IPSEC_STATUS_SECP			0x00020000
-#define	IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL	0x08000000
-#define	IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH		0x10000000
-#define	IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED		0x18000000
-#define	IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK		0x18000000
-
+#define IXGBE_RXDADV_IPSEC_STATUS_SECP                  0x00020000
+#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
+#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
+#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED            0x18000000
+#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK               0x18000000
 /* Multiple Transmit Queue Command Register */
-#define	IXGBE_MTQC_RT_ENA	0x1 /* DCB Enable */
-#define	IXGBE_MTQC_VT_ENA	0x2 /* VMDQ2 Enable */
-#define	IXGBE_MTQC_64Q_1PB	0x0 /* 64 queues 1 pack buffer */
-#define	IXGBE_MTQC_32VF		0x8 /* 4 TX Queues per pool w/32VF's */
-#define	IXGBE_MTQC_64VF		0x4 /* 2 TX Queues per pool w/64VF's */
-#define	IXGBE_MTQC_4TC_4TQ	0x8 /* 4 TC if RT_ENA and VT_ENA */
-#define	IXGBE_MTQC_8TC_8TQ	0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
+#define IXGBE_MTQC_RT_ENA       0x1 /* DCB Enable */
+#define IXGBE_MTQC_VT_ENA       0x2 /* VMDQ2 Enable */
+#define IXGBE_MTQC_64Q_1PB      0x0 /* 64 queues 1 pack buffer */
+#define IXGBE_MTQC_32VF         0x8 /* 4 TX Queues per pool w/32VF's */
+#define IXGBE_MTQC_64VF         0x4 /* 2 TX Queues per pool w/64VF's */
+#define IXGBE_MTQC_4TC_4TQ      0x8 /* 4 TC if RT_ENA and VT_ENA */
+#define IXGBE_MTQC_8TC_8TQ      0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
 
 /* Receive Descriptor bit definitions */
-#define	IXGBE_RXD_STAT_DD	0x01    /* Descriptor Done */
-#define	IXGBE_RXD_STAT_EOP	0x02    /* End of Packet */
-#define	IXGBE_RXD_STAT_FLM	0x04    /* FDir Match */
-#define	IXGBE_RXD_STAT_VP	0x08    /* IEEE VLAN Packet */
-#define	IXGBE_RXDADV_NEXTP_MASK	0x000FFFF0 /* Next Descriptor Index */
-#define	IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
-#define	IXGBE_RXD_STAT_UDPCS	0x10    /* UDP xsum calculated */
-#define	IXGBE_RXD_STAT_L4CS	0x20    /* L4 xsum calculated */
-#define	IXGBE_RXD_STAT_IPCS	0x40    /* IP xsum calculated */
-#define	IXGBE_RXD_STAT_PIF	0x80    /* passed in-exact filter */
-#define	IXGBE_RXD_STAT_CRCV	0x100   /* Speculative CRC Valid */
-#define	IXGBE_RXD_STAT_VEXT	0x200   /* 1st VLAN found */
-#define	IXGBE_RXD_STAT_UDPV	0x400   /* Valid UDP checksum */
-#define	IXGBE_RXD_STAT_DYNINT	0x800   /* Pkt caused INT via DYNINT */
-#define	IXGBE_RXD_STAT_LLINT	0x800   /* Pkt caused Low Latency Interrupt */
-#define	IXGBE_RXD_STAT_TS	0x10000 /* Time Stamp */
-#define	IXGBE_RXD_STAT_SECP	0x20000 /* Security Processing */
-#define	IXGBE_RXD_STAT_LB	0x40000 /* Loopback Status */
-#define	IXGBE_RXD_STAT_ACK	0x8000  /* ACK Packet indication */
-#define	IXGBE_RXD_ERR_CE	0x01    /* CRC Error */
-#define	IXGBE_RXD_ERR_LE	0x02    /* Length Error */
-#define	IXGBE_RXD_ERR_PE	0x08    /* Packet Error */
-#define	IXGBE_RXD_ERR_OSE	0x10    /* Oversize Error */
-#define	IXGBE_RXD_ERR_USE	0x20    /* Undersize Error */
-#define	IXGBE_RXD_ERR_TCPE	0x40    /* TCP/UDP Checksum Error */
-#define	IXGBE_RXD_ERR_IPE	0x80    /* IP Checksum Error */
-#define	IXGBE_RXDADV_ERR_MASK		0xfff00000 /* RDESC.ERRORS mask */
-#define	IXGBE_RXDADV_ERR_SHIFT		20	/* RDESC.ERRORS shift */
-#define	IXGBE_RXDADV_ERR_FCEOFE		0x80000000 /* FCoEFe/IPE */
-#define	IXGBE_RXDADV_ERR_FCERR		0x00700000 /* FCERR/FDIRERR */
-#define	IXGBE_RXDADV_ERR_FDIR_LEN	0x00100000 /* FDIR Length error */
-#define	IXGBE_RXDADV_ERR_FDIR_DROP	0x00200000 /* FDIR Drop error */
-#define	IXGBE_RXDADV_ERR_FDIR_COLL	0x00400000 /* FDIR Collision error */
-#define	IXGBE_RXDADV_ERR_HBO	0x00800000 /* Header Buffer Overflow */
-#define	IXGBE_RXDADV_ERR_CE	0x01000000 /* CRC Error */
-#define	IXGBE_RXDADV_ERR_LE	0x02000000 /* Length Error */
-#define	IXGBE_RXDADV_ERR_PE	0x08000000 /* Packet Error */
-#define	IXGBE_RXDADV_ERR_OSE	0x10000000 /* Oversize Error */
-#define	IXGBE_RXDADV_ERR_USE	0x20000000 /* Undersize Error */
-#define	IXGBE_RXDADV_ERR_TCPE	0x40000000 /* TCP/UDP Checksum Error */
-#define	IXGBE_RXDADV_ERR_IPE	0x80000000 /* IP Checksum Error */
-#define	IXGBE_RXD_VLAN_ID_MASK	0x0FFF  /* VLAN ID is in lower 12 bits */
-#define	IXGBE_RXD_PRI_MASK	0xE000  /* Priority is in upper 3 bits */
-#define	IXGBE_RXD_PRI_SHIFT	13
-#define	IXGBE_RXD_CFI_MASK	0x1000  /* CFI is bit 12 */
-#define	IXGBE_RXD_CFI_SHIFT	12
+#define IXGBE_RXD_STAT_DD       0x01    /* Descriptor Done */
+#define IXGBE_RXD_STAT_EOP      0x02    /* End of Packet */
+#define IXGBE_RXD_STAT_FLM      0x04    /* FDir Match */
+#define IXGBE_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
+#define IXGBE_RXDADV_NEXTP_MASK   0x000FFFF0 /* Next Descriptor Index */
+#define IXGBE_RXDADV_NEXTP_SHIFT  0x00000004
+#define IXGBE_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
+#define IXGBE_RXD_STAT_L4CS     0x20    /* L4 xsum calculated */
+#define IXGBE_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
+#define IXGBE_RXD_STAT_PIF      0x80    /* passed in-exact filter */
+#define IXGBE_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
+#define IXGBE_RXD_STAT_VEXT     0x200   /* 1st VLAN found */
+#define IXGBE_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
+#define IXGBE_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
+#define IXGBE_RXD_STAT_LLINT    0x800   /* Pkt caused Low Latency Interrupt */
+#define IXGBE_RXD_STAT_TS       0x10000 /* Time Stamp */
+#define IXGBE_RXD_STAT_SECP     0x20000 /* Security Processing */
+#define IXGBE_RXD_STAT_LB       0x40000 /* Loopback Status */
+#define IXGBE_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
+#define IXGBE_RXD_ERR_CE        0x01    /* CRC Error */
+#define IXGBE_RXD_ERR_LE        0x02    /* Length Error */
+#define IXGBE_RXD_ERR_PE        0x08    /* Packet Error */
+#define IXGBE_RXD_ERR_OSE       0x10    /* Oversize Error */
+#define IXGBE_RXD_ERR_USE       0x20    /* Undersize Error */
+#define IXGBE_RXD_ERR_TCPE      0x40    /* TCP/UDP Checksum Error */
+#define IXGBE_RXD_ERR_IPE       0x80    /* IP Checksum Error */
+#define IXGBE_RXDADV_ERR_MASK           0xfff00000 /* RDESC.ERRORS mask */
+#define IXGBE_RXDADV_ERR_SHIFT          20         /* RDESC.ERRORS shift */
+#define IXGBE_RXDADV_ERR_FCEOFE         0x80000000 /* FCoEFe/IPE */
+#define IXGBE_RXDADV_ERR_FCERR          0x00700000 /* FCERR/FDIRERR */
+#define IXGBE_RXDADV_ERR_FDIR_LEN       0x00100000 /* FDIR Length error */
+#define IXGBE_RXDADV_ERR_FDIR_DROP      0x00200000 /* FDIR Drop error */
+#define IXGBE_RXDADV_ERR_FDIR_COLL      0x00400000 /* FDIR Collision error */
+#define IXGBE_RXDADV_ERR_HBO    0x00800000 /*Header Buffer Overflow */
+#define IXGBE_RXDADV_ERR_CE     0x01000000 /* CRC Error */
+#define IXGBE_RXDADV_ERR_LE     0x02000000 /* Length Error */
+#define IXGBE_RXDADV_ERR_PE     0x08000000 /* Packet Error */
+#define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */
+#define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */
+#define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */
+#define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */
+#define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
+#define IXGBE_RXD_PRI_MASK      0xE000  /* Priority is in upper 3 bits */
+#define IXGBE_RXD_PRI_SHIFT     13
+#define IXGBE_RXD_CFI_MASK      0x1000  /* CFI is bit 12 */
+#define IXGBE_RXD_CFI_SHIFT     12
 
-#define	IXGBE_RXDADV_STAT_DD		IXGBE_RXD_STAT_DD  /* Done */
-#define	IXGBE_RXDADV_STAT_EOP		IXGBE_RXD_STAT_EOP /* End of Packet */
-#define	IXGBE_RXDADV_STAT_FLM		IXGBE_RXD_STAT_FLM /* FDir Match */
-#define	IXGBE_RXDADV_STAT_VP		IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
-#define	IXGBE_RXDADV_STAT_MASK		0x000fffff /* Stat/NEXTP: bit 0-19 */
-#define	IXGBE_RXDADV_STAT_FCEOFS	0x00000040 /* FCoE EOF/SOF Stat */
-#define	IXGBE_RXDADV_STAT_FCSTAT	0x00000030 /* FCoE Pkt Stat */
-#define	IXGBE_RXDADV_STAT_FCSTAT_NOMTCH	0x00000000 /* 00: No Ctxt Match */
-#define	IXGBE_RXDADV_STAT_FCSTAT_NODDP	0x00000010 /* 01: Ctxt w/o DDP */
-#define	IXGBE_RXDADV_STAT_FCSTAT_FCPRSP	0x00000020 /* 10: Recv. FCP_RSP */
-#define	IXGBE_RXDADV_STAT_FCSTAT_DDP	0x00000030 /* 11: Ctxt w/ DDP */
+#define IXGBE_RXDADV_STAT_DD            IXGBE_RXD_STAT_DD  /* Done */
+#define IXGBE_RXDADV_STAT_EOP           IXGBE_RXD_STAT_EOP /* End of Packet */
+#define IXGBE_RXDADV_STAT_FLM           IXGBE_RXD_STAT_FLM /* FDir Match */
+#define IXGBE_RXDADV_STAT_VP            IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
+#define IXGBE_RXDADV_STAT_MASK          0x000fffff /* Stat/NEXTP: bit 0-19 */
+#define IXGBE_RXDADV_STAT_FCEOFS        0x00000040 /* FCoE EOF/SOF Stat */
+#define IXGBE_RXDADV_STAT_FCSTAT        0x00000030 /* FCoE Pkt Stat */
+#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
+#define IXGBE_RXDADV_STAT_FCSTAT_NODDP  0x00000010 /* 01: Ctxt w/o DDP */
+#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
+#define IXGBE_RXDADV_STAT_FCSTAT_DDP    0x00000030 /* 11: Ctxt w/ DDP */
 
 /* PSRTYPE bit definitions */
-#define	IXGBE_PSRTYPE_TCPHDR		0x00000010
-#define	IXGBE_PSRTYPE_UDPHDR		0x00000020
-#define	IXGBE_PSRTYPE_IPV4HDR		0x00000100
-#define	IXGBE_PSRTYPE_IPV6HDR		0x00000200
-#define	IXGBE_PSRTYPE_L2HDR		0x00001000
+#define IXGBE_PSRTYPE_TCPHDR    0x00000010
+#define IXGBE_PSRTYPE_UDPHDR    0x00000020
+#define IXGBE_PSRTYPE_IPV4HDR   0x00000100
+#define IXGBE_PSRTYPE_IPV6HDR   0x00000200
+#define IXGBE_PSRTYPE_L2HDR     0x00001000
 
 /* SRRCTL bit definitions */
-#define	IXGBE_SRRCTL_BSIZEPKT_SHIFT	10	/* so many KBs */
-#define	IXGBE_SRRCTL_RDMTS_SHIFT	22
-#define	IXGBE_SRRCTL_RDMTS_MASK		0x01C00000
-#define	IXGBE_SRRCTL_DROP_EN		0x10000000
-#define	IXGBE_SRRCTL_BSIZEPKT_MASK	0x0000007F
-#define	IXGBE_SRRCTL_BSIZEHDR_MASK	0x00003F00
-#define	IXGBE_SRRCTL_DESCTYPE_LEGACY	0x00000000
-#define	IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
-#define	IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT  0x04000000
-#define	IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
-#define	IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
-#define	IXGBE_SRRCTL_DESCTYPE_MASK	0x0E000000
+#define IXGBE_SRRCTL_BSIZEPKT_SHIFT     10     /* so many KBs */
+#define IXGBE_SRRCTL_RDMTS_SHIFT        22
+#define IXGBE_SRRCTL_RDMTS_MASK         0x01C00000
+#define IXGBE_SRRCTL_DROP_EN            0x10000000
+#define IXGBE_SRRCTL_BSIZEPKT_MASK      0x0000007F
+#define IXGBE_SRRCTL_BSIZEHDR_MASK      0x00003F00
+#define IXGBE_SRRCTL_DESCTYPE_LEGACY    0x00000000
+#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
+#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT  0x04000000
+#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
+#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
+#define IXGBE_SRRCTL_DESCTYPE_MASK      0x0E000000
 
-#define	IXGBE_RXDPS_HDRSTAT_HDRSP	0x00008000
-#define	IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
+#define IXGBE_RXDPS_HDRSTAT_HDRSP       0x00008000
+#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
 
-#define	IXGBE_RXDADV_RSSTYPE_MASK	0x0000000F
-#define	IXGBE_RXDADV_PKTTYPE_MASK	0x0000FFF0
-#define	IXGBE_RXDADV_PKTTYPE_MASK_EX	0x0001FFF0
-#define	IXGBE_RXDADV_HDRBUFLEN_MASK	0x00007FE0
-#define	IXGBE_RXDADV_RSCCNT_MASK	0x001E0000
-#define	IXGBE_RXDADV_RSCCNT_SHIFT	17
-#define	IXGBE_RXDADV_HDRBUFLEN_SHIFT	5
-#define	IXGBE_RXDADV_SPLITHEADER_EN	0x00001000
-#define	IXGBE_RXDADV_SPH		0x8000
+#define IXGBE_RXDADV_RSSTYPE_MASK       0x0000000F
+#define IXGBE_RXDADV_PKTTYPE_MASK       0x0000FFF0
+#define IXGBE_RXDADV_PKTTYPE_MASK_EX    0x0001FFF0
+#define IXGBE_RXDADV_HDRBUFLEN_MASK     0x00007FE0
+#define IXGBE_RXDADV_RSCCNT_MASK        0x001E0000
+#define IXGBE_RXDADV_RSCCNT_SHIFT       17
+#define IXGBE_RXDADV_HDRBUFLEN_SHIFT    5
+#define IXGBE_RXDADV_SPLITHEADER_EN     0x00001000
+#define IXGBE_RXDADV_SPH                0x8000
 
 /* RSS Hash results */
-#define	IXGBE_RXDADV_RSSTYPE_NONE	0x00000000
-#define	IXGBE_RXDADV_RSSTYPE_IPV4_TCP	0x00000001
-#define	IXGBE_RXDADV_RSSTYPE_IPV4	0x00000002
-#define	IXGBE_RXDADV_RSSTYPE_IPV6_TCP	0x00000003
-#define	IXGBE_RXDADV_RSSTYPE_IPV6_EX	0x00000004
-#define	IXGBE_RXDADV_RSSTYPE_IPV6	0x00000005
-#define	IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
-#define	IXGBE_RXDADV_RSSTYPE_IPV4_UDP	0x00000007
-#define	IXGBE_RXDADV_RSSTYPE_IPV6_UDP	0x00000008
-#define	IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
+#define IXGBE_RXDADV_RSSTYPE_NONE       0x00000000
+#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
+#define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002
+#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
+#define IXGBE_RXDADV_RSSTYPE_IPV6_EX    0x00000004
+#define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005
+#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
+#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
+#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
+#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
 
 /* RSS Packet Types as indicated in the receive descriptor. */
-#define	IXGBE_RXDADV_PKTTYPE_NONE	0x00000000
-#define	IXGBE_RXDADV_PKTTYPE_IPV4	0x00000010 /* IPv4 hdr present */
-#define	IXGBE_RXDADV_PKTTYPE_IPV4_EX	0x00000020 /* IPv4 hdr + extensions */
-#define	IXGBE_RXDADV_PKTTYPE_IPV6	0x00000040 /* IPv6 hdr present */
-#define	IXGBE_RXDADV_PKTTYPE_IPV6_EX	0x00000080 /* IPv6 hdr + extensions */
-#define	IXGBE_RXDADV_PKTTYPE_TCP	0x00000100 /* TCP hdr present */
-#define	IXGBE_RXDADV_PKTTYPE_UDP	0x00000200 /* UDP hdr present */
-#define	IXGBE_RXDADV_PKTTYPE_SCTP	0x00000400 /* SCTP hdr present */
-#define	IXGBE_RXDADV_PKTTYPE_NFS	0x00000800 /* NFS hdr present */
-#define	IXGBE_RXDADV_PKTTYPE_IPSEC_ESP	0x00001000 /* IPSec ESP */
-#define	IXGBE_RXDADV_PKTTYPE_IPSEC_AH	0x00002000 /* IPSec AH */
-#define	IXGBE_RXDADV_PKTTYPE_LINKSEC	0x00004000 /* LinkSec Encap */
-#define	IXGBE_RXDADV_PKTTYPE_ETQF	0x00008000 /* PKTTYPE is ETQF index */
-#define	IXGBE_RXDADV_PKTTYPE_ETQF_MASK	0x00000070 /* ETQF has 8 indices */
-#define	IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT	4	/* Right-shift 4 bits */
+#define IXGBE_RXDADV_PKTTYPE_NONE       0x00000000
+#define IXGBE_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPv4 hdr present */
+#define IXGBE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPv4 hdr + extensions */
+#define IXGBE_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPv6 hdr present */
+#define IXGBE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPv6 hdr + extensions */
+#define IXGBE_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
+#define IXGBE_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
+#define IXGBE_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
+#define IXGBE_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */
+#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
+#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
+#define IXGBE_RXDADV_PKTTYPE_LINKSEC    0x00004000 /* LinkSec Encap */
+#define IXGBE_RXDADV_PKTTYPE_ETQF       0x00008000 /* PKTTYPE is ETQF index */
+#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 /* ETQF has 8 indices */
+#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4          /* Right-shift 4 bits */
 
 /* Security Processing bit Indication */
-#define	IXGBE_RXDADV_LNKSEC_STATUS_SECP		0x00020000
-#define	IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH	0x08000000
-#define	IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR	0x10000000
-#define	IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK	0x18000000
-#define	IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG	0x18000000
+#define IXGBE_RXDADV_LNKSEC_STATUS_SECP         0x00020000
+#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
+#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
+#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
+#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
 
 /* Masks to determine if packets should be dropped due to frame errors */
-#define	IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
-	IXGBE_RXD_ERR_CE | IXGBE_RXD_ERR_LE | \
-	IXGBE_RXD_ERR_PE | IXGBE_RXD_ERR_OSE | IXGBE_RXD_ERR_USE)
+#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
+                                      IXGBE_RXD_ERR_CE | \
+                                      IXGBE_RXD_ERR_LE | \
+                                      IXGBE_RXD_ERR_PE | \
+                                      IXGBE_RXD_ERR_OSE | \
+                                      IXGBE_RXD_ERR_USE)
 
-#define	IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
-	IXGBE_RXDADV_ERR_CE | IXGBE_RXDADV_ERR_LE | \
-	IXGBE_RXDADV_ERR_PE | IXGBE_RXDADV_ERR_OSE | IXGBE_RXDADV_ERR_USE)
+#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
+                                      IXGBE_RXDADV_ERR_CE | \
+                                      IXGBE_RXDADV_ERR_LE | \
+                                      IXGBE_RXDADV_ERR_PE | \
+                                      IXGBE_RXDADV_ERR_OSE | \
+                                      IXGBE_RXDADV_ERR_USE)
 
 /* Multicast bit mask */
-#define	IXGBE_MCSTCTRL_MFE	0x4
+#define IXGBE_MCSTCTRL_MFE      0x4
 
 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
-#define	IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE  8
-#define	IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE  8
-#define	IXGBE_REQ_TX_BUFFER_GRANULARITY   1024
+#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE  8
+#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE  8
+#define IXGBE_REQ_TX_BUFFER_GRANULARITY   1024
 
 /* Vlan-specific macros */
-#define	IXGBE_RX_DESC_SPECIAL_VLAN_MASK  0x0FFF /* VLAN ID in lower 12 bits */
-#define	IXGBE_RX_DESC_SPECIAL_PRI_MASK   0xE000 /* Priority in upper 3 bits */
-#define	IXGBE_RX_DESC_SPECIAL_PRI_SHIFT  0x000D /* Priority in upper 3 of 16 */
-#define	IXGBE_TX_DESC_SPECIAL_PRI_SHIFT  IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
+#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK  0x0FFF /* VLAN ID in lower 12 bits */
+#define IXGBE_RX_DESC_SPECIAL_PRI_MASK   0xE000 /* Priority in upper 3 bits */
+#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT  0x000D /* Priority in upper 3 of 16 */
+#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT  IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
 
 /* SR-IOV specific macros */
-#define	IXGBE_MBVFICR_INDEX(vf_number)	(vf_number >> 4)
-#define	IXGBE_MBVFICR(_i)		(0x00710 + (_i * 4))
-#define	IXGBE_VFLRE(_i)			(((_i & 1) ? 0x001C0 : 0x00600))
-#define	IXGBE_VFLREC(_i)		(0x00700 + (_i * 4))
-/* Translated register #defines */
-#define	IXGBE_PVFCTRL(P)	(0x00300 + (4 * P))
-#define	IXGBE_PVFSTATUS(P)	(0x00008 + (0 * P))
-#define	IXGBE_PVFLINKS(P)	(0x042A4 + (0 * P))
-#define	IXGBE_PVFRTIMER(P)	(0x00048 + (0 * P))
-#define	IXGBE_PVFMAILBOX(P)	(0x04C00 + (4 * P))
-#define	IXGBE_PVFRXMEMWRAP(P)	(0x03190 + (0 * P))
-#define	IXGBE_PVTEICR(P)	(0x00B00 + (4 * P))
-#define	IXGBE_PVTEICS(P)	(0x00C00 + (4 * P))
-#define	IXGBE_PVTEIMS(P)	(0x00D00 + (4 * P))
-#define	IXGBE_PVTEIMC(P)	(0x00E00 + (4 * P))
-#define	IXGBE_PVTEIAC(P)	(0x00F00 + (4 * P))
-#define	IXGBE_PVTEIAM(P)	(0x04D00 + (4 * P))
-#define	IXGBE_PVTEITR(P)	(((P) < 24) ? (0x00820 + ((P) * 4)) : \
-	(0x012300 + (((P) - 24) * 4)))
-#define	IXGBE_PVTIVAR(P)	(0x12500 + (4 * P))
-#define	IXGBE_PVTIVAR_MISC(P)	(0x04E00 + (4 * P))
-#define	IXGBE_PVTRSCINT(P)	(0x12000 + (4 * P))
-#define	IXGBE_VFPBACL(P)	(0x110C8 + (4 * P))
-#define	IXGBE_PVFRDBAL(P)	((P < 64) ? (0x01000 + (0x40 * P)) \
-	: (0x0D000 + (0x40 * (P - 64))))
-#define	IXGBE_PVFRDBAH(P)	((P < 64) ? (0x01004 + (0x40 * P)) \
-	: (0x0D004 + (0x40 * (P - 64))))
-#define	IXGBE_PVFRDLEN(P)	((P < 64) ? (0x01008 + (0x40 * P)) \
-	: (0x0D008 + (0x40 * (P - 64))))
-#define	IXGBE_PVFRDH(P)		((P < 64) ? (0x01010 + (0x40 * P)) \
-	: (0x0D010 + (0x40 * (P - 64))))
-#define	IXGBE_PVFRDT(P)		((P < 64) ? (0x01018 + (0x40 * P)) \
-	: (0x0D018 + (0x40 * (P - 64))))
-#define	IXGBE_PVFRXDCTL(P)	((P < 64) ? (0x01028 + (0x40 * P)) \
-	: (0x0D028 + (0x40 * (P - 64))))
-#define	IXGBE_PVFSRRCTL(P)	((P < 64) ? (0x01014 + (0x40 * P)) \
-	: (0x0D014 + (0x40 * (P - 64))))
-#define	IXGBE_PVFPSRTYPE(P)	(0x0EA00 + (4 * P))
-#define	IXGBE_PVFTDBAL(P)	(0x06000 + (0x40 * P))
-#define	IXGBE_PVFTDBAH(P)	(0x06004 + (0x40 * P))
-#define	IXGBE_PVFTTDLEN(P)	(0x06008 + (0x40 * P))
-#define	IXGBE_PVFTDH(P)		(0x06010 + (0x40 * P))
-#define	IXGBE_PVFTDT(P)		(0x06018 + (0x40 * P))
-#define	IXGBE_PVFTXDCTL(P)	(0x06028 + (0x40 * P))
-#define	IXGBE_PVFTDWBAL(P)	(0x06038 + (0x40 * P))
-#define	IXGBE_PVFTDWBAH(P)	(0x0603C + (0x40 * P))
-#define	IXGBE_PVFDCA_RXCTRL(P) ((P < 64) ? (0x0100C + (0x40 * P)) \
-	: (0x0D00C + (0x40 * (P - 64))))
-#define	IXGBE_PVFDCA_TXCTRL(P)	(0x0600C + (0x40 * P))
-#define	IXGBE_PVFGPRC(x)	(0x0101C + (0x40 * x))
-#define	IXGBE_PVFGPTC(x)	(0x08300 + (0x04 * x))
-#define	IXGBE_PVFGORC_LSB(x)	(0x01020 + (0x40 * x))
-#define	IXGBE_PVFGORC_MSB(x)	(0x0D020 + (0x40 * x))
-#define	IXGBE_PVFGOTC_LSB(x)	(0x08400 + (0x08 * x))
-#define	IXGBE_PVFGOTC_MSB(x)	(0x08404 + (0x08 * x))
-#define	IXGBE_PVFMPRC(x)	(0x0D01C + (0x40 * x))
+#define IXGBE_MBVFICR_INDEX(vf_number)   (vf_number >> 4)
+#define IXGBE_MBVFICR(_i)                (0x00710 + (_i * 4))
+#define IXGBE_VFLRE(_i)                  (((_i & 1) ? 0x001C0 : 0x00600))
+#define IXGBE_VFLREC(_i)                 (0x00700 + (_i * 4))
 
-#ifndef	__le16
 /* Little Endian defines */
-#define	__le16	u16
-
-#define	__le32	u32
-#define	__le64	u64
+#ifndef __le16
+#define __le16  u16
 #endif
+#ifndef __le32
+#define __le32  u32
+#endif
+#ifndef __le64
+#define __le64  u64
 
-#ifndef	__be16
-/* Big Endian defines */
-#define	__be16	u16
-#define	__be32	u32
-#define	__be64	u64
 #endif
+#ifndef __be16
+/* Big Endian defines */
+#define __be16  u16
+#define __be32  u32
+#define __be64  u64
 
+#endif
 enum ixgbe_fdir_pballoc_type {
 	IXGBE_FDIR_PBALLOC_64K = 0,
 	IXGBE_FDIR_PBALLOC_128K,
 	IXGBE_FDIR_PBALLOC_256K,
 };
-#define	IXGBE_FDIR_PBALLOC_SIZE_SHIFT		16
+#define IXGBE_FDIR_PBALLOC_SIZE_SHIFT           16
 
 /* Flow Director register values */
-#define	IXGBE_FDIRCTRL_PBALLOC_64K		0x00000001
-#define	IXGBE_FDIRCTRL_PBALLOC_128K		0x00000002
-#define	IXGBE_FDIRCTRL_PBALLOC_256K		0x00000003
-#define	IXGBE_FDIRCTRL_INIT_DONE		0x00000008
-#define	IXGBE_FDIRCTRL_PERFECT_MATCH		0x00000010
-#define	IXGBE_FDIRCTRL_REPORT_STATUS		0x00000020
-#define	IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS	0x00000080
-#define	IXGBE_FDIRCTRL_DROP_Q_SHIFT		8
-#define	IXGBE_FDIRCTRL_FLEX_SHIFT		16
-#define	IXGBE_FDIRCTRL_SEARCHLIM		0x00800000
-#define	IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT		24
-#define	IXGBE_FDIRCTRL_FULL_THRESH_MASK		0xF0000000
-#define	IXGBE_FDIRCTRL_FULL_THRESH_SHIFT	28
+#define IXGBE_FDIRCTRL_PBALLOC_64K              0x00000001
+#define IXGBE_FDIRCTRL_PBALLOC_128K             0x00000002
+#define IXGBE_FDIRCTRL_PBALLOC_256K             0x00000003
+#define IXGBE_FDIRCTRL_INIT_DONE                0x00000008
+#define IXGBE_FDIRCTRL_PERFECT_MATCH            0x00000010
+#define IXGBE_FDIRCTRL_REPORT_STATUS            0x00000020
+#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS     0x00000080
+#define IXGBE_FDIRCTRL_DROP_Q_SHIFT             8
+#define IXGBE_FDIRCTRL_FLEX_SHIFT               16
+#define IXGBE_FDIRCTRL_SEARCHLIM                0x00800000
+#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT         24
+#define IXGBE_FDIRCTRL_FULL_THRESH_MASK         0xF0000000
+#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT        28
 
-#define	IXGBE_FDIRTCPM_DPORTM_SHIFT		16
-#define	IXGBE_FDIRUDPM_DPORTM_SHIFT		16
-#define	IXGBE_FDIRIP6M_DIPM_SHIFT		16
-#define	IXGBE_FDIRM_VLANID			0x00000001
-#define	IXGBE_FDIRM_VLANP			0x00000002
-#define	IXGBE_FDIRM_POOL			0x00000004
-#define	IXGBE_FDIRM_L4P				0x00000008
-#define	IXGBE_FDIRM_FLEX			0x00000010
-#define	IXGBE_FDIRM_DIPv6			0x00000020
+#define IXGBE_FDIRTCPM_DPORTM_SHIFT             16
+#define IXGBE_FDIRUDPM_DPORTM_SHIFT             16
+#define IXGBE_FDIRIP6M_DIPM_SHIFT               16
+#define IXGBE_FDIRM_VLANID                      0x00000001
+#define IXGBE_FDIRM_VLANP                       0x00000002
+#define IXGBE_FDIRM_POOL                        0x00000004
+#define IXGBE_FDIRM_L4P                         0x00000008
+#define IXGBE_FDIRM_FLEX                        0x00000010
+#define IXGBE_FDIRM_DIPv6                       0x00000020
 
-#define	IXGBE_FDIRFREE_FREE_MASK		0xFFFF
-#define	IXGBE_FDIRFREE_FREE_SHIFT		0
-#define	IXGBE_FDIRFREE_COLL_MASK		0x7FFF0000
-#define	IXGBE_FDIRFREE_COLL_SHIFT		16
-#define	IXGBE_FDIRLEN_MAXLEN_MASK		0x3F
-#define	IXGBE_FDIRLEN_MAXLEN_SHIFT		0
-#define	IXGBE_FDIRLEN_MAXHASH_MASK		0x7FFF0000
-#define	IXGBE_FDIRLEN_MAXHASH_SHIFT		16
-#define	IXGBE_FDIRUSTAT_ADD_MASK		0xFFFF
-#define	IXGBE_FDIRUSTAT_ADD_SHIFT		0
-#define	IXGBE_FDIRUSTAT_REMOVE_MASK		0xFFFF0000
-#define	IXGBE_FDIRUSTAT_REMOVE_SHIFT		16
-#define	IXGBE_FDIRFSTAT_FADD_MASK		0x00FF
-#define	IXGBE_FDIRFSTAT_FADD_SHIFT		0
-#define	IXGBE_FDIRFSTAT_FREMOVE_MASK		0xFF00
-#define	IXGBE_FDIRFSTAT_FREMOVE_SHIFT		8
-#define	IXGBE_FDIRPORT_DESTINATION_SHIFT	16
-#define	IXGBE_FDIRVLAN_FLEX_SHIFT		16
-#define	IXGBE_FDIRHASH_BUCKET_VALID_SHIFT	15
-#define	IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT	16
+#define IXGBE_FDIRFREE_FREE_MASK                0xFFFF
+#define IXGBE_FDIRFREE_FREE_SHIFT               0
+#define IXGBE_FDIRFREE_COLL_MASK                0x7FFF0000
+#define IXGBE_FDIRFREE_COLL_SHIFT               16
+#define IXGBE_FDIRLEN_MAXLEN_MASK               0x3F
+#define IXGBE_FDIRLEN_MAXLEN_SHIFT              0
+#define IXGBE_FDIRLEN_MAXHASH_MASK              0x7FFF0000
+#define IXGBE_FDIRLEN_MAXHASH_SHIFT             16
+#define IXGBE_FDIRUSTAT_ADD_MASK                0xFFFF
+#define IXGBE_FDIRUSTAT_ADD_SHIFT               0
+#define IXGBE_FDIRUSTAT_REMOVE_MASK             0xFFFF0000
+#define IXGBE_FDIRUSTAT_REMOVE_SHIFT            16
+#define IXGBE_FDIRFSTAT_FADD_MASK               0x00FF
+#define IXGBE_FDIRFSTAT_FADD_SHIFT              0
+#define IXGBE_FDIRFSTAT_FREMOVE_MASK            0xFF00
+#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT           8
+#define IXGBE_FDIRPORT_DESTINATION_SHIFT        16
+#define IXGBE_FDIRVLAN_FLEX_SHIFT               16
+#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT       15
+#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT       16
 
-#define	IXGBE_FDIRCMD_CMD_MASK			0x00000003
-#define	IXGBE_FDIRCMD_CMD_ADD_FLOW		0x00000001
-#define	IXGBE_FDIRCMD_CMD_REMOVE_FLOW		0x00000002
-#define	IXGBE_FDIRCMD_CMD_QUERY_REM_FILT	0x00000003
-#define	IXGBE_FDIRCMD_CMD_QUERY_REM_HASH	0x00000007
-#define	IXGBE_FDIRCMD_FILTER_UPDATE		0x00000008
-#define	IXGBE_FDIRCMD_IPv6DMATCH		0x00000010
-#define	IXGBE_FDIRCMD_L4TYPE_UDP		0x00000020
-#define	IXGBE_FDIRCMD_L4TYPE_TCP		0x00000040
-#define	IXGBE_FDIRCMD_L4TYPE_SCTP		0x00000060
-#define	IXGBE_FDIRCMD_IPV6			0x00000080
-#define	IXGBE_FDIRCMD_CLEARHT			0x00000100
-#define	IXGBE_FDIRCMD_DROP			0x00000200
-#define	IXGBE_FDIRCMD_INT			0x00000400
-#define	IXGBE_FDIRCMD_LAST			0x00000800
-#define	IXGBE_FDIRCMD_COLLISION			0x00001000
-#define	IXGBE_FDIRCMD_QUEUE_EN			0x00008000
-#define	IXGBE_FDIRCMD_RX_QUEUE_SHIFT		16
-#define	IXGBE_FDIRCMD_VT_POOL_SHIFT		24
-#define	IXGBE_FDIR_INIT_DONE_POLL		10
-#define	IXGBE_FDIRCMD_CMD_POLL			10
+#define IXGBE_FDIRCMD_CMD_MASK                  0x00000003
+#define IXGBE_FDIRCMD_CMD_ADD_FLOW              0x00000001
+#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW           0x00000002
+#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT        0x00000003
+#define IXGBE_FDIRCMD_CMD_QUERY_REM_HASH        0x00000007
+#define IXGBE_FDIRCMD_FILTER_UPDATE             0x00000008
+#define IXGBE_FDIRCMD_IPv6DMATCH                0x00000010
+#define IXGBE_FDIRCMD_L4TYPE_UDP                0x00000020
+#define IXGBE_FDIRCMD_L4TYPE_TCP                0x00000040
+#define IXGBE_FDIRCMD_L4TYPE_SCTP               0x00000060
+#define IXGBE_FDIRCMD_IPV6                      0x00000080
+#define IXGBE_FDIRCMD_CLEARHT                   0x00000100
+#define IXGBE_FDIRCMD_DROP                      0x00000200
+#define IXGBE_FDIRCMD_INT                       0x00000400
+#define IXGBE_FDIRCMD_LAST                      0x00000800
+#define IXGBE_FDIRCMD_COLLISION                 0x00001000
+#define IXGBE_FDIRCMD_QUEUE_EN                  0x00008000
+#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT           5
+#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT            16
+#define IXGBE_FDIRCMD_VT_POOL_SHIFT             24
+#define IXGBE_FDIR_INIT_DONE_POLL               10
+#define IXGBE_FDIRCMD_CMD_POLL                  10
 
 /* Transmit Descriptor - Legacy */
 struct ixgbe_legacy_tx_desc {
-	u64 buffer_addr;	/* Address of the descriptor's data buffer */
+	u64 buffer_addr;       /* Address of the descriptor's data buffer */
 	union {
 		__le32 data;
 		struct {
-			__le16 length;	/* Data buffer length */
-			u8 cso;		/* Checksum offset */
-			u8 cmd;		/* Descriptor control */
+			__le16 length;    /* Data buffer length */
+			u8 cso;           /* Checksum offset */
+			u8 cmd;           /* Descriptor control */
 		} flags;
 	} lower;
 	union {
 		__le32 data;
 		struct {
-			u8 status;	/* Descriptor status */
-			u8 css;		/* Checksum start */
+			u8 status;        /* Descriptor status */
+			u8 css;           /* Checksum start */
 			__le16 vlan;
 		} fields;
 	} upper;
@@ -2142,12 +2129,12 @@
 /* Transmit Descriptor - Advanced */
 union ixgbe_adv_tx_desc {
 	struct {
-		__le64 buffer_addr;	/* Address of descriptor's data buf */
+		__le64 buffer_addr;      /* Address of descriptor's data buf */
 		__le32 cmd_type_len;
 		__le32 olinfo_status;
 	} read;
 	struct {
-		__le64 rsvd;	/* Reserved */
+		__le64 rsvd;       /* Reserved */
 		__le32 nxtseq_seed;
 		__le32 status;
 	} wb;
@@ -2155,11 +2142,11 @@
 
 /* Receive Descriptor - Legacy */
 struct ixgbe_legacy_rx_desc {
-	__le64 buffer_addr;	/* Address of the descriptor's data buffer */
-	__le16 length;		/* Length of data DMAed into data buffer */
-	__le16 csum;		/* Packet checksum */
-	u8 status;		/* Descriptor status */
-	u8 errors;		/* Descriptor Errors */
+	__le64 buffer_addr; /* Address of the descriptor's data buffer */
+	__le16 length;      /* Length of data DMAed into data buffer */
+	__le16 csum;        /* Packet checksum */
+	u8 status;          /* Descriptor status */
+	u8 errors;          /* Descriptor Errors */
 	__le16 vlan;
 };
 
@@ -2174,10 +2161,8 @@
 			union {
 				__le32 data;
 				struct {
-					/* RSS type, Packet type */
-					__le16 pkt_info;
-					/* Split Header, header len */
-					__le16 hdr_info;
+					__le16 pkt_info; /* RSS, Pkt type */
+					__le16 hdr_info; /* Splithdr, hdrlen */
 				} hs_rss;
 			} lo_dword;
 			union {
@@ -2205,139 +2190,177 @@
 };
 
 /* Adv Transmit Descriptor Config Masks */
-#define	IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buffer length(bytes) */
-#define	IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
-#define	IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
-#define	IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK	0x000001FF /* IPSec ESP length */
-#define	IXGBE_ADVTXD_DTYP_MASK  0x00F00000 /* DTYP mask */
-#define	IXGBE_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Desc */
-#define	IXGBE_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
-#define	IXGBE_ADVTXD_DCMD_EOP   IXGBE_TXD_CMD_EOP  /* End of Packet */
-#define	IXGBE_ADVTXD_DCMD_IFCS  IXGBE_TXD_CMD_IFCS /* Insert FCS */
-#define	IXGBE_ADVTXD_DCMD_RS    IXGBE_TXD_CMD_RS   /* Report Status */
-#define	IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
-#define	IXGBE_ADVTXD_DCMD_DEXT  IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
-#define	IXGBE_ADVTXD_DCMD_VLE   IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
-#define	IXGBE_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */
-#define	IXGBE_ADVTXD_STAT_DD    IXGBE_TXD_STAT_DD  /* Descriptor Done */
-#define	IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED present in WB */
-#define	IXGBE_ADVTXD_STAT_RSV   0x0000000C /* STA Reserved */
-#define	IXGBE_ADVTXD_IDX_SHIFT  4 /* Adv desc Index shift */
-#define	IXGBE_ADVTXD_CC		0x00000080 /* Check Context */
-#define	IXGBE_ADVTXD_POPTS_SHIFT	8  /* Adv desc POPTS shift */
-#define	IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
-	IXGBE_ADVTXD_POPTS_SHIFT)
-#define	IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
-	IXGBE_ADVTXD_POPTS_SHIFT)
-#define	IXGBE_ADVTXD_POPTS_ISCO_1ST   0x00000000 /* 1st TSO of iSCSI PDU */
-#define	IXGBE_ADVTXD_POPTS_ISCO_MDL   0x00000800 /* Middle TSO of iSCSI PDU */
-#define	IXGBE_ADVTXD_POPTS_ISCO_LAST  0x00001000 /* Last TSO of iSCSI PDU */
-#define	IXGBE_ADVTXD_POPTS_ISCO_FULL  0x00001800
-					/* 1st&Last TSO-full iSCSI PDU */
-#define	IXGBE_ADVTXD_POPTS_RSV  0x00002000 /* POPTS Reserved */
-#define	IXGBE_ADVTXD_PAYLEN_SHIFT  14 /* Adv desc PAYLEN shift */
-#define	IXGBE_ADVTXD_MACLEN_SHIFT  9  /* Adv ctxt desc mac len shift */
-#define	IXGBE_ADVTXD_VLAN_SHIFT    16  /* Adv ctxt vlan tag shift */
-#define	IXGBE_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
-#define	IXGBE_ADVTXD_TUCMD_IPV6    0x00000000  /* IP Packet Type: 0=IPv6 */
-#define	IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000  /* L4 Packet TYPE of UDP */
-#define	IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
-#define	IXGBE_ADVTXD_TUCMD_L4T_SCTP	0x00001000  /* L4 Packet TYPE of SCTP */
-#define	IXGBE_ADVTXD_TUCMD_MKRREQ  0x00002000 /* Req requires Markers and CRC */
-#define	IXGBE_ADVTXD_POPTS_IPSEC  0x00000400 /* IPSec offload request */
-#define	IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
-#define	IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 /* ESP Encrypt Enable */
-#define	IXGBE_ADVTXT_TUCMD_FCOE		0x00008000	/* FCoE Frame Type */
-#define	IXGBE_ADVTXD_FCOEF_EOF_MASK	(0x3 << 10)	/* FC EOF index */
-#define	IXGBE_ADVTXD_FCOEF_SOF		((1 << 2) << 10) /* FC SOF index */
-#define	IXGBE_ADVTXD_FCOEF_PARINC	((1 << 3) << 10) /* Rel_Off in F_CTL */
-#define	IXGBE_ADVTXD_FCOEF_ORIE	((1 << 4) << 10) /* Orientation: End */
-#define	IXGBE_ADVTXD_FCOEF_ORIS	((1 << 5) << 10) /* Orientation: Start */
-#define	IXGBE_ADVTXD_FCOEF_EOF_N	(0x0 << 10)	/* 00: EOFn */
-#define	IXGBE_ADVTXD_FCOEF_EOF_T	(0x1 << 10)	/* 01: EOFt */
-#define	IXGBE_ADVTXD_FCOEF_EOF_NI	(0x2 << 10)	/* 10: EOFni */
-#define	IXGBE_ADVTXD_FCOEF_EOF_A	(0x3 << 10)	/* 11: EOFa */
-#define	IXGBE_ADVTXD_L4LEN_SHIFT   8  /* Adv ctxt L4LEN shift */
-#define	IXGBE_ADVTXD_MSS_SHIFT	16  /* Adv ctxt MSS shift */
+#define IXGBE_ADVTXD_DTALEN_MASK      0x0000FFFF /* Data buf length(bytes) */
+#define IXGBE_ADVTXD_MAC_LINKSEC      0x00040000 /* Insert LinkSec */
+#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK   0x000003FF /* IPSec SA index */
+#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK    0x000001FF /* IPSec ESP length */
+#define IXGBE_ADVTXD_DTYP_MASK  0x00F00000 /* DTYP mask */
+#define IXGBE_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Desc */
+#define IXGBE_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
+#define IXGBE_ADVTXD_DCMD_EOP   IXGBE_TXD_CMD_EOP  /* End of Packet */
+#define IXGBE_ADVTXD_DCMD_IFCS  IXGBE_TXD_CMD_IFCS /* Insert FCS */
+#define IXGBE_ADVTXD_DCMD_RS    IXGBE_TXD_CMD_RS   /* Report Status */
+#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000    /* DDP hdr type or iSCSI */
+#define IXGBE_ADVTXD_DCMD_DEXT  IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
+#define IXGBE_ADVTXD_DCMD_VLE   IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
+#define IXGBE_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */
+#define IXGBE_ADVTXD_STAT_DD    IXGBE_TXD_STAT_DD  /* Descriptor Done */
+#define IXGBE_ADVTXD_STAT_SN_CRC      0x00000002 /* NXTSEQ/SEED pres in WB */
+#define IXGBE_ADVTXD_STAT_RSV   0x0000000C /* STA Reserved */
+#define IXGBE_ADVTXD_IDX_SHIFT  4 /* Adv desc Index shift */
+#define IXGBE_ADVTXD_CC         0x00000080 /* Check Context */
+#define IXGBE_ADVTXD_POPTS_SHIFT      8  /* Adv desc POPTS shift */
+#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
+                                 IXGBE_ADVTXD_POPTS_SHIFT)
+#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
+                                 IXGBE_ADVTXD_POPTS_SHIFT)
+#define IXGBE_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
+#define IXGBE_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
+#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
+#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
+#define IXGBE_ADVTXD_POPTS_RSV       0x00002000 /* POPTS Reserved */
+#define IXGBE_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
+#define IXGBE_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
+#define IXGBE_ADVTXD_VLAN_SHIFT      16  /* Adv ctxt vlan tag shift */
+#define IXGBE_ADVTXD_TUCMD_IPV4      0x00000400  /* IP Packet Type: 1=IPv4 */
+#define IXGBE_ADVTXD_TUCMD_IPV6      0x00000000  /* IP Packet Type: 0=IPv6 */
+#define IXGBE_ADVTXD_TUCMD_L4T_UDP   0x00000000  /* L4 Packet TYPE of UDP */
+#define IXGBE_ADVTXD_TUCMD_L4T_TCP   0x00000800  /* L4 Packet TYPE of TCP */
+#define IXGBE_ADVTXD_TUCMD_L4T_SCTP  0x00001000  /* L4 Packet TYPE of SCTP */
+#define IXGBE_ADVTXD_TUCMD_MKRREQ    0x00002000 /*Req requires Markers and CRC*/
+#define IXGBE_ADVTXD_POPTS_IPSEC      0x00000400 /* IPSec offload request */
+#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
+#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
+#define IXGBE_ADVTXT_TUCMD_FCOE      0x00008000       /* FCoE Frame Type */
+#define IXGBE_ADVTXD_FCOEF_EOF_MASK  (0x3 << 10)      /* FC EOF index */
+#define IXGBE_ADVTXD_FCOEF_SOF       ((1 << 2) << 10) /* FC SOF index */
+#define IXGBE_ADVTXD_FCOEF_PARINC    ((1 << 3) << 10) /* Rel_Off in F_CTL */
+#define IXGBE_ADVTXD_FCOEF_ORIE      ((1 << 4) << 10) /* Orientation: End */
+#define IXGBE_ADVTXD_FCOEF_ORIS      ((1 << 5) << 10) /* Orientation: Start */
+#define IXGBE_ADVTXD_FCOEF_EOF_N     (0x0 << 10)      /* 00: EOFn */
+#define IXGBE_ADVTXD_FCOEF_EOF_T     (0x1 << 10)      /* 01: EOFt */
+#define IXGBE_ADVTXD_FCOEF_EOF_NI    (0x2 << 10)      /* 10: EOFni */
+#define IXGBE_ADVTXD_FCOEF_EOF_A     (0x3 << 10)      /* 11: EOFa */
+#define IXGBE_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
+#define IXGBE_ADVTXD_MSS_SHIFT       16  /* Adv ctxt MSS shift */
 
 /* Autonegotiation advertised speeds */
 typedef u32 ixgbe_autoneg_advertised;
 /* Link speed */
 typedef u32 ixgbe_link_speed;
-#define	IXGBE_LINK_SPEED_UNKNOWN   0
-#define	IXGBE_LINK_SPEED_100_FULL  0x0008
-#define	IXGBE_LINK_SPEED_1GB_FULL  0x0020
-#define	IXGBE_LINK_SPEED_10GB_FULL 0x0080
-#define	IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
-	IXGBE_LINK_SPEED_10GB_FULL)
-#define	IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
-	IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_10GB_FULL)
+#define IXGBE_LINK_SPEED_UNKNOWN   0
+#define IXGBE_LINK_SPEED_100_FULL  0x0008
+#define IXGBE_LINK_SPEED_1GB_FULL  0x0020
+#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
+#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
+                                        IXGBE_LINK_SPEED_10GB_FULL)
+#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
+                                        IXGBE_LINK_SPEED_1GB_FULL | \
+                                        IXGBE_LINK_SPEED_10GB_FULL)
 
+
 /* Physical layer type */
 typedef u32 ixgbe_physical_layer;
-#define	IXGBE_PHYSICAL_LAYER_UNKNOWN		0
-#define	IXGBE_PHYSICAL_LAYER_10GBASE_T		0x0001
-#define	IXGBE_PHYSICAL_LAYER_1000BASE_T		0x0002
-#define	IXGBE_PHYSICAL_LAYER_100BASE_TX		0x0004
-#define	IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU	0x0008
-#define	IXGBE_PHYSICAL_LAYER_10GBASE_LR		0x0010
-#define	IXGBE_PHYSICAL_LAYER_10GBASE_LRM	0x0020
-#define	IXGBE_PHYSICAL_LAYER_10GBASE_SR		0x0040
-#define	IXGBE_PHYSICAL_LAYER_10GBASE_KX4	0x0080
-#define	IXGBE_PHYSICAL_LAYER_10GBASE_CX4	0x0100
-#define	IXGBE_PHYSICAL_LAYER_1000BASE_KX	0x0200
-#define	IXGBE_PHYSICAL_LAYER_1000BASE_BX	0x0400
-#define	IXGBE_PHYSICAL_LAYER_10GBASE_KR		0x0800
-#define	IXGBE_PHYSICAL_LAYER_10GBASE_XAUI	0x1000
-#define	IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA	0x2000
+#define IXGBE_PHYSICAL_LAYER_UNKNOWN      0
+#define IXGBE_PHYSICAL_LAYER_10GBASE_T    0x0001
+#define IXGBE_PHYSICAL_LAYER_1000BASE_T   0x0002
+#define IXGBE_PHYSICAL_LAYER_100BASE_TX   0x0004
+#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU  0x0008
+#define IXGBE_PHYSICAL_LAYER_10GBASE_LR   0x0010
+#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM  0x0020
+#define IXGBE_PHYSICAL_LAYER_10GBASE_SR   0x0040
+#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4  0x0080
+#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4  0x0100
+#define IXGBE_PHYSICAL_LAYER_1000BASE_KX  0x0200
+#define IXGBE_PHYSICAL_LAYER_1000BASE_BX  0x0400
+#define IXGBE_PHYSICAL_LAYER_10GBASE_KR   0x0800
+#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
+#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
 
-/* Software ATR hash keys */
-#define	IXGBE_ATR_BUCKET_HASH_KEY	0xE214AD3D
-#define	IXGBE_ATR_SIGNATURE_HASH_KEY	0x14364D17
+/* Flow Control Macros */
+#define PAUSE_RTT	8
+#define PAUSE_MTU(MTU)	((MTU + 1024 - 1) / 1024)
 
-/* Software ATR input stream offsets and masks */
-#define	IXGBE_ATR_VLAN_OFFSET		0
-#define	IXGBE_ATR_SRC_IPV6_OFFSET	2
-#define	IXGBE_ATR_SRC_IPV4_OFFSET	14
-#define	IXGBE_ATR_DST_IPV6_OFFSET	18
-#define	IXGBE_ATR_DST_IPV4_OFFSET	30
-#define	IXGBE_ATR_SRC_PORT_OFFSET	34
-#define	IXGBE_ATR_DST_PORT_OFFSET	36
-#define	IXGBE_ATR_FLEX_BYTE_OFFSET	38
-#define	IXGBE_ATR_VM_POOL_OFFSET	40
-#define	IXGBE_ATR_L4TYPE_OFFSET		41
+#define FC_HIGH_WATER(MTU) ((((PAUSE_RTT + PAUSE_MTU(MTU)) * 144) + 99) / 100 +\
+				PAUSE_MTU(MTU))
+#define FC_LOW_WATER(MTU)  (2 * (2 * PAUSE_MTU(MTU) + PAUSE_RTT))
 
-#define	IXGBE_ATR_L4TYPE_MASK		0x3
-#define	IXGBE_ATR_L4TYPE_IPV6_MASK	0x4
-#define	IXGBE_ATR_L4TYPE_UDP		0x1
-#define	IXGBE_ATR_L4TYPE_TCP		0x2
-#define	IXGBE_ATR_L4TYPE_SCTP		0x3
-#define	IXGBE_ATR_HASH_MASK		0x7fff
+/* Software ATR hash keys */
+#define IXGBE_ATR_BUCKET_HASH_KEY    0x3DAD14E2
+#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
 
+/* Software ATR input stream values and masks */
+#define IXGBE_ATR_HASH_MASK     0x7fff
+#define IXGBE_ATR_L4TYPE_MASK      0x3
+#define IXGBE_ATR_L4TYPE_UDP       0x1
+#define IXGBE_ATR_L4TYPE_TCP       0x2
+#define IXGBE_ATR_L4TYPE_SCTP      0x3
+#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
+enum ixgbe_atr_flow_type {
+	IXGBE_ATR_FLOW_TYPE_IPV4   = 0x0,
+	IXGBE_ATR_FLOW_TYPE_UDPV4  = 0x1,
+	IXGBE_ATR_FLOW_TYPE_TCPV4  = 0x2,
+	IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
+	IXGBE_ATR_FLOW_TYPE_IPV6   = 0x4,
+	IXGBE_ATR_FLOW_TYPE_UDPV6  = 0x5,
+	IXGBE_ATR_FLOW_TYPE_TCPV6  = 0x6,
+	IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
+};
+
 /* Flow Director ATR input struct. */
-struct ixgbe_atr_input {
+union ixgbe_atr_input {
 	/*
 	 * Byte layout in order, all values with MSB first:
 	 *
-	 * vlan_id	- 2 bytes
-	 * src_ip	- 16 bytes
-	 * dst_ip	- 16 bytes
-	 * src_port	- 2 bytes
-	 * dst_port	- 2 bytes
-	 * flex_bytes	- 2 bytes
-	 * vm_pool	- 1 byte
-	 * l4type	- 1 byte
+	 * vm_pool    - 1 byte
+	 * flow_type  - 1 byte
+	 * vlan_id    - 2 bytes
+	 * src_ip     - 16 bytes
+	 * dst_ip     - 16 bytes
+	 * src_port   - 2 bytes
+	 * dst_port   - 2 bytes
+	 * flex_bytes - 2 bytes
+	 * rsvd0      - 2 bytes - space reserved must be 0.
 	 */
-	u8 byte_stream[42];
+	struct {
+		u8     vm_pool;
+		u8     flow_type;
+		__be16 vlan_id;
+		__be32 dst_ip[4];
+		__be32 src_ip[4];
+		__be16 src_port;
+		__be16 dst_port;
+		__be16 flex_bytes;
+		__be16 rsvd0;
+	} formatted;
+	__be32 dword_stream[11];
 };
 
+/* Flow Director compressed ATR hash input struct */
+union ixgbe_atr_hash_dword {
+	struct {
+		u8 vm_pool;
+		u8 flow_type;
+		__be16 vlan_id;
+	} formatted;
+	__be32 ip;
+	struct {
+		__be16 src;
+		__be16 dst;
+	} port;
+	__be16 flex_bytes;
+	__be32 dword;
+};
+
+
 struct ixgbe_atr_input_masks {
-	u32 src_ip_mask;
-	u32 dst_ip_mask;
-	u16 src_port_mask;
-	u16 dst_port_mask;
-	u16 vlan_id_mask;
-	u16 data_mask;
+	__be16 rsvd0;
+	__be16 vlan_id_mask;
+	__be32 dst_ip_mask[4];
+	__be32 src_ip_mask[4];
+	__be16 src_port_mask;
+	__be16 dst_port_mask;
+	__be16 flex_mask;
 };
 
 /*
@@ -2346,9 +2369,9 @@
  * Enabled: Present; boot order is set for at least one target on the port.
  */
 enum ixgbe_fcoe_boot_status {
-    ixgbe_fcoe_bootstatus_disabled = 0,
-    ixgbe_fcoe_bootstatus_enabled = 1,
-    ixgbe_fcoe_bootstatus_unavailable = 0xFFFF
+    ixgbe_fcoe_bootstatus_disabled        = 0,
+    ixgbe_fcoe_bootstatus_enabled         = 1,
+    ixgbe_fcoe_bootstatus_unavailable     = 0xFFFF
 };
 
 enum ixgbe_eeprom_type {
@@ -2382,7 +2405,7 @@
 	ixgbe_phy_sfp_ftl_active,
 	ixgbe_phy_sfp_unknown,
 	ixgbe_phy_sfp_intel,
-	ixgbe_phy_sfp_unsupported, /* Enforce bit set with unsupported module */
+	ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/
 	ixgbe_phy_generic
 };
 
@@ -2389,11 +2412,11 @@
 /*
  * SFP+ module type IDs:
  *
- * ID   Module Type
+ * ID	Module Type
  * =============
- * 0    SFP_DA_CU
- * 1    SFP_SR
- * 2    SFP_LR
+ * 0	SFP_DA_CU
+ * 1	SFP_SR
+ * 2	SFP_LR
  * 3    SFP_DA_CU_CORE0 - 82599-specific
  * 4    SFP_DA_CU_CORE1 - 82599-specific
  * 5    SFP_SR/LR_CORE0 - 82599-specific
@@ -2434,7 +2457,7 @@
 };
 
 /* Smart Speed Settings */
-#define	IXGBE_SMARTSPEED_MAX_RETRIES	3
+#define IXGBE_SMARTSPEED_MAX_RETRIES	3
 enum ixgbe_smart_speed {
 	ixgbe_smart_speed_auto = 0,
 	ixgbe_smart_speed_on,
@@ -2453,13 +2476,13 @@
 /* PCI bus speeds */
 enum ixgbe_bus_speed {
 	ixgbe_bus_speed_unknown = 0,
-	ixgbe_bus_speed_33 = 33,
-	ixgbe_bus_speed_66 = 66,
-	ixgbe_bus_speed_100 = 100,
-	ixgbe_bus_speed_120 = 120,
-	ixgbe_bus_speed_133 = 133,
-	ixgbe_bus_speed_2500 = 2500,
-	ixgbe_bus_speed_5000 = 5000,
+	ixgbe_bus_speed_33      = 33,
+	ixgbe_bus_speed_66      = 66,
+	ixgbe_bus_speed_100     = 100,
+	ixgbe_bus_speed_120     = 120,
+	ixgbe_bus_speed_133     = 133,
+	ixgbe_bus_speed_2500    = 2500,
+	ixgbe_bus_speed_5000    = 5000,
 	ixgbe_bus_speed_reserved
 };
 
@@ -2470,8 +2493,8 @@
 	ixgbe_bus_width_pcie_x2 = 2,
 	ixgbe_bus_width_pcie_x4 = 4,
 	ixgbe_bus_width_pcie_x8 = 8,
-	ixgbe_bus_width_32 = 32,
-	ixgbe_bus_width_64 = 64,
+	ixgbe_bus_width_32      = 32,
+	ixgbe_bus_width_64      = 64,
 	ixgbe_bus_width_reserved
 };
 
@@ -2583,7 +2606,7 @@
 
 /* iterator type for walking multicast address lists */
 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
-	u32 *vmdq);
+                                  u32 *vmdq);
 
 /* Function pointer table */
 struct ixgbe_eeprom_operations {
@@ -2612,8 +2635,8 @@
 	s32 (*stop_adapter)(struct ixgbe_hw *);
 	s32 (*get_bus_info)(struct ixgbe_hw *);
 	void (*set_lan_id)(struct ixgbe_hw *);
-	s32 (*read_analog_reg8)(struct ixgbe_hw *, u32, u8 *);
-	s32 (*write_analog_reg8)(struct ixgbe_hw *, u32, u8);
+	s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
+	s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
 	s32 (*setup_sfp)(struct ixgbe_hw *);
 	s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
 	s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
@@ -2626,7 +2649,7 @@
 	s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
 	s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
 	s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
-	    bool *);
+	                             bool *);
 
 	/* LED */
 	s32 (*led_on)(struct ixgbe_hw *, u32);
@@ -2642,14 +2665,16 @@
 	s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
 	s32 (*init_rx_addrs)(struct ixgbe_hw *);
 	s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
-	    ixgbe_mc_addr_itr);
+	                           ixgbe_mc_addr_itr);
 	s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
-	    ixgbe_mc_addr_itr);
+	                           ixgbe_mc_addr_itr);
 	s32 (*enable_mc)(struct ixgbe_hw *);
 	s32 (*disable_mc)(struct ixgbe_hw *);
 	s32 (*clear_vfta)(struct ixgbe_hw *);
 	s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
 	s32 (*init_uta_tables)(struct ixgbe_hw *);
+	void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
+	void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
 
 	/* Flow Control */
 	s32 (*fc_enable)(struct ixgbe_hw *, s32);
@@ -2664,12 +2689,12 @@
 	s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
 	s32 (*setup_link)(struct ixgbe_hw *);
 	s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
-	    bool);
+	                        bool);
 	s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
 	s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
 	s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
 	s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
-	s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8, u8 *);
+	s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
 	s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
 	void (*i2c_bus_clear)(struct ixgbe_hw *);
 	s32 (*check_overtemp)(struct ixgbe_hw *);
@@ -2676,117 +2701,116 @@
 };
 
 struct ixgbe_eeprom_info {
-	struct ixgbe_eeprom_operations	ops;
-	enum ixgbe_eeprom_type		type;
-	u32				semaphore_delay;
-	u16				word_size;
-	u16				address_bits;
+	struct ixgbe_eeprom_operations  ops;
+	enum ixgbe_eeprom_type          type;
+	u32                             semaphore_delay;
+	u16                             word_size;
+	u16                             address_bits;
 };
 
-#define	IXGBE_FLAGS_DOUBLE_RESET_REQUIRED	0x01
+#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED	0x01
 struct ixgbe_mac_info {
-	struct ixgbe_mac_operations	ops;
-	enum ixgbe_mac_type		type;
-	u8				addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
-	u8				perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
-	u8				san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
+	struct ixgbe_mac_operations     ops;
+	enum ixgbe_mac_type             type;
+	u8                              addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
+	u8                              perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
+	u8                              san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
 	/* prefix for World Wide Node Name (WWNN) */
-	u16				wwnn_prefix;
+	u16                             wwnn_prefix;
 	/* prefix for World Wide Port Name (WWPN) */
-	u16				wwpn_prefix;
-#define	IXGBE_MAX_MTA			128
+	u16                             wwpn_prefix;
+#define IXGBE_MAX_MTA			128
 	u32				mta_shadow[IXGBE_MAX_MTA];
-	s32				mc_filter_type;
-	u32				mcft_size;
-	u32				vft_size;
-	u32				num_rar_entries;
-	u32				rar_highwater;
-	u32				max_tx_queues;
-	u32				max_rx_queues;
-	u32				max_msix_vectors;
-	bool				msix_vectors_from_pcie;
-	u32				orig_autoc;
-	u32				orig_autoc2;
-	bool				orig_link_settings_stored;
-	bool				autotry_restart;
-	u8				flags;
+	s32                             mc_filter_type;
+	u32                             mcft_size;
+	u32                             vft_size;
+	u32                             num_rar_entries;
+	u32                             rar_highwater;
+	u32                             rx_pb_size;
+	u32                             max_tx_queues;
+	u32                             max_rx_queues;
+	u32                             max_msix_vectors;
+	bool                            msix_vectors_from_pcie;
+	u32                             orig_autoc;
+	u32                             orig_autoc2;
+	bool                            orig_link_settings_stored;
+	bool                            autotry_restart;
+	u8                              flags;
 };
 
 struct ixgbe_phy_info {
-	struct ixgbe_phy_operations	ops;
-	enum ixgbe_phy_type		type;
-	u32				addr;
-	u32				id;
-	enum ixgbe_sfp_type		sfp_type;
-	bool				sfp_setup_needed;
-	u32				revision;
-	enum ixgbe_media_type		media_type;
-	bool				reset_disable;
-	ixgbe_autoneg_advertised	autoneg_advertised;
-	enum ixgbe_smart_speed		smart_speed;
-	bool				smart_speed_active;
-	bool				multispeed_fiber;
-	bool				reset_if_overtemp;
+	struct ixgbe_phy_operations     ops;
+	enum ixgbe_phy_type             type;
+	u32                             addr;
+	u32                             id;
+	enum ixgbe_sfp_type             sfp_type;
+	bool                            sfp_setup_needed;
+	u32                             revision;
+	enum ixgbe_media_type           media_type;
+	bool                            reset_disable;
+	ixgbe_autoneg_advertised        autoneg_advertised;
+	enum ixgbe_smart_speed          smart_speed;
+	bool                            smart_speed_active;
+	bool                            multispeed_fiber;
+	bool                            reset_if_overtemp;
 };
 
 struct ixgbe_hw {
-	u8				*hw_addr;
-	void				*back;
-	struct ixgbe_mac_info		mac;
-	struct ixgbe_addr_filter_info	addr_ctrl;
-	struct ixgbe_fc_info		fc;
-	struct ixgbe_phy_info		phy;
-	struct ixgbe_eeprom_info	eeprom;
-	struct ixgbe_bus_info		bus;
-	u16				device_id;
-	u16				vendor_id;
-	u16				subsystem_device_id;
-	u16				subsystem_vendor_id;
-	u8				revision_id;
-	bool				adapter_stopped;
+	u8                              *hw_addr;
+	void                            *back;
+	struct ixgbe_mac_info           mac;
+	struct ixgbe_addr_filter_info   addr_ctrl;
+	struct ixgbe_fc_info            fc;
+	struct ixgbe_phy_info           phy;
+	struct ixgbe_eeprom_info        eeprom;
+	struct ixgbe_bus_info           bus;
+	u16                             device_id;
+	u16                             vendor_id;
+	u16                             subsystem_device_id;
+	u16                             subsystem_vendor_id;
+	u8                              revision_id;
+	bool                            adapter_stopped;
 };
 
-#define	ixgbe_call_func(hw, func, params, error) \
-	(func != NULL) ? func params: error
+#define ixgbe_call_func(hw, func, params, error) \
+                (func != NULL) ? func params : error
 
+
 /* Error Codes */
-#define	IXGBE_SUCCESS				0
-#define	IXGBE_ERR_EEPROM			-1
-#define	IXGBE_ERR_EEPROM_CHECKSUM		-2
-#define	IXGBE_ERR_PHY				-3
-#define	IXGBE_ERR_CONFIG			-4
-#define	IXGBE_ERR_PARAM				-5
-#define	IXGBE_ERR_MAC_TYPE			-6
-#define	IXGBE_ERR_UNKNOWN_PHY			-7
-#define	IXGBE_ERR_LINK_SETUP			-8
-#define	IXGBE_ERR_ADAPTER_STOPPED		-9
-#define	IXGBE_ERR_INVALID_MAC_ADDR		-10
-#define	IXGBE_ERR_DEVICE_NOT_SUPPORTED		-11
-#define	IXGBE_ERR_MASTER_REQUESTS_PENDING	-12
-#define	IXGBE_ERR_INVALID_LINK_SETTINGS		-13
-#define	IXGBE_ERR_AUTONEG_NOT_COMPLETE		-14
-#define	IXGBE_ERR_RESET_FAILED			-15
-#define	IXGBE_ERR_SWFW_SYNC			-16
-#define	IXGBE_ERR_PHY_ADDR_INVALID		-17
-#define	IXGBE_ERR_I2C				-18
-#define	IXGBE_ERR_SFP_NOT_SUPPORTED		-19
-#define	IXGBE_ERR_SFP_NOT_PRESENT		-20
-#define	IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT	-21
-#define	IXGBE_ERR_NO_SAN_ADDR_PTR		-22
-#define	IXGBE_ERR_FDIR_REINIT_FAILED		-23
-#define	IXGBE_ERR_EEPROM_VERSION		-24
-#define	IXGBE_ERR_NO_SPACE			-25
-#define	IXGBE_ERR_OVERTEMP			-26
-#define	IXGBE_ERR_FC_NOT_NEGOTIATED		-27
-#define	IXGBE_ERR_FC_NOT_SUPPORTED		-28
-#define	IXGBE_ERR_FLOW_CONTROL			-29
-#define	IXGBE_NOT_IMPLEMENTED			0x7FFFFFFF
+#define IXGBE_SUCCESS                           0
+#define IXGBE_ERR_EEPROM                        -1
+#define IXGBE_ERR_EEPROM_CHECKSUM               -2
+#define IXGBE_ERR_PHY                           -3
+#define IXGBE_ERR_CONFIG                        -4
+#define IXGBE_ERR_PARAM                         -5
+#define IXGBE_ERR_MAC_TYPE                      -6
+#define IXGBE_ERR_UNKNOWN_PHY                   -7
+#define IXGBE_ERR_LINK_SETUP                    -8
+#define IXGBE_ERR_ADAPTER_STOPPED               -9
+#define IXGBE_ERR_INVALID_MAC_ADDR              -10
+#define IXGBE_ERR_DEVICE_NOT_SUPPORTED          -11
+#define IXGBE_ERR_MASTER_REQUESTS_PENDING       -12
+#define IXGBE_ERR_INVALID_LINK_SETTINGS         -13
+#define IXGBE_ERR_AUTONEG_NOT_COMPLETE          -14
+#define IXGBE_ERR_RESET_FAILED                  -15
+#define IXGBE_ERR_SWFW_SYNC                     -16
+#define IXGBE_ERR_PHY_ADDR_INVALID              -17
+#define IXGBE_ERR_I2C                           -18
+#define IXGBE_ERR_SFP_NOT_SUPPORTED             -19
+#define IXGBE_ERR_SFP_NOT_PRESENT               -20
+#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT       -21
+#define IXGBE_ERR_NO_SAN_ADDR_PTR               -22
+#define IXGBE_ERR_FDIR_REINIT_FAILED            -23
+#define IXGBE_ERR_EEPROM_VERSION                -24
+#define IXGBE_ERR_NO_SPACE                      -25
+#define IXGBE_ERR_OVERTEMP                      -26
+#define IXGBE_ERR_FC_NOT_NEGOTIATED             -27
+#define IXGBE_ERR_FC_NOT_SUPPORTED              -28
+#define IXGBE_ERR_FLOW_CONTROL                  -29
+#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE        -30
+#define IXGBE_ERR_PBA_SECTION                   -31
+#define IXGBE_ERR_INVALID_ARGUMENT              -32
+#define IXGBE_NOT_IMPLEMENTED                   0x7FFFFFFF
 
-#ifndef UNREFERENCED_PARAMETER
-#define	UNREFERENCED_PARAMETER(_p)		(_p);
-#define	UNREFERENCED_2PARAMETER(_p, _q) 	(_p); (_q);
-#define	UNREFERENCED_3PARAMETER(_p, _q, _r)	(_p); (_q); (_r);
-#define	UNREFERENCED_4PARAMETER(_p, _q, _r, _s)	(_p); (_q); (_r); (_s);
-#endif
 
-#endif /* _IXGBE_TYPE_H */
+#endif /* _IXGBE_TYPE_H_ */
