7315         size_t *real_length, ddi_acc_handle_t *handlep)
7316 {
7317         ddi_dma_impl_t *hp = (ddi_dma_impl_t *)handle;
7318         dev_info_t *dip = hp->dmai_rdip;
7319         ddi_acc_hdl_t *ap;
7320         ddi_dma_attr_t *attrp = &hp->dmai_attr;
7321         uint_t sleepflag, xfermodes;
7322         int (*fp)(caddr_t);
7323         int rval;
7324 
7325         if (waitfp == DDI_DMA_SLEEP)
7326                 fp = (int (*)())KM_SLEEP;
7327         else if (waitfp == DDI_DMA_DONTWAIT)
7328                 fp = (int (*)())KM_NOSLEEP;
7329         else
7330                 fp = waitfp;
7331         *handlep = impl_acc_hdl_alloc(fp, arg);
7332         if (*handlep == NULL)
7333                 return (DDI_FAILURE);
7334 
7335 /* SPARC mappings are always cacheable, as SPARC guarantees cache coherency. */
7336 #ifndef __sparc
7337         /* Transform attributes into correct cache flags. */
7338         if ((flags & IOMEM_DATA_MASK) == 0) {
7339                 switch (accattrp->devacc_attr_dataorder) {
7340                 case DDI_STRICTORDER_ACC:
7341                         flags |= IOMEM_DATA_UNCACHED;
7342                         break;
7343                 case DDI_MERGING_OK_ACC:
7344                         flags |= IOMEM_DATA_UC_WR_COMBINE;
7345                         break;
7346                 default:
7347                         flags |= IOMEM_DATA_CACHED;
7348                         break;
7349                 }
7350         }
7351 #endif
7352 
7353         /* check if the cache attributes are supported */
7354         if (i_ddi_check_cache_attr(flags) == B_FALSE)
7355                 return (DDI_FAILURE);
7356 
7357         /*
7358          * Transfer the meaningful bits to xfermodes.
7359          * Double-check if the 3rd party driver correctly sets the bits.
7360          * If not, set DDI_DMA_STREAMING to keep compatibility.
7361          */
7362         xfermodes = flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING);
7363         if (xfermodes == 0) {
7364                 xfermodes = DDI_DMA_STREAMING;
7365         }
7366 
7367         /*
7368          * initialize the common elements of data access handle
7369          */
7370         ap = impl_acc_hdl_get(*handlep);
7371         ap->ah_vers = VERS_ACCHDL;
7372         ap->ah_dip = dip;

7315         size_t *real_length, ddi_acc_handle_t *handlep)
7316 {
7317         ddi_dma_impl_t *hp = (ddi_dma_impl_t *)handle;
7318         dev_info_t *dip = hp->dmai_rdip;
7319         ddi_acc_hdl_t *ap;
7320         ddi_dma_attr_t *attrp = &hp->dmai_attr;
7321         uint_t sleepflag, xfermodes;
7322         int (*fp)(caddr_t);
7323         int rval;
7324 
7325         if (waitfp == DDI_DMA_SLEEP)
7326                 fp = (int (*)())KM_SLEEP;
7327         else if (waitfp == DDI_DMA_DONTWAIT)
7328                 fp = (int (*)())KM_NOSLEEP;
7329         else
7330                 fp = waitfp;
7331         *handlep = impl_acc_hdl_alloc(fp, arg);
7332         if (*handlep == NULL)
7333                 return (DDI_FAILURE);
7334 


















7335         /* check if the cache attributes are supported */
7336         if (i_ddi_check_cache_attr(flags) == B_FALSE)
7337                 return (DDI_FAILURE);
7338 
7339         /*
7340          * Transfer the meaningful bits to xfermodes.
7341          * Double-check if the 3rd party driver correctly sets the bits.
7342          * If not, set DDI_DMA_STREAMING to keep compatibility.
7343          */
7344         xfermodes = flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING);
7345         if (xfermodes == 0) {
7346                 xfermodes = DDI_DMA_STREAMING;
7347         }
7348 
7349         /*
7350          * initialize the common elements of data access handle
7351          */
7352         ap = impl_acc_hdl_get(*handlep);
7353         ap->ah_vers = VERS_ACCHDL;
7354         ap->ah_dip = dip;