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13902 Fix for 13717 may break 8-disk raidz2
13915 installctx() blocking allocate causes problems
Portions contributed by: Jerry Jelinek <gjelinek@gmail.com>
Change-Id: I934d69946cec42630fc541fa8c7385b862b69ca2
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--- old/usr/src/uts/intel/ia32/os/cpc_subr.c
+++ new/usr/src/uts/intel/ia32/os/cpc_subr.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
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13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
23 - * Copyright 2019 Joyent, Inc.
23 + * Copyright 2021 Joyent, Inc.
24 24 */
25 25
26 26 /*
27 27 * x86-specific routines used by the CPU Performance counter driver.
28 28 */
29 29
30 30 #include <sys/types.h>
31 31 #include <sys/time.h>
32 32 #include <sys/atomic.h>
33 33 #include <sys/regset.h>
34 34 #include <sys/privregs.h>
35 35 #include <sys/x86_archext.h>
36 36 #include <sys/cpuvar.h>
37 37 #include <sys/machcpuvar.h>
38 38 #include <sys/archsystm.h>
39 39 #include <sys/cpc_pcbe.h>
40 40 #include <sys/cpc_impl.h>
41 41 #include <sys/x_call.h>
42 42 #include <sys/cmn_err.h>
43 43 #include <sys/cmt.h>
44 44 #include <sys/spl.h>
45 45 #include <sys/apic.h>
46 46
47 47 static const uint64_t allstopped = 0;
48 48 static kcpc_ctx_t *(*overflow_intr_handler)(caddr_t);
49 49
50 50 /* Do threads share performance monitoring hardware? */
51 51 static int strands_perfmon_shared = 0;
52 52
53 53 int kcpc_hw_overflow_intr_installed; /* set by APIC code */
54 54 extern kcpc_ctx_t *kcpc_overflow_intr(caddr_t arg, uint64_t bitmap);
55 55
56 56 extern int kcpc_counts_include_idle; /* Project Private /etc/system variable */
57 57
58 58 void (*kcpc_hw_enable_cpc_intr)(void); /* set by APIC code */
59 59
60 60 int
61 61 kcpc_hw_add_ovf_intr(kcpc_ctx_t *(*handler)(caddr_t))
62 62 {
63 63 if (x86_type != X86_TYPE_P6)
64 64 return (0);
65 65 overflow_intr_handler = handler;
66 66 return (ipltospl(APIC_PCINT_IPL));
67 67 }
68 68
69 69 void
70 70 kcpc_hw_rem_ovf_intr(void)
71 71 {
72 72 overflow_intr_handler = NULL;
73 73 }
74 74
75 75 /*
76 76 * Hook used on P4 systems to catch online/offline events.
77 77 */
78 78 /*ARGSUSED*/
79 79 static int
80 80 kcpc_cpu_setup(cpu_setup_t what, int cpuid, void *arg)
81 81 {
82 82 pg_cmt_t *chip_pg;
83 83 int active_cpus_cnt;
84 84
85 85 if (what != CPU_ON)
86 86 return (0);
87 87
88 88 /*
89 89 * If any CPU-bound contexts exist, we don't need to invalidate
90 90 * anything, as no per-LWP contexts can coexist.
91 91 */
92 92 if (kcpc_cpuctx || dtrace_cpc_in_use)
93 93 return (0);
94 94
95 95 /*
96 96 * If this chip now has more than 1 active cpu, we must invalidate all
97 97 * contexts in the system.
98 98 */
99 99 chip_pg = (pg_cmt_t *)pghw_find_pg(cpu[cpuid], PGHW_CHIP);
100 100 if (chip_pg != NULL) {
101 101 active_cpus_cnt = GROUP_SIZE(&chip_pg->cmt_cpus_actv);
102 102 if (active_cpus_cnt > 1)
103 103 kcpc_invalidate_all();
104 104 }
105 105
106 106 return (0);
107 107 }
108 108
109 109 static kmutex_t cpu_setup_lock; /* protects setup_registered */
110 110 static int setup_registered;
111 111
112 112
113 113 void
114 114 kcpc_hw_init(cpu_t *cp)
115 115 {
116 116 kthread_t *t = cp->cpu_idle_thread;
117 117 uint32_t versionid;
118 118 struct cpuid_regs cpuid;
119 119
120 120 strands_perfmon_shared = 0;
121 121 if (is_x86_feature(x86_featureset, X86FSET_HTT)) {
122 122 if (cpuid_getvendor(cpu[0]) == X86_VENDOR_Intel) {
123 123 /*
124 124 * Intel processors that support Architectural
125 125 * Performance Monitoring Version 3 have per strand
126 126 * performance monitoring hardware.
127 127 * Hence we can allow use of performance counters on
128 128 * multiple strands on the same core simultaneously.
129 129 */
130 130 cpuid.cp_eax = 0x0;
131 131 (void) __cpuid_insn(&cpuid);
132 132 if (cpuid.cp_eax < 0xa) {
133 133 strands_perfmon_shared = 1;
134 134 } else {
135 135 cpuid.cp_eax = 0xa;
136 136 (void) __cpuid_insn(&cpuid);
137 137
138 138 versionid = cpuid.cp_eax & 0xFF;
139 139 if (versionid < 3) {
140 140 strands_perfmon_shared = 1;
141 141 }
142 142 }
143 143 } else if (cpuid_getvendor(cpu[0]) == X86_VENDOR_AMD ||
144 144 cpuid_getvendor(cpu[0]) == X86_VENDOR_HYGON) {
145 145 /*
146 146 * On AMD systems with HT, all of the performance
147 147 * monitors exist on a per-logical CPU basis.
148 148 */
149 149 strands_perfmon_shared = 0;
150 150 } else {
151 151 strands_perfmon_shared = 1;
152 152 }
153 153 }
154 154
155 155 if (strands_perfmon_shared) {
156 156 mutex_enter(&cpu_setup_lock);
157 157 if (setup_registered == 0) {
158 158 mutex_enter(&cpu_lock);
159 159 register_cpu_setup_func(kcpc_cpu_setup, NULL);
160 160 mutex_exit(&cpu_lock);
161 161 setup_registered = 1;
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162 162 }
163 163 mutex_exit(&cpu_setup_lock);
164 164 }
165 165
166 166 mutex_init(&cp->cpu_cpc_ctxlock, "cpu_cpc_ctxlock", MUTEX_DEFAULT, 0);
167 167
168 168 if (kcpc_counts_include_idle)
169 169 return;
170 170
171 171 installctx(t, cp, kcpc_idle_save, kcpc_idle_restore,
172 - NULL, NULL, NULL, NULL);
172 + NULL, NULL, NULL, NULL, NULL);
173 173 }
174 174
175 175 void
176 176 kcpc_hw_fini(cpu_t *cp)
177 177 {
178 178 ASSERT(cp->cpu_idle_thread == NULL);
179 179
180 180 mutex_destroy(&cp->cpu_cpc_ctxlock);
181 181 }
182 182
183 183 #define BITS(v, u, l) \
184 184 (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1))
185 185
186 186 #define PCBE_NAMELEN 30 /* Enough Room for pcbe.manuf.model.family.stepping */
187 187
188 188 /*
189 189 * Examine the processor and load an appropriate PCBE.
190 190 */
191 191 int
192 192 kcpc_hw_load_pcbe(void)
193 193 {
194 194 return (kcpc_pcbe_tryload(cpuid_getvendorstr(CPU), cpuid_getfamily(CPU),
195 195 cpuid_getmodel(CPU), cpuid_getstep(CPU)));
196 196 }
197 197
198 198 /*
199 199 * Called by the generic framework to check if it's OK to bind a set to a CPU.
200 200 */
201 201 int
202 202 kcpc_hw_cpu_hook(processorid_t cpuid, ulong_t *kcpc_cpumap)
203 203 {
204 204 cpu_t *cpu, *p;
205 205 pg_t *chip_pg;
206 206 pg_cpu_itr_t itr;
207 207
208 208 if (!strands_perfmon_shared)
209 209 return (0);
210 210
211 211 /*
212 212 * Only one logical CPU on each Pentium 4 HT CPU may be bound to at
213 213 * once.
214 214 *
215 215 * This loop is protected by holding cpu_lock, in order to properly
216 216 * access the cpu_t of the desired cpu.
217 217 */
218 218 mutex_enter(&cpu_lock);
219 219 if ((cpu = cpu_get(cpuid)) == NULL) {
220 220 mutex_exit(&cpu_lock);
221 221 return (-1);
222 222 }
223 223
224 224 chip_pg = (pg_t *)pghw_find_pg(cpu, PGHW_CHIP);
225 225
226 226 PG_CPU_ITR_INIT(chip_pg, itr);
227 227 while ((p = pg_cpu_next(&itr)) != NULL) {
228 228 if (p == cpu)
229 229 continue;
230 230 if (BT_TEST(kcpc_cpumap, p->cpu_id)) {
231 231 mutex_exit(&cpu_lock);
232 232 return (-1);
233 233 }
234 234 }
235 235
236 236 mutex_exit(&cpu_lock);
237 237 return (0);
238 238 }
239 239
240 240 /*
241 241 * Called by the generic framework to check if it's OK to bind a set to an LWP.
242 242 */
243 243 int
244 244 kcpc_hw_lwp_hook(void)
245 245 {
246 246 pg_cmt_t *chip;
247 247 group_t *chips;
248 248 group_iter_t i;
249 249
250 250 if (!strands_perfmon_shared)
251 251 return (0);
252 252
253 253 /*
254 254 * Only one CPU per chip may be online.
255 255 */
256 256 mutex_enter(&cpu_lock);
257 257
258 258 chips = pghw_set_lookup(PGHW_CHIP);
259 259 if (chips == NULL) {
260 260 mutex_exit(&cpu_lock);
261 261 return (0);
262 262 }
263 263
264 264 group_iter_init(&i);
265 265 while ((chip = group_iterate(chips, &i)) != NULL) {
266 266 if (GROUP_SIZE(&chip->cmt_cpus_actv) > 1) {
267 267 mutex_exit(&cpu_lock);
268 268 return (-1);
269 269 }
270 270 }
271 271
272 272 mutex_exit(&cpu_lock);
273 273 return (0);
274 274 }
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