917 #define X86FSET_AVX512VNNI 91
918 #define X86FSET_AMD_PCEC 92
919 #define X86FSET_MD_CLEAR 93
920 #define X86FSET_MDS_NO 94
921 #define X86FSET_CORE_THERMAL 95
922 #define X86FSET_PKG_THERMAL 96
923 #define X86FSET_TSX_CTRL 97
924 #define X86FSET_TAA_NO 98
925 #define X86FSET_PPIN 99
926 #define X86FSET_VAES 100
927 #define X86FSET_VPCLMULQDQ 101
928 #define X86FSET_LFENCE_SER 102
929 #define X86FSET_GFNI 103
930 #define X86FSET_AVX512_VP2INT 104
931 #define X86FSET_AVX512_BITALG 105
932 #define X86FSET_AVX512_VBMI2 106
933 #define X86FSET_AVX512_BF16 107
934 #define X86FSET_AUTO_IBRS 108
935 #define X86FSET_RFDS_NO 109
936 #define X86FSET_RFDS_CLEAR 110
937
938 /*
939 * Intel Deep C-State invariant TSC in leaf 0x80000007.
940 */
941 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
942
943 /*
944 * Intel TSC deadline timer
945 */
946 #define CPUID_DEADLINE_TSC (1 << 24)
947
948 /*
949 * x86_type is a legacy concept; this is supplanted
950 * for most purposes by x86_featureset; modern CPUs
951 * should be X86_TYPE_OTHER
952 */
953 #define X86_TYPE_OTHER 0
954 #define X86_TYPE_486 1
955 #define X86_TYPE_P5 2
956 #define X86_TYPE_P6 3
1569 #define XFEATURE_PKRU (1 << 9)
1570 #define XFEATURE_FP_ALL \
1571 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
1572 XFEATURE_AVX512 | XFEATURE_PKRU)
1573
1574 /*
1575 * Define the set of xfeature flags that should be considered valid in the xsave
1576 * state vector when we initialize an lwp. This is distinct from the full set so
1577 * that all of the processor's normal logic and tracking of the xsave state is
1578 * usable. This should correspond to the state that's been initialized by the
1579 * ABI to hold meaningful values. Adding additional bits here can have serious
1580 * performance implications and cause performance degradations when using the
1581 * FPU vector (xmm) registers.
1582 */
1583 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE)
1584
1585 #if !defined(_ASM)
1586
1587 #if defined(_KERNEL) || defined(_KMEMUSER)
1588
1589 #define NUM_X86_FEATURES 111
1590 extern uchar_t x86_featureset[];
1591
1592 extern void free_x86_featureset(void *featureset);
1593 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
1594 extern void add_x86_feature(void *featureset, uint_t feature);
1595 extern void remove_x86_feature(void *featureset, uint_t feature);
1596 extern boolean_t compare_x86_featureset(void *setA, void *setB);
1597 extern void print_x86_featureset(void *featureset);
1598
1599
1600 extern uint_t x86_type;
1601 extern uint_t x86_vendor;
1602 extern uint_t x86_clflush_size;
1603
1604 extern uint_t pentiumpro_bug4046376;
1605
1606 /*
1607 * These functions are all used to perform various side-channel mitigations.
1608 * Please see uts/i86pc/os/cpuid.c for more information.
1609 */
1610 extern void (*spec_uarch_flush)(void);
1611 extern void x86_rsb_stuff(void);
1612 extern void x86_md_clear(void);
1613
1614 #endif
1615
1616 #if defined(_KERNEL)
1617
1618 /*
1619 * This structure is used to pass arguments and get return values back
1620 * from the CPUID instruction in __cpuid_insn() routine.
1621 */
1622 struct cpuid_regs {
1623 uint32_t cp_eax;
1624 uint32_t cp_ebx;
1625 uint32_t cp_ecx;
1626 uint32_t cp_edx;
1627 };
1628
1629 extern int x86_use_pcid;
1630 extern int x86_use_invpcid;
1631
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917 #define X86FSET_AVX512VNNI 91
918 #define X86FSET_AMD_PCEC 92
919 #define X86FSET_MD_CLEAR 93
920 #define X86FSET_MDS_NO 94
921 #define X86FSET_CORE_THERMAL 95
922 #define X86FSET_PKG_THERMAL 96
923 #define X86FSET_TSX_CTRL 97
924 #define X86FSET_TAA_NO 98
925 #define X86FSET_PPIN 99
926 #define X86FSET_VAES 100
927 #define X86FSET_VPCLMULQDQ 101
928 #define X86FSET_LFENCE_SER 102
929 #define X86FSET_GFNI 103
930 #define X86FSET_AVX512_VP2INT 104
931 #define X86FSET_AVX512_BITALG 105
932 #define X86FSET_AVX512_VBMI2 106
933 #define X86FSET_AVX512_BF16 107
934 #define X86FSET_AUTO_IBRS 108
935 #define X86FSET_RFDS_NO 109
936 #define X86FSET_RFDS_CLEAR 110
937 #define X86FSET_PBRSB_NO 111
938
939 /*
940 * Intel Deep C-State invariant TSC in leaf 0x80000007.
941 */
942 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
943
944 /*
945 * Intel TSC deadline timer
946 */
947 #define CPUID_DEADLINE_TSC (1 << 24)
948
949 /*
950 * x86_type is a legacy concept; this is supplanted
951 * for most purposes by x86_featureset; modern CPUs
952 * should be X86_TYPE_OTHER
953 */
954 #define X86_TYPE_OTHER 0
955 #define X86_TYPE_486 1
956 #define X86_TYPE_P5 2
957 #define X86_TYPE_P6 3
1570 #define XFEATURE_PKRU (1 << 9)
1571 #define XFEATURE_FP_ALL \
1572 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
1573 XFEATURE_AVX512 | XFEATURE_PKRU)
1574
1575 /*
1576 * Define the set of xfeature flags that should be considered valid in the xsave
1577 * state vector when we initialize an lwp. This is distinct from the full set so
1578 * that all of the processor's normal logic and tracking of the xsave state is
1579 * usable. This should correspond to the state that's been initialized by the
1580 * ABI to hold meaningful values. Adding additional bits here can have serious
1581 * performance implications and cause performance degradations when using the
1582 * FPU vector (xmm) registers.
1583 */
1584 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE)
1585
1586 #if !defined(_ASM)
1587
1588 #if defined(_KERNEL) || defined(_KMEMUSER)
1589
1590 #define NUM_X86_FEATURES 112
1591 extern uchar_t x86_featureset[];
1592
1593 extern void free_x86_featureset(void *featureset);
1594 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
1595 extern void add_x86_feature(void *featureset, uint_t feature);
1596 extern void remove_x86_feature(void *featureset, uint_t feature);
1597 extern boolean_t compare_x86_featureset(void *setA, void *setB);
1598 extern void print_x86_featureset(void *featureset);
1599
1600
1601 extern uint_t x86_type;
1602 extern uint_t x86_vendor;
1603 extern uint_t x86_clflush_size;
1604
1605 extern uint_t pentiumpro_bug4046376;
1606
1607 /*
1608 * These functions are all used to perform various side-channel mitigations.
1609 * Please see uts/i86pc/os/cpuid.c for more information.
1610 */
1611 extern void (*spec_uarch_flush)(void);
1612 extern void x86_rsb_stuff(void);
1613 extern void x86_rsb_stuff_vmexit(void);
1614 extern void x86_md_clear(void);
1615
1616 #endif
1617
1618 #if defined(_KERNEL)
1619
1620 /*
1621 * This structure is used to pass arguments and get return values back
1622 * from the CPUID instruction in __cpuid_insn() routine.
1623 */
1624 struct cpuid_regs {
1625 uint32_t cp_eax;
1626 uint32_t cp_ebx;
1627 uint32_t cp_ecx;
1628 uint32_t cp_edx;
1629 };
1630
1631 extern int x86_use_pcid;
1632 extern int x86_use_invpcid;
1633
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