1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright 2020 Joyent, Inc.
31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34 * Copyright 2018 Nexenta Systems, Inc.
35 * Copyright 2024 Oxide Computer Company
36 * Copyright 2024 MNX Cloud, Inc.
37 */
38
39 #ifndef _SYS_X86_ARCHEXT_H
40 #define _SYS_X86_ARCHEXT_H
41
42 #if !defined(_ASM)
43 #include <sys/bitext.h>
44 #include <sys/regset.h>
45 #include <sys/processor.h>
46 #include <vm/seg_enum.h>
47 #include <vm/page.h>
48 #endif /* _ASM */
49
50 #ifdef __cplusplus
51 extern "C" {
52 #endif
53
54 /*
55 * cpuid instruction feature flags in %edx (standard function 1)
56 */
57
58 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
59 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
60 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
61 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
62 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
63 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
64 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
65 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
66 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
67 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
68 /* 0x400 - reserved */
69 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
70 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
71 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
72 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
73 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
74 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
75 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
76 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
77 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
78 /* 0x100000 - reserved */
79 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
80 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
81 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
82 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
83 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
84 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
85 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
86 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
87 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
88 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
89 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
90
91 /*
92 * cpuid instruction feature flags in %ecx (standard function 1)
93 */
94
95 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
96 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
97 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
98 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
99 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
100 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
101 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
102 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
103 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
104 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
105 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
106 /* 0x00000800 - reserved */
107 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
108 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
109 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
110 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */
111 /* 0x00010000 - reserved */
112 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
113 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
114 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
115 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
116 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
117 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
118 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
119 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */
120 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
121 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
122 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
123 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
124 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
125 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
126 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
127
128 /*
129 * cpuid instruction feature flags in %edx (extended function 0x80000001)
130 */
131
132 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
133 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
134 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
135 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
136 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
137 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
138 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
139 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
140 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
141 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
142 /* 0x00000400 - sysc on K6m6 */
143 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
144 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
145 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
146 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
147 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
148 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
149 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
150 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
151 /* 0x00040000 - reserved */
152 /* 0x00080000 - reserved */
153 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
154 /* 0x00200000 - reserved */
155 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
156 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
157 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
158 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
159 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
160 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
161 /* 0x10000000 - reserved */
162 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
163 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
164 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
165
166 /*
167 * AMD extended function 0x80000001 %ecx
168 */
169
170 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
171 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
172 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
173 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
174 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
175 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
176 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
177 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
178 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
179 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
180 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
181 #define CPUID_AMD_ECX_XOP 0x00000800 /* AMD: Extended Operation */
182 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
183 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
184 /* 0x00004000 - reserved */
185 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */
186 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
187 /* 0x00020000 - reserved */
188 /* 0x00040000 - reserved */
189 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */
190 /* 0x00100000 - reserved */
191 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */
192 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
193 #define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */
194 #define CUPID_AMD_ECX_PCENB 0x01000000 /* AMD: NB ext perf counter */
195 /* 0x02000000 - reserved */
196 #define CPUID_AMD_ECX_DBKP 0x40000000 /* AMD: Data breakpoint */
197 #define CPUID_AMD_ECX_PERFTSC 0x08000000 /* AMD: TSC Perf Counter */
198 #define CPUID_AMD_ECX_PERFL3 0x10000000 /* AMD: L3 Perf Counter */
199 #define CPUID_AMD_ECX_MONITORX 0x20000000 /* AMD: clzero */
200 /* 0x40000000 - reserved */
201 /* 0x80000000 - reserved */
202
203 /*
204 * AMD uses %ebx for some of their features (extended function 0x80000008).
205 */
206 #define CPUID_AMD_EBX_CLZERO 0x000000001 /* AMD: CLZERO instr */
207 #define CPUID_AMD_EBX_IRCMSR 0x000000002 /* AMD: Ret. instrs MSR */
208 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */
209 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */
210 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */
211 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */
212 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */
213 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */
214 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */
215 #define CPUID_AMD_EBX_PPIN 0x000800000 /* AMD: PPIN Support */
216 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */
217 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */
218 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */
219
220 /*
221 * AMD SVM features (extended function 0x8000000A).
222 */
223 #define CPUID_AMD_EDX_NESTED_PAGING (1 << 0) /* AMD: Nested paging */
224 #define CPUID_AMD_EDX_LBR_VIRT (1 << 1) /* AMD: LBR virt. */
225 #define CPUID_AMD_EDX_SVML (1 << 2) /* AMD: SVM lock */
226 #define CPUID_AMD_EDX_NRIPS (1 << 3) /* AMD: NRIP save */
227 #define CPUID_AMD_EDX_TSC_RATE_MSR (1 << 4) /* AMD: TSC ratio ctrl */
228 #define CPUID_AMD_EDX_VMCB_CLEAN (1 << 5) /* AMD: VMCB clean bits */
229 #define CPUID_AMD_EDX_FLUSH_ASID (1 << 6) /* AMD: flush by ASID */
230 #define CPUID_AMD_EDX_DECODE_ASSISTS (1 << 7) /* AMD: decode assists */
231 #define CPUID_AMD_EDX_PAUSE_INCPT (1 << 8) /* AMD: pause intercept */
232 #define CPUID_AMD_EDX_PAUSE_TRSH (1 << 9) /* AMD: pause threshold */
233 #define CPUID_AMD_EDX_AVIC (1 << 10) /* AMD: AVIC */
234
235 /*
236 * AMD Encrypted Memory Capabilities -- 0x8000_001F
237 *
238 * %ecx is the number of encrypted guests.
239 * %edx is the minimum ASID value for SEV enabled, SEV-ES disabled guests
240 */
241 #define CPUID_AMD_8X1F_EAX_NVS (1 << 29) /* VIRT_RMPUPDATE MSR */
242 #define CPUID_AMD_8X1F_EAX_SCP (1 << 28) /* SVSM Comm Page MSR */
243 #define CPUID_AMD_8X1F_EAX_SMT_PROT (1 << 25) /* SMT Protection */
244 #define CPUID_AMD_8X1F_EAX_VMSAR_PROT (1 << 24) /* VMSA Reg Protection */
245 #define CPUID_AMD_8X1F_EAX_IBSVGC (1 << 19) /* IBS Virt. for SEV-ES */
246 #define CPUID_AMD_8X1F_EAX_VIRT_TOM (1 << 18) /* Virt TOM MSR */
247 #define CPUID_AMD_8X1F_EAX_VMGEXIT (1 << 17) /* VMGEXIT Parameter */
248 #define CPUID_AMD_8X1F_EAX_VTE (1 << 16) /* Virt Transparent Enc. */
249 #define CPUID_AMD_8X1F_EAX_NO_IBS (1 << 15) /* No IBS by host */
250 #define CPUID_AMD_8X1F_EAX_DBGSWP (1 << 14) /* Debug state for SEV-ES */
251 #define CPUID_AMD_8X1F_EAX_ALT_INJ (1 << 13) /* Alternate Injection */
252 #define CPUID_AMD_8X1F_EAX_RES_INJ (1 << 12) /* Restricted Injection */
253 #define CPUID_AMD_8X1F_EAX_64B_HOST (1 << 11) /* SEV requires amd64 */
254 #define CPUID_AMD_8X1F_EAX_HWECC (1 << 10) /* HW cache coherency req */
255 #define CPUID_AMD_8X1F_EAX_TSC_AUX (1 << 9) /* TSC AUX Virtualization */
256 #define CPUID_AMD_8X1F_EAX_SEC_TSC (1 << 8) /* Secure TSC */
257 #define CPUID_AMD_8X1F_EAX_VSSS (1 << 7) /* VMPL Super. Shadow Stack */
258 #define CPUID_AMD_8X1F_EAX_RMPQUERY (1 << 6) /* RMPQUERY Instr */
259 #define CPUID_AMD_8X1F_EAX_VMPL (1 << 5) /* VM Permission Levels */
260 #define CPUID_AMD_8X1F_EAX_SEV_SNP (1 << 4) /* SEV Secure Nested Paging */
261 #define CPUID_AMD_8X1F_EAX_SEV_ES (1 << 3) /* SEV Encrypted State */
262 #define CPUID_AMD_8X1F_EAX_PAGE_FLUSH (1 << 2) /* Page Flush MSR */
263 #define CPUID_AMD_8X1F_EAX_SEV (1 << 1) /* Secure Encrypted Virt. */
264 #define CPUID_AMD_8X1F_EAX_SME (1 << 0) /* Secure Memory Encrypt. */
265
266 #define CPUID_AMD_8X1F_EBX_NVMPL(r) bitx32(r, 15, 12) /* num VM Perm lvl */
267 #define CPUID_AMD_8X1F_EBX_PAR(r) bitx32(r, 11, 6) /* paddr bit rem */
268 #define CPUID_AMD_8X1F_EBX_CBIT(r) bitx32(r, 5, 0) /* C-bit loc in PTE */
269
270 /*
271 * AMD Platform QoS Extended Features -- 0x8000_0020
272 */
273 #define CPUID_AMD_8X20_EBX_L3RR (1 << 4) /* L3 Range Reservations */
274
275 /*
276 * AMD Extended Feature 2 -- 0x8000_0021
277 */
278 #define CPUID_AMD_8X21_EAX_CPUID_DIS (1 << 17) /* CPUID dis for CPL > 0 */
279 #define CPUID_AMD_8X21_EAX_PREFETCH (1 << 13) /* Prefetch control MSR */
280 #define CPUID_AMD_8X21_EAX_NO_SMMCTL (1 << 9) /* No SMM_CTL MSR */
281 #define CPUID_AMD_8X21_EAX_AIBRS (1 << 8) /* Automatic IBRS */
282 #define CPUID_AMD_8X21_EAX_UAI (1 << 7) /* Upper Address Ignore */
283 #define CPUID_AMD_8X21_EAX_SMM_PGLK (1 << 3) /* SMM Page config lock */
284 #define CPUID_AMD_8X21_EAX_LFENCE_SER (1 << 2) /* LFENCE is dispatch serial */
285 #define CPUID_AMD_8X21_EAX_NO_NDBP (1 << 0) /* No nested data #BP */
286
287 #define CPUID_AMD_8X21_EBX_MPS(r) bitx32(11, 0) /* MCU Patch size x 16B */
288
289 /*
290 * AMD Extended Performance Monitoring and Debug -- 0x8000_0022
291 */
292 #define CPUID_AMD_8X22_LBR_FRZ (1 << 2) /* Freeze PMC / LBR on ovflw */
293 #define CPUID_AMD_8X22_LBR_STK (1 << 1) /* Last Branch Record Stack */
294 #define CPUID_AMD_8X22_EAX_PMV2 (1 << 0) /* Perfmon v2 */
295
296 #define CPUID_AMD_8X22_EBX_NPMC_NB(r) bitx32(r, 15, 10) /* # NB PMC */
297 #define CPUID_AMD_8X22_EBX_LBR_SZ(r) bitx32(r, 9, 4) /* # LBR Stack ents. */
298 #define CPUID_AMD_8X22_EBX_NPMC_CORE(r) bitx32(r, 3, 0) /* # core PMC */
299
300 /*
301 * AMD Secure Multi-key Encryption -- 0x8000_00023
302 */
303 #define CPUID_AMD_8X23_EAX_MEMHMK (1 << 0) /* Secure Host Multi-Key Mem */
304
305 #define CPUID_AMD_8X23_EBX_MAX_HMK(r) bitx32(r, 15, 0) /* Max HMK IDs */
306
307 /*
308 * AMD Extended CPU Topology -- 0x8000_0026
309 *
310 * This is AMD's version of extended CPU topology. The topology level is placed
311 * in %ecx and also contains information about the heterogeneity of the CPUs at
312 * the core level. Note, this is similar to, but not the same as Intel's 0x1f.
313 *
314 * The %eax values other than the APIC shift are only available when the type is
315 * a core. The %ebx values other than the number of logical processors are only
316 * available when the type is a core. The core and native model ID values are
317 * processor specific.
318 *
319 * %edx is the entire extended APIC ID of the logical processor we're on.
320 */
321 #define CPUID_AMD_8X26_EAX_ASYM_TOPO(r) bitx32(r, 31, 31)
322 #define CPUID_AMD_8x26_EAX_HET_CORES(r) bitx32(r, 30, 30)
323 #define CPUID_AMD_8X26_EAX_EFF_AVAIL(r) bitx32(r, 29, 29)
324 #define CPUID_AMD_8X26_EAX_APIC_SHIFT(r) bitx32(r, 4, 0)
325
326 #define CPUID_AMD_8X26_EBX_CORE_TYPE(r) bitx32(r, 31, 28)
327 #define CPUID_AMD_8X26_EBX_MODEL_ID(r) bitx32(r, 27, 24)
328 #define CPUID_AMD_8X26_EBX_PWR_EFF(r) bitx32(r, 23, 16)
329 #define CPUID_AMD_8X26_EBX_NLOG_PROC(r) bitx32(r, 15, 0)
330
331 #define CPUID_AMD_8X26_ECX_TYPE(r) bitx32(r, 15, 8)
332 #define CPUID_AMD_8X26_TYPE_DONE 0 /* Technically reserved */
333 #define CUPID_AMD_8X26_TYPE_CORE 1
334 #define CUPID_AMD_8X26_TYPE_COMPLEX 2
335 #define CUPID_AMD_8X26_TYPE_DIE 3
336 #define CUPID_AMD_8X26_TYPE_SOCK 4
337 #define CPUID_AMD_8X26_ECX_INPUT(r) bitx32(r, 7, 0)
338
339 /*
340 * Intel now seems to have claimed part of the "extended" function
341 * space that we previously for non-Intel implementors to use.
342 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
343 * is available in long mode i.e. what AMD indicate using bit 0.
344 * On the other hand, everything else is labelled as reserved.
345 */
346 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
347
348 /*
349 * Intel uses cpuid leaf 6 to cover various thermal and power control
350 * operations.
351 */
352 #define CPUID_INTC_EAX_DTS 0x00000001 /* Digital Thermal Sensor */
353 #define CPUID_INTC_EAX_TURBO 0x00000002 /* Turboboost */
354 #define CPUID_INTC_EAX_ARAT 0x00000004 /* APIC-Timer-Always-Running */
355 /* bit 3 is reserved */
356 #define CPUID_INTC_EAX_PLN 0x00000010 /* Power limit notification */
357 #define CPUID_INTC_EAX_ECMD 0x00000020 /* Clock mod. duty cycle */
358 #define CPUID_INTC_EAX_PTM 0x00000040 /* Package thermal management */
359 #define CPUID_INTC_EAX_HWP 0x00000080 /* HWP base registers */
360 #define CPUID_INTC_EAX_HWP_NOT 0x00000100 /* HWP Notification */
361 #define CPUID_INTC_EAX_HWP_ACT 0x00000200 /* HWP Activity Window */
362 #define CPUID_INTC_EAX_HWP_EPR 0x00000400 /* HWP Energy Perf. Pref. */
363 #define CPUID_INTC_EAX_HWP_PLR 0x00000800 /* HWP Package Level Request */
364 /* bit 12 is reserved */
365 #define CPUID_INTC_EAX_HDC 0x00002000 /* HDC */
366 #define CPUID_INTC_EAX_TURBO3 0x00004000 /* Turbo Boost Max Tech 3.0 */
367 #define CPUID_INTC_EAX_HWP_CAP 0x00008000 /* HWP Capabilities */
368 #define CPUID_INTC_EAX_HWP_PECI 0x00010000 /* HWP PECI override */
369 #define CPUID_INTC_EAX_HWP_FLEX 0x00020000 /* Flexible HWP */
370 #define CPUID_INTC_EAX_HWP_FAST 0x00040000 /* Fast IA32_HWP_REQUEST */
371 /* bit 19 is reserved */
372 #define CPUID_INTC_EAX_HWP_IDLE 0x00100000 /* Ignore Idle Logical HWP */
373
374 #define CPUID_INTC_EBX_DTS_NTRESH(x) ((x) & 0xf)
375
376 #define CPUID_INTC_ECX_MAPERF 0x00000001 /* IA32_MPERF / IA32_APERF */
377 /* bits 1-2 are reserved */
378 #define CPUID_INTC_ECX_PERFBIAS 0x00000008 /* IA32_ENERGY_PERF_BIAS */
379
380 /*
381 * Intel also uses cpuid leaf 7 to have additional instructions and features.
382 * Like some other leaves, but unlike the current ones we care about, it
383 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
384 * with the potential use of additional sub-leaves in the future, we now
385 * specifically label the EBX features with their leaf and sub-leaf.
386 */
387 #define CPUID_INTC_EBX_7_0_FSGSBASE 0x00000001 /* FSGSBASE */
388 #define CPUID_INTC_EBX_7_0_TSC_ADJ 0x00000002 /* TSC adjust MSR */
389 #define CPUID_INTC_EBX_7_0_SGX 0x00000004 /* SGX */
390 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
391 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */
392 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
393 #define CPUID_INTC_EBX_7_0_FDP_EXCPN 0x00000040 /* FDP on exception */
394 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
395 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */
396 #define CPUID_INTC_EBX_7_0_ENH_REP_MOV 0x00000200 /* Enhanced REP MOVSB */
397 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */
398 #define CPUID_INTC_EBX_7_0_RTM 0x00000800 /* RTM instrs */
399 #define CPUID_INTC_EBX_7_0_PQM 0x00001000 /* QoS Monitoring */
400 #define CPUID_INTC_EBX_7_0_DEP_CSDS 0x00002000 /* Deprecates CS/DS */
401 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */
402 #define CPUID_INTC_EBX_7_0_PQE 0x00080000 /* QoS Enforcement */
403 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */
404 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */
405 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */
406 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */
407 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */
408 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */
409 /* Bit 22 is reserved */
410 #define CPUID_INTC_EBX_7_0_CLFLUSHOPT 0x00800000 /* CLFLUSOPT */
411 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */
412 #define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */
413 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */
414 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */
415 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */
416 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */
417 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */
418 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */
419
420 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
421 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
422 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
423 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
424 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
425
426 #define CPUID_INTC_ECX_7_0_PREFETCHWT1 0x00000001 /* PREFETCHWT1 */
427 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */
428 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */
429 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */
430 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */
431 #define CPUID_INTC_ECX_7_0_WAITPKG 0x00000020 /* WAITPKG */
432 #define CPUID_INTC_ECX_7_0_AVX512VBMI2 0x00000040 /* AVX512 VBMI2 */
433 #define CPUID_INTC_ECX_7_0_CET_SS 0x00000080 /* CET Shadow Stack */
434 #define CPUID_INTC_ECX_7_0_GFNI 0x00000100 /* GFNI */
435 #define CPUID_INTC_ECX_7_0_VAES 0x00000200 /* VAES */
436 #define CPUID_INTC_ECX_7_0_VPCLMULQDQ 0x00000400 /* VPCLMULQDQ */
437 #define CPUID_INTC_ECX_7_0_AVX512VNNI 0x00000800 /* AVX512 VNNI */
438 #define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000 /* AVX512 BITALG */
439 #define CPUID_INTC_ECX_7_0_TME_EN 0x00002000 /* Total Memory Encr. */
440 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */
441 /* bit 15 is reserved */
442 #define CPUID_INTC_ECX_7_0_LA57 0x00010000 /* 57-bit paging */
443 /* bits 17-21 are the value of MAWAU */
444 #define CPUID_INTC_ECX_7_0_RDPID 0x00400000 /* RPID, IA32_TSC_AUX */
445 #define CPUID_INTC_ECX_7_0_KLSUP 0x00800000 /* Key Locker */
446 /* bit 24 is reserved */
447 #define CPUID_INTC_ECX_7_0_CLDEMOTE 0x02000000 /* Cache line demote */
448 /* bit 26 is resrved */
449 #define CPUID_INTC_ECX_7_0_MOVDIRI 0x08000000 /* MOVDIRI insn */
450 #define CPUID_INTC_ECX_7_0_MOVDIR64B 0x10000000 /* MOVDIR64B insn */
451 #define CPUID_INTC_ECX_7_0_ENQCMD 0x20000000 /* Enqueue Stores */
452 #define CPUID_INTC_ECX_7_0_SGXLC 0x40000000 /* SGX Launch config */
453 #define CPUID_INTC_ECX_7_0_PKS 0x80000000 /* protection keys */
454
455 /*
456 * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and
457 * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still
458 * valid when AVX512 is not. However, the following flags all are only valid
459 * when AVX512 is present.
460 */
461 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \
462 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \
463 CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
464
465 /* bits 0-1 are reserved */
466 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */
467 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */
468 #define CPUID_INTC_EDX_7_0_FSREPMOV 0x00000010 /* fast short rep mov */
469 #define CPUID_INTC_EDX_7_0_UINTR 0x00000020 /* user interrupts */
470 /* bits 6-7 are reserved */
471 #define CPUID_INTC_EDX_7_0_AVX512VP2INT 0x00000100 /* VP2INTERSECT */
472 /* bit 9 is reserved */
473 #define CPUID_INTC_EDX_7_0_MD_CLEAR 0x00000400 /* MB VERW */
474 /* bits 11-13 are reserved */
475 #define CPUID_INTC_EDX_7_0_SERIALIZE 0x00004000 /* Serialize instr */
476 #define CPUID_INTC_EDX_7_0_HYBRID 0x00008000 /* Hybrid CPU */
477 #define CPUID_INTC_EDX_7_0_TSXLDTRK 0x00010000 /* TSX load track */
478 /* bit 17 is reserved */
479 #define CPUID_INTC_EDX_7_0_PCONFIG 0x00040000 /* PCONFIG */
480 /* bit 19 is reserved */
481 #define CPUID_INTC_EDX_7_0_CET_IBT 0x00100000 /* CET ind. branch */
482 /* bit 21 is reserved */
483 #define CPUID_INTC_EDX_7_0_AMX_BF16 0x00400000 /* Tile F16 */
484 #define CPUID_INTC_EDX_7_0_AVX512FP16 0x00800000 /* AVX512 FP16 */
485 #define CPUID_INTC_EDX_7_0_AMX_TILE 0x01000000 /* Tile arch */
486 #define CPUID_INTC_EDX_7_0_AMX_INT8 0x02000000 /* Tile INT8 */
487 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */
488 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */
489 #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */
490 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */
491 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */
492
493 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \
494 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS | \
495 CPUID_INTC_EDX_7_0_AVX512VP2INT | CPUID_INTC_EDX_7_0_AVX512FP16)
496
497 /* bits 0-3 are reserved */
498 #define CPUID_INTC_EAX_7_1_AVXVNNI 0x00000010 /* VEX VNNI */
499 #define CPUID_INTC_EAX_7_1_AVX512_BF16 0x00000020 /* AVX512 BF16 */
500 /* bits 6-9 are reserved */
501 #define CPUID_INTC_EAX_7_1_ZL_MOVSB 0x00000400 /* zero-length MOVSB */
502 #define CPUID_INTC_EAX_7_1_FS_STOSB 0x00000800 /* fast short STOSB */
503 #define CPUID_INTC_EAX_7_1_FS_CMPSB 0x00001000 /* fast CMPSB, SCASB */
504 /* bits 13-21 are reserved */
505 #define CPUID_INTC_EAX_7_1_HRESET 0x00400000 /* History Reset leaf */
506 /* bits 23-25 are reserved */
507 #define CPUID_INTC_EAX_7_1_LAM 0x02000000 /* Linear addr mask */
508 /* bits 27-31 are reserved */
509
510 /*
511 * Intel also uses cpuid leaf 0xd to report additional instructions and features
512 * when the sub-leaf in %ecx == 1. We label these using the same convention as
513 * with leaf 7.
514 */
515 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */
516 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */
517 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */
518
519 #define REG_PAT 0x277
520 #define REG_TSC 0x10 /* timestamp counter */
521 #define REG_APIC_BASE_MSR 0x1b
522 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
523
524 #if !defined(__xpv)
525 /*
526 * AMD C1E
527 */
528 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
529 #define AMD_ACTONCMPHALT_SHIFT 27
530 #define AMD_ACTONCMPHALT_MASK 3
531 #endif
532
533 #define MSR_DEBUGCTL 0x1d9
534
535 #define DEBUGCTL_LBR 0x01
536 #define DEBUGCTL_BTF 0x02
537
538 /* Intel P6, AMD */
539 #define MSR_LBR_FROM 0x1db
540 #define MSR_LBR_TO 0x1dc
541 #define MSR_LEX_FROM 0x1dd
542 #define MSR_LEX_TO 0x1de
543
544 /* Intel P4 (pre-Prescott, non P4 M) */
545 #define MSR_P4_LBSTK_TOS 0x1da
546 #define MSR_P4_LBSTK_0 0x1db
547 #define MSR_P4_LBSTK_1 0x1dc
548 #define MSR_P4_LBSTK_2 0x1dd
549 #define MSR_P4_LBSTK_3 0x1de
550
551 /* Intel Pentium M */
552 #define MSR_P6M_LBSTK_TOS 0x1c9
553 #define MSR_P6M_LBSTK_0 0x040
554 #define MSR_P6M_LBSTK_1 0x041
555 #define MSR_P6M_LBSTK_2 0x042
556 #define MSR_P6M_LBSTK_3 0x043
557 #define MSR_P6M_LBSTK_4 0x044
558 #define MSR_P6M_LBSTK_5 0x045
559 #define MSR_P6M_LBSTK_6 0x046
560 #define MSR_P6M_LBSTK_7 0x047
561
562 /* Intel P4 (Prescott) */
563 #define MSR_PRP4_LBSTK_TOS 0x1da
564 #define MSR_PRP4_LBSTK_FROM_0 0x680
565 #define MSR_PRP4_LBSTK_FROM_1 0x681
566 #define MSR_PRP4_LBSTK_FROM_2 0x682
567 #define MSR_PRP4_LBSTK_FROM_3 0x683
568 #define MSR_PRP4_LBSTK_FROM_4 0x684
569 #define MSR_PRP4_LBSTK_FROM_5 0x685
570 #define MSR_PRP4_LBSTK_FROM_6 0x686
571 #define MSR_PRP4_LBSTK_FROM_7 0x687
572 #define MSR_PRP4_LBSTK_FROM_8 0x688
573 #define MSR_PRP4_LBSTK_FROM_9 0x689
574 #define MSR_PRP4_LBSTK_FROM_10 0x68a
575 #define MSR_PRP4_LBSTK_FROM_11 0x68b
576 #define MSR_PRP4_LBSTK_FROM_12 0x68c
577 #define MSR_PRP4_LBSTK_FROM_13 0x68d
578 #define MSR_PRP4_LBSTK_FROM_14 0x68e
579 #define MSR_PRP4_LBSTK_FROM_15 0x68f
580 #define MSR_PRP4_LBSTK_TO_0 0x6c0
581 #define MSR_PRP4_LBSTK_TO_1 0x6c1
582 #define MSR_PRP4_LBSTK_TO_2 0x6c2
583 #define MSR_PRP4_LBSTK_TO_3 0x6c3
584 #define MSR_PRP4_LBSTK_TO_4 0x6c4
585 #define MSR_PRP4_LBSTK_TO_5 0x6c5
586 #define MSR_PRP4_LBSTK_TO_6 0x6c6
587 #define MSR_PRP4_LBSTK_TO_7 0x6c7
588 #define MSR_PRP4_LBSTK_TO_8 0x6c8
589 #define MSR_PRP4_LBSTK_TO_9 0x6c9
590 #define MSR_PRP4_LBSTK_TO_10 0x6ca
591 #define MSR_PRP4_LBSTK_TO_11 0x6cb
592 #define MSR_PRP4_LBSTK_TO_12 0x6cc
593 #define MSR_PRP4_LBSTK_TO_13 0x6cd
594 #define MSR_PRP4_LBSTK_TO_14 0x6ce
595 #define MSR_PRP4_LBSTK_TO_15 0x6cf
596
597 /*
598 * PPIN definitions for Intel and AMD. Unfortunately, Intel and AMD use
599 * different MSRS for this and different MSRS to control whether or not it
600 * should be readable.
601 */
602 #define MSR_PPIN_CTL_INTC 0x04e
603 #define MSR_PPIN_INTC 0x04f
604 #define MSR_PLATFORM_INFO 0x0ce
605 #define MSR_PLATFORM_INFO_PPIN (1 << 23)
606
607 #define MSR_PPIN_CTL_AMD 0xC00102F0
608 #define MSR_PPIN_AMD 0xC00102F1
609
610 /*
611 * These values are currently the same between Intel and AMD.
612 */
613 #define MSR_PPIN_CTL_MASK 0x03
614 #define MSR_PPIN_CTL_DISABLED 0x00
615 #define MSR_PPIN_CTL_LOCKED 0x01
616 #define MSR_PPIN_CTL_ENABLED 0x02
617
618 /*
619 * Intel IA32_ARCH_CAPABILITIES MSR.
620 */
621 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
622 #define IA32_ARCH_CAP_RDCL_NO (1UL << 0)
623 #define IA32_ARCH_CAP_IBRS_ALL (1UL << 1)
624 #define IA32_ARCH_CAP_RSBA (1UL << 2)
625 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY (1UL << 3)
626 #define IA32_ARCH_CAP_SSB_NO (1UL << 4)
627 #define IA32_ARCH_CAP_MDS_NO (1UL << 5)
628 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO (1UL << 6)
629 #define IA32_ARCH_CAP_TSX_CTRL (1UL << 7)
630 #define IA32_ARCH_CAP_TAA_NO (1UL << 8)
631 #define IA32_ARCH_CAP_RESERVED_1 (1UL << 9)
632 #define IA32_ARCH_CAP_MCU_CONTROL (1UL << 10)
633 #define IA32_ARCH_CAP_ENERGY_FILTERING_CTL (1UL << 11)
634 #define IA32_ARCH_CAP_DOITM (1UL << 12)
635 #define IA32_ARCH_CAP_SBDR_SSDP_NO (1UL << 13)
636 #define IA32_ARCH_CAP_FBSDP_NO (1UL << 14)
637 #define IA32_ARCH_CAP_PSDP_NO (1UL << 15)
638 #define IA32_ARCH_CAP_RESERVED_2 (1UL << 16)
639 #define IA32_ARCH_CAP_FB_CLEAR (1UL << 17)
640 #define IA32_ARCH_CAP_FB_CLEAR_CTRL (1UL << 18)
641 #define IA32_ARCH_CAP_RRSBA (1UL << 19)
642 #define IA32_ARCH_CAP_BHI_NO (1UL << 20)
643 #define IA32_ARCH_CAP_XAPIC_DISABLE_STATUS (1UL << 21)
644 #define IA32_ARCH_CAP_RESERVED_3 (1UL << 22)
645 #define IA32_ARCH_CAP_OVERCLOCKING_STATUS (1UL << 23)
646 #define IA32_ARCH_CAP_PBRSB_NO (1UL << 24)
647 #define IA32_ARCH_CAP_GDS_CTRL (1UL << 25)
648 #define IA32_ARCH_CAP_GDS_NO (1UL << 26)
649 #define IA32_ARCH_CAP_RFDS_NO (1UL << 27)
650 #define IA32_ARCH_CAP_RFDS_CLEAR (1UL << 28)
651
652 /*
653 * Intel Speculation related MSRs
654 */
655 #define MSR_IA32_SPEC_CTRL 0x48
656 #define IA32_SPEC_CTRL_IBRS (1UL << 0)
657 #define IA32_SPEC_CTRL_STIBP (1UL << 1)
658 #define IA32_SPEC_CTRL_SSBD (1UL << 2)
659 #define IA32_SPEC_CTRL_IPRED_DIS_U (1UL << 3)
660 #define IA32_SPEC_CTRL_IPRED_DIS_S (1UL << 4)
661 #define IA32_SPEC_CTRL_RRSBA_DIS_U (1UL << 5)
662 #define IA32_SPEC_CTRL_RRSBA_DIS_S (1UL << 6)
663 #define IA32_SPEC_CTRL_PSFD (1UL << 7)
664 #define IA32_SPEC_CTRL_DDPD_U (1UL << 8)
665 #define IA32_SPEC_CTRL_BHI_DIS_S (1UL << 10)
666
667 #define MSR_IA32_PRED_CMD 0x49
668 #define IA32_PRED_CMD_IBPB 0x01
669
670 #define MSR_IA32_FLUSH_CMD 0x10b
671 #define IA32_FLUSH_CMD_L1D 0x01
672
673 /*
674 * Intel VMX related MSRs
675 */
676 #define MSR_IA32_FEAT_CTRL 0x03a
677 #define IA32_FEAT_CTRL_LOCK 0x1
678 #define IA32_FEAT_CTRL_SMX_EN 0x2
679 #define IA32_FEAT_CTRL_VMX_EN 0x4
680
681 #define MSR_IA32_VMX_BASIC 0x480
682 #define IA32_VMX_BASIC_INS_OUTS (1UL << 54)
683 #define IA32_VMX_BASIC_TRUE_CTRLS (1UL << 55)
684
685 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482
686 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e
687 #define IA32_VMX_PROCBASED_2ND_CTLS (1UL << 31)
688
689 #define MSR_IA32_VMX_PROCBASED2_CTLS 0x48b
690 #define IA32_VMX_PROCBASED2_EPT (1UL << 1)
691 #define IA32_VMX_PROCBASED2_VPID (1UL << 5)
692
693 #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c
694 #define IA32_VMX_EPT_VPID_EXEC_ONLY (1UL << 0)
695 #define IA32_VMX_EPT_VPID_PWL4 (1UL << 6)
696 #define IA32_VMX_EPT_VPID_TYPE_UC (1UL << 8)
697 #define IA32_VMX_EPT_VPID_TYPE_WB (1UL << 14)
698 #define IA32_VMX_EPT_VPID_MAP_2M (1UL << 16)
699 #define IA32_VMX_EPT_VPID_MAP_1G (1UL << 17)
700 #define IA32_VMX_EPT_VPID_HW_AD (1UL << 21)
701 #define IA32_VMX_EPT_VPID_INVEPT (1UL << 20)
702 #define IA32_VMX_EPT_VPID_INVEPT_SINGLE (1UL << 25)
703 #define IA32_VMX_EPT_VPID_INVEPT_ALL (1UL << 26)
704 #define IA32_VMX_EPT_VPID_INVVPID (1UL << 32)
705 #define IA32_VMX_EPT_VPID_INVVPID_ADDR (1UL << 40)
706 #define IA32_VMX_EPT_VPID_INVVPID_SINGLE (1UL << 41)
707 #define IA32_VMX_EPT_VPID_INVVPID_ALL (1UL << 42)
708 #define IA32_VMX_EPT_VPID_INVVPID_RETAIN (1UL << 43)
709
710 /*
711 * Intel TSX Control MSRs
712 */
713 #define MSR_IA32_TSX_CTRL 0x122
714 #define IA32_TSX_CTRL_RTM_DISABLE 0x01
715 #define IA32_TSX_CTRL_CPUID_CLEAR 0x02
716
717 /*
718 * Intel Thermal MSRs
719 */
720 #define MSR_IA32_THERM_INTERRUPT 0x19b
721 #define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001
722 #define IA32_THERM_INTERRUPT_LOW_IE 0x00000002
723 #define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004
724 #define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008
725 #define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010
726 #define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f)
727 #define IA32_THERM_INTTERUPT_TR1_IE 0x00008000
728 #define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f)
729 #define IA32_THERM_INTERRUPT_TR2_IE 0x00800000
730 #define IA32_THERM_INTERRUPT_PL_NE 0x01000000
731
732 #define MSR_IA32_THERM_STATUS 0x19c
733 #define IA32_THERM_STATUS_STATUS 0x00000001
734 #define IA32_THERM_STATUS_STATUS_LOG 0x00000002
735 #define IA32_THERM_STATUS_PROCHOT 0x00000004
736 #define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008
737 #define IA32_THERM_STATUS_CRIT_STATUS 0x00000010
738 #define IA32_THERM_STATUS_CRIT_LOG 0x00000020
739 #define IA32_THERM_STATUS_TR1_STATUS 0x00000040
740 #define IA32_THERM_STATUS_TR1_LOG 0x00000080
741 #define IA32_THERM_STATUS_TR2_STATUS 0x00000100
742 #define IA32_THERM_STATUS_TR2_LOG 0x00000200
743 #define IA32_THERM_STATUS_POWER_LIMIT_STATUS 0x00000400
744 #define IA32_THERM_STATUS_POWER_LIMIT_LOG 0x00000800
745 #define IA32_THERM_STATUS_CURRENT_STATUS 0x00001000
746 #define IA32_THERM_STATUS_CURRENT_LOG 0x00002000
747 #define IA32_THERM_STATUS_CROSS_DOMAIN_STATUS 0x00004000
748 #define IA32_THERM_STATUS_CROSS_DOMAIN_LOG 0x00008000
749 #define IA32_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f)
750 #define IA32_THERM_STATUS_RESOLUTION(x) (((x) >> 27) & 0x0f)
751 #define IA32_THERM_STATUS_READ_VALID 0x80000000
752
753 #define MSR_TEMPERATURE_TARGET 0x1a2
754 #define MSR_TEMPERATURE_TARGET_TARGET(x) (((x) >> 16) & 0xff)
755 /*
756 * Not all models support the offset. Refer to the Intel SDM Volume 4 for a list
757 * of which models have support for which bits.
758 */
759 #define MSR_TEMPERATURE_TARGET_OFFSET(x) (((x) >> 24) & 0x0f)
760
761 #define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1
762 #define IA32_PKG_THERM_STATUS_STATUS 0x00000001
763 #define IA32_PKG_THERM_STATUS_STATUS_LOG 0x00000002
764 #define IA32_PKG_THERM_STATUS_PROCHOT 0x00000004
765 #define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008
766 #define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010
767 #define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020
768 #define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040
769 #define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080
770 #define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100
771 #define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200
772 #define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f)
773
774 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2
775 #define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001
776 #define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002
777 #define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004
778 #define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010
779 #define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f)
780 #define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000
781 #define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f)
782 #define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000
783 #define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000
784
785 /*
786 * AMD TOM and TOM2 MSRs. These control the split between DRAM and MMIO below
787 * and above 4 GiB respectively. These have existed since family 0xf.
788 */
789 #define MSR_AMD_TOM 0xc001001a
790 #define MSR_AMD_TOM_MASK(x) ((x) & 0xffffff800000)
791 #define MSR_AMD_TOM2 0xc001001d
792 #define MSR_AMD_TOM2_MASK(x) ((x) & 0xffffff800000)
793
794
795 #define MCI_CTL_VALUE 0xffffffff
796
797 #define MTRR_TYPE_UC 0
798 #define MTRR_TYPE_WC 1
799 #define MTRR_TYPE_WT 4
800 #define MTRR_TYPE_WP 5
801 #define MTRR_TYPE_WB 6
802 #define MTRR_TYPE_UC_ 7
803
804 /*
805 * For Solaris we set up the page attritubute table in the following way:
806 * PAT0 Write-Back
807 * PAT1 Write-Through
808 * PAT2 Unchacheable-
809 * PAT3 Uncacheable
810 * PAT4 Write-Back
811 * PAT5 Write-Through
812 * PAT6 Write-Combine
813 * PAT7 Uncacheable
814 * The only difference from h/w default is entry 6.
815 */
816 #define PAT_DEFAULT_ATTRIBUTE \
817 ((uint64_t)MTRR_TYPE_WB | \
818 ((uint64_t)MTRR_TYPE_WT << 8) | \
819 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
820 ((uint64_t)MTRR_TYPE_UC << 24) | \
821 ((uint64_t)MTRR_TYPE_WB << 32) | \
822 ((uint64_t)MTRR_TYPE_WT << 40) | \
823 ((uint64_t)MTRR_TYPE_WC << 48) | \
824 ((uint64_t)MTRR_TYPE_UC << 56))
825
826 #define X86FSET_LARGEPAGE 0
827 #define X86FSET_TSC 1
828 #define X86FSET_MSR 2
829 #define X86FSET_MTRR 3
830 #define X86FSET_PGE 4
831 #define X86FSET_DE 5
832 #define X86FSET_CMOV 6
833 #define X86FSET_MMX 7
834 #define X86FSET_MCA 8
835 #define X86FSET_PAE 9
836 #define X86FSET_CX8 10
837 #define X86FSET_PAT 11
838 #define X86FSET_SEP 12
839 #define X86FSET_SSE 13
840 #define X86FSET_SSE2 14
841 #define X86FSET_HTT 15
842 #define X86FSET_ASYSC 16
843 #define X86FSET_NX 17
844 #define X86FSET_SSE3 18
845 #define X86FSET_CX16 19
846 #define X86FSET_CMP 20
847 #define X86FSET_TSCP 21
848 #define X86FSET_MWAIT 22
849 #define X86FSET_SSE4A 23
850 #define X86FSET_CPUID 24
851 #define X86FSET_SSSE3 25
852 #define X86FSET_SSE4_1 26
853 #define X86FSET_SSE4_2 27
854 #define X86FSET_1GPG 28
855 #define X86FSET_CLFSH 29
856 #define X86FSET_64 30
857 #define X86FSET_AES 31
858 #define X86FSET_PCLMULQDQ 32
859 #define X86FSET_XSAVE 33
860 #define X86FSET_AVX 34
861 #define X86FSET_VMX 35
862 #define X86FSET_SVM 36
863 #define X86FSET_TOPOEXT 37
864 #define X86FSET_F16C 38
865 #define X86FSET_RDRAND 39
866 #define X86FSET_X2APIC 40
867 #define X86FSET_AVX2 41
868 #define X86FSET_BMI1 42
869 #define X86FSET_BMI2 43
870 #define X86FSET_FMA 44
871 #define X86FSET_SMEP 45
872 #define X86FSET_SMAP 46
873 #define X86FSET_ADX 47
874 #define X86FSET_RDSEED 48
875 #define X86FSET_MPX 49
876 #define X86FSET_AVX512F 50
877 #define X86FSET_AVX512DQ 51
878 #define X86FSET_AVX512PF 52
879 #define X86FSET_AVX512ER 53
880 #define X86FSET_AVX512CD 54
881 #define X86FSET_AVX512BW 55
882 #define X86FSET_AVX512VL 56
883 #define X86FSET_AVX512FMA 57
884 #define X86FSET_AVX512VBMI 58
885 #define X86FSET_AVX512VPOPCDQ 59
886 #define X86FSET_AVX512NNIW 60
887 #define X86FSET_AVX512FMAPS 61
888 #define X86FSET_XSAVEOPT 62
889 #define X86FSET_XSAVEC 63
890 #define X86FSET_XSAVES 64
891 #define X86FSET_SHA 65
892 #define X86FSET_UMIP 66
893 #define X86FSET_PKU 67
894 #define X86FSET_OSPKE 68
895 #define X86FSET_PCID 69
896 #define X86FSET_INVPCID 70
897 #define X86FSET_IBRS 71
898 #define X86FSET_IBPB 72
899 #define X86FSET_STIBP 73
900 #define X86FSET_SSBD 74
901 #define X86FSET_SSBD_VIRT 75
902 #define X86FSET_RDCL_NO 76
903 #define X86FSET_IBRS_ALL 77
904 #define X86FSET_RSBA 78
905 #define X86FSET_SSB_NO 79
906 #define X86FSET_STIBP_ALL 80
907 #define X86FSET_FLUSH_CMD 81
908 #define X86FSET_L1D_VM_NO 82
909 #define X86FSET_FSGSBASE 83
910 #define X86FSET_CLFLUSHOPT 84
911 #define X86FSET_CLWB 85
912 #define X86FSET_MONITORX 86
913 #define X86FSET_CLZERO 87
914 #define X86FSET_XOP 88
915 #define X86FSET_FMA4 89
916 #define X86FSET_TBM 90
917 #define X86FSET_AVX512VNNI 91
918 #define X86FSET_AMD_PCEC 92
919 #define X86FSET_MD_CLEAR 93
920 #define X86FSET_MDS_NO 94
921 #define X86FSET_CORE_THERMAL 95
922 #define X86FSET_PKG_THERMAL 96
923 #define X86FSET_TSX_CTRL 97
924 #define X86FSET_TAA_NO 98
925 #define X86FSET_PPIN 99
926 #define X86FSET_VAES 100
927 #define X86FSET_VPCLMULQDQ 101
928 #define X86FSET_LFENCE_SER 102
929 #define X86FSET_GFNI 103
930 #define X86FSET_AVX512_VP2INT 104
931 #define X86FSET_AVX512_BITALG 105
932 #define X86FSET_AVX512_VBMI2 106
933 #define X86FSET_AVX512_BF16 107
934 #define X86FSET_AUTO_IBRS 108
935 #define X86FSET_RFDS_NO 109
936 #define X86FSET_RFDS_CLEAR 110
937 #define X86FSET_PBRSB_NO 111
938
939 /*
940 * Intel Deep C-State invariant TSC in leaf 0x80000007.
941 */
942 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
943
944 /*
945 * Intel TSC deadline timer
946 */
947 #define CPUID_DEADLINE_TSC (1 << 24)
948
949 /*
950 * x86_type is a legacy concept; this is supplanted
951 * for most purposes by x86_featureset; modern CPUs
952 * should be X86_TYPE_OTHER
953 */
954 #define X86_TYPE_OTHER 0
955 #define X86_TYPE_486 1
956 #define X86_TYPE_P5 2
957 #define X86_TYPE_P6 3
958 #define X86_TYPE_CYRIX_486 4
959 #define X86_TYPE_CYRIX_6x86L 5
960 #define X86_TYPE_CYRIX_6x86 6
961 #define X86_TYPE_CYRIX_GXm 7
962 #define X86_TYPE_CYRIX_6x86MX 8
963 #define X86_TYPE_CYRIX_MediaGX 9
964 #define X86_TYPE_CYRIX_MII 10
965 #define X86_TYPE_VIA_CYRIX_III 11
966 #define X86_TYPE_P4 12
967
968 /*
969 * x86_vendor allows us to select between
970 * implementation features and helps guide
971 * the interpretation of the cpuid instruction.
972 */
973 #define X86_VENDOR_Intel 0
974 #define X86_VENDORSTR_Intel "GenuineIntel"
975
976 #define X86_VENDOR_IntelClone 1
977
978 #define X86_VENDOR_AMD 2
979 #define X86_VENDORSTR_AMD "AuthenticAMD"
980
981 #define X86_VENDOR_Cyrix 3
982 #define X86_VENDORSTR_CYRIX "CyrixInstead"
983
984 #define X86_VENDOR_UMC 4
985 #define X86_VENDORSTR_UMC "UMC UMC UMC "
986
987 #define X86_VENDOR_NexGen 5
988 #define X86_VENDORSTR_NexGen "NexGenDriven"
989
990 #define X86_VENDOR_Centaur 6
991 #define X86_VENDORSTR_Centaur "CentaurHauls"
992
993 #define X86_VENDOR_Rise 7
994 #define X86_VENDORSTR_Rise "RiseRiseRise"
995
996 #define X86_VENDOR_SiS 8
997 #define X86_VENDORSTR_SiS "SiS SiS SiS "
998
999 #define X86_VENDOR_TM 9
1000 #define X86_VENDORSTR_TM "GenuineTMx86"
1001
1002 #define X86_VENDOR_NSC 10
1003 #define X86_VENDORSTR_NSC "Geode by NSC"
1004
1005 #define X86_VENDOR_HYGON 11
1006 #define X86_VENDORSTR_HYGON "HygonGenuine"
1007
1008 /*
1009 * Vendor string max len + \0
1010 */
1011 #define X86_VENDOR_STRLEN 13
1012
1013 /*
1014 * For lookups and matching functions only; not an actual vendor.
1015 */
1016 #define _X86_VENDOR_MATCH_ALL 0xff
1017
1018 /*
1019 * See the big theory statement at the top of cpuid.c for information about how
1020 * processor families and microarchitecture families relate to cpuid families,
1021 * models, and steppings.
1022 */
1023
1024 #define _X86_CHIPREV_VENDOR_SHIFT 24
1025 #define _X86_CHIPREV_FAMILY_SHIFT 16
1026
1027 #define _X86_CHIPREV_VENDOR(x) \
1028 bitx32((uint32_t)(x), 31, _X86_CHIPREV_VENDOR_SHIFT)
1029
1030 #define _X86_CHIPREV_FAMILY(x) \
1031 bitx32((uint32_t)(x), 23, _X86_CHIPREV_FAMILY_SHIFT)
1032
1033 #define _X86_CHIPREV_REV(x) \
1034 bitx32((uint32_t)(x), 15, 0)
1035
1036 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
1037 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
1038 (uint32_t)(family) << _X86_CHIPREV_FAMILY_SHIFT | (uint32_t)(rev))
1039
1040 /*
1041 * The legacy families here are a little bit unfortunate. Part of this is that
1042 * the way AMD used the cpuid family/model/stepping changed somewhat over time,
1043 * but the more immediate reason it's this way is more that the way we use
1044 * chiprev/processor family changed with it. The ancient amd_opteron and mc-amd
1045 * drivers used the chiprevs that were based on cpuid family, mainly 0xf and
1046 * 0x10. amdzen_umc wants the processor family, in part because AMD's
1047 * overloading of the cpuid family has made it effectively useless for
1048 * discerning anything about the processor. That also tied into the way
1049 * amd_revmap was previously organised in cpuid_subr.c: up to family 0x14
1050 * everything was just "rev A", "rev B", etc.; afterward we started using the
1051 * new shorthand, again tied to how AMD was presenting this information.
1052 * Because there are other consumers of the processor family, it no longer made
1053 * sense for amdzen to derive the processor family from the cpuid family/model
1054 * given that we have this collection of definitions already and code in
1055 * cpuid_subr.c to make use of them. The result is this unified approach that
1056 * tries to keep old consumers happy while allowing new ones to get the degree
1057 * of detail they need and expect. That required bending things a bit to make
1058 * them fit, though critically as long as AMD keep on their current path and all
1059 * new consumers look like the ones we are adding these days, we will be able to
1060 * continue making new additions that will match all the recent ones and the way
1061 * AMD are currently using families and models. There is absolutely no reason
1062 * we couldn't go back and dig through all the legacy parts and break them down
1063 * the same way, then change the old MC and CPU drivers to match, but I didn't
1064 * feel like doing a lot of work for processors that it's unlikely anyone is
1065 * still using and even more unlikely anyone will introduce new code to support.
1066 * My compromise was to flesh things out starting where we already had more
1067 * detail even if nothing was consuming it programmatically: at 0x15. Before
1068 * that, processor family and cpuid family were effectively the same, because
1069 * that's what those old consumers expect.
1070 */
1071
1072 #ifndef _ASM
1073 typedef enum x86_processor_family {
1074 X86_PF_UNKNOWN,
1075 X86_PF_AMD_LEGACY_F = 0xf,
1076 X86_PF_AMD_LEGACY_10 = 0x10,
1077 X86_PF_AMD_LEGACY_11 = 0x11,
1078 X86_PF_AMD_LEGACY_12 = 0x12,
1079 X86_PF_AMD_LEGACY_14 = 0x14,
1080 X86_PF_AMD_OROCHI,
1081 X86_PF_AMD_TRINITY,
1082 X86_PF_AMD_KAVERI,
1083 X86_PF_AMD_CARRIZO,
1084 X86_PF_AMD_STONEY_RIDGE,
1085 X86_PF_AMD_KABINI,
1086 X86_PF_AMD_MULLINS,
1087 X86_PF_AMD_NAPLES,
1088 X86_PF_AMD_PINNACLE_RIDGE,
1089 X86_PF_AMD_RAVEN_RIDGE,
1090 X86_PF_AMD_PICASSO,
1091 X86_PF_AMD_DALI,
1092 X86_PF_AMD_ROME,
1093 X86_PF_AMD_RENOIR,
1094 X86_PF_AMD_MATISSE,
1095 X86_PF_AMD_VAN_GOGH,
1096 X86_PF_AMD_MENDOCINO,
1097 X86_PF_HYGON_DHYANA,
1098 X86_PF_AMD_MILAN,
1099 X86_PF_AMD_GENOA,
1100 X86_PF_AMD_VERMEER,
1101 X86_PF_AMD_REMBRANDT,
1102 X86_PF_AMD_CEZANNE,
1103 X86_PF_AMD_RAPHAEL,
1104 X86_PF_AMD_PHOENIX,
1105 X86_PF_AMD_BERGAMO,
1106
1107 X86_PF_ANY = 0xff
1108 } x86_processor_family_t;
1109
1110 #define _DECL_CHIPREV(_v, _f, _revn, _revb) \
1111 X86_CHIPREV_ ## _v ## _ ## _f ## _ ## _revn = \
1112 _X86_CHIPREV_MKREV(X86_VENDOR_ ## _v, X86_PF_ ## _v ## _ ## _f, _revb)
1113
1114 #define _X86_CHIPREV_REV_MATCH_ALL 0xffff
1115
1116 typedef enum x86_chiprev {
1117 X86_CHIPREV_UNKNOWN,
1118 _DECL_CHIPREV(AMD, LEGACY_F, REV_B, 0x0001),
1119 /*
1120 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
1121 * sufficiently different that we will distinguish them; in all other
1122 * case we will identify the major revision.
1123 */
1124 _DECL_CHIPREV(AMD, LEGACY_F, REV_C0, 0x0002),
1125 _DECL_CHIPREV(AMD, LEGACY_F, REV_CG, 0x0004),
1126 _DECL_CHIPREV(AMD, LEGACY_F, REV_D, 0x0008),
1127 _DECL_CHIPREV(AMD, LEGACY_F, REV_E, 0x0010),
1128 _DECL_CHIPREV(AMD, LEGACY_F, REV_F, 0x0020),
1129 _DECL_CHIPREV(AMD, LEGACY_F, REV_G, 0x0040),
1130 _DECL_CHIPREV(AMD, LEGACY_F, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1131
1132 _DECL_CHIPREV(AMD, LEGACY_10, UNKNOWN, 0x0001),
1133 _DECL_CHIPREV(AMD, LEGACY_10, REV_A, 0x0002),
1134 _DECL_CHIPREV(AMD, LEGACY_10, REV_B, 0x0004),
1135 _DECL_CHIPREV(AMD, LEGACY_10, REV_C2, 0x0008),
1136 _DECL_CHIPREV(AMD, LEGACY_10, REV_C3, 0x0010),
1137 _DECL_CHIPREV(AMD, LEGACY_10, REV_D0, 0x0020),
1138 _DECL_CHIPREV(AMD, LEGACY_10, REV_D1, 0x0040),
1139 _DECL_CHIPREV(AMD, LEGACY_10, REV_E, 0x0080),
1140 _DECL_CHIPREV(AMD, LEGACY_10, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1141
1142 _DECL_CHIPREV(AMD, LEGACY_11, UNKNOWN, 0x0001),
1143 _DECL_CHIPREV(AMD, LEGACY_11, REV_B, 0x0002),
1144 _DECL_CHIPREV(AMD, LEGACY_11, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1145
1146 _DECL_CHIPREV(AMD, LEGACY_12, UNKNOWN, 0x0001),
1147 _DECL_CHIPREV(AMD, LEGACY_12, REV_B, 0x0002),
1148 _DECL_CHIPREV(AMD, LEGACY_12, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1149
1150 _DECL_CHIPREV(AMD, LEGACY_14, UNKNOWN, 0x0001),
1151 _DECL_CHIPREV(AMD, LEGACY_14, REV_B, 0x0002),
1152 _DECL_CHIPREV(AMD, LEGACY_14, REV_C, 0x0004),
1153 _DECL_CHIPREV(AMD, LEGACY_14, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1154
1155 _DECL_CHIPREV(AMD, OROCHI, UNKNOWN, 0x0001),
1156 _DECL_CHIPREV(AMD, OROCHI, REV_B2, 0x0002),
1157 _DECL_CHIPREV(AMD, OROCHI, REV_C0, 0x0004),
1158 _DECL_CHIPREV(AMD, OROCHI, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1159
1160 _DECL_CHIPREV(AMD, TRINITY, UNKNOWN, 0x0001),
1161 _DECL_CHIPREV(AMD, TRINITY, REV_A1, 0x0002),
1162 _DECL_CHIPREV(AMD, TRINITY, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1163
1164 _DECL_CHIPREV(AMD, KAVERI, UNKNOWN, 0x0001),
1165 _DECL_CHIPREV(AMD, KAVERI, REV_A1, 0x0002),
1166 _DECL_CHIPREV(AMD, KAVERI, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1167
1168 _DECL_CHIPREV(AMD, CARRIZO, UNKNOWN, 0x0001),
1169 _DECL_CHIPREV(AMD, CARRIZO, REV_A0, 0x0002),
1170 _DECL_CHIPREV(AMD, CARRIZO, REV_A1, 0x0004),
1171 _DECL_CHIPREV(AMD, CARRIZO, REV_DDR4, 0x0008),
1172 _DECL_CHIPREV(AMD, CARRIZO, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1173
1174 _DECL_CHIPREV(AMD, STONEY_RIDGE, UNKNOWN, 0x0001),
1175 _DECL_CHIPREV(AMD, STONEY_RIDGE, REV_A0, 0x0002),
1176 _DECL_CHIPREV(AMD, STONEY_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1177
1178 _DECL_CHIPREV(AMD, KABINI, UNKNOWN, 0x0001),
1179 _DECL_CHIPREV(AMD, KABINI, A1, 0x0002),
1180 _DECL_CHIPREV(AMD, KABINI, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1181
1182 _DECL_CHIPREV(AMD, MULLINS, UNKNOWN, 0x0001),
1183 _DECL_CHIPREV(AMD, MULLINS, A1, 0x0002),
1184 _DECL_CHIPREV(AMD, MULLINS, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1185
1186 _DECL_CHIPREV(AMD, NAPLES, UNKNOWN, 0x0001),
1187 _DECL_CHIPREV(AMD, NAPLES, A0, 0x0002),
1188 _DECL_CHIPREV(AMD, NAPLES, B1, 0x0004),
1189 _DECL_CHIPREV(AMD, NAPLES, B2, 0x0008),
1190 _DECL_CHIPREV(AMD, NAPLES, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1191
1192 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, UNKNOWN, 0x0001),
1193 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, B2, 0x0002),
1194 _DECL_CHIPREV(AMD, PINNACLE_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1195
1196 _DECL_CHIPREV(AMD, RAVEN_RIDGE, UNKNOWN, 0x0001),
1197 _DECL_CHIPREV(AMD, RAVEN_RIDGE, B0, 0x0002),
1198 _DECL_CHIPREV(AMD, RAVEN_RIDGE, B1, 0x0004),
1199 _DECL_CHIPREV(AMD, RAVEN_RIDGE, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1200
1201 _DECL_CHIPREV(AMD, PICASSO, UNKNOWN, 0x0001),
1202 _DECL_CHIPREV(AMD, PICASSO, B1, 0x0002),
1203 _DECL_CHIPREV(AMD, PICASSO, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1204
1205 _DECL_CHIPREV(AMD, DALI, UNKNOWN, 0x0001),
1206 _DECL_CHIPREV(AMD, DALI, A1, 0x0002),
1207 _DECL_CHIPREV(AMD, DALI, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1208
1209 _DECL_CHIPREV(AMD, ROME, UNKNOWN, 0x0001),
1210 _DECL_CHIPREV(AMD, ROME, A0, 0x0002),
1211 _DECL_CHIPREV(AMD, ROME, B0, 0x0004),
1212 _DECL_CHIPREV(AMD, ROME, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1213
1214 _DECL_CHIPREV(AMD, RENOIR, UNKNOWN, 0x0001),
1215 _DECL_CHIPREV(AMD, RENOIR, A1, 0x0002),
1216 _DECL_CHIPREV(AMD, RENOIR, LCN_A1, 0x0004),
1217 _DECL_CHIPREV(AMD, RENOIR, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1218
1219 _DECL_CHIPREV(AMD, MATISSE, UNKNOWN, 0x0001),
1220 _DECL_CHIPREV(AMD, MATISSE, B0, 0x0002),
1221 _DECL_CHIPREV(AMD, MATISSE, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1222
1223 _DECL_CHIPREV(AMD, VAN_GOGH, UNKNOWN, 0x0001),
1224 _DECL_CHIPREV(AMD, VAN_GOGH, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1225
1226 _DECL_CHIPREV(AMD, MENDOCINO, UNKNOWN, 0x0001),
1227 _DECL_CHIPREV(AMD, MENDOCINO, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1228
1229 _DECL_CHIPREV(HYGON, DHYANA, UNKNOWN, 0x0001),
1230 _DECL_CHIPREV(HYGON, DHYANA, A1, 0x0002),
1231 _DECL_CHIPREV(HYGON, DHYANA, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1232
1233 _DECL_CHIPREV(AMD, MILAN, UNKNOWN, 0x0001),
1234 _DECL_CHIPREV(AMD, MILAN, A0, 0x0002),
1235 _DECL_CHIPREV(AMD, MILAN, B0, 0x0004),
1236 _DECL_CHIPREV(AMD, MILAN, B1, 0x0008),
1237 _DECL_CHIPREV(AMD, MILAN, B2, 0x0010),
1238 _DECL_CHIPREV(AMD, MILAN, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1239
1240 _DECL_CHIPREV(AMD, GENOA, UNKNOWN, 0x0001),
1241 _DECL_CHIPREV(AMD, GENOA, A0, 0x0002),
1242 _DECL_CHIPREV(AMD, GENOA, A1, 0x0004),
1243 _DECL_CHIPREV(AMD, GENOA, B0, 0x0008),
1244 _DECL_CHIPREV(AMD, GENOA, B1, 0x0010),
1245 _DECL_CHIPREV(AMD, GENOA, B2, 0x0020),
1246 _DECL_CHIPREV(AMD, GENOA, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1247
1248 _DECL_CHIPREV(AMD, VERMEER, UNKNOWN, 0x0001),
1249 _DECL_CHIPREV(AMD, VERMEER, A0, 0x0002),
1250 _DECL_CHIPREV(AMD, VERMEER, B0, 0x0004),
1251 _DECL_CHIPREV(AMD, VERMEER, B2, 0x0008), /* No B1 */
1252 _DECL_CHIPREV(AMD, VERMEER, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1253
1254 _DECL_CHIPREV(AMD, REMBRANDT, UNKNOWN, 0x0001),
1255 _DECL_CHIPREV(AMD, REMBRANDT, A0, 0x0002),
1256 _DECL_CHIPREV(AMD, REMBRANDT, B0, 0x0004),
1257 _DECL_CHIPREV(AMD, REMBRANDT, B1, 0x0008),
1258 _DECL_CHIPREV(AMD, REMBRANDT, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1259
1260 _DECL_CHIPREV(AMD, CEZANNE, UNKNOWN, 0x0001),
1261 _DECL_CHIPREV(AMD, CEZANNE, A0, 0x0002),
1262 _DECL_CHIPREV(AMD, CEZANNE, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1263
1264 _DECL_CHIPREV(AMD, RAPHAEL, UNKNOWN, 0x0001),
1265 _DECL_CHIPREV(AMD, RAPHAEL, B2, 0x0002),
1266 _DECL_CHIPREV(AMD, RAPHAEL, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1267
1268 _DECL_CHIPREV(AMD, PHOENIX, UNKNOWN, 0x0001),
1269 _DECL_CHIPREV(AMD, PHOENIX, A0, 0x0002),
1270 _DECL_CHIPREV(AMD, PHOENIX, A1, 0x0004),
1271 _DECL_CHIPREV(AMD, PHOENIX, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1272
1273 _DECL_CHIPREV(AMD, BERGAMO, UNKNOWN, 0x0001),
1274 _DECL_CHIPREV(AMD, BERGAMO, A0, 0x0002),
1275 _DECL_CHIPREV(AMD, BERGAMO, A1, 0x0004),
1276 _DECL_CHIPREV(AMD, BERGAMO, A2, 0x0008),
1277 _DECL_CHIPREV(AMD, BERGAMO, ANY, _X86_CHIPREV_REV_MATCH_ALL),
1278
1279 /* Keep at the end */
1280 X86_CHIPREV_ANY = _X86_CHIPREV_MKREV(_X86_VENDOR_MATCH_ALL, X86_PF_ANY,
1281 _X86_CHIPREV_REV_MATCH_ALL)
1282 } x86_chiprev_t;
1283
1284 #undef _DECL_CHIPREV
1285
1286 /*
1287 * Same thing, but for microarchitecture (core implementations). We are not
1288 * attempting to capture every possible fine-grained detail here; to the extent
1289 * that it matters, we do so in cpuid.c via ISA/feature bits. We use the same
1290 * number of bits for each field as in chiprev.
1291 */
1292
1293 #define _X86_UARCHREV_VENDOR(x) _X86_CHIPREV_VENDOR(x)
1294 #define _X86_UARCHREV_UARCH(x) _X86_CHIPREV_FAMILY(x)
1295 #define _X86_UARCHREV_REV(x) _X86_CHIPREV_REV(x)
1296
1297 #define _X86_UARCHREV_MKREV(vendor, family, rev) \
1298 _X86_CHIPREV_MKREV(vendor, family, rev)
1299
1300 typedef enum x86_uarch {
1301 X86_UARCH_UNKNOWN,
1302
1303 X86_UARCH_AMD_LEGACY,
1304 X86_UARCH_AMD_ZEN1,
1305 X86_UARCH_AMD_ZENPLUS,
1306 X86_UARCH_AMD_ZEN2,
1307 X86_UARCH_AMD_ZEN3,
1308 X86_UARCH_AMD_ZEN4,
1309
1310 X86_UARCH_ANY = 0xff
1311 } x86_uarch_t;
1312
1313 #define _DECL_UARCHREV(_v, _f, _revn, _revb) \
1314 X86_UARCHREV_ ## _v ## _ ## _f ## _ ## _revn = \
1315 _X86_UARCHREV_MKREV(X86_VENDOR_ ## _v, X86_UARCH_ ## _v ## _ ## _f, \
1316 _revb)
1317
1318 #define _DECL_UARCHREV_NOREV(_v, _f, _revb) \
1319 X86_UARCHREV_ ## _v ## _ ## _f = \
1320 _X86_UARCHREV_MKREV(X86_VENDOR_ ## _v, X86_UARCH_ ## _v ## _ ## _f, \
1321 _revb)
1322
1323 #define _X86_UARCHREV_REV_MATCH_ALL 0xffff
1324
1325 typedef enum x86_uarchrev {
1326 X86_UARCHREV_UNKNOWN,
1327 _DECL_UARCHREV_NOREV(AMD, LEGACY, 0x0001),
1328 _DECL_UARCHREV(AMD, LEGACY, ANY, _X86_UARCHREV_REV_MATCH_ALL),
1329
1330 _DECL_UARCHREV_NOREV(AMD, ZEN1, 0x0001),
1331 _DECL_UARCHREV(AMD, ZEN1, ANY, _X86_UARCHREV_REV_MATCH_ALL),
1332
1333 _DECL_UARCHREV_NOREV(AMD, ZENPLUS, 0x0001),
1334 _DECL_UARCHREV(AMD, ZENPLUS, ANY, _X86_UARCHREV_REV_MATCH_ALL),
1335
1336 _DECL_UARCHREV(AMD, ZEN2, UNKNOWN, 0x0001),
1337 _DECL_UARCHREV(AMD, ZEN2, A0, 0x0002),
1338 _DECL_UARCHREV(AMD, ZEN2, B0, 0x0004),
1339 _DECL_UARCHREV(AMD, ZEN2, ANY, _X86_UARCHREV_REV_MATCH_ALL),
1340
1341 _DECL_UARCHREV(AMD, ZEN3, UNKNOWN, 0x0001),
1342 _DECL_UARCHREV(AMD, ZEN3, A0, 0x0002),
1343 _DECL_UARCHREV(AMD, ZEN3, B0, 0x0004),
1344 _DECL_UARCHREV(AMD, ZEN3, B1, 0x0008),
1345 _DECL_UARCHREV(AMD, ZEN3, B2, 0x0010),
1346 _DECL_UARCHREV(AMD, ZEN3, ANY, _X86_UARCHREV_REV_MATCH_ALL),
1347
1348 _DECL_UARCHREV(AMD, ZEN4, UNKNOWN, 0x0001),
1349 _DECL_UARCHREV(AMD, ZEN4, A0, 0x0002),
1350 _DECL_UARCHREV(AMD, ZEN4, A1, 0x0004),
1351 _DECL_UARCHREV(AMD, ZEN4, A2, 0x0008),
1352 _DECL_UARCHREV(AMD, ZEN4, B0, 0x0010),
1353 _DECL_UARCHREV(AMD, ZEN4, B1, 0x0020),
1354 _DECL_UARCHREV(AMD, ZEN4, B2, 0x0040),
1355 _DECL_UARCHREV(AMD, ZEN4, ANY, _X86_UARCHREV_REV_MATCH_ALL),
1356
1357 /* Keep at the end */
1358 _X86_UARCHREV_ANY = _X86_UARCHREV_MKREV(_X86_VENDOR_MATCH_ALL,
1359 X86_UARCH_ANY, _X86_UARCHREV_REV_MATCH_ALL)
1360 } x86_uarchrev_t;
1361
1362 #undef _DECL_UARCHREV
1363
1364 #endif /* !_ASM */
1365
1366 /*
1367 * Various socket/package types, extended as the need to distinguish
1368 * a new type arises. The top 8 byte identfies the vendor and the
1369 * remaining 24 bits describe 24 socket types.
1370 */
1371
1372 #define _X86_SOCKET_VENDOR_SHIFT 24
1373 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
1374 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
1375 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
1376
1377 #define _X86_SOCKET_MKVAL(vendor, bitval) \
1378 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
1379
1380 #define X86_SOCKET_MATCH(s, mask) \
1381 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
1382 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
1383
1384 #define X86_SOCKET_UNKNOWN 0x0
1385 /*
1386 * AMD socket types
1387 */
1388 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01)
1389 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02)
1390 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03)
1391 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04)
1392 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05)
1393 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06)
1394 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07)
1395 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08)
1396 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09)
1397 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a)
1398 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b)
1399 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c)
1400 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d)
1401 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e)
1402 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f)
1403 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10)
1404 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11)
1405 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12)
1406 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13)
1407 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14)
1408 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15)
1409 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16)
1410 #define X86_SOCKET_FP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17)
1411 #define X86_SOCKET_FM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18)
1412 #define X86_SOCKET_FP4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19)
1413 #define X86_SOCKET_AM4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a)
1414 #define X86_SOCKET_FT3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b)
1415 #define X86_SOCKET_FT4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c)
1416 #define X86_SOCKET_FS1B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d)
1417 #define X86_SOCKET_FT3B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e)
1418 #define X86_SOCKET_SP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f)
1419 #define X86_SOCKET_SP3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20)
1420 #define X86_SOCKET_FP5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x21)
1421 #define X86_SOCKET_FP6 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x22)
1422 #define X86_SOCKET_STRX4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x23)
1423 #define X86_SOCKET_SP5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x24)
1424 #define X86_SOCKET_AM5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x25)
1425 #define X86_SOCKET_FP7 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x26)
1426 #define X86_SOCKET_FP7R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x27)
1427 #define X86_SOCKET_FF3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x28)
1428 #define X86_SOCKET_FT6 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x29)
1429 #define X86_SOCKET_FP8 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2a)
1430 #define X86_SOCKET_FL1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2b)
1431 #define X86_SOCKET_SP6 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2c)
1432 #define X86_SOCKET_TR5 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x2d)
1433 #define X86_NUM_SOCKETS_AMD 0x2d
1434
1435 /*
1436 * Hygon socket types
1437 */
1438 #define X86_SOCKET_SL1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x01)
1439 #define X86_SOCKET_SL1R2 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x02)
1440 #define X86_SOCKET_DM1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x03)
1441 #define X86_NUM_SOCKETS_HYGON 0x03
1442
1443 #define X86_NUM_SOCKETS (X86_NUM_SOCKETS_AMD + X86_NUM_SOCKETS_HYGON)
1444
1445 /*
1446 * Definitions for Intel processor models. These are all for Family 6
1447 * processors. This list and the Atom set below it are not exhuastive.
1448 */
1449 #define INTC_MODEL_YONAH 0x0e
1450 #define INTC_MODEL_MEROM 0x0f
1451 #define INTC_MODEL_MEROM_L 0x16
1452 #define INTC_MODEL_PENRYN 0x17
1453 #define INTC_MODEL_DUNNINGTON 0x1d
1454
1455 #define INTC_MODEL_NEHALEM 0x1e
1456 #define INTC_MODEL_NEHALEM2 0x1f
1457 #define INTC_MODEL_NEHALEM_EP 0x1a
1458 #define INTC_MODEL_NEHALEM_EX 0x2e
1459
1460 #define INTC_MODEL_WESTMERE 0x25
1461 #define INTC_MODEL_WESTMERE_EP 0x2c
1462 #define INTC_MODEL_WESTMERE_EX 0x2f
1463
1464 #define INTC_MODEL_SANDYBRIDGE 0x2a
1465 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d
1466 #define INTC_MODEL_IVYBRIDGE 0x3a
1467 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e
1468
1469 #define INTC_MODEL_HASWELL 0x3c
1470 #define INTC_MODEL_HASWELL_ULT 0x45
1471 #define INTC_MODEL_HASWELL_GT3E 0x46
1472 #define INTC_MODEL_HASWELL_XEON 0x3f
1473
1474 #define INTC_MODEL_BROADWELL 0x3d
1475 #define INTC_MODEL_BROADWELL_2 0x47
1476 #define INTC_MODEL_BROADWELL_XEON 0x4f
1477 #define INTC_MODEL_BROADWELL_XEON_D 0x56
1478
1479 #define INTC_MODEL_SKYLAKE_MOBILE 0x4e
1480 /*
1481 * Note, this model is shared with Cascade Lake and Cooper Lake.
1482 */
1483 #define INTC_MODEL_SKYLAKE_XEON 0x55
1484 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e
1485
1486 #define INTC_MODEL_CANNON_LAKE 0x66
1487
1488 /*
1489 * Note, both Kaby Lake models are shared with Coffee Lake, Whiskey Lake, Amber
1490 * Lake, and some Comet Lake parts.
1491 */
1492 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e
1493 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e
1494
1495 #define INTC_MODEL_ICELAKE_XEON 0x6a
1496 #define INTC_MODEL_ICELAKE_MOBILE 0x7e
1497 #define INTC_MODEL_ICELAKE_XEON_DE 0x6c
1498
1499 #define INTC_MODEL_TIGERLAKE_MOBILE 0x8c
1500 #define INTC_MODEL_TIGERLAKE_MOBILE_2 0x8d
1501 #define INTC_MODEL_SAPPHIRE_RAPIDS 0x8f
1502
1503 #define INTC_MODEL_COMETLAKE 0xa5
1504 #define INTC_MODEL_COMETLAKE_MOBILE 0xa6
1505 #define INTC_MODEL_ROCKETLAKE 0xa7
1506
1507 #define INTC_MODEL_ALDER_LAKE_DESKTOP 0x97
1508 #define INTC_MODEL_ALDER_LAKE_MOBILE 0x9a /* And some Atom parts too */
1509 #define INTC_MODEL_RAPTOR_LAKE_MOBILE_1 0xb7
1510 #define INTC_MODEL_RAPTOR_LAKE_MOBILE_2 0xba
1511 #define INTC_MODEL_RAPTOR_LAKE_MOBILE_3 0xbf
1512
1513 #define INTC_MODEL_METEOR_LAKE 0xaa
1514
1515 #define INTC_MODEL_EMERALD_RAPIDS 0xcf
1516
1517 /*
1518 * Atom Processors
1519 */
1520 #define INTC_MODEL_SILVERTHORNE 0x1c
1521 #define INTC_MODEL_LINCROFT 0x26
1522 #define INTC_MODEL_PENWELL 0x27
1523 #define INTC_MODEL_CLOVERVIEW 0x35
1524 #define INTC_MODEL_CEDARVIEW 0x36
1525 #define INTC_MODEL_BAY_TRAIL 0x37
1526 #define INTC_MODEL_MERRIFIELD 0x4a
1527 #define INTC_MODEL_AVATON 0x4d
1528 #define INTC_MODEL_AIRMONT 0x4c
1529 #define INTC_MODEL_MOOREFIELD 0x5a
1530 #define INTC_MODEL_APOLLO_LAKE 0x5c
1531 #define INTC_MODEL_SOFIA_3G_R 0x5d
1532 #define INTC_MODEL_DENVERTON 0x5f
1533 #define INTC_MODEL_GEMINI_LAKE 0x7a
1534 #define INTC_MODEL_TREMONT 0x86 /* Parker Ridge & Snow Ridge */
1535 #define INTC_MODEL_LAKEFIELD 0x8a
1536 #define INTC_MODEL_ELKHART_LAKE 0x96
1537 #define INTC_MODEL_JASPER_LAKE 0x9c
1538 #define INTC_MODEL_ALDER_LAKE_N 0xbe /* And some {desk,lap}top too */
1539
1540 /*
1541 * xgetbv/xsetbv support
1542 * See section 13.3 in vol. 1 of the Intel Developer's manual.
1543 */
1544
1545 #define XFEATURE_ENABLED_MASK 0x0
1546 /*
1547 * XFEATURE_ENABLED_MASK values (eax)
1548 * See setup_xfem().
1549 */
1550 #define XFEATURE_LEGACY_FP (1 << 0)
1551 #define XFEATURE_SSE (1 << 1)
1552 #define XFEATURE_AVX (1 << 2)
1553 /*
1554 * MPX is meant to be all or nothing, therefore for most of the kernel prefer
1555 * the XFEATURE_MPX definition over the individual state bits.
1556 */
1557 #define XFEATURE_MPX_BNDREGS (1 << 3)
1558 #define XFEATURE_MPX_BNDCSR (1 << 4)
1559 #define XFEATURE_MPX (XFEATURE_MPX_BNDREGS | XFEATURE_MPX_BNDCSR)
1560 /*
1561 * AX512 is meant to be all or nothing, therefore for most of the kernel prefer
1562 * the XFEATURE_AVX512 definition over the individual state bits.
1563 */
1564 #define XFEATURE_AVX512_OPMASK (1 << 5)
1565 #define XFEATURE_AVX512_ZMM (1 << 6)
1566 #define XFEATURE_AVX512_HI_ZMM (1 << 7)
1567 #define XFEATURE_AVX512 (XFEATURE_AVX512_OPMASK | \
1568 XFEATURE_AVX512_ZMM | XFEATURE_AVX512_HI_ZMM)
1569 /* bit 8 unused */
1570 #define XFEATURE_PKRU (1 << 9)
1571 #define XFEATURE_FP_ALL \
1572 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
1573 XFEATURE_AVX512 | XFEATURE_PKRU)
1574
1575 /*
1576 * Define the set of xfeature flags that should be considered valid in the xsave
1577 * state vector when we initialize an lwp. This is distinct from the full set so
1578 * that all of the processor's normal logic and tracking of the xsave state is
1579 * usable. This should correspond to the state that's been initialized by the
1580 * ABI to hold meaningful values. Adding additional bits here can have serious
1581 * performance implications and cause performance degradations when using the
1582 * FPU vector (xmm) registers.
1583 */
1584 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE)
1585
1586 #if !defined(_ASM)
1587
1588 #if defined(_KERNEL) || defined(_KMEMUSER)
1589
1590 #define NUM_X86_FEATURES 112
1591 extern uchar_t x86_featureset[];
1592
1593 extern void free_x86_featureset(void *featureset);
1594 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
1595 extern void add_x86_feature(void *featureset, uint_t feature);
1596 extern void remove_x86_feature(void *featureset, uint_t feature);
1597 extern boolean_t compare_x86_featureset(void *setA, void *setB);
1598 extern void print_x86_featureset(void *featureset);
1599
1600
1601 extern uint_t x86_type;
1602 extern uint_t x86_vendor;
1603 extern uint_t x86_clflush_size;
1604
1605 extern uint_t pentiumpro_bug4046376;
1606
1607 /*
1608 * These functions are all used to perform various side-channel mitigations.
1609 * Please see uts/i86pc/os/cpuid.c for more information.
1610 */
1611 extern void (*spec_uarch_flush)(void);
1612 extern void x86_rsb_stuff(void);
1613 extern void x86_rsb_stuff_vmexit(void);
1614 extern void x86_md_clear(void);
1615
1616 #endif
1617
1618 #if defined(_KERNEL)
1619
1620 /*
1621 * This structure is used to pass arguments and get return values back
1622 * from the CPUID instruction in __cpuid_insn() routine.
1623 */
1624 struct cpuid_regs {
1625 uint32_t cp_eax;
1626 uint32_t cp_ebx;
1627 uint32_t cp_ecx;
1628 uint32_t cp_edx;
1629 };
1630
1631 extern int x86_use_pcid;
1632 extern int x86_use_invpcid;
1633
1634 /*
1635 * Utility functions to get/set extended control registers (XCR)
1636 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
1637 */
1638 extern uint64_t get_xcr(uint_t);
1639 extern void set_xcr(uint_t, uint64_t);
1640
1641 extern uint64_t rdmsr(uint_t);
1642 extern void wrmsr(uint_t, const uint64_t);
1643 extern uint64_t xrdmsr(uint_t);
1644 extern void xwrmsr(uint_t, const uint64_t);
1645 extern int checked_rdmsr(uint_t, uint64_t *);
1646 extern int checked_wrmsr(uint_t, uint64_t);
1647
1648 extern void invalidate_cache(void);
1649 extern ulong_t getcr4(void);
1650 extern void setcr4(ulong_t);
1651
1652 extern void mtrr_sync(void);
1653
1654 extern void cpu_fast_syscall_enable(void);
1655 extern void cpu_fast_syscall_disable(void);
1656
1657 typedef enum cpuid_pass {
1658 CPUID_PASS_NONE = 0,
1659 CPUID_PASS_PRELUDE,
1660 CPUID_PASS_IDENT,
1661 CPUID_PASS_BASIC,
1662 CPUID_PASS_EXTENDED,
1663 CPUID_PASS_DYNAMIC,
1664 CPUID_PASS_RESOLVE
1665 } cpuid_pass_t;
1666
1667 struct cpu;
1668
1669 extern boolean_t cpuid_checkpass(const struct cpu *const, const cpuid_pass_t);
1670 extern void cpuid_execpass(struct cpu *, const cpuid_pass_t, void *);
1671 extern void cpuid_pass_ucode(struct cpu *, uchar_t *);
1672 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
1673 extern uint32_t __cpuid_insn(struct cpuid_regs *);
1674 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
1675 extern int cpuid_getidstr(struct cpu *, char *, size_t);
1676 extern const char *cpuid_getvendorstr(struct cpu *);
1677 extern uint_t cpuid_getvendor(struct cpu *);
1678 extern uint_t cpuid_getfamily(struct cpu *);
1679 extern uint_t cpuid_getmodel(struct cpu *);
1680 extern uint_t cpuid_getstep(struct cpu *);
1681 extern uint_t cpuid_getsig(struct cpu *);
1682 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
1683 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
1684 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
1685 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
1686 extern int cpuid_get_chipid(struct cpu *);
1687 extern id_t cpuid_get_coreid(struct cpu *);
1688 extern int cpuid_get_pkgcoreid(struct cpu *);
1689 extern int cpuid_get_clogid(struct cpu *);
1690 extern int cpuid_get_cacheid(struct cpu *);
1691 extern uint32_t cpuid_get_apicid(struct cpu *);
1692 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
1693 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
1694 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
1695 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
1696 extern size_t cpuid_get_xsave_size(void);
1697 extern void cpuid_get_xsave_info(uint64_t, size_t *, size_t *);
1698 extern boolean_t cpuid_need_fp_excp_handling(void);
1699 extern int cpuid_is_cmt(struct cpu *);
1700 extern int cpuid_syscall32_insn(struct cpu *);
1701 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
1702
1703 extern x86_chiprev_t cpuid_getchiprev(struct cpu *);
1704 extern const char *cpuid_getchiprevstr(struct cpu *);
1705 extern uint32_t cpuid_getsockettype(struct cpu *);
1706 extern const char *cpuid_getsocketstr(struct cpu *);
1707 extern x86_uarchrev_t cpuid_getuarchrev(struct cpu *);
1708
1709 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
1710
1711 struct cpuid_info;
1712
1713 extern void setx86isalist(void);
1714 extern void cpuid_alloc_space(struct cpu *);
1715 extern void cpuid_free_space(struct cpu *);
1716 extern void cpuid_set_cpu_properties(void *, processorid_t,
1717 struct cpuid_info *);
1718 extern void cpuid_post_ucodeadm(void);
1719
1720 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
1721 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
1722
1723 #if !defined(__xpv)
1724 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
1725 extern void cpuid_mwait_free(struct cpu *);
1726 extern int cpuid_deep_cstates_supported(void);
1727 extern int cpuid_arat_supported(void);
1728 extern int cpuid_iepb_supported(struct cpu *);
1729 extern int cpuid_deadline_tsc_supported(void);
1730 extern void vmware_port(int, uint32_t *);
1731 #endif
1732
1733 extern x86_processor_family_t chiprev_family(const x86_chiprev_t);
1734 extern boolean_t chiprev_matches(const x86_chiprev_t, const x86_chiprev_t);
1735 extern boolean_t chiprev_at_least(const x86_chiprev_t, const x86_chiprev_t);
1736
1737 extern x86_uarch_t uarchrev_uarch(const x86_uarchrev_t);
1738 extern boolean_t uarchrev_matches(const x86_uarchrev_t, const x86_uarchrev_t);
1739 extern boolean_t uarchrev_at_least(const x86_uarchrev_t, const x86_uarchrev_t);
1740
1741 /*
1742 * Cache information intended for topology and wider use.
1743 */
1744 typedef enum {
1745 X86_CACHE_TYPE_DATA,
1746 X86_CACHE_TYPE_INST,
1747 X86_CACHE_TYPE_UNIFIED
1748 } x86_cache_type_t;
1749
1750 typedef enum {
1751 X86_CACHE_F_FULL_ASSOC = 1 << 0
1752 } x86_cache_flags_t;
1753
1754 typedef struct x86_cache {
1755 uint32_t xc_level;
1756 x86_cache_type_t xc_type;
1757 x86_cache_flags_t xc_flags;
1758 uint32_t xc_nparts;
1759 uint32_t xc_nways;
1760 uint32_t xc_line_size;
1761 uint64_t xc_nsets;
1762 uint64_t xc_size;
1763 uint64_t xc_id;
1764 uint32_t xc_apic_shift;
1765 } x86_cache_t;
1766
1767 extern int cpuid_getncaches(struct cpu *, uint32_t *);
1768 extern int cpuid_getcache(struct cpu *, uint32_t, x86_cache_t *);
1769
1770 struct cpu_ucode_info;
1771
1772 extern void ucode_alloc_space(struct cpu *);
1773 extern void ucode_free_space(struct cpu *);
1774 extern void ucode_init(void);
1775 extern void ucode_check(struct cpu *);
1776 extern void ucode_cleanup();
1777
1778 #if !defined(__xpv)
1779 extern char _tsc_mfence_start;
1780 extern char _tsc_mfence_end;
1781 extern char _tscp_start;
1782 extern char _tscp_end;
1783 extern char _no_rdtsc_start;
1784 extern char _no_rdtsc_end;
1785 extern char _tsc_lfence_start;
1786 extern char _tsc_lfence_end;
1787 #endif
1788
1789 #if !defined(__xpv)
1790 extern char bcopy_patch_start;
1791 extern char bcopy_patch_end;
1792 extern char bcopy_ck_size;
1793 #endif
1794
1795 extern void post_startup_cpu_fixups(void);
1796
1797 extern uint_t workaround_errata(struct cpu *);
1798
1799 #if defined(OPTERON_ERRATUM_93)
1800 extern int opteron_erratum_93;
1801 #endif
1802
1803 #if defined(OPTERON_ERRATUM_91)
1804 extern int opteron_erratum_91;
1805 #endif
1806
1807 #if defined(OPTERON_ERRATUM_100)
1808 extern int opteron_erratum_100;
1809 #endif
1810
1811 #if defined(OPTERON_ERRATUM_121)
1812 extern int opteron_erratum_121;
1813 #endif
1814
1815 #if defined(OPTERON_ERRATUM_147)
1816 extern int opteron_erratum_147;
1817 extern void patch_erratum_147(void);
1818 #endif
1819
1820 #if !defined(__xpv)
1821 extern void determine_platform(void);
1822 #endif
1823 extern int get_hwenv(void);
1824 extern int is_controldom(void);
1825
1826 extern void enable_pcid(void);
1827
1828 extern void xsave_setup_msr(struct cpu *);
1829
1830 #if !defined(__xpv)
1831 extern void reset_gdtr_limit(void);
1832 #endif
1833
1834 extern int enable_platform_detection;
1835
1836 /*
1837 * Hypervisor signatures
1838 */
1839 #define HVSIG_XEN_HVM "XenVMMXenVMM"
1840 #define HVSIG_VMWARE "VMwareVMware"
1841 #define HVSIG_KVM "KVMKVMKVM"
1842 #define HVSIG_MICROSOFT "Microsoft Hv"
1843 #define HVSIG_BHYVE "bhyve bhyve "
1844 #define HVSIG_QEMU_TCG "TCGTCGTCGTCG"
1845
1846 /*
1847 * Defined hardware environments
1848 */
1849 #define HW_NATIVE (1 << 0) /* Running on bare metal */
1850 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
1851
1852 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
1853 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
1854 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
1855 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
1856 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */
1857 #define HW_QEMU_TCG (1 << 7) /* Running on QEMU TCG hypervisor */
1858
1859 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \
1860 HW_BHYVE | HW_QEMU_TCG)
1861
1862 #endif /* _KERNEL */
1863
1864 #endif /* !_ASM */
1865
1866 /*
1867 * VMware hypervisor related defines
1868 */
1869 #define VMWARE_HVMAGIC 0x564d5868
1870 #define VMWARE_HVPORT 0x5658
1871 #define VMWARE_HVCMD_GETVERSION 0x0a
1872 #define VMWARE_HVCMD_GETTSCFREQ 0x2d
1873
1874 #ifdef __cplusplus
1875 }
1876 #endif
1877
1878 #endif /* _SYS_X86_ARCHEXT_H */