1 /*
   2  * This file and its contents are supplied under the terms of the
   3  * Common Development and Distribution License ("CDDL"), version 1.0.
   4  * You may only use this file in accordance with the terms of version
   5  * 1.0 of the CDDL.
   6  *
   7  * A full copy of the text of the CDDL should have accompanied this
   8  * source.  A copy of the CDDL is also available via the Internet at
   9  * http://www.illumos.org/license/CDDL.
  10  */
  11 
  12 /*
  13  * Copyright 2018, Joyent, Inc.
  14  */
  15 
  16 /*
  17  * Test our disassembly of the RV32I instructions. Instructions are ordered per
  18  * the ISA manual. Supervisor and CSR instructions are elsewhere.
  19  */
  20 
  21 .text
  22 .align 16
  23 .globl libdis_test
  24 .type libdis_test, @function
  25 libdis_test:
  26         lui     ra, 0x00
  27         lui     ra, 0x23
  28         lui     ra, 0xfffff
  29         auipc   ra, 0x00
  30         auipc   ra, 0x23
  31         auipc   ra, 0xfffff
  32         /*
  33          * Branches are not tested at this time as they basially always end up
  34          * wanting to create which ends up not really lending itself to
  35          * automated testing here. 
  36          */
  37         lb      s0, 0x7ff(s1)
  38         lb      s1, (s1)
  39         lb      s2, -0x800(s1)
  40         lh      s3, 0x7ff(s1)
  41         lh      s4, (s1)
  42         lh      s5, -0x800(s1)
  43         lw      s6, 0x7ff(s1)
  44         lw      s7, (s1)
  45         lw      s8, -0x800(s1)
  46         lbu     s7, 0x7ff(s1)
  47         lbu     s6, (s1)
  48         lbu     s5, -0x800(s1)
  49         lhu     s4, 0x7ff(s1)
  50         lhu     s3, (s1)
  51         lhu     s2, -0x800(s1)
  52         sb      t0, 0x7ff(t1)
  53         sb      t1, (t2)
  54         sb      t2, -0x800(t3)
  55         sh      t3, 0x7ff(t1)
  56         sh      t4, (t2)
  57         sh      t5, -0x800(t3)
  58         sw      t4, 0x7ff(t1)
  59         sw      t3, (t2)
  60         sw      t2, -0x800(t3)
  61         addi    ra, t0, 0x4
  62         addi    ra, t0, -0x4
  63         slti    ra, t0, 0x4
  64         slti    ra, t0, -0x4
  65         sltiu   ra, t0, 0x4
  66         sltiu   ra, t0, -0x4
  67         xori    ra, t0, 0x4
  68         xori    ra, t0, -0x4
  69         ori     ra, t0, 0x4
  70         ori     ra, t0, -0x4
  71         andi    ra, t0, 0x4
  72         andi    ra, t0, -0x4
  73         slli    t4, t5, 0x12
  74         srli    t4, t5, 0x13
  75         srai    t4, t5, 0x14
  76         add     s0, s1, s2
  77         sub     s1, s2, s3
  78         sll     s3, s4, s5
  79         slt     s4, s5, s6
  80         sltu    a0, a1, ra
  81         xor     s5, s6, s7
  82         srl     s6, s7, s8
  83         sra     s7, s8, s9
  84         or      s8, s9, s10
  85         and     s9, s10, s11
  86         fence
  87         fence   ow, ir
  88         fence   ir, ow
  89         fence   ior, iorw
  90         fence.i
  91 .size libdis_test, [.-libdis_test]