riscv New usr/src/test/util-tests/tests/dis/risc-v-c/64.int.out

   1     libdis_test:     fd 24              c.addiw s1,0x1f
   2     libdis_test+0x2: 8d 24              c.addiw s1,0x3
   3     libdis_test+0x4: 81 34              c.addiw s1,-0x20
   4     libdis_test+0x6: b1 9d              c.addw a1,a2
   5     libdis_test+0x8: 15 9c              c.subw s0,a3