OS-7095 Want risc-v disassembler

@@ -24,10 +24,11 @@
  * Use is subject to license terms.
  *
  * Copyright 2011 Jason King.  All rights reserved.
  * Copyright 2012 Joshua M. Clulow <josh@sysmgr.org>
  * Copyright 2015 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
+ * Copyright 2018, Joyent, Inc.
  */
 
 #include <ctype.h>
 #include <getopt.h>
 #include <stdio.h>

@@ -575,10 +576,33 @@
 
                         if (ehdr.e_ident[EI_DATA] != ELFDATA2MSB) {
                                 warn("invalid E_IDENT field for S390 object");
                                 return;
                         }
+                        break;
+
+                case EM_RISCV:
+                        /*
+                         * RISC-V is defined to be litle endian. The current ISA
+                         * makes it clear that the 64-bit instructions can
+                         * co-eixst with the 32-bit ones and therefore we don't
+                         * need a separate elf class at this time.
+                         */
+                        if (ehdr.e_ident[EI_DATA] != ELFDATA2LSB) {
+                                warn("invalid EI_DATA field for RISC-V object");
+                                return;
+                        }
+
+                        if (ehdr.e_ident[EI_CLASS] == ELFCLASS32) {
+                                g_flags |= DIS_RISCV_32;
+                        } else if (ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
+                                g_flags |= DIS_RISCV_64;
+                        } else {
+                                warn("invalid EI_CLASS field for RISC-V "
+                                    "object");
+                                return;
+                        }
                         break;
 
                 default:
                         die("%s: unsupported ELF machine 0x%x", filename,
                             ehdr.e_machine);