8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 #include "ixgbe_sw.h"
31
32 /*
33 * Update driver private statistics.
34 */
35 static int
36 ixgbe_update_stats(kstat_t *ks, int rw)
37 {
38 ixgbe_t *ixgbe;
39 struct ixgbe_hw *hw;
40 ixgbe_stat_t *ixgbe_ks;
41 int i;
42
43 if (rw == KSTAT_WRITE)
44 return (EACCES);
45
46 ixgbe = (ixgbe_t *)ks->ks_private;
47 ixgbe_ks = (ixgbe_stat_t *)ks->ks_data;
95 ixgbe_ks->gptc.value.ui64 = 0;
96 ixgbe_ks->tor.value.ui64 = 0;
97 ixgbe_ks->tot.value.ui64 = 0;
98 for (i = 0; i < 16; i++) {
99 ixgbe_ks->qprc[i].value.ui64 +=
100 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
101 ixgbe_ks->gprc.value.ui64 += ixgbe_ks->qprc[i].value.ui64;
102 ixgbe_ks->qptc[i].value.ui64 +=
103 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
104 ixgbe_ks->gptc.value.ui64 += ixgbe_ks->qptc[i].value.ui64;
105 ixgbe_ks->qbrc[i].value.ui64 +=
106 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
107 ixgbe_ks->tor.value.ui64 += ixgbe_ks->qbrc[i].value.ui64;
108 switch (hw->mac.type) {
109 case ixgbe_mac_82598EB:
110 ixgbe_ks->qbtc[i].value.ui64 +=
111 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
112 break;
113
114 case ixgbe_mac_82599EB:
115 ixgbe_ks->qbtc[i].value.ui64 +=
116 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
117 ixgbe_ks->qbtc[i].value.ui64 +=
118 ((uint64_t)((IXGBE_READ_REG(hw,
119 IXGBE_QBTC_H(i))) & 0xF) << 32);
120 break;
121
122 default:
123 break;
124 }
125 ixgbe_ks->tot.value.ui64 += ixgbe_ks->qbtc[i].value.ui64;
126 }
127 /*
128 * This is a Workaround:
129 * Currently h/w GORCH, GOTCH, TORH registers are not
130 * correctly implemented. We found that the values in
131 * these registers are same as those in corresponding
132 * *L registers (i.e. GORCL, GOTCL, and TORL). Here the
133 * gor and got stat data will not be retrieved through
134 * GORC{H/L} and GOTC{H/L} registers but be obtained by
148 ixgbe_ks->ptc127.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC127);
149 ixgbe_ks->ptc255.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC255);
150 ixgbe_ks->ptc511.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC511);
151 ixgbe_ks->ptc1023.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC1023);
152 ixgbe_ks->ptc1522.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC1522);
153
154 ixgbe_ks->mspdc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MSPDC);
155 for (i = 0; i < 8; i++)
156 ixgbe_ks->mpc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MPC(i));
157 ixgbe_ks->mlfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MLFC);
158 ixgbe_ks->mrfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MRFC);
159 ixgbe_ks->rlec.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RLEC);
160 ixgbe_ks->lxontxc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_LXONTXC);
161 switch (hw->mac.type) {
162 case ixgbe_mac_82598EB:
163 ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
164 IXGBE_LXONRXC);
165 break;
166
167 case ixgbe_mac_82599EB:
168 ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
169 IXGBE_LXONRXCNT);
170 break;
171
172 default:
173 break;
174 }
175 ixgbe_ks->lxofftxc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
176 switch (hw->mac.type) {
177 case ixgbe_mac_82598EB:
178 ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
179 IXGBE_LXOFFRXC);
180 break;
181
182 case ixgbe_mac_82599EB:
183 ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
184 IXGBE_LXOFFRXCNT);
185 break;
186
187 default:
188 break;
189 }
190 ixgbe_ks->ruc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RUC);
191 ixgbe_ks->rfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RFC);
192 ixgbe_ks->roc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_ROC);
193 ixgbe_ks->rjc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RJC);
194
195 mutex_exit(&ixgbe->gen_lock);
196
197 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK)
198 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_UNAFFECTED);
199
200 return (0);
201 }
202
539 ixgbe_ks->tor.value.ui64 = 0;
540 for (i = 0; i < 16; i++) {
541 ixgbe_ks->qbrc[i].value.ui64 +=
542 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
543 ixgbe_ks->tor.value.ui64 +=
544 ixgbe_ks->qbrc[i].value.ui64;
545 }
546 *val = ixgbe_ks->tor.value.ui64;
547 break;
548
549 case MAC_STAT_OBYTES:
550 ixgbe_ks->tot.value.ui64 = 0;
551 for (i = 0; i < 16; i++) {
552 switch (hw->mac.type) {
553 case ixgbe_mac_82598EB:
554 ixgbe_ks->qbtc[i].value.ui64 +=
555 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
556 break;
557
558 case ixgbe_mac_82599EB:
559 ixgbe_ks->qbtc[i].value.ui64 +=
560 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
561 ixgbe_ks->qbtc[i].value.ui64 +=
562 ((uint64_t)((IXGBE_READ_REG(hw,
563 IXGBE_QBTC_H(i))) & 0xF) << 32);
564 break;
565
566 default:
567 break;
568 }
569 ixgbe_ks->tot.value.ui64 +=
570 ixgbe_ks->qbtc[i].value.ui64;
571 }
572 *val = ixgbe_ks->tot.value.ui64;
573 break;
574
575 case MAC_STAT_IPACKETS:
576 ixgbe_ks->tpr.value.ui64 +=
577 IXGBE_READ_REG(hw, IXGBE_TPR);
578 *val = ixgbe_ks->tpr.value.ui64;
|
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
29 */
30
31 #include "ixgbe_sw.h"
32
33 /*
34 * Update driver private statistics.
35 */
36 static int
37 ixgbe_update_stats(kstat_t *ks, int rw)
38 {
39 ixgbe_t *ixgbe;
40 struct ixgbe_hw *hw;
41 ixgbe_stat_t *ixgbe_ks;
42 int i;
43
44 if (rw == KSTAT_WRITE)
45 return (EACCES);
46
47 ixgbe = (ixgbe_t *)ks->ks_private;
48 ixgbe_ks = (ixgbe_stat_t *)ks->ks_data;
96 ixgbe_ks->gptc.value.ui64 = 0;
97 ixgbe_ks->tor.value.ui64 = 0;
98 ixgbe_ks->tot.value.ui64 = 0;
99 for (i = 0; i < 16; i++) {
100 ixgbe_ks->qprc[i].value.ui64 +=
101 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
102 ixgbe_ks->gprc.value.ui64 += ixgbe_ks->qprc[i].value.ui64;
103 ixgbe_ks->qptc[i].value.ui64 +=
104 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
105 ixgbe_ks->gptc.value.ui64 += ixgbe_ks->qptc[i].value.ui64;
106 ixgbe_ks->qbrc[i].value.ui64 +=
107 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
108 ixgbe_ks->tor.value.ui64 += ixgbe_ks->qbrc[i].value.ui64;
109 switch (hw->mac.type) {
110 case ixgbe_mac_82598EB:
111 ixgbe_ks->qbtc[i].value.ui64 +=
112 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
113 break;
114
115 case ixgbe_mac_82599EB:
116 case ixgbe_mac_X540:
117 ixgbe_ks->qbtc[i].value.ui64 +=
118 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
119 ixgbe_ks->qbtc[i].value.ui64 +=
120 ((uint64_t)((IXGBE_READ_REG(hw,
121 IXGBE_QBTC_H(i))) & 0xF) << 32);
122 break;
123
124 default:
125 break;
126 }
127 ixgbe_ks->tot.value.ui64 += ixgbe_ks->qbtc[i].value.ui64;
128 }
129 /*
130 * This is a Workaround:
131 * Currently h/w GORCH, GOTCH, TORH registers are not
132 * correctly implemented. We found that the values in
133 * these registers are same as those in corresponding
134 * *L registers (i.e. GORCL, GOTCL, and TORL). Here the
135 * gor and got stat data will not be retrieved through
136 * GORC{H/L} and GOTC{H/L} registers but be obtained by
150 ixgbe_ks->ptc127.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC127);
151 ixgbe_ks->ptc255.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC255);
152 ixgbe_ks->ptc511.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC511);
153 ixgbe_ks->ptc1023.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC1023);
154 ixgbe_ks->ptc1522.value.ul += IXGBE_READ_REG(hw, IXGBE_PTC1522);
155
156 ixgbe_ks->mspdc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MSPDC);
157 for (i = 0; i < 8; i++)
158 ixgbe_ks->mpc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MPC(i));
159 ixgbe_ks->mlfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MLFC);
160 ixgbe_ks->mrfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_MRFC);
161 ixgbe_ks->rlec.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RLEC);
162 ixgbe_ks->lxontxc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_LXONTXC);
163 switch (hw->mac.type) {
164 case ixgbe_mac_82598EB:
165 ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
166 IXGBE_LXONRXC);
167 break;
168
169 case ixgbe_mac_82599EB:
170 case ixgbe_mac_X540:
171 ixgbe_ks->lxonrxc.value.ui64 += IXGBE_READ_REG(hw,
172 IXGBE_LXONRXCNT);
173 break;
174
175 default:
176 break;
177 }
178 ixgbe_ks->lxofftxc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
179 switch (hw->mac.type) {
180 case ixgbe_mac_82598EB:
181 ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
182 IXGBE_LXOFFRXC);
183 break;
184
185 case ixgbe_mac_82599EB:
186 case ixgbe_mac_X540:
187 ixgbe_ks->lxoffrxc.value.ui64 += IXGBE_READ_REG(hw,
188 IXGBE_LXOFFRXCNT);
189 break;
190
191 default:
192 break;
193 }
194 ixgbe_ks->ruc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RUC);
195 ixgbe_ks->rfc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RFC);
196 ixgbe_ks->roc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_ROC);
197 ixgbe_ks->rjc.value.ui64 += IXGBE_READ_REG(hw, IXGBE_RJC);
198
199 mutex_exit(&ixgbe->gen_lock);
200
201 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK)
202 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_UNAFFECTED);
203
204 return (0);
205 }
206
543 ixgbe_ks->tor.value.ui64 = 0;
544 for (i = 0; i < 16; i++) {
545 ixgbe_ks->qbrc[i].value.ui64 +=
546 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
547 ixgbe_ks->tor.value.ui64 +=
548 ixgbe_ks->qbrc[i].value.ui64;
549 }
550 *val = ixgbe_ks->tor.value.ui64;
551 break;
552
553 case MAC_STAT_OBYTES:
554 ixgbe_ks->tot.value.ui64 = 0;
555 for (i = 0; i < 16; i++) {
556 switch (hw->mac.type) {
557 case ixgbe_mac_82598EB:
558 ixgbe_ks->qbtc[i].value.ui64 +=
559 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
560 break;
561
562 case ixgbe_mac_82599EB:
563 case ixgbe_mac_X540:
564 ixgbe_ks->qbtc[i].value.ui64 +=
565 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
566 ixgbe_ks->qbtc[i].value.ui64 +=
567 ((uint64_t)((IXGBE_READ_REG(hw,
568 IXGBE_QBTC_H(i))) & 0xF) << 32);
569 break;
570
571 default:
572 break;
573 }
574 ixgbe_ks->tot.value.ui64 +=
575 ixgbe_ks->qbtc[i].value.ui64;
576 }
577 *val = ixgbe_ks->tot.value.ui64;
578 break;
579
580 case MAC_STAT_IPACKETS:
581 ixgbe_ks->tpr.value.ui64 +=
582 IXGBE_READ_REG(hw, IXGBE_TPR);
583 *val = ixgbe_ks->tpr.value.ui64;
|