1 /******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37 #include "ixgbe_phy.h"
38
39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
50 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
51
52 /**
53 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
54 * @hw: pointer to the hardware structure
55 *
56 * Initialize the function pointers.
57 **/
58 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
59 {
60 struct ixgbe_phy_info *phy = &hw->phy;
61
62 DEBUGFUNC("ixgbe_init_phy_ops_generic");
63
64 /* PHY */
65 phy->ops.identify = &ixgbe_identify_phy_generic;
66 phy->ops.reset = &ixgbe_reset_phy_generic;
67 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
68 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
69 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
70 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
71 phy->ops.check_link = NULL;
72 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
73 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
74 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
75 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
76 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
77 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
78 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic;
79 phy->sfp_type = ixgbe_sfp_type_unknown;
80 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
81 return IXGBE_SUCCESS;
82 }
83
84 /**
85 * ixgbe_identify_phy_generic - Get physical layer module
86 * @hw: pointer to hardware structure
87 *
88 * Determines the physical layer module found on the current adapter.
89 **/
90 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
91 {
92 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
93 u32 phy_addr;
94 u16 ext_ability = 0;
95
96 DEBUGFUNC("ixgbe_identify_phy_generic");
97
98 if (hw->phy.type == ixgbe_phy_unknown) {
99 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
100 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
101 hw->phy.addr = phy_addr;
102 (void) ixgbe_get_phy_id(hw);
103 hw->phy.type =
104 ixgbe_get_phy_type_from_id(hw->phy.id);
105
106 if (hw->phy.type == ixgbe_phy_unknown) {
107 hw->phy.ops.read_reg(hw,
108 IXGBE_MDIO_PHY_EXT_ABILITY,
109 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
110 &ext_ability);
111 if (ext_ability &
112 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
113 IXGBE_MDIO_PHY_1000BASET_ABILITY))
114 hw->phy.type =
115 ixgbe_phy_cu_unknown;
116 else
117 hw->phy.type =
118 ixgbe_phy_generic;
119 }
120
121 status = IXGBE_SUCCESS;
122 break;
180 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
181 }
182 return status;
183 }
184
185 /**
186 * ixgbe_get_phy_type_from_id - Get the phy type
187 * @hw: pointer to hardware structure
188 *
189 **/
190 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
191 {
192 enum ixgbe_phy_type phy_type;
193
194 DEBUGFUNC("ixgbe_get_phy_type_from_id");
195
196 switch (phy_id) {
197 case TN1010_PHY_ID:
198 phy_type = ixgbe_phy_tn;
199 break;
200 case AQ1002_PHY_ID:
201 phy_type = ixgbe_phy_aq;
202 break;
203 case QT2022_PHY_ID:
204 phy_type = ixgbe_phy_qt;
205 break;
206 case ATH_PHY_ID:
207 phy_type = ixgbe_phy_nl;
208 break;
209 default:
210 phy_type = ixgbe_phy_unknown;
211 break;
212 }
213
214 DEBUGOUT1("phy type found is %d\n", phy_type);
215 return phy_type;
216 }
217
218 /**
219 * ixgbe_reset_phy_generic - Performs a PHY reset
220 * @hw: pointer to hardware structure
275 * @hw: pointer to hardware structure
276 * @reg_addr: 32 bit address of PHY register to read
277 * @phy_data: Pointer to read data from PHY register
278 **/
279 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
280 u32 device_type, u16 *phy_data)
281 {
282 u32 command;
283 u32 i;
284 u32 data;
285 s32 status = IXGBE_SUCCESS;
286 u16 gssr;
287
288 DEBUGFUNC("ixgbe_read_phy_reg_generic");
289
290 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
291 gssr = IXGBE_GSSR_PHY1_SM;
292 else
293 gssr = IXGBE_GSSR_PHY0_SM;
294
295 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
296 status = IXGBE_ERR_SWFW_SYNC;
297
298 if (status == IXGBE_SUCCESS) {
299 /* Setup and write the address cycle command */
300 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
301 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
302 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
303 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
304
305 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
306
307 /*
308 * Check every 10 usec to see if the address cycle completed.
309 * The MDI Command bit will clear when the operation is
310 * complete
311 */
312 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
313 usec_delay(10);
314
315 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
346 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
347
348 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
349 break;
350 }
351
352 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
353 DEBUGOUT("PHY read command didn't complete\n");
354 status = IXGBE_ERR_PHY;
355 } else {
356 /*
357 * Read operation is complete. Get the data
358 * from MSRWD
359 */
360 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
361 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
362 *phy_data = (u16)(data);
363 }
364 }
365
366 ixgbe_release_swfw_sync(hw, gssr);
367 }
368
369 return status;
370 }
371
372 /**
373 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
374 * @hw: pointer to hardware structure
375 * @reg_addr: 32 bit PHY register to write
376 * @device_type: 5 bit device type
377 * @phy_data: Data to write to the PHY register
378 **/
379 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
380 u32 device_type, u16 phy_data)
381 {
382 u32 command;
383 u32 i;
384 s32 status = IXGBE_SUCCESS;
385 u16 gssr;
386
387 DEBUGFUNC("ixgbe_write_phy_reg_generic");
388
389 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
390 gssr = IXGBE_GSSR_PHY1_SM;
391 else
392 gssr = IXGBE_GSSR_PHY0_SM;
393
394 if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
395 status = IXGBE_ERR_SWFW_SYNC;
396
397 if (status == IXGBE_SUCCESS) {
398 /* Put the data in the MDI single read and write data register*/
399 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
400
401 /* Setup and write the address cycle command */
402 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
403 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
404 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
405 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
406
407 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
408
409 /*
410 * Check every 10 usec to see if the address cycle completed.
411 * The MDI Command bit will clear when the operation is
412 * complete
413 */
414 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
440 /*
441 * Check every 10 usec to see if the address cycle
442 * completed. The MDI Command bit will clear when the
443 * operation is complete
444 */
445 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
446 usec_delay(10);
447
448 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
449
450 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
451 break;
452 }
453
454 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
455 DEBUGOUT("PHY address cmd didn't complete\n");
456 status = IXGBE_ERR_PHY;
457 }
458 }
459
460 ixgbe_release_swfw_sync(hw, gssr);
461 }
462
463 return status;
464 }
465
466 /**
467 * ixgbe_setup_phy_link_generic - Set and restart autoneg
468 * @hw: pointer to hardware structure
469 *
470 * Restart autonegotiation and PHY and waits for completion.
471 **/
472 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
473 {
474 s32 status = IXGBE_SUCCESS;
475 u32 time_out;
476 u32 max_time_out = 10;
477 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
478 bool autoneg = FALSE;
479 ixgbe_link_speed speed;
480
481 DEBUGFUNC("ixgbe_setup_phy_link_generic");
482
483 (void) ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
484
485 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
486 /* Set or unset auto-negotiation 10G advertisement */
487 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
488 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
489 &autoneg_reg);
490
491 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
492 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
493 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
494
495 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
496 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
497 autoneg_reg);
498 }
499
500 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
501 /* Set or unset auto-negotiation 1G advertisement */
502 hw->phy.ops.read_reg(hw,
503 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
504 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
505 &autoneg_reg);
506
507 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
508 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
509 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
510
511 hw->phy.ops.write_reg(hw,
512 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
513 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
514 autoneg_reg);
515 }
516
517 if (speed & IXGBE_LINK_SPEED_100_FULL) {
518 /* Set or unset auto-negotiation 100M advertisement */
519 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
520 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
521 &autoneg_reg);
522
523 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
524 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
525 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
526
527 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
528 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
529 autoneg_reg);
530 }
531
532 /* Restart PHY autonegotiation and wait for completion */
533 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
534 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
535
536 autoneg_reg |= IXGBE_MII_RESTART;
537
538 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
539 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
540
541 /* Wait for autonegotiation to finish */
542 for (time_out = 0; time_out < max_time_out; time_out++) {
543 usec_delay(10);
544 /* Restart PHY autonegotiation and wait for completion */
545 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
546 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
547 &autoneg_reg);
548
549 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
550 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
551 break;
552 }
553 }
554
555 if (time_out == max_time_out) {
556 status = IXGBE_ERR_LINK_SETUP;
557 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
558 }
559
560 return status;
561 }
562
563 /**
564 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
565 * @hw: pointer to hardware structure
566 * @speed: new link speed
567 * @autoneg: TRUE if autonegotiation enabled
568 **/
569 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
570 ixgbe_link_speed speed,
571 bool autoneg,
572 bool autoneg_wait_to_complete)
573 {
574 UNREFERENCED_PARAMETER(autoneg);
575 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
576
577 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
578
579 /*
580 * Clear autoneg_advertised and set new values based on input link
581 * speed.
582 */
583 hw->phy.autoneg_advertised = 0;
584
585 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
586 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
587
588 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
589 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
590
591 if (speed & IXGBE_LINK_SPEED_100_FULL)
592 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
593
594 /* Setup link based on the new speed settings */
595 hw->phy.ops.setup_link(hw);
650 u16 phy_speed = 0;
651 u16 phy_data = 0;
652
653 DEBUGFUNC("ixgbe_check_phy_link_tnx");
654
655 /* Initialize speed and link to default case */
656 *link_up = FALSE;
657 *speed = IXGBE_LINK_SPEED_10GB_FULL;
658
659 /*
660 * Check current speed and link status of the PHY register.
661 * This is a vendor specific register and may have to
662 * be changed for other copper PHYs.
663 */
664 for (time_out = 0; time_out < max_time_out; time_out++) {
665 usec_delay(10);
666 status = hw->phy.ops.read_reg(hw,
667 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
668 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
669 &phy_data);
670 phy_link = phy_data &
671 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
672 phy_speed = phy_data &
673 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
674 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
675 *link_up = TRUE;
676 if (phy_speed ==
677 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
678 *speed = IXGBE_LINK_SPEED_1GB_FULL;
679 break;
680 }
681 }
682
683 return status;
684 }
685
686 /**
687 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
688 * @hw: pointer to hardware structure
689 *
690 * Restart autonegotiation and PHY and waits for completion.
691 **/
692 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
693 {
694 s32 status = IXGBE_SUCCESS;
695 u32 time_out;
696 u32 max_time_out = 10;
697 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
698 bool autoneg = FALSE;
699 ixgbe_link_speed speed;
700
701 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
702
703 (void) ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
704
705 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
706 /* Set or unset auto-negotiation 10G advertisement */
707 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
708 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
709 &autoneg_reg);
710
711 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
712 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
713 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
714
715 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
716 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
717 autoneg_reg);
718 }
719
720 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
721 /* Set or unset auto-negotiation 1G advertisement */
722 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
723 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
748 }
749
750 /* Restart PHY autonegotiation and wait for completion */
751 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
752 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
753
754 autoneg_reg |= IXGBE_MII_RESTART;
755
756 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
757 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
758
759 /* Wait for autonegotiation to finish */
760 for (time_out = 0; time_out < max_time_out; time_out++) {
761 usec_delay(10);
762 /* Restart PHY autonegotiation and wait for completion */
763 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
764 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
765 &autoneg_reg);
766
767 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
768 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
769 break;
770 }
771 }
772
773 if (time_out == max_time_out) {
774 status = IXGBE_ERR_LINK_SETUP;
775 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
776 }
777
778 return status;
779 }
780
781 /**
782 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
783 * @hw: pointer to hardware structure
784 * @firmware_version: pointer to the PHY Firmware Version
785 **/
786 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
787 u16 *firmware_version)
788 {
789 s32 status = IXGBE_SUCCESS;
790
791 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
859 if (ret_val != IXGBE_SUCCESS)
860 goto out;
861
862 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
863 data_offset++;
864 while (!end_data) {
865 /*
866 * Read control word from PHY init contents offset
867 */
868 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
869 control = (eword & IXGBE_CONTROL_MASK_NL) >>
870 IXGBE_CONTROL_SHIFT_NL;
871 edata = eword & IXGBE_DATA_MASK_NL;
872 switch (control) {
873 case IXGBE_DELAY_NL:
874 data_offset++;
875 DEBUGOUT1("DELAY: %d MS\n", edata);
876 msec_delay(edata);
877 break;
878 case IXGBE_DATA_NL:
879 DEBUGOUT("DATA: \n");
880 data_offset++;
881 hw->eeprom.ops.read(hw, data_offset++,
882 &phy_offset);
883 for (i = 0; i < edata; i++) {
884 hw->eeprom.ops.read(hw, data_offset, &eword);
885 hw->phy.ops.write_reg(hw, phy_offset,
886 IXGBE_TWINAX_DEV, eword);
887 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
888 phy_offset);
889 data_offset++;
890 phy_offset++;
891 }
892 break;
893 case IXGBE_CONTROL_NL:
894 data_offset++;
895 DEBUGOUT("CONTROL: \n");
896 if (edata == IXGBE_CONTROL_EOL_NL) {
897 DEBUGOUT("EOL\n");
898 end_data = TRUE;
899 } else if (edata == IXGBE_CONTROL_SOL_NL) {
900 DEBUGOUT("SOL\n");
901 } else {
902 DEBUGOUT("Bad control value\n");
903 ret_val = IXGBE_ERR_PHY;
904 goto out;
905 }
906 break;
907 default:
908 DEBUGOUT("Bad control type\n");
909 ret_val = IXGBE_ERR_PHY;
910 goto out;
911 }
912 }
913
914 out:
915 return ret_val;
916 }
917
918 /**
919 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
920 * @hw: pointer to hardware structure
921 *
922 * Searches for and identifies the SFP module and assigns appropriate PHY type.
923 **/
924 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
925 {
926 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
927 u32 vendor_oui = 0;
928 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
929 u8 identifier = 0;
930 u8 comp_codes_1g = 0;
931 u8 comp_codes_10g = 0;
932 u8 oui_bytes[3] = {0, 0, 0};
933 u8 cable_tech = 0;
934 u8 cable_spec = 0;
935 u16 enforce_sfp = 0;
936
937 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
938
980 &cable_tech);
981
982 if (status == IXGBE_ERR_SWFW_SYNC ||
983 status == IXGBE_ERR_I2C ||
984 status == IXGBE_ERR_SFP_NOT_PRESENT)
985 goto err_read_i2c_eeprom;
986
987 /* ID Module
988 * =========
989 * 0 SFP_DA_CU
990 * 1 SFP_SR
991 * 2 SFP_LR
992 * 3 SFP_DA_CORE0 - 82599-specific
993 * 4 SFP_DA_CORE1 - 82599-specific
994 * 5 SFP_SR/LR_CORE0 - 82599-specific
995 * 6 SFP_SR/LR_CORE1 - 82599-specific
996 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
997 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
998 * 9 SFP_1g_cu_CORE0 - 82599-specific
999 * 10 SFP_1g_cu_CORE1 - 82599-specific
1000 */
1001 if (hw->mac.type == ixgbe_mac_82598EB) {
1002 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1003 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1004 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1005 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1006 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1007 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1008 else
1009 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1010 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1011 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1012 if (hw->bus.lan_id == 0)
1013 hw->phy.sfp_type =
1014 ixgbe_sfp_type_da_cu_core0;
1015 else
1016 hw->phy.sfp_type =
1017 ixgbe_sfp_type_da_cu_core1;
1018 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1019 hw->phy.ops.read_i2c_eeprom(
1030 } else {
1031 hw->phy.sfp_type =
1032 ixgbe_sfp_type_unknown;
1033 }
1034 } else if (comp_codes_10g &
1035 (IXGBE_SFF_10GBASESR_CAPABLE |
1036 IXGBE_SFF_10GBASELR_CAPABLE)) {
1037 if (hw->bus.lan_id == 0)
1038 hw->phy.sfp_type =
1039 ixgbe_sfp_type_srlr_core0;
1040 else
1041 hw->phy.sfp_type =
1042 ixgbe_sfp_type_srlr_core1;
1043 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1044 if (hw->bus.lan_id == 0)
1045 hw->phy.sfp_type =
1046 ixgbe_sfp_type_1g_cu_core0;
1047 else
1048 hw->phy.sfp_type =
1049 ixgbe_sfp_type_1g_cu_core1;
1050 } else {
1051 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1052 }
1053 }
1054
1055 if (hw->phy.sfp_type != stored_sfp_type)
1056 hw->phy.sfp_setup_needed = TRUE;
1057
1058 /* Determine if the SFP+ PHY is dual speed or not. */
1059 hw->phy.multispeed_fiber = FALSE;
1060 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1061 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1062 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1063 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1064 hw->phy.multispeed_fiber = TRUE;
1065
1066 /* Determine PHY vendor */
1067 if (hw->phy.type != ixgbe_phy_nl) {
1068 hw->phy.id = identifier;
1069 status = hw->phy.ops.read_i2c_eeprom(hw,
1122 ixgbe_phy_sfp_passive_unknown;
1123 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1124 hw->phy.type =
1125 ixgbe_phy_sfp_active_unknown;
1126 else
1127 hw->phy.type = ixgbe_phy_sfp_unknown;
1128 break;
1129 }
1130 }
1131
1132 /* Allow any DA cable vendor */
1133 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1134 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1135 status = IXGBE_SUCCESS;
1136 goto out;
1137 }
1138
1139 /* Verify supported 1G SFP modules */
1140 if (comp_codes_10g == 0 &&
1141 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1142 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
1143 hw->phy.type = ixgbe_phy_sfp_unsupported;
1144 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1145 goto out;
1146 }
1147
1148 /* Anything else 82598-based is supported */
1149 if (hw->mac.type == ixgbe_mac_82598EB) {
1150 status = IXGBE_SUCCESS;
1151 goto out;
1152 }
1153
1154 (void) ixgbe_get_device_caps(hw, &enforce_sfp);
1155 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1156 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1157 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
1158 /* Make sure we're a supported PHY type */
1159 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1160 status = IXGBE_SUCCESS;
1161 } else {
1162 DEBUGOUT("SFP+ module not supported\n");
1163 hw->phy.type = ixgbe_phy_sfp_unsupported;
1164 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1165 }
1166 } else {
1167 status = IXGBE_SUCCESS;
1168 }
1169 }
1170
1171 out:
1172 return status;
1173
1174 err_read_i2c_eeprom:
1175 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1176 if (hw->phy.type != ixgbe_phy_nl) {
1177 hw->phy.id = 0;
1178 hw->phy.type = ixgbe_phy_unknown;
1179 }
1180 return IXGBE_ERR_SFP_NOT_PRESENT;
1181 }
1182
1183 /**
1184 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1185 * @hw: pointer to hardware structure
1186 * @list_offset: offset to the SFP ID list
1187 * @data_offset: offset to the SFP data block
1188 *
1189 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1190 * so it returns the offsets to the phy init sequence block.
1191 **/
1192 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1193 u16 *list_offset,
1194 u16 *data_offset)
1195 {
1196 u16 sfp_id;
1197 u16 sfp_type = hw->phy.sfp_type;
1198
1199 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1200
1201 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1202 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1203
1204 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1205 return IXGBE_ERR_SFP_NOT_PRESENT;
1206
1207 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1208 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1209 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1210
1211 /*
1212 * Limiting active cables and 1G Phys must be initialized as
1213 * SR modules
1214 */
1215 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1216 sfp_type == ixgbe_sfp_type_1g_cu_core0)
1217 sfp_type = ixgbe_sfp_type_srlr_core0;
1218 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1219 sfp_type == ixgbe_sfp_type_1g_cu_core1)
1220 sfp_type = ixgbe_sfp_type_srlr_core1;
1221
1222 /* Read offset to PHY init contents */
1223 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1224
1225 if ((!*list_offset) || (*list_offset == 0xFFFF))
1226 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1227
1228 /* Shift offset to first ID word */
1229 (*list_offset)++;
1230
1231 /*
1232 * Find the matching SFP ID in the EEPROM
1233 * and program the init sequence
1234 */
1235 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1236
1237 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1238 if (sfp_id == sfp_type) {
1239 (*list_offset)++;
1285 *
1286 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1287 **/
1288 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1289 u8 eeprom_data)
1290 {
1291 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1292
1293 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1294 IXGBE_I2C_EEPROM_DEV_ADDR,
1295 eeprom_data);
1296 }
1297
1298 /**
1299 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1300 * @hw: pointer to hardware structure
1301 * @byte_offset: byte offset to read
1302 * @data: value read
1303 *
1304 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1305 * a specified deivce address.
1306 **/
1307 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1308 u8 dev_addr, u8 *data)
1309 {
1310 s32 status = IXGBE_SUCCESS;
1311 u32 max_retry = 10;
1312 u32 retry = 0;
1313 u16 swfw_mask = 0;
1314 bool nack = 1;
1315
1316 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1317
1318 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1319 swfw_mask = IXGBE_GSSR_PHY1_SM;
1320 else
1321 swfw_mask = IXGBE_GSSR_PHY0_SM;
1322
1323 do {
1324 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1325 status = IXGBE_ERR_SWFW_SYNC;
1326 goto read_byte_out;
1327 }
1328
1329 ixgbe_i2c_start(hw);
1330
1331 /* Device Address and write indication */
1332 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1333 if (status != IXGBE_SUCCESS)
1334 goto fail;
1335
1336 status = ixgbe_get_i2c_ack(hw);
1337 if (status != IXGBE_SUCCESS)
1338 goto fail;
1339
1340 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1341 if (status != IXGBE_SUCCESS)
1342 goto fail;
1343
1344 status = ixgbe_get_i2c_ack(hw);
1351 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1352 if (status != IXGBE_SUCCESS)
1353 goto fail;
1354
1355 status = ixgbe_get_i2c_ack(hw);
1356 if (status != IXGBE_SUCCESS)
1357 goto fail;
1358
1359 status = ixgbe_clock_in_i2c_byte(hw, data);
1360 if (status != IXGBE_SUCCESS)
1361 goto fail;
1362
1363 status = ixgbe_clock_out_i2c_bit(hw, nack);
1364 if (status != IXGBE_SUCCESS)
1365 goto fail;
1366
1367 ixgbe_i2c_stop(hw);
1368 break;
1369
1370 fail:
1371 ixgbe_release_swfw_sync(hw, swfw_mask);
1372 msec_delay(100);
1373 ixgbe_i2c_bus_clear(hw);
1374 retry++;
1375 if (retry < max_retry)
1376 DEBUGOUT("I2C byte read error - Retrying.\n");
1377 else
1378 DEBUGOUT("I2C byte read error.\n");
1379
1380 } while (retry < max_retry);
1381
1382 ixgbe_release_swfw_sync(hw, swfw_mask);
1383
1384 read_byte_out:
1385 return status;
1386 }
1387
1388 /**
1389 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1390 * @hw: pointer to hardware structure
1391 * @byte_offset: byte offset to write
1392 * @data: value to write
1393 *
1394 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1395 * a specified device address.
1396 **/
1397 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1398 u8 dev_addr, u8 data)
1399 {
1400 s32 status = IXGBE_SUCCESS;
1401 u32 max_retry = 1;
1402 u32 retry = 0;
1403 u16 swfw_mask = 0;
1404
1405 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1406
1407 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1408 swfw_mask = IXGBE_GSSR_PHY1_SM;
1409 else
1410 swfw_mask = IXGBE_GSSR_PHY0_SM;
1411
1412 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1413 status = IXGBE_ERR_SWFW_SYNC;
1414 goto write_byte_out;
1415 }
1416
1417 do {
1418 ixgbe_i2c_start(hw);
1419
1420 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1421 if (status != IXGBE_SUCCESS)
1422 goto fail;
1423
1424 status = ixgbe_get_i2c_ack(hw);
1425 if (status != IXGBE_SUCCESS)
1426 goto fail;
1427
1428 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1429 if (status != IXGBE_SUCCESS)
1430 goto fail;
1431
1432 status = ixgbe_get_i2c_ack(hw);
1436 status = ixgbe_clock_out_i2c_byte(hw, data);
1437 if (status != IXGBE_SUCCESS)
1438 goto fail;
1439
1440 status = ixgbe_get_i2c_ack(hw);
1441 if (status != IXGBE_SUCCESS)
1442 goto fail;
1443
1444 ixgbe_i2c_stop(hw);
1445 break;
1446
1447 fail:
1448 ixgbe_i2c_bus_clear(hw);
1449 retry++;
1450 if (retry < max_retry)
1451 DEBUGOUT("I2C byte write error - Retrying.\n");
1452 else
1453 DEBUGOUT("I2C byte write error.\n");
1454 } while (retry < max_retry);
1455
1456 ixgbe_release_swfw_sync(hw, swfw_mask);
1457
1458 write_byte_out:
1459 return status;
1460 }
1461
1462 /**
1463 * ixgbe_i2c_start - Sets I2C start condition
1464 * @hw: pointer to hardware structure
1465 *
1466 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1467 **/
1468 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1469 {
1470 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1471
1472 DEBUGFUNC("ixgbe_i2c_start");
1473
1474 /* Start condition must begin with data and clock high */
1475 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1476 (void) ixgbe_raise_i2c_clk(hw, &i2cctl);
1477
1478 /* Setup time for start condition (4.7us) */
1479 usec_delay(IXGBE_I2C_T_SU_STA);
1480
1481 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1482
1483 /* Hold time for start condition (4us) */
1484 usec_delay(IXGBE_I2C_T_HD_STA);
1485
1486 ixgbe_lower_i2c_clk(hw, &i2cctl);
1487
1488 /* Minimum low period of clock is 4.7 us */
1489 usec_delay(IXGBE_I2C_T_LOW);
1490
1491 }
1492
1493 /**
1494 * ixgbe_i2c_stop - Sets I2C stop condition
1495 * @hw: pointer to hardware structure
1496 *
1497 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1498 **/
1499 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1500 {
1501 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1502
1503 DEBUGFUNC("ixgbe_i2c_stop");
1504
1505 /* Stop condition must begin with data low and clock high */
1506 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1507 (void) ixgbe_raise_i2c_clk(hw, &i2cctl);
1508
1509 /* Setup time for stop condition (4us) */
1510 usec_delay(IXGBE_I2C_T_SU_STO);
1511
1512 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1513
1514 /* bus free time between stop and start (4.7us)*/
1515 usec_delay(IXGBE_I2C_T_BUF);
1516 }
1517
1518 /**
1519 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1520 * @hw: pointer to hardware structure
1521 * @data: data byte to clock in
1522 *
1523 * Clocks in one byte data via I2C data/clock
1524 **/
1525 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1526 {
1527 s32 status = IXGBE_SUCCESS;
1528 s32 i;
1529 bool bit = 0;
1530
1531 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1532
1533 for (i = 7; i >= 0; i--) {
1534 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1535 *data |= bit << i;
1536
1537 if (status != IXGBE_SUCCESS)
1538 break;
1539 }
1540
1541 return status;
1542 }
1543
1544 /**
1545 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1546 * @hw: pointer to hardware structure
1547 * @data: data byte clocked out
1548 *
1549 * Clocks out one byte data via I2C data/clock
1550 **/
1551 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1552 {
1553 s32 status = IXGBE_SUCCESS;
1554 s32 i;
1555 u32 i2cctl;
1556 bool bit = 0;
1557
1558 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1559
1560 for (i = 7; i >= 0; i--) {
1561 bit = (data >> i) & 0x1;
1562 status = ixgbe_clock_out_i2c_bit(hw, bit);
1563
1564 if (status != IXGBE_SUCCESS)
1565 break;
1566 }
1567
1568 /* Release SDA line (set high) */
1569 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1570 i2cctl |= IXGBE_I2C_DATA_OUT;
1571 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1572
1573 return status;
1574 }
1575
1576 /**
1577 * ixgbe_get_i2c_ack - Polls for I2C ACK
1578 * @hw: pointer to hardware structure
1579 *
1580 * Clocks in/out one bit via I2C data/clock
1581 **/
1582 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1583 {
1584 s32 status;
1585 u32 i = 0;
1586 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1587 u32 timeout = 10;
1588 bool ack = 1;
1589
1590 DEBUGFUNC("ixgbe_get_i2c_ack");
1591
1592 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1593
1594 if (status != IXGBE_SUCCESS)
1595 goto out;
1596
1597 /* Minimum high period of clock is 4us */
1598 usec_delay(IXGBE_I2C_T_HIGH);
1599
1600 /* Poll for ACK. Note that ACK in I2C spec is
1601 * transition from 1 to 0 */
1602 for (i = 0; i < timeout; i++) {
1603 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1604 ack = ixgbe_get_i2c_data(&i2cctl);
1605
1606 usec_delay(1);
1607 if (ack == 0)
1608 break;
1609 }
1610
1611 if (ack == 1) {
1612 DEBUGOUT("I2C ack was not received.\n");
1613 status = IXGBE_ERR_I2C;
1614 }
1615
1616 ixgbe_lower_i2c_clk(hw, &i2cctl);
1617
1618 /* Minimum low period of clock is 4.7 us */
1619 usec_delay(IXGBE_I2C_T_LOW);
1620
1621 out:
1622 return status;
1623 }
1624
1625 /**
1626 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1627 * @hw: pointer to hardware structure
1628 * @data: read data value
1629 *
1630 * Clocks in one bit via I2C data/clock
1631 **/
1632 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1633 {
1634 s32 status;
1635 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1636
1637 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1638
1639 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1640
1641 /* Minimum high period of clock is 4us */
1642 usec_delay(IXGBE_I2C_T_HIGH);
1643
1644 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1645 *data = ixgbe_get_i2c_data(&i2cctl);
1646
1647 ixgbe_lower_i2c_clk(hw, &i2cctl);
1648
1649 /* Minimum low period of clock is 4.7 us */
1650 usec_delay(IXGBE_I2C_T_LOW);
1651
1652 return status;
1653 }
1654
1655 /**
1656 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1657 * @hw: pointer to hardware structure
1658 * @data: data value to write
1659 *
1660 * Clocks out one bit via I2C data/clock
1661 **/
1662 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1663 {
1664 s32 status;
1665 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1666
1667 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1668
1669 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1670 if (status == IXGBE_SUCCESS) {
1671 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1672
1673 /* Minimum high period of clock is 4us */
1674 usec_delay(IXGBE_I2C_T_HIGH);
1675
1676 ixgbe_lower_i2c_clk(hw, &i2cctl);
1677
1678 /* Minimum low period of clock is 4.7 us.
1679 * This also takes care of the data hold time.
1680 */
1681 usec_delay(IXGBE_I2C_T_LOW);
1682 } else {
1683 status = IXGBE_ERR_I2C;
1684 DEBUGOUT1("I2C data was not set to %X\n", data);
1685 }
1686
1687 return status;
1688 }
1689 /**
1690 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1691 * @hw: pointer to hardware structure
1692 * @i2cctl: Current value of I2CCTL register
1693 *
1694 * Raises the I2C clock line '0'->'1'
1695 **/
1696 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1697 {
1698 s32 status = IXGBE_SUCCESS;
1699
1700 DEBUGFUNC("ixgbe_raise_i2c_clk");
1701
1702 *i2cctl |= IXGBE_I2C_CLK_OUT;
1703
1704 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1705
1706 /* SCL rise time (1000ns) */
1707 usec_delay(IXGBE_I2C_T_RISE);
1708
1709 return status;
1710 }
1711
1712 /**
1713 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1714 * @hw: pointer to hardware structure
1715 * @i2cctl: Current value of I2CCTL register
1716 *
1717 * Lowers the I2C clock line '1'->'0'
1718 **/
1719 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1720 {
1721
1722 DEBUGFUNC("ixgbe_lower_i2c_clk");
1723
1724 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1725
1726 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1727
1728 /* SCL fall time (300ns) */
1729 usec_delay(IXGBE_I2C_T_FALL);
1730 }
1731
1732 /**
1733 * ixgbe_set_i2c_data - Sets the I2C data bit
1734 * @hw: pointer to hardware structure
1735 * @i2cctl: Current value of I2CCTL register
1736 * @data: I2C data value (0 or 1) to set
1737 *
1738 * Sets the I2C data bit
1739 **/
1740 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1741 {
1742 s32 status = IXGBE_SUCCESS;
1743
1744 DEBUGFUNC("ixgbe_set_i2c_data");
1745
1746 if (data)
1747 *i2cctl |= IXGBE_I2C_DATA_OUT;
1748 else
1749 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1750
1751 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1752
1753 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1754 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1755
1756 /* Verify data was set correctly */
1757 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1758 if (data != ixgbe_get_i2c_data(i2cctl)) {
1759 status = IXGBE_ERR_I2C;
1760 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1761 }
1762
1763 return status;
1764 }
1765
1766 /**
1767 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1768 * @hw: pointer to hardware structure
1769 * @i2cctl: Current value of I2CCTL register
1770 *
1771 * Returns the I2C data bit value
1783
1784 return data;
1785 }
1786
1787 /**
1788 * ixgbe_i2c_bus_clear - Clears the I2C bus
1789 * @hw: pointer to hardware structure
1790 *
1791 * Clears the I2C bus by sending nine clock pulses.
1792 * Used when data line is stuck low.
1793 **/
1794 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1795 {
1796 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1797 u32 i;
1798
1799 DEBUGFUNC("ixgbe_i2c_bus_clear");
1800
1801 ixgbe_i2c_start(hw);
1802
1803 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1804
1805 for (i = 0; i < 9; i++) {
1806 (void) ixgbe_raise_i2c_clk(hw, &i2cctl);
1807
1808 /* Min high period of clock is 4us */
1809 usec_delay(IXGBE_I2C_T_HIGH);
1810
1811 ixgbe_lower_i2c_clk(hw, &i2cctl);
1812
1813 /* Min low period of clock is 4.7us*/
1814 usec_delay(IXGBE_I2C_T_LOW);
1815 }
1816
1817 ixgbe_i2c_start(hw);
1818
1819 /* Put the i2c bus back to default state */
1820 ixgbe_i2c_stop(hw);
1821 }
1822
1823 /**
1824 * ixgbe_tn_check_overtemp - Checks if an overtemp occured.
1825 * @hw: pointer to hardware structure
1826 *
1827 * Checks if the LASI temp alarm status was triggered due to overtemp
1828 **/
1829 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1830 {
1831 s32 status = IXGBE_SUCCESS;
1832 u16 phy_data = 0;
1833
1834 DEBUGFUNC("ixgbe_tn_check_overtemp");
1835
1836 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1837 goto out;
1838
1839 /* Check that the LASI temp alarm status was triggered */
1840 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1841 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1842
1843 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1844 goto out;
|
1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37 #include "ixgbe_phy.h"
38
39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
50
51 /**
52 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
53 * @hw: pointer to the hardware structure
54 *
55 * Initialize the function pointers.
56 **/
57 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
58 {
59 struct ixgbe_phy_info *phy = &hw->phy;
60
61 DEBUGFUNC("ixgbe_init_phy_ops_generic");
62
63 /* PHY */
64 phy->ops.identify = &ixgbe_identify_phy_generic;
65 phy->ops.reset = &ixgbe_reset_phy_generic;
66 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
67 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
68 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
69 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
70 phy->ops.check_link = NULL;
71 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
72 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
73 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
74 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
75 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
76 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
77 phy->ops.identify_sfp = &ixgbe_identify_module_generic;
78 phy->sfp_type = ixgbe_sfp_type_unknown;
79 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
80 return IXGBE_SUCCESS;
81 }
82
83 /**
84 * ixgbe_identify_phy_generic - Get physical layer module
85 * @hw: pointer to hardware structure
86 *
87 * Determines the physical layer module found on the current adapter.
88 **/
89 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
90 {
91 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
92 u32 phy_addr;
93 u16 ext_ability = 0;
94
95 DEBUGFUNC("ixgbe_identify_phy_generic");
96
97 if (hw->phy.type == ixgbe_phy_unknown) {
98 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
99 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
100 hw->phy.addr = phy_addr;
101 ixgbe_get_phy_id(hw);
102 hw->phy.type =
103 ixgbe_get_phy_type_from_id(hw->phy.id);
104
105 if (hw->phy.type == ixgbe_phy_unknown) {
106 hw->phy.ops.read_reg(hw,
107 IXGBE_MDIO_PHY_EXT_ABILITY,
108 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
109 &ext_ability);
110 if (ext_ability &
111 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
112 IXGBE_MDIO_PHY_1000BASET_ABILITY))
113 hw->phy.type =
114 ixgbe_phy_cu_unknown;
115 else
116 hw->phy.type =
117 ixgbe_phy_generic;
118 }
119
120 status = IXGBE_SUCCESS;
121 break;
179 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
180 }
181 return status;
182 }
183
184 /**
185 * ixgbe_get_phy_type_from_id - Get the phy type
186 * @hw: pointer to hardware structure
187 *
188 **/
189 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
190 {
191 enum ixgbe_phy_type phy_type;
192
193 DEBUGFUNC("ixgbe_get_phy_type_from_id");
194
195 switch (phy_id) {
196 case TN1010_PHY_ID:
197 phy_type = ixgbe_phy_tn;
198 break;
199 case X540_PHY_ID:
200 phy_type = ixgbe_phy_aq;
201 break;
202 case QT2022_PHY_ID:
203 phy_type = ixgbe_phy_qt;
204 break;
205 case ATH_PHY_ID:
206 phy_type = ixgbe_phy_nl;
207 break;
208 default:
209 phy_type = ixgbe_phy_unknown;
210 break;
211 }
212
213 DEBUGOUT1("phy type found is %d\n", phy_type);
214 return phy_type;
215 }
216
217 /**
218 * ixgbe_reset_phy_generic - Performs a PHY reset
219 * @hw: pointer to hardware structure
274 * @hw: pointer to hardware structure
275 * @reg_addr: 32 bit address of PHY register to read
276 * @phy_data: Pointer to read data from PHY register
277 **/
278 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
279 u32 device_type, u16 *phy_data)
280 {
281 u32 command;
282 u32 i;
283 u32 data;
284 s32 status = IXGBE_SUCCESS;
285 u16 gssr;
286
287 DEBUGFUNC("ixgbe_read_phy_reg_generic");
288
289 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
290 gssr = IXGBE_GSSR_PHY1_SM;
291 else
292 gssr = IXGBE_GSSR_PHY0_SM;
293
294 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
295 status = IXGBE_ERR_SWFW_SYNC;
296
297 if (status == IXGBE_SUCCESS) {
298 /* Setup and write the address cycle command */
299 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
300 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
301 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
302 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
303
304 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
305
306 /*
307 * Check every 10 usec to see if the address cycle completed.
308 * The MDI Command bit will clear when the operation is
309 * complete
310 */
311 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
312 usec_delay(10);
313
314 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
345 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
346
347 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
348 break;
349 }
350
351 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
352 DEBUGOUT("PHY read command didn't complete\n");
353 status = IXGBE_ERR_PHY;
354 } else {
355 /*
356 * Read operation is complete. Get the data
357 * from MSRWD
358 */
359 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
360 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
361 *phy_data = (u16)(data);
362 }
363 }
364
365 hw->mac.ops.release_swfw_sync(hw, gssr);
366 }
367
368 return status;
369 }
370
371 /**
372 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
373 * @hw: pointer to hardware structure
374 * @reg_addr: 32 bit PHY register to write
375 * @device_type: 5 bit device type
376 * @phy_data: Data to write to the PHY register
377 **/
378 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
379 u32 device_type, u16 phy_data)
380 {
381 u32 command;
382 u32 i;
383 s32 status = IXGBE_SUCCESS;
384 u16 gssr;
385
386 DEBUGFUNC("ixgbe_write_phy_reg_generic");
387
388 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
389 gssr = IXGBE_GSSR_PHY1_SM;
390 else
391 gssr = IXGBE_GSSR_PHY0_SM;
392
393 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
394 status = IXGBE_ERR_SWFW_SYNC;
395
396 if (status == IXGBE_SUCCESS) {
397 /* Put the data in the MDI single read and write data register*/
398 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
399
400 /* Setup and write the address cycle command */
401 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
402 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
403 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
404 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
405
406 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
407
408 /*
409 * Check every 10 usec to see if the address cycle completed.
410 * The MDI Command bit will clear when the operation is
411 * complete
412 */
413 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
439 /*
440 * Check every 10 usec to see if the address cycle
441 * completed. The MDI Command bit will clear when the
442 * operation is complete
443 */
444 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
445 usec_delay(10);
446
447 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
448
449 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
450 break;
451 }
452
453 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
454 DEBUGOUT("PHY address cmd didn't complete\n");
455 status = IXGBE_ERR_PHY;
456 }
457 }
458
459 hw->mac.ops.release_swfw_sync(hw, gssr);
460 }
461
462 return status;
463 }
464
465 /**
466 * ixgbe_setup_phy_link_generic - Set and restart autoneg
467 * @hw: pointer to hardware structure
468 *
469 * Restart autonegotiation and PHY and waits for completion.
470 **/
471 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
472 {
473 s32 status = IXGBE_SUCCESS;
474 u32 time_out;
475 u32 max_time_out = 10;
476 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
477 bool autoneg = FALSE;
478 ixgbe_link_speed speed;
479
480 DEBUGFUNC("ixgbe_setup_phy_link_generic");
481
482 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
483
484 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
485 /* Set or unset auto-negotiation 10G advertisement */
486 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
487 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
488 &autoneg_reg);
489
490 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
491 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
492 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
493
494 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
495 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
496 autoneg_reg);
497 }
498
499 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
500 /* Set or unset auto-negotiation 1G advertisement */
501 hw->phy.ops.read_reg(hw,
502 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
503 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
504 &autoneg_reg);
505
506 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
507 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
508 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
509
510 hw->phy.ops.write_reg(hw,
511 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
512 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
513 autoneg_reg);
514 }
515
516 if (speed & IXGBE_LINK_SPEED_100_FULL) {
517 /* Set or unset auto-negotiation 100M advertisement */
518 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
519 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
520 &autoneg_reg);
521
522 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
523 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
524 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
525 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
526
527 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
528 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
529 autoneg_reg);
530 }
531
532 /* Restart PHY autonegotiation and wait for completion */
533 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
534 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
535
536 autoneg_reg |= IXGBE_MII_RESTART;
537
538 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
539 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
540
541 /* Wait for autonegotiation to finish */
542 for (time_out = 0; time_out < max_time_out; time_out++) {
543 usec_delay(10);
544 /* Restart PHY autonegotiation and wait for completion */
545 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
546 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
547 &autoneg_reg);
548
549 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
550 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
551 break;
552 }
553
554 if (time_out == max_time_out) {
555 status = IXGBE_ERR_LINK_SETUP;
556 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
557 }
558
559 return status;
560 }
561
562 /**
563 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
564 * @hw: pointer to hardware structure
565 * @speed: new link speed
566 * @autoneg: TRUE if autonegotiation enabled
567 **/
568 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
569 ixgbe_link_speed speed,
570 bool autoneg,
571 bool autoneg_wait_to_complete)
572 {
573 UNREFERENCED_2PARAMETER(autoneg, autoneg_wait_to_complete);
574
575 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
576
577 /*
578 * Clear autoneg_advertised and set new values based on input link
579 * speed.
580 */
581 hw->phy.autoneg_advertised = 0;
582
583 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
584 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
585
586 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
587 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
588
589 if (speed & IXGBE_LINK_SPEED_100_FULL)
590 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
591
592 /* Setup link based on the new speed settings */
593 hw->phy.ops.setup_link(hw);
648 u16 phy_speed = 0;
649 u16 phy_data = 0;
650
651 DEBUGFUNC("ixgbe_check_phy_link_tnx");
652
653 /* Initialize speed and link to default case */
654 *link_up = FALSE;
655 *speed = IXGBE_LINK_SPEED_10GB_FULL;
656
657 /*
658 * Check current speed and link status of the PHY register.
659 * This is a vendor specific register and may have to
660 * be changed for other copper PHYs.
661 */
662 for (time_out = 0; time_out < max_time_out; time_out++) {
663 usec_delay(10);
664 status = hw->phy.ops.read_reg(hw,
665 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
666 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
667 &phy_data);
668 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
669 phy_speed = phy_data &
670 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
671 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
672 *link_up = TRUE;
673 if (phy_speed ==
674 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
675 *speed = IXGBE_LINK_SPEED_1GB_FULL;
676 break;
677 }
678 }
679
680 return status;
681 }
682
683 /**
684 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
685 * @hw: pointer to hardware structure
686 *
687 * Restart autonegotiation and PHY and waits for completion.
688 **/
689 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
690 {
691 s32 status = IXGBE_SUCCESS;
692 u32 time_out;
693 u32 max_time_out = 10;
694 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
695 bool autoneg = FALSE;
696 ixgbe_link_speed speed;
697
698 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
699
700 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
701
702 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
703 /* Set or unset auto-negotiation 10G advertisement */
704 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
705 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
706 &autoneg_reg);
707
708 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
709 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
710 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
711
712 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
713 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
714 autoneg_reg);
715 }
716
717 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
718 /* Set or unset auto-negotiation 1G advertisement */
719 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
720 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
745 }
746
747 /* Restart PHY autonegotiation and wait for completion */
748 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
749 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
750
751 autoneg_reg |= IXGBE_MII_RESTART;
752
753 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
754 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
755
756 /* Wait for autonegotiation to finish */
757 for (time_out = 0; time_out < max_time_out; time_out++) {
758 usec_delay(10);
759 /* Restart PHY autonegotiation and wait for completion */
760 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
761 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
762 &autoneg_reg);
763
764 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
765 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
766 break;
767 }
768
769 if (time_out == max_time_out) {
770 status = IXGBE_ERR_LINK_SETUP;
771 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
772 }
773
774 return status;
775 }
776
777 /**
778 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
779 * @hw: pointer to hardware structure
780 * @firmware_version: pointer to the PHY Firmware Version
781 **/
782 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
783 u16 *firmware_version)
784 {
785 s32 status = IXGBE_SUCCESS;
786
787 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
855 if (ret_val != IXGBE_SUCCESS)
856 goto out;
857
858 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
859 data_offset++;
860 while (!end_data) {
861 /*
862 * Read control word from PHY init contents offset
863 */
864 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
865 control = (eword & IXGBE_CONTROL_MASK_NL) >>
866 IXGBE_CONTROL_SHIFT_NL;
867 edata = eword & IXGBE_DATA_MASK_NL;
868 switch (control) {
869 case IXGBE_DELAY_NL:
870 data_offset++;
871 DEBUGOUT1("DELAY: %d MS\n", edata);
872 msec_delay(edata);
873 break;
874 case IXGBE_DATA_NL:
875 DEBUGOUT("DATA:\n");
876 data_offset++;
877 hw->eeprom.ops.read(hw, data_offset++,
878 &phy_offset);
879 for (i = 0; i < edata; i++) {
880 hw->eeprom.ops.read(hw, data_offset, &eword);
881 hw->phy.ops.write_reg(hw, phy_offset,
882 IXGBE_TWINAX_DEV, eword);
883 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
884 phy_offset);
885 data_offset++;
886 phy_offset++;
887 }
888 break;
889 case IXGBE_CONTROL_NL:
890 data_offset++;
891 DEBUGOUT("CONTROL:\n");
892 if (edata == IXGBE_CONTROL_EOL_NL) {
893 DEBUGOUT("EOL\n");
894 end_data = TRUE;
895 } else if (edata == IXGBE_CONTROL_SOL_NL) {
896 DEBUGOUT("SOL\n");
897 } else {
898 DEBUGOUT("Bad control value\n");
899 ret_val = IXGBE_ERR_PHY;
900 goto out;
901 }
902 break;
903 default:
904 DEBUGOUT("Bad control type\n");
905 ret_val = IXGBE_ERR_PHY;
906 goto out;
907 }
908 }
909
910 out:
911 return ret_val;
912 }
913
914 /**
915 * ixgbe_identify_module_generic - Identifies module type
916 * @hw: pointer to hardware structure
917 *
918 * Determines HW type and calls appropriate function.
919 **/
920 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
921 {
922 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
923
924 DEBUGFUNC("ixgbe_identify_module_generic");
925
926 switch (hw->mac.ops.get_media_type(hw)) {
927 case ixgbe_media_type_fiber:
928 status = ixgbe_identify_sfp_module_generic(hw);
929 break;
930
931
932 default:
933 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
934 status = IXGBE_ERR_SFP_NOT_PRESENT;
935 break;
936 }
937
938 return status;
939 }
940
941 /**
942 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
943 * @hw: pointer to hardware structure
944 *
945 * Searches for and identifies the SFP module and assigns appropriate PHY type.
946 **/
947 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
948 {
949 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
950 u32 vendor_oui = 0;
951 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
952 u8 identifier = 0;
953 u8 comp_codes_1g = 0;
954 u8 comp_codes_10g = 0;
955 u8 oui_bytes[3] = {0, 0, 0};
956 u8 cable_tech = 0;
957 u8 cable_spec = 0;
958 u16 enforce_sfp = 0;
959
960 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
961
1003 &cable_tech);
1004
1005 if (status == IXGBE_ERR_SWFW_SYNC ||
1006 status == IXGBE_ERR_I2C ||
1007 status == IXGBE_ERR_SFP_NOT_PRESENT)
1008 goto err_read_i2c_eeprom;
1009
1010 /* ID Module
1011 * =========
1012 * 0 SFP_DA_CU
1013 * 1 SFP_SR
1014 * 2 SFP_LR
1015 * 3 SFP_DA_CORE0 - 82599-specific
1016 * 4 SFP_DA_CORE1 - 82599-specific
1017 * 5 SFP_SR/LR_CORE0 - 82599-specific
1018 * 6 SFP_SR/LR_CORE1 - 82599-specific
1019 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1020 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1021 * 9 SFP_1g_cu_CORE0 - 82599-specific
1022 * 10 SFP_1g_cu_CORE1 - 82599-specific
1023 * 11 SFP_1g_sx_CORE0 - 82599-specific
1024 * 12 SFP_1g_sx_CORE1 - 82599-specific
1025 */
1026 if (hw->mac.type == ixgbe_mac_82598EB) {
1027 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1028 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1029 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1030 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1031 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1032 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1033 else
1034 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1035 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1036 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1037 if (hw->bus.lan_id == 0)
1038 hw->phy.sfp_type =
1039 ixgbe_sfp_type_da_cu_core0;
1040 else
1041 hw->phy.sfp_type =
1042 ixgbe_sfp_type_da_cu_core1;
1043 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1044 hw->phy.ops.read_i2c_eeprom(
1055 } else {
1056 hw->phy.sfp_type =
1057 ixgbe_sfp_type_unknown;
1058 }
1059 } else if (comp_codes_10g &
1060 (IXGBE_SFF_10GBASESR_CAPABLE |
1061 IXGBE_SFF_10GBASELR_CAPABLE)) {
1062 if (hw->bus.lan_id == 0)
1063 hw->phy.sfp_type =
1064 ixgbe_sfp_type_srlr_core0;
1065 else
1066 hw->phy.sfp_type =
1067 ixgbe_sfp_type_srlr_core1;
1068 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1069 if (hw->bus.lan_id == 0)
1070 hw->phy.sfp_type =
1071 ixgbe_sfp_type_1g_cu_core0;
1072 else
1073 hw->phy.sfp_type =
1074 ixgbe_sfp_type_1g_cu_core1;
1075 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1076 if (hw->bus.lan_id == 0)
1077 hw->phy.sfp_type =
1078 ixgbe_sfp_type_1g_sx_core0;
1079 else
1080 hw->phy.sfp_type =
1081 ixgbe_sfp_type_1g_sx_core1;
1082 } else {
1083 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1084 }
1085 }
1086
1087 if (hw->phy.sfp_type != stored_sfp_type)
1088 hw->phy.sfp_setup_needed = TRUE;
1089
1090 /* Determine if the SFP+ PHY is dual speed or not. */
1091 hw->phy.multispeed_fiber = FALSE;
1092 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1093 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1094 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1095 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1096 hw->phy.multispeed_fiber = TRUE;
1097
1098 /* Determine PHY vendor */
1099 if (hw->phy.type != ixgbe_phy_nl) {
1100 hw->phy.id = identifier;
1101 status = hw->phy.ops.read_i2c_eeprom(hw,
1154 ixgbe_phy_sfp_passive_unknown;
1155 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1156 hw->phy.type =
1157 ixgbe_phy_sfp_active_unknown;
1158 else
1159 hw->phy.type = ixgbe_phy_sfp_unknown;
1160 break;
1161 }
1162 }
1163
1164 /* Allow any DA cable vendor */
1165 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1166 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1167 status = IXGBE_SUCCESS;
1168 goto out;
1169 }
1170
1171 /* Verify supported 1G SFP modules */
1172 if (comp_codes_10g == 0 &&
1173 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1174 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1175 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1176 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1177 hw->phy.type = ixgbe_phy_sfp_unsupported;
1178 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1179 goto out;
1180 }
1181
1182 /* Anything else 82598-based is supported */
1183 if (hw->mac.type == ixgbe_mac_82598EB) {
1184 status = IXGBE_SUCCESS;
1185 goto out;
1186 }
1187
1188 ixgbe_get_device_caps(hw, &enforce_sfp);
1189 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1190 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1191 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1192 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
1193 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1194 /* Make sure we're a supported PHY type */
1195 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1196 status = IXGBE_SUCCESS;
1197 } else {
1198 if (hw->allow_unsupported_sfp == TRUE) {
1199 EWARN(hw, "WARNING: Intel (R) Network "
1200 "Connections are quality tested "
1201 "using Intel (R) Ethernet Optics."
1202 " Using untested modules is not "
1203 "supported and may cause unstable"
1204 " operation or damage to the "
1205 "module or the adapter. Intel "
1206 "Corporation is not responsible "
1207 "for any harm caused by using "
1208 "untested modules.\n", status);
1209 status = IXGBE_SUCCESS;
1210 } else {
1211 DEBUGOUT("SFP+ module not supported\n");
1212 hw->phy.type =
1213 ixgbe_phy_sfp_unsupported;
1214 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1215 }
1216 }
1217 } else {
1218 status = IXGBE_SUCCESS;
1219 }
1220 }
1221
1222 out:
1223 return status;
1224
1225 err_read_i2c_eeprom:
1226 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1227 if (hw->phy.type != ixgbe_phy_nl) {
1228 hw->phy.id = 0;
1229 hw->phy.type = ixgbe_phy_unknown;
1230 }
1231 return IXGBE_ERR_SFP_NOT_PRESENT;
1232 }
1233
1234
1235
1236 /**
1237 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1238 * @hw: pointer to hardware structure
1239 * @list_offset: offset to the SFP ID list
1240 * @data_offset: offset to the SFP data block
1241 *
1242 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1243 * so it returns the offsets to the phy init sequence block.
1244 **/
1245 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1246 u16 *list_offset,
1247 u16 *data_offset)
1248 {
1249 u16 sfp_id;
1250 u16 sfp_type = hw->phy.sfp_type;
1251
1252 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1253
1254 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1255 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1256
1257 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1258 return IXGBE_ERR_SFP_NOT_PRESENT;
1259
1260 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1261 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1262 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1263
1264 /*
1265 * Limiting active cables and 1G Phys must be initialized as
1266 * SR modules
1267 */
1268 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1269 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1270 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1271 sfp_type = ixgbe_sfp_type_srlr_core0;
1272 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1273 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1274 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1275 sfp_type = ixgbe_sfp_type_srlr_core1;
1276
1277 /* Read offset to PHY init contents */
1278 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1279
1280 if ((!*list_offset) || (*list_offset == 0xFFFF))
1281 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1282
1283 /* Shift offset to first ID word */
1284 (*list_offset)++;
1285
1286 /*
1287 * Find the matching SFP ID in the EEPROM
1288 * and program the init sequence
1289 */
1290 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1291
1292 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1293 if (sfp_id == sfp_type) {
1294 (*list_offset)++;
1340 *
1341 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1342 **/
1343 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1344 u8 eeprom_data)
1345 {
1346 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1347
1348 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1349 IXGBE_I2C_EEPROM_DEV_ADDR,
1350 eeprom_data);
1351 }
1352
1353 /**
1354 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1355 * @hw: pointer to hardware structure
1356 * @byte_offset: byte offset to read
1357 * @data: value read
1358 *
1359 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1360 * a specified device address.
1361 **/
1362 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1363 u8 dev_addr, u8 *data)
1364 {
1365 s32 status = IXGBE_SUCCESS;
1366 u32 max_retry = 10;
1367 u32 retry = 0;
1368 u16 swfw_mask = 0;
1369 bool nack = 1;
1370 *data = 0;
1371
1372 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1373
1374 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1375 swfw_mask = IXGBE_GSSR_PHY1_SM;
1376 else
1377 swfw_mask = IXGBE_GSSR_PHY0_SM;
1378
1379 do {
1380 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1381 != IXGBE_SUCCESS) {
1382 status = IXGBE_ERR_SWFW_SYNC;
1383 goto read_byte_out;
1384 }
1385
1386 ixgbe_i2c_start(hw);
1387
1388 /* Device Address and write indication */
1389 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1390 if (status != IXGBE_SUCCESS)
1391 goto fail;
1392
1393 status = ixgbe_get_i2c_ack(hw);
1394 if (status != IXGBE_SUCCESS)
1395 goto fail;
1396
1397 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1398 if (status != IXGBE_SUCCESS)
1399 goto fail;
1400
1401 status = ixgbe_get_i2c_ack(hw);
1408 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1409 if (status != IXGBE_SUCCESS)
1410 goto fail;
1411
1412 status = ixgbe_get_i2c_ack(hw);
1413 if (status != IXGBE_SUCCESS)
1414 goto fail;
1415
1416 status = ixgbe_clock_in_i2c_byte(hw, data);
1417 if (status != IXGBE_SUCCESS)
1418 goto fail;
1419
1420 status = ixgbe_clock_out_i2c_bit(hw, nack);
1421 if (status != IXGBE_SUCCESS)
1422 goto fail;
1423
1424 ixgbe_i2c_stop(hw);
1425 break;
1426
1427 fail:
1428 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1429 msec_delay(100);
1430 ixgbe_i2c_bus_clear(hw);
1431 retry++;
1432 if (retry < max_retry)
1433 DEBUGOUT("I2C byte read error - Retrying.\n");
1434 else
1435 DEBUGOUT("I2C byte read error.\n");
1436
1437 } while (retry < max_retry);
1438
1439 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1440
1441 read_byte_out:
1442 return status;
1443 }
1444
1445 /**
1446 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1447 * @hw: pointer to hardware structure
1448 * @byte_offset: byte offset to write
1449 * @data: value to write
1450 *
1451 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1452 * a specified device address.
1453 **/
1454 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1455 u8 dev_addr, u8 data)
1456 {
1457 s32 status = IXGBE_SUCCESS;
1458 u32 max_retry = 1;
1459 u32 retry = 0;
1460 u16 swfw_mask = 0;
1461
1462 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1463
1464 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1465 swfw_mask = IXGBE_GSSR_PHY1_SM;
1466 else
1467 swfw_mask = IXGBE_GSSR_PHY0_SM;
1468
1469 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1470 status = IXGBE_ERR_SWFW_SYNC;
1471 goto write_byte_out;
1472 }
1473
1474 do {
1475 ixgbe_i2c_start(hw);
1476
1477 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1478 if (status != IXGBE_SUCCESS)
1479 goto fail;
1480
1481 status = ixgbe_get_i2c_ack(hw);
1482 if (status != IXGBE_SUCCESS)
1483 goto fail;
1484
1485 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1486 if (status != IXGBE_SUCCESS)
1487 goto fail;
1488
1489 status = ixgbe_get_i2c_ack(hw);
1493 status = ixgbe_clock_out_i2c_byte(hw, data);
1494 if (status != IXGBE_SUCCESS)
1495 goto fail;
1496
1497 status = ixgbe_get_i2c_ack(hw);
1498 if (status != IXGBE_SUCCESS)
1499 goto fail;
1500
1501 ixgbe_i2c_stop(hw);
1502 break;
1503
1504 fail:
1505 ixgbe_i2c_bus_clear(hw);
1506 retry++;
1507 if (retry < max_retry)
1508 DEBUGOUT("I2C byte write error - Retrying.\n");
1509 else
1510 DEBUGOUT("I2C byte write error.\n");
1511 } while (retry < max_retry);
1512
1513 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1514
1515 write_byte_out:
1516 return status;
1517 }
1518
1519 /**
1520 * ixgbe_i2c_start - Sets I2C start condition
1521 * @hw: pointer to hardware structure
1522 *
1523 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1524 **/
1525 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1526 {
1527 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1528
1529 DEBUGFUNC("ixgbe_i2c_start");
1530
1531 /* Start condition must begin with data and clock high */
1532 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1533 ixgbe_raise_i2c_clk(hw, &i2cctl);
1534
1535 /* Setup time for start condition (4.7us) */
1536 usec_delay(IXGBE_I2C_T_SU_STA);
1537
1538 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1539
1540 /* Hold time for start condition (4us) */
1541 usec_delay(IXGBE_I2C_T_HD_STA);
1542
1543 ixgbe_lower_i2c_clk(hw, &i2cctl);
1544
1545 /* Minimum low period of clock is 4.7 us */
1546 usec_delay(IXGBE_I2C_T_LOW);
1547
1548 }
1549
1550 /**
1551 * ixgbe_i2c_stop - Sets I2C stop condition
1552 * @hw: pointer to hardware structure
1553 *
1554 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1555 **/
1556 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1557 {
1558 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1559
1560 DEBUGFUNC("ixgbe_i2c_stop");
1561
1562 /* Stop condition must begin with data low and clock high */
1563 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1564 ixgbe_raise_i2c_clk(hw, &i2cctl);
1565
1566 /* Setup time for stop condition (4us) */
1567 usec_delay(IXGBE_I2C_T_SU_STO);
1568
1569 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1570
1571 /* bus free time between stop and start (4.7us)*/
1572 usec_delay(IXGBE_I2C_T_BUF);
1573 }
1574
1575 /**
1576 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1577 * @hw: pointer to hardware structure
1578 * @data: data byte to clock in
1579 *
1580 * Clocks in one byte data via I2C data/clock
1581 **/
1582 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1583 {
1584 s32 i;
1585 bool bit = 0;
1586
1587 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1588
1589 for (i = 7; i >= 0; i--) {
1590 ixgbe_clock_in_i2c_bit(hw, &bit);
1591 *data |= bit << i;
1592 }
1593
1594 return IXGBE_SUCCESS;
1595 }
1596
1597 /**
1598 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1599 * @hw: pointer to hardware structure
1600 * @data: data byte clocked out
1601 *
1602 * Clocks out one byte data via I2C data/clock
1603 **/
1604 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1605 {
1606 s32 status = IXGBE_SUCCESS;
1607 s32 i;
1608 u32 i2cctl;
1609 bool bit = 0;
1610
1611 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1612
1613 for (i = 7; i >= 0; i--) {
1614 bit = (data >> i) & 0x1;
1615 status = ixgbe_clock_out_i2c_bit(hw, bit);
1616
1617 if (status != IXGBE_SUCCESS)
1618 break;
1619 }
1620
1621 /* Release SDA line (set high) */
1622 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1623 i2cctl |= IXGBE_I2C_DATA_OUT;
1624 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1625 IXGBE_WRITE_FLUSH(hw);
1626
1627 return status;
1628 }
1629
1630 /**
1631 * ixgbe_get_i2c_ack - Polls for I2C ACK
1632 * @hw: pointer to hardware structure
1633 *
1634 * Clocks in/out one bit via I2C data/clock
1635 **/
1636 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1637 {
1638 s32 status = IXGBE_SUCCESS;
1639 u32 i = 0;
1640 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1641 u32 timeout = 10;
1642 bool ack = 1;
1643
1644 DEBUGFUNC("ixgbe_get_i2c_ack");
1645
1646 ixgbe_raise_i2c_clk(hw, &i2cctl);
1647
1648
1649 /* Minimum high period of clock is 4us */
1650 usec_delay(IXGBE_I2C_T_HIGH);
1651
1652 /* Poll for ACK. Note that ACK in I2C spec is
1653 * transition from 1 to 0 */
1654 for (i = 0; i < timeout; i++) {
1655 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1656 ack = ixgbe_get_i2c_data(&i2cctl);
1657
1658 usec_delay(1);
1659 if (ack == 0)
1660 break;
1661 }
1662
1663 if (ack == 1) {
1664 DEBUGOUT("I2C ack was not received.\n");
1665 status = IXGBE_ERR_I2C;
1666 }
1667
1668 ixgbe_lower_i2c_clk(hw, &i2cctl);
1669
1670 /* Minimum low period of clock is 4.7 us */
1671 usec_delay(IXGBE_I2C_T_LOW);
1672
1673 return status;
1674 }
1675
1676 /**
1677 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1678 * @hw: pointer to hardware structure
1679 * @data: read data value
1680 *
1681 * Clocks in one bit via I2C data/clock
1682 **/
1683 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1684 {
1685 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1686
1687 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1688
1689 ixgbe_raise_i2c_clk(hw, &i2cctl);
1690
1691 /* Minimum high period of clock is 4us */
1692 usec_delay(IXGBE_I2C_T_HIGH);
1693
1694 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1695 *data = ixgbe_get_i2c_data(&i2cctl);
1696
1697 ixgbe_lower_i2c_clk(hw, &i2cctl);
1698
1699 /* Minimum low period of clock is 4.7 us */
1700 usec_delay(IXGBE_I2C_T_LOW);
1701
1702 return IXGBE_SUCCESS;
1703 }
1704
1705 /**
1706 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1707 * @hw: pointer to hardware structure
1708 * @data: data value to write
1709 *
1710 * Clocks out one bit via I2C data/clock
1711 **/
1712 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1713 {
1714 s32 status;
1715 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1716
1717 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1718
1719 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1720 if (status == IXGBE_SUCCESS) {
1721 ixgbe_raise_i2c_clk(hw, &i2cctl);
1722
1723 /* Minimum high period of clock is 4us */
1724 usec_delay(IXGBE_I2C_T_HIGH);
1725
1726 ixgbe_lower_i2c_clk(hw, &i2cctl);
1727
1728 /* Minimum low period of clock is 4.7 us.
1729 * This also takes care of the data hold time.
1730 */
1731 usec_delay(IXGBE_I2C_T_LOW);
1732 } else {
1733 status = IXGBE_ERR_I2C;
1734 DEBUGOUT1("I2C data was not set to %X\n", data);
1735 }
1736
1737 return status;
1738 }
1739 /**
1740 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1741 * @hw: pointer to hardware structure
1742 * @i2cctl: Current value of I2CCTL register
1743 *
1744 * Raises the I2C clock line '0'->'1'
1745 **/
1746 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1747 {
1748 u32 i = 0;
1749 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1750 u32 i2cctl_r = 0;
1751
1752 DEBUGFUNC("ixgbe_raise_i2c_clk");
1753
1754 for (i = 0; i < timeout; i++) {
1755 *i2cctl |= IXGBE_I2C_CLK_OUT;
1756
1757 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1758 IXGBE_WRITE_FLUSH(hw);
1759 /* SCL rise time (1000ns) */
1760 usec_delay(IXGBE_I2C_T_RISE);
1761
1762 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1763 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1764 break;
1765 }
1766 }
1767
1768 /**
1769 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1770 * @hw: pointer to hardware structure
1771 * @i2cctl: Current value of I2CCTL register
1772 *
1773 * Lowers the I2C clock line '1'->'0'
1774 **/
1775 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1776 {
1777
1778 DEBUGFUNC("ixgbe_lower_i2c_clk");
1779
1780 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1781
1782 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1783 IXGBE_WRITE_FLUSH(hw);
1784
1785 /* SCL fall time (300ns) */
1786 usec_delay(IXGBE_I2C_T_FALL);
1787 }
1788
1789 /**
1790 * ixgbe_set_i2c_data - Sets the I2C data bit
1791 * @hw: pointer to hardware structure
1792 * @i2cctl: Current value of I2CCTL register
1793 * @data: I2C data value (0 or 1) to set
1794 *
1795 * Sets the I2C data bit
1796 **/
1797 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1798 {
1799 s32 status = IXGBE_SUCCESS;
1800
1801 DEBUGFUNC("ixgbe_set_i2c_data");
1802
1803 if (data)
1804 *i2cctl |= IXGBE_I2C_DATA_OUT;
1805 else
1806 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1807
1808 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1809 IXGBE_WRITE_FLUSH(hw);
1810
1811 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1812 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1813
1814 /* Verify data was set correctly */
1815 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1816 if (data != ixgbe_get_i2c_data(i2cctl)) {
1817 status = IXGBE_ERR_I2C;
1818 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1819 }
1820
1821 return status;
1822 }
1823
1824 /**
1825 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1826 * @hw: pointer to hardware structure
1827 * @i2cctl: Current value of I2CCTL register
1828 *
1829 * Returns the I2C data bit value
1841
1842 return data;
1843 }
1844
1845 /**
1846 * ixgbe_i2c_bus_clear - Clears the I2C bus
1847 * @hw: pointer to hardware structure
1848 *
1849 * Clears the I2C bus by sending nine clock pulses.
1850 * Used when data line is stuck low.
1851 **/
1852 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1853 {
1854 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1855 u32 i;
1856
1857 DEBUGFUNC("ixgbe_i2c_bus_clear");
1858
1859 ixgbe_i2c_start(hw);
1860
1861 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1862
1863 for (i = 0; i < 9; i++) {
1864 ixgbe_raise_i2c_clk(hw, &i2cctl);
1865
1866 /* Min high period of clock is 4us */
1867 usec_delay(IXGBE_I2C_T_HIGH);
1868
1869 ixgbe_lower_i2c_clk(hw, &i2cctl);
1870
1871 /* Min low period of clock is 4.7us*/
1872 usec_delay(IXGBE_I2C_T_LOW);
1873 }
1874
1875 ixgbe_i2c_start(hw);
1876
1877 /* Put the i2c bus back to default state */
1878 ixgbe_i2c_stop(hw);
1879 }
1880
1881 /**
1882 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1883 * @hw: pointer to hardware structure
1884 *
1885 * Checks if the LASI temp alarm status was triggered due to overtemp
1886 **/
1887 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1888 {
1889 s32 status = IXGBE_SUCCESS;
1890 u16 phy_data = 0;
1891
1892 DEBUGFUNC("ixgbe_tn_check_overtemp");
1893
1894 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1895 goto out;
1896
1897 /* Check that the LASI temp alarm status was triggered */
1898 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1899 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1900
1901 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1902 goto out;
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