13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39
40 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
41 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
47 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
48 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
49 ixgbe_link_speed speed, bool autoneg,
50 bool autoneg_wait_to_complete);
51 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
52 ixgbe_link_speed speed, bool autoneg,
53 bool autoneg_wait_to_complete);
54 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55 bool autoneg_wait_to_complete);
56 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
58 bool autoneg,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
61 ixgbe_link_speed speed,
62 bool autoneg,
63 bool autoneg_wait_to_complete);
64 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw);
65 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw);
66 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
67 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
68 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
69 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw);
70 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
71 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
72 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
73 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
74 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
75 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
76
77
78 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
79 {
80 struct ixgbe_mac_info *mac = &hw->mac;
81
82 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
83
84 /* enable the laser control functions for SFP+ fiber */
85 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
86 mac->ops.disable_tx_laser =
87 &ixgbe_disable_tx_laser_multispeed_fiber;
88 mac->ops.enable_tx_laser =
89 &ixgbe_enable_tx_laser_multispeed_fiber;
90 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
91
92 } else {
93 mac->ops.disable_tx_laser = NULL;
94 mac->ops.enable_tx_laser = NULL;
95 mac->ops.flap_tx_laser = NULL;
96 }
97
135 /* Setup function pointers based on detected SFP module and speeds */
136 ixgbe_init_mac_link_ops_82599(hw);
137 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
138 hw->phy.ops.reset = NULL;
139
140 /* If copper media, overwrite with copper function pointers */
141 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
142 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
143 mac->ops.get_link_capabilities =
144 &ixgbe_get_copper_link_capabilities_generic;
145 }
146
147 /* Set necessary function pointers based on phy type */
148 switch (hw->phy.type) {
149 case ixgbe_phy_tn:
150 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
151 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
152 phy->ops.get_firmware_version =
153 &ixgbe_get_phy_firmware_version_tnx;
154 break;
155 case ixgbe_phy_aq:
156 phy->ops.get_firmware_version =
157 &ixgbe_get_phy_firmware_version_generic;
158 break;
159 default:
160 break;
161 }
162 init_phy_ops_out:
163 return ret_val;
164 }
165
166 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
167 {
168 s32 ret_val = IXGBE_SUCCESS;
169 u32 reg_anlp1 = 0;
170 u32 i = 0;
171 u16 list_offset, data_offset, data_value;
172
173 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
174
175 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
176 ixgbe_init_mac_link_ops_82599(hw);
177
178 hw->phy.ops.reset = NULL;
179
180 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
181 &data_offset);
182 if (ret_val != IXGBE_SUCCESS)
183 goto setup_sfp_out;
184
185 /* PHY config will finish before releasing the semaphore */
186 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
187 if (ret_val != IXGBE_SUCCESS) {
188 ret_val = IXGBE_ERR_SWFW_SYNC;
189 goto setup_sfp_out;
190 }
191
192 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
193 while (data_value != 0xffff) {
194 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
195 IXGBE_WRITE_FLUSH(hw);
196 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
197 }
198
199 /* Release the semaphore */
200 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
201 /* Delay obtaining semaphore again to allow FW access */
202 msec_delay(hw->eeprom.semaphore_delay);
203
204 /* Now restart DSP by setting Restart_AN and clearing LMS */
205 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
206 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
207 IXGBE_AUTOC_AN_RESTART));
208
209 /* Wait for AN to leave state 0 */
210 for (i = 0; i < 10; i++) {
211 msec_delay(4);
212 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
213 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
214 break;
215 }
216 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
217 DEBUGOUT("sfp module setup not complete\n");
218 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
219 goto setup_sfp_out;
220 }
224 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
225 IXGBE_AUTOC_AN_RESTART));
226 }
227
228 setup_sfp_out:
229 return ret_val;
230 }
231
232 /**
233 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
234 * @hw: pointer to hardware structure
235 *
236 * Initialize the function pointers and assign the MAC type for 82599.
237 * Does not touch the hardware.
238 **/
239
240 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
241 {
242 struct ixgbe_mac_info *mac = &hw->mac;
243 struct ixgbe_phy_info *phy = &hw->phy;
244 s32 ret_val;
245
246 DEBUGFUNC("ixgbe_init_ops_82599");
247
248 ret_val = ixgbe_init_phy_ops_generic(hw);
249 ret_val = ixgbe_init_ops_generic(hw);
250
251 /* PHY */
252 phy->ops.identify = &ixgbe_identify_phy_82599;
253 phy->ops.init = &ixgbe_init_phy_ops_82599;
254
255 /* MAC */
256 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
257 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
258 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
259 mac->ops.get_supported_physical_layer =
260 &ixgbe_get_supported_physical_layer_82599;
261 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
262 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
263 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
264 mac->ops.start_hw = &ixgbe_start_hw_rev_1_82599;
265 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
266 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
267 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
268 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
269 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
270
271 /* RAR, Multicast, VLAN */
272 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
273 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
274 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
275 mac->rar_highwater = 1;
276 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
277 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
278 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
279 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
280 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
281 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
282
283 /* Link */
284 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
285 mac->ops.check_link = &ixgbe_check_mac_link_generic;
286 ixgbe_init_mac_link_ops_82599(hw);
287
288 mac->mcft_size = 128;
289 mac->vft_size = 128;
290 mac->num_rar_entries = 128;
291 mac->rx_pb_size = 512;
292 mac->max_tx_queues = 128;
293 mac->max_rx_queues = 128;
294 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
295
296 return ret_val;
297 }
298
299 /**
300 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
301 * @hw: pointer to hardware structure
302 * @speed: pointer to link speed
303 * @negotiation: TRUE when autoneg or autotry is enabled
304 *
305 * Determines the link capabilities by reading the AUTOC register.
306 **/
307 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
308 ixgbe_link_speed *speed,
309 bool *negotiation)
310 {
311 s32 status = IXGBE_SUCCESS;
312 u32 autoc = 0;
313
314 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
315
316
317 /* Check if 1G SFP module. */
318 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
319 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
320 *speed = IXGBE_LINK_SPEED_1GB_FULL;
321 *negotiation = TRUE;
322 goto out;
323 }
324
325 /*
326 * Determine link capabilities based on the stored value of AUTOC,
327 * which represents EEPROM defaults. If AUTOC value has not
328 * been stored, use the current register values.
329 */
330 if (hw->mac.orig_link_settings_stored)
331 autoc = hw->mac.orig_autoc;
332 else
333 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
334
335 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
336 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
337 *speed = IXGBE_LINK_SPEED_1GB_FULL;
338 *negotiation = FALSE;
339 break;
395 out:
396 return status;
397 }
398
399 /**
400 * ixgbe_get_media_type_82599 - Get media type
401 * @hw: pointer to hardware structure
402 *
403 * Returns the media type (fiber, copper, backplane)
404 **/
405 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
406 {
407 enum ixgbe_media_type media_type;
408
409 DEBUGFUNC("ixgbe_get_media_type_82599");
410
411 /* Detect if there is a copper PHY attached. */
412 switch (hw->phy.type) {
413 case ixgbe_phy_cu_unknown:
414 case ixgbe_phy_tn:
415 case ixgbe_phy_aq:
416 media_type = ixgbe_media_type_copper;
417 goto out;
418 default:
419 break;
420 }
421
422 switch (hw->device_id) {
423 case IXGBE_DEV_ID_82599_KX4:
424 case IXGBE_DEV_ID_82599_KX4_MEZZ:
425 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
426 case IXGBE_DEV_ID_82599_KR:
427 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
428 case IXGBE_DEV_ID_82599_XAUI_LOM:
429 /* Default device ID is mezzanine card KX/KX4 */
430 media_type = ixgbe_media_type_backplane;
431 break;
432 case IXGBE_DEV_ID_82599_SFP:
433 case IXGBE_DEV_ID_82599_SFP_FCOE:
434 case IXGBE_DEV_ID_82599_SFP_EM:
435 case IXGBE_DEV_ID_82599_SFP_SF2:
946 * @hw: pointer to hardware structure
947 * @speed: new link speed
948 * @autoneg: TRUE if autonegotiation enabled
949 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
950 *
951 * Restarts link on PHY and MAC based on settings passed in.
952 **/
953 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
954 ixgbe_link_speed speed,
955 bool autoneg,
956 bool autoneg_wait_to_complete)
957 {
958 s32 status;
959
960 DEBUGFUNC("ixgbe_setup_copper_link_82599");
961
962 /* Setup the PHY according to input speed */
963 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
964 autoneg_wait_to_complete);
965 /* Set up MAC */
966 (void) ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
967
968 return status;
969 }
970
971 /**
972 * ixgbe_reset_hw_82599 - Perform hardware reset
973 * @hw: pointer to hardware structure
974 *
975 * Resets the hardware by resetting the transmit and receive units, masks
976 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
977 * reset.
978 **/
979 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
980 {
981 s32 status = IXGBE_SUCCESS;
982 u32 ctrl;
983 u32 i;
984 u32 autoc;
985 u32 autoc2;
986
987 DEBUGFUNC("ixgbe_reset_hw_82599");
988
989 /* Call adapter stop to disable tx/rx and clear interrupts */
990 hw->mac.ops.stop_adapter(hw);
991
992 /* PHY ops must be identified and initialized prior to reset */
993
994 /* Identify PHY and related function pointers */
995 status = hw->phy.ops.init(hw);
996
997 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
998 goto reset_hw_out;
999
1000 /* Setup SFP module if there is one present. */
1001 if (hw->phy.sfp_setup_needed) {
1002 status = hw->mac.ops.setup_sfp(hw);
1003 hw->phy.sfp_setup_needed = FALSE;
1004 }
1005
1006 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1007 goto reset_hw_out;
1008
1009 /* Reset PHY */
1010 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
1011 hw->phy.ops.reset(hw);
1012
1013 /*
1014 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
1015 * access and verify no pending requests before reset
1016 */
1017 (void) ixgbe_disable_pcie_master(hw);
1018
1019 mac_reset_top:
1020 /*
1021 * Issue global reset to the MAC. This needs to be a SW reset.
1022 * If link reset is used, it might reset the MAC when mng is using it
1023 */
1024 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1025 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
1026 IXGBE_WRITE_FLUSH(hw);
1027
1028 /* Poll for reset bit to self-clear indicating reset is complete */
1029 for (i = 0; i < 10; i++) {
1030 usec_delay(1);
1031 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1032 if (!(ctrl & IXGBE_CTRL_RST))
1033 break;
1034 }
1035 if (ctrl & IXGBE_CTRL_RST) {
1036 status = IXGBE_ERR_RESET_FAILED;
1037 DEBUGOUT("Reset polling failed to complete.\n");
1038 }
1039
1040 /*
1041 * Double resets are required for recovery from certain error
1042 * conditions. Between resets, it is necessary to stall to allow time
1043 * for any pending HW events to complete. We use 1usec since that is
1044 * what is needed for ixgbe_disable_pcie_master(). The second reset
1045 * then clears out any effects of those events.
1046 */
1047 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1048 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1049 usec_delay(1);
1050 goto mac_reset_top;
1051 }
1052
1053 msec_delay(50);
1054
1055 /*
1056 * Store the original AUTOC/AUTOC2 values if they have not been
1057 * stored off yet. Otherwise restore the stored original
1058 * values since the reset operation sets back to defaults.
1059 */
1060 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1061 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1062 if (hw->mac.orig_link_settings_stored == FALSE) {
1063 hw->mac.orig_autoc = autoc;
1064 hw->mac.orig_autoc2 = autoc2;
1065 hw->mac.orig_link_settings_stored = TRUE;
1066 } else {
1067 if (autoc != hw->mac.orig_autoc)
1068 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
1069 IXGBE_AUTOC_AN_RESTART));
1070
1071 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1072 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1073 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1074 autoc2 |= (hw->mac.orig_autoc2 &
1079
1080 /* Store the permanent mac address */
1081 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1082
1083 /*
1084 * Store MAC address from RAR0, clear receive address registers, and
1085 * clear the multicast table. Also reset num_rar_entries to 128,
1086 * since we modify this value when programming the SAN MAC address.
1087 */
1088 hw->mac.num_rar_entries = 128;
1089 hw->mac.ops.init_rx_addrs(hw);
1090
1091 /* Store the permanent SAN mac address */
1092 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1093
1094 /* Add the SAN MAC address to the RAR only if it's a valid address */
1095 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1096 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1097 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1098
1099 /* Reserve the last RAR for the SAN MAC address */
1100 hw->mac.num_rar_entries--;
1101 }
1102
1103 /* Store the alternative WWNN/WWPN prefix */
1104 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1105 &hw->mac.wwpn_prefix);
1106
1107 reset_hw_out:
1108 return status;
1109 }
1110
1111 /**
1112 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1113 * @hw: pointer to hardware structure
1114 **/
1115 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1116 {
1117 int i;
1118 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1119 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1120
1121 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1122
1123 /*
1124 * Before starting reinitialization process,
1125 * FDIRCMD.CMD must be zero.
1126 */
1127 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1128 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1129 IXGBE_FDIRCMD_CMD_MASK))
1130 break;
1131 usec_delay(10);
1132 }
1133 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1134 DEBUGOUT("Flow Director previous command isn't complete, "
1135 "aborting table re-initialization. \n");
1136 return IXGBE_ERR_FDIR_REINIT_FAILED;
1137 }
1138
1139 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1140 IXGBE_WRITE_FLUSH(hw);
1141 /*
1142 * 82599 adapters flow director init flow cannot be restarted,
1143 * Workaround 82599 silicon errata by performing the following steps
1144 * before re-writing the FDIRCTRL control register with the same value.
1145 * - write 1 to bit 8 of FDIRCMD register &
1146 * - write 0 to bit 8 of FDIRCMD register
1147 */
1148 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1149 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1150 IXGBE_FDIRCMD_CLEARHT));
1151 IXGBE_WRITE_FLUSH(hw);
1152 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1153 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1154 ~IXGBE_FDIRCMD_CLEARHT));
1155 IXGBE_WRITE_FLUSH(hw);
1159 */
1160 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1161 IXGBE_WRITE_FLUSH(hw);
1162
1163 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1164 IXGBE_WRITE_FLUSH(hw);
1165
1166 /* Poll init-done after we write FDIRCTRL register */
1167 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1168 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1169 IXGBE_FDIRCTRL_INIT_DONE)
1170 break;
1171 usec_delay(10);
1172 }
1173 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1174 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1175 return IXGBE_ERR_FDIR_REINIT_FAILED;
1176 }
1177
1178 /* Clear FDIR statistics registers (read to clear) */
1179 (void) IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1180 (void) IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1181 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1182 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1183 (void) IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1184
1185 return IXGBE_SUCCESS;
1186 }
1187
1188 /**
1189 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1190 * @hw: pointer to hardware structure
1191 * @pballoc: which mode to allocate filters with
1192 **/
1193 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1194 {
1195 u32 fdirctrl = 0;
1196 u32 pbsize;
1197 int i;
1198
1199 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1200
1201 /*
1202 * Before enabling Flow Director, the Rx Packet Buffer size
1203 * must be reduced. The new value is the current size minus
1204 * flow director memory usage size.
1205 */
1206 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1207 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1208 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1209
1210 /*
1211 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1212 * intialized to zero for non DCB mode otherwise actual total RX PB
1213 * would be bigger than programmed and filter space would run into
1214 * the PB 0 region.
1215 */
1216 for (i = 1; i < 8; i++)
1217 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1218
1219 /* Send interrupt when 64 filters are left */
1220 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1221
1222 /* Set the maximum length per hash bucket to 0xA filters */
1223 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1224
1225 switch (pballoc) {
1226 case IXGBE_FDIR_PBALLOC_64K:
1227 /* 8k - 1 signature filters */
1228 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1229 break;
1230 case IXGBE_FDIR_PBALLOC_128K:
1231 /* 16k - 1 signature filters */
1232 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1233 break;
1234 case IXGBE_FDIR_PBALLOC_256K:
1235 /* 32k - 1 signature filters */
1236 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1237 break;
1238 default:
1239 /* bad value */
1240 return IXGBE_ERR_CONFIG;
1241 };
1242
1243 /* Move the flexible bytes to use the ethertype - shift 6 words */
1244 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1245
1246
1247 /* Prime the keys for hashing */
1248 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1249 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1250
1251 /*
1252 * Poll init-done after we write the register. Estimated times:
1253 * 10G: PBALLOC = 11b, timing is 60us
1254 * 1G: PBALLOC = 11b, timing is 600us
1255 * 100M: PBALLOC = 11b, timing is 6ms
1256 *
1257 * Multiple these timings by 4 if under full Rx load
1258 *
1259 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1260 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1261 * this might not finish in our poll time, but we can live with that
1262 * for now.
1263 */
1264 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1265 IXGBE_WRITE_FLUSH(hw);
1266 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1267 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1268 IXGBE_FDIRCTRL_INIT_DONE)
1269 break;
1270 msec_delay(1);
1271 }
1272 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1273 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1274
1275 return IXGBE_SUCCESS;
1276 }
1277
1278 /**
1279 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1280 * @hw: pointer to hardware structure
1281 * @pballoc: which mode to allocate filters with
1282 **/
1283 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1284 {
1285 u32 fdirctrl = 0;
1286 u32 pbsize;
1287 int i;
1288
1289 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1290
1291 /*
1292 * Before enabling Flow Director, the Rx Packet Buffer size
1293 * must be reduced. The new value is the current size minus
1294 * flow director memory usage size.
1295 */
1296 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1297 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1298 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1299
1300 /*
1301 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1302 * intialized to zero for non DCB mode otherwise actual total RX PB
1303 * would be bigger than programmed and filter space would run into
1304 * the PB 0 region.
1305 */
1306 for (i = 1; i < 8; i++)
1307 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1308
1309 /* Send interrupt when 64 filters are left */
1310 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1311
1312 /* Initialize the drop queue to Rx queue 127 */
1313 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1314
1315 switch (pballoc) {
1316 case IXGBE_FDIR_PBALLOC_64K:
1317 /* 2k - 1 perfect filters */
1318 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1319 break;
1320 case IXGBE_FDIR_PBALLOC_128K:
1321 /* 4k - 1 perfect filters */
1322 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1323 break;
1324 case IXGBE_FDIR_PBALLOC_256K:
1325 /* 8k - 1 perfect filters */
1326 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1327 break;
1328 default:
1329 /* bad value */
1330 return IXGBE_ERR_CONFIG;
1331 };
1332
1333 /* Turn perfect match filtering on */
1334 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1335 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1336
1337 /* Move the flexible bytes to use the ethertype - shift 6 words */
1338 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1339
1340 /* Prime the keys for hashing */
1341 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1342 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,IXGBE_ATR_SIGNATURE_HASH_KEY);
1343
1344 /*
1345 * Poll init-done after we write the register. Estimated times:
1346 * 10G: PBALLOC = 11b, timing is 60us
1347 * 1G: PBALLOC = 11b, timing is 600us
1348 * 100M: PBALLOC = 11b, timing is 6ms
1349 *
1350 * Multiple these timings by 4 if under full Rx load
1351 *
1352 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1353 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1354 * this might not finish in our poll time, but we can live with that
1355 * for now.
1356 */
1357
1358 /* Set the maximum length per hash bucket to 0xA filters */
1359 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1360
1361 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1362 IXGBE_WRITE_FLUSH(hw);
1363 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1364 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1365 IXGBE_FDIRCTRL_INIT_DONE)
1366 break;
1367 msec_delay(1);
1368 }
1369 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1370 DEBUGOUT("Flow Director Perfect poll time exceeded!\n");
1371
1372 return IXGBE_SUCCESS;
1373 }
1374
1375 /**
1376 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1377 * @stream: input bitstream to compute the hash on
1378 * @key: 32-bit hash key
1379 **/
1380 u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
1381 u32 key)
1382 {
1383 /*
1384 * The algorithm is as follows:
1385 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1386 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1387 * and A[n] x B[n] is bitwise AND between same length strings
1388 *
1389 * K[n] is 16 bits, defined as:
1390 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1391 * for n modulo 32 < 15, K[n] =
1392 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1393 *
1394 * S[n] is 16 bits, defined as:
1395 * for n >= 15, S[n] = S[n:n - 15]
1396 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1397 *
1398 * To simplify for programming, the algorithm is implemented
1399 * in software this way:
1400 *
1401 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1402 *
1403 * for (i = 0; i < 352; i+=32)
1404 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1405 *
1406 * lo_hash_dword[15:0] ^= Stream[15:0];
1407 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1408 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
1409 *
1410 * hi_hash_dword[31:0] ^= Stream[351:320];
1411 *
1412 * if(key[0])
1413 * hash[15:0] ^= Stream[15:0];
1414 *
1415 * for (i = 0; i < 16; i++) {
1416 * if (key[i])
1417 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1418 * if (key[i + 16])
1419 * hash[15:0] ^= hi_hash_dword[(i+15):i];
1420 * }
1421 *
1422 */
1423 __be32 common_hash_dword = 0;
1424 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1425 u32 hash_result = 0;
1426 u8 i;
1427
1428 /* record the flow_vm_vlan bits as they are a key part to the hash */
1429 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
1430
1431 /* generate common hash dword */
1432 for (i = 10; i; i -= 2)
1433 common_hash_dword ^= atr_input->dword_stream[i] ^
1434 atr_input->dword_stream[i - 1];
1435
1436 hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
1437
1438 /* low dword is word swapped version of common */
1439 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1440
1441 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1442 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1443
1444 /* Process bits 0 and 16 */
1445 if (key & 0x0001) hash_result ^= lo_hash_dword;
1446 if (key & 0x00010000) hash_result ^= hi_hash_dword;
1447
1448 /*
1449 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1450 * delay this because bit 0 of the stream should not be processed
1451 * so we do not add the vlan until after bit 0 was processed
1452 */
1453 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1454
1455
1456 /* process the remaining 30 bits in the key 2 bits at a time */
1457 for (i = 15; i; i-- ) {
1458 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
1459 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
1460 }
1461
1462 return hash_result & IXGBE_ATR_HASH_MASK;
1463 }
1464
1465 /*
1466 * These defines allow us to quickly generate all of the necessary instructions
1467 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1468 * for values 0 through 15
1469 */
1470 #define IXGBE_ATR_COMMON_HASH_KEY \
1471 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1472 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1473 { \
1474 u32 n = (_n); \
1475 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1476 common_hash ^= lo_hash_dword >> n; \
1477 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1478 bucket_hash ^= lo_hash_dword >> n; \
1479 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1480 sig_hash ^= lo_hash_dword << (16 - n); \
1481 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1482 common_hash ^= hi_hash_dword >> n; \
1483 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1484 bucket_hash ^= hi_hash_dword >> n; \
1485 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1486 sig_hash ^= hi_hash_dword << (16 - n); \
1487 }
1488
1489 /**
1490 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1491 * @stream: input bitstream to compute the hash on
1492 *
1493 * This function is almost identical to the function above but contains
1494 * several optomizations such as unwinding all of the loops, letting the
1495 * compiler work out all of the conditional ifs since the keys are static
1496 * defines, and computing two keys at once since the hashed dword stream
1497 * will be the same for both keys.
1498 **/
1499 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1500 union ixgbe_atr_hash_dword common)
1501 {
1502 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1503 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1504
1505 /* record the flow_vm_vlan bits as they are a key part to the hash */
1506 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1507
1508 /* generate common hash dword */
1509 hi_hash_dword = IXGBE_NTOHL(common.dword);
1510
1511 /* low dword is word swapped version of common */
1512 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1513
1514 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1515 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1516
1517 /* Process bits 0 and 16 */
1518 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1519
1538 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1539 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1540 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1541 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1542 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1543
1544 /* combine common_hash result with signature and bucket hashes */
1545 bucket_hash ^= common_hash;
1546 bucket_hash &= IXGBE_ATR_HASH_MASK;
1547
1548 sig_hash ^= common_hash << 16;
1549 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1550
1551 /* return completed signature hash */
1552 return sig_hash ^ bucket_hash;
1553 }
1554
1555 /**
1556 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1557 * @hw: pointer to hardware structure
1558 * @stream: input bitstream
1559 * @queue: queue index to direct traffic to
1560 **/
1561 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1562 union ixgbe_atr_hash_dword input,
1563 union ixgbe_atr_hash_dword common,
1564 u8 queue)
1565 {
1566 u64 fdirhashcmd;
1567 u32 fdircmd;
1568
1569 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1570
1571 /*
1572 * Get the flow_type in order to program FDIRCMD properly
1573 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1574 */
1575 switch (input.formatted.flow_type) {
1576 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1577 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1578 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1587
1588 /* configure FDIRCMD register */
1589 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1590 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1591 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1592 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1593
1594 /*
1595 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1596 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1597 */
1598 fdirhashcmd = (u64)fdircmd << 32;
1599 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1600 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1601
1602 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1603
1604 return IXGBE_SUCCESS;
1605 }
1606
1607 /**
1608 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1609 * @input_mask: mask to be bit swapped
1610 *
1611 * The source and destination port masks for flow director are bit swapped
1612 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1613 * generate a correctly swapped value we need to bit swap the mask and that
1614 * is what is accomplished by this function.
1615 **/
1616 static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
1617 {
1618 u32 mask = IXGBE_NTOHS(input_masks->dst_port_mask);
1619 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1620 mask |= IXGBE_NTOHS(input_masks->src_port_mask);
1621 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1622 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1623 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1624 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1625 }
1626
1627 /*
1628 * These two macros are meant to address the fact that we have registers
1629 * that are either all or in part big-endian. As a result on big-endian
1630 * systems we will end up byte swapping the value to little-endian before
1631 * it is byte swapped again and written to the hardware in the original
1632 * big-endian format.
1633 */
1634 #define IXGBE_STORE_AS_BE32(_value) \
1635 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1636 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1637
1638 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1639 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1640
1641 #define IXGBE_STORE_AS_BE16(_value) \
1642 (((u16)(_value) >> 8) | ((u16)(_value) << 8))
1643
1644
1645 /**
1646 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1647 * @hw: pointer to hardware structure
1648 * @input: input bitstream
1649 * @input_masks: masks for the input bitstream
1650 * @soft_id: software index for the filters
1651 * @queue: queue index to direct traffic to
1652 *
1653 * Note that the caller to this function must lock before calling, since the
1654 * hardware writes must be protected from one another.
1655 **/
1656 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1657 union ixgbe_atr_input *input,
1658 struct ixgbe_atr_input_masks *input_masks,
1659 u16 soft_id, u8 queue)
1660 {
1661 u32 fdirhash;
1662 u32 fdircmd;
1663 u32 fdirport, fdirtcpm;
1664 u32 fdirvlan;
1665 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1666 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
1667 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
1668
1669 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1670
1671 /*
1672 * Check flow_type formatting, and bail out before we touch the hardware
1673 * if there's a configuration issue
1674 */
1675 switch (input->formatted.flow_type) {
1676 case IXGBE_ATR_FLOW_TYPE_IPV4:
1677 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1678 fdirm |= IXGBE_FDIRM_L4P;
1679 /* FALLTHRU */
1680 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1681 if (input_masks->dst_port_mask || input_masks->src_port_mask) {
1682 DEBUGOUT(" Error on src/dst port mask\n");
1683 return IXGBE_ERR_CONFIG;
1684 }
1685 break;
1686 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1687 break;
1688 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1689 break;
1690 default:
1691 DEBUGOUT(" Error on flow type input\n");
1692 return IXGBE_ERR_CONFIG;
1693 }
1694
1695 /*
1696 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1697 * are zero, then assume a full mask for that field. Also assume that
1698 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1699 * cannot be masked out in this implementation.
1700 *
1701 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1702 * point in time.
1703 */
1704
1705 /* Program FDIRM */
1706 switch (IXGBE_NTOHS(input_masks->vlan_id_mask) & 0xEFFF) {
1707 case 0xEFFF:
1708 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
1709 fdirm &= ~IXGBE_FDIRM_VLANID;
1710 /* FALLTHRU */
1711 case 0xE000:
1712 /* Unmask VLAN prio - bit 1 */
1713 fdirm &= ~IXGBE_FDIRM_VLANP;
1714 break;
1715 case 0x0FFF:
1716 /* Unmask VLAN ID - bit 0 */
1717 fdirm &= ~IXGBE_FDIRM_VLANID;
1718 break;
1719 case 0x0000:
1720 /* do nothing, vlans already masked */
1721 break;
1722 default:
1723 DEBUGOUT(" Error on VLAN mask\n");
1724 return IXGBE_ERR_CONFIG;
1725 }
1726
1727 if (input_masks->flex_mask & 0xFFFF) {
1728 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
1729 DEBUGOUT(" Error on flexible byte mask\n");
1730 return IXGBE_ERR_CONFIG;
1731 }
1732 /* Unmask Flex Bytes - bit 4 */
1733 fdirm &= ~IXGBE_FDIRM_FLEX;
1734 }
1735
1736 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1737 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1738
1739 /* store the TCP/UDP port masks, bit reversed from port layout */
1740 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
1741
1742 /* write both the same so that UDP and TCP use the same mask */
1743 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1744 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1745
1746 /* store source and destination IP masks (big-enian) */
1747 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1748 ~input_masks->src_ip_mask[0]);
1749 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1750 ~input_masks->dst_ip_mask[0]);
1751
1752 /* Apply masks to input data */
1753 input->formatted.vlan_id &= input_masks->vlan_id_mask;
1754 input->formatted.flex_bytes &= input_masks->flex_mask;
1755 input->formatted.src_port &= input_masks->src_port_mask;
1756 input->formatted.dst_port &= input_masks->dst_port_mask;
1757 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
1758 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
1759
1760 /* record vlan (little-endian) and flex_bytes(big-endian) */
1761 fdirvlan =
1762 IXGBE_STORE_AS_BE16(IXGBE_NTOHS(input->formatted.flex_bytes));
1763 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1764 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1765 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1766
1767 /* record source and destination port (little-endian)*/
1768 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1769 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1770 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1771 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1772
1773 /* record the first 32 bits of the destination address (big-endian) */
1774 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1775
1776 /* record the source address (big-endian) */
1777 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1778
1779 /* configure FDIRCMD register */
1780 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1781 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1782 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1783 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1784
1785 /* we only want the bucket hash so drop the upper 16 bits */
1786 fdirhash = ixgbe_atr_compute_hash_82599(input,
1787 IXGBE_ATR_BUCKET_HASH_KEY);
1788 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1789
1790 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1791 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1792
1793 return IXGBE_SUCCESS;
1794 }
1795
1796 /**
1797 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1798 * @hw: pointer to hardware structure
1799 * @reg: analog register to read
1800 * @val: read value
1801 *
1802 * Performs read operation to Omer analog register specified.
1803 **/
1804 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1805 {
1806 u32 core_ctl;
1807
1808 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1809
1810 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1811 (reg << 8));
1812 IXGBE_WRITE_FLUSH(hw);
1813 usec_delay(10);
1814 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1815 *val = (u8)core_ctl;
1816
1823 * @reg: atlas register to write
1824 * @val: value to write
1825 *
1826 * Performs write operation to Omer analog register specified.
1827 **/
1828 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1829 {
1830 u32 core_ctl;
1831
1832 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
1833
1834 core_ctl = (reg << 8) | val;
1835 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1836 IXGBE_WRITE_FLUSH(hw);
1837 usec_delay(10);
1838
1839 return IXGBE_SUCCESS;
1840 }
1841
1842 /**
1843 * ixgbe_start_hw_rev_1_82599 - Prepare hardware for Tx/Rx
1844 * @hw: pointer to hardware structure
1845 *
1846 * Starts the hardware using the generic start_hw function
1847 * and the generation start_hw function.
1848 * Then performs revision-specific operations, if any.
1849 **/
1850 s32 ixgbe_start_hw_rev_1_82599(struct ixgbe_hw *hw)
1851 {
1852 s32 ret_val = IXGBE_SUCCESS;
1853
1854 DEBUGFUNC("ixgbe_start_hw_rev_1__82599");
1855
1856 ret_val = ixgbe_start_hw_generic(hw);
1857 if (ret_val != IXGBE_SUCCESS)
1858 goto out;
1859
1860 ret_val = ixgbe_start_hw_gen2(hw);
1861 if (ret_val != IXGBE_SUCCESS)
1862 goto out;
1863
1864 /* We need to run link autotry after the driver loads */
1865 hw->mac.autotry_restart = TRUE;
1866
1867 if (ret_val == IXGBE_SUCCESS)
1868 ret_val = ixgbe_verify_fw_version_82599(hw);
1869 out:
1870 return ret_val;
1871 }
1872
1873 /**
1874 * ixgbe_identify_phy_82599 - Get physical layer module
1875 * @hw: pointer to hardware structure
1876 *
1877 * Determines the physical layer module found on the current adapter.
1878 * If PHY already detected, maintains current PHY type in hw struct,
1879 * otherwise executes the PHY detection routine.
1880 **/
1881 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1882 {
1883 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1884
1885 DEBUGFUNC("ixgbe_identify_phy_82599");
1886
1887 /* Detect PHY if not unknown - returns success if already detected. */
1888 status = ixgbe_identify_phy_generic(hw);
1889 if (status != IXGBE_SUCCESS) {
1890 /* 82599 10GBASE-T requires an external PHY */
1891 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1892 goto out;
1893 else
1894 status = ixgbe_identify_sfp_module_generic(hw);
1895 }
1896
1897 /* Set PHY type none if no PHY detected */
1898 if (hw->phy.type == ixgbe_phy_unknown) {
1899 hw->phy.type = ixgbe_phy_none;
1900 status = IXGBE_SUCCESS;
1901 }
1902
1903 /* Return error if SFP module has been detected but is not supported */
1904 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1905 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1906
1907 out:
1908 return status;
1909 }
1910
1911 /**
1912 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1913 * @hw: pointer to hardware structure
1914 *
1915 * Determines physical layer capabilities of the current configuration.
1916 **/
1917 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1918 {
1919 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1920 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1921 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1922 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1923 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1924 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1925 u16 ext_ability = 0;
1926 u8 comp_codes_10g = 0;
1927 u8 comp_codes_1g = 0;
1928
1929 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
1930
1931 hw->phy.ops.identify(hw);
1932
1933 switch (hw->phy.type) {
1934 case ixgbe_phy_tn:
1935 case ixgbe_phy_aq:
1936 case ixgbe_phy_cu_unknown:
1937 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1938 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1939 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1940 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1941 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1942 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1943 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1944 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1945 goto out;
1946 default:
1947 break;
1948 }
1949
1950 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1951 case IXGBE_AUTOC_LMS_1G_AN:
1952 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1953 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1954 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1955 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1999 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2000 break;
2001 case ixgbe_phy_sfp_ftl_active:
2002 case ixgbe_phy_sfp_active_unknown:
2003 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2004 break;
2005 case ixgbe_phy_sfp_avago:
2006 case ixgbe_phy_sfp_ftl:
2007 case ixgbe_phy_sfp_intel:
2008 case ixgbe_phy_sfp_unknown:
2009 hw->phy.ops.read_i2c_eeprom(hw,
2010 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2011 hw->phy.ops.read_i2c_eeprom(hw,
2012 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2013 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2014 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2015 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2016 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2017 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2018 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2019 break;
2020 default:
2021 break;
2022 }
2023
2024 out:
2025 return physical_layer;
2026 }
2027
2028 /**
2029 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2030 * @hw: pointer to hardware structure
2031 * @regval: register value to write to RXCTRL
2032 *
2033 * Enables the Rx DMA unit for 82599
2034 **/
2035 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2036 {
2037 #define IXGBE_MAX_SECRX_POLL 30
2038 int i;
2039 int secrxreg;
2040
2041 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2042
2043 /*
2044 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2045 * If traffic is incoming before we enable the Rx unit, it could hang
2046 * the Rx DMA unit. Therefore, make sure the security engine is
2047 * completely disabled prior to enabling the Rx unit.
2048 */
2049 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2050 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2051 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2052 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2053 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2054 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2055 break;
2056 else
2057 /* Use interrupt-safe sleep just in case */
2058 usec_delay(10);
2059 }
2060
2061 /* For informational purposes only */
2062 if (i >= IXGBE_MAX_SECRX_POLL)
2063 DEBUGOUT("Rx unit being enabled before security "
2064 "path fully disabled. Continuing with init.\n");
2065
2066 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2067 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2068 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2069 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2070 IXGBE_WRITE_FLUSH(hw);
2071
2072 return IXGBE_SUCCESS;
2073 }
2074
2075 /**
2076 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2077 * @hw: pointer to hardware structure
2078 *
2079 * Verifies that installed the firmware version is 0.6 or higher
2080 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2081 *
2082 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2083 * if the FW version is not supported.
2084 **/
2085 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2086 {
2087 s32 status = IXGBE_ERR_EEPROM_VERSION;
2088 u16 fw_offset, fw_ptp_cfg_offset;
2089 u16 fw_version = 0;
2090
2091 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2095 status = IXGBE_SUCCESS;
2096 goto fw_version_out;
2097 }
2098
2099 /* get the offset to the Firmware Module block */
2100 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2101
2102 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2103 goto fw_version_out;
2104
2105 /* get the offset to the Pass Through Patch Configuration block */
2106 hw->eeprom.ops.read(hw, (fw_offset +
2107 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2108 &fw_ptp_cfg_offset);
2109
2110 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2111 goto fw_version_out;
2112
2113 /* get the firmware version */
2114 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2115 IXGBE_FW_PATCH_VERSION_4),
2116 &fw_version);
2117
2118 if (fw_version > 0x5)
2119 status = IXGBE_SUCCESS;
2120
2121 fw_version_out:
2122 return status;
2123 }
2124
2125 /**
2126 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2127 * @hw: pointer to hardware structure
2128 *
2129 * Returns TRUE if the LESM FW module is present and enabled. Otherwise
2130 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled.
2131 **/
2132 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2133 {
2134 bool lesm_enabled = FALSE;
2135 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2136 s32 status;
2149 IXGBE_FW_LESM_PARAMETERS_PTR),
2150 &fw_lesm_param_offset);
2151
2152 if ((status != IXGBE_SUCCESS) ||
2153 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2154 goto out;
2155
2156 /* get the lesm state word */
2157 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2158 IXGBE_FW_LESM_STATE_1),
2159 &fw_lesm_state);
2160
2161 if ((status == IXGBE_SUCCESS) &&
2162 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2163 lesm_enabled = TRUE;
2164
2165 out:
2166 return lesm_enabled;
2167 }
2168
2169
|
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c,v 1.8 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_type.h"
36 #include "ixgbe_82599.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
40
41 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
43 bool autoneg,
44 bool autoneg_wait_to_complete);
45 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
46 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
47 u16 offset, u16 *data);
48 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
49 u16 words, u16 *data);
50
51 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
52 {
53 struct ixgbe_mac_info *mac = &hw->mac;
54
55 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
56
57 /* enable the laser control functions for SFP+ fiber */
58 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
59 mac->ops.disable_tx_laser =
60 &ixgbe_disable_tx_laser_multispeed_fiber;
61 mac->ops.enable_tx_laser =
62 &ixgbe_enable_tx_laser_multispeed_fiber;
63 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
64
65 } else {
66 mac->ops.disable_tx_laser = NULL;
67 mac->ops.enable_tx_laser = NULL;
68 mac->ops.flap_tx_laser = NULL;
69 }
70
108 /* Setup function pointers based on detected SFP module and speeds */
109 ixgbe_init_mac_link_ops_82599(hw);
110 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
111 hw->phy.ops.reset = NULL;
112
113 /* If copper media, overwrite with copper function pointers */
114 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
115 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
116 mac->ops.get_link_capabilities =
117 &ixgbe_get_copper_link_capabilities_generic;
118 }
119
120 /* Set necessary function pointers based on phy type */
121 switch (hw->phy.type) {
122 case ixgbe_phy_tn:
123 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
124 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
125 phy->ops.get_firmware_version =
126 &ixgbe_get_phy_firmware_version_tnx;
127 break;
128 default:
129 break;
130 }
131 init_phy_ops_out:
132 return ret_val;
133 }
134
135 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
136 {
137 s32 ret_val = IXGBE_SUCCESS;
138 u32 reg_anlp1 = 0;
139 u32 i = 0;
140 u16 list_offset, data_offset, data_value;
141
142 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
143
144 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
145 ixgbe_init_mac_link_ops_82599(hw);
146
147 hw->phy.ops.reset = NULL;
148
149 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
150 &data_offset);
151 if (ret_val != IXGBE_SUCCESS)
152 goto setup_sfp_out;
153
154 /* PHY config will finish before releasing the semaphore */
155 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
156 IXGBE_GSSR_MAC_CSR_SM);
157 if (ret_val != IXGBE_SUCCESS) {
158 ret_val = IXGBE_ERR_SWFW_SYNC;
159 goto setup_sfp_out;
160 }
161
162 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
163 while (data_value != 0xffff) {
164 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
165 IXGBE_WRITE_FLUSH(hw);
166 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
167 }
168
169 /* Release the semaphore */
170 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
171 /* Delay obtaining semaphore again to allow FW access */
172 msec_delay(hw->eeprom.semaphore_delay);
173
174 /* Now restart DSP by setting Restart_AN and clearing LMS */
175 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
176 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
177 IXGBE_AUTOC_AN_RESTART));
178
179 /* Wait for AN to leave state 0 */
180 for (i = 0; i < 10; i++) {
181 msec_delay(4);
182 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
183 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
184 break;
185 }
186 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
187 DEBUGOUT("sfp module setup not complete\n");
188 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
189 goto setup_sfp_out;
190 }
194 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
195 IXGBE_AUTOC_AN_RESTART));
196 }
197
198 setup_sfp_out:
199 return ret_val;
200 }
201
202 /**
203 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
204 * @hw: pointer to hardware structure
205 *
206 * Initialize the function pointers and assign the MAC type for 82599.
207 * Does not touch the hardware.
208 **/
209
210 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
211 {
212 struct ixgbe_mac_info *mac = &hw->mac;
213 struct ixgbe_phy_info *phy = &hw->phy;
214 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
215 s32 ret_val;
216
217 DEBUGFUNC("ixgbe_init_ops_82599");
218
219 ret_val = ixgbe_init_phy_ops_generic(hw);
220 ret_val = ixgbe_init_ops_generic(hw);
221
222 /* PHY */
223 phy->ops.identify = &ixgbe_identify_phy_82599;
224 phy->ops.init = &ixgbe_init_phy_ops_82599;
225
226 /* MAC */
227 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
228 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
229 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
230 mac->ops.get_supported_physical_layer =
231 &ixgbe_get_supported_physical_layer_82599;
232 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
233 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
234 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
235 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
236 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
237 mac->ops.start_hw = &ixgbe_start_hw_82599;
238 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
239 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
240 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
241 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
242 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
243
244 /* RAR, Multicast, VLAN */
245 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
246 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
247 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
248 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
249 mac->rar_highwater = 1;
250 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
251 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
252 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
253 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
254 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
255 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
256 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
257
258 /* Link */
259 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
260 mac->ops.check_link = &ixgbe_check_mac_link_generic;
261 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
262 ixgbe_init_mac_link_ops_82599(hw);
263
264 mac->mcft_size = 128;
265 mac->vft_size = 128;
266 mac->num_rar_entries = 128;
267 mac->rx_pb_size = 512;
268 mac->max_tx_queues = 128;
269 mac->max_rx_queues = 128;
270 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
271
272 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
273 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
274
275 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
276
277 /* EEPROM */
278 eeprom->ops.read = &ixgbe_read_eeprom_82599;
279 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
280
281 /* Manageability interface */
282 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
283
284
285 return ret_val;
286 }
287
288 /**
289 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
290 * @hw: pointer to hardware structure
291 * @speed: pointer to link speed
292 * @negotiation: TRUE when autoneg or autotry is enabled
293 *
294 * Determines the link capabilities by reading the AUTOC register.
295 **/
296 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
297 ixgbe_link_speed *speed,
298 bool *negotiation)
299 {
300 s32 status = IXGBE_SUCCESS;
301 u32 autoc = 0;
302
303 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
304
305
306 /* Check if 1G SFP module. */
307 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
308 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
309 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
310 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
311 *speed = IXGBE_LINK_SPEED_1GB_FULL;
312 *negotiation = TRUE;
313 goto out;
314 }
315
316 /*
317 * Determine link capabilities based on the stored value of AUTOC,
318 * which represents EEPROM defaults. If AUTOC value has not
319 * been stored, use the current register values.
320 */
321 if (hw->mac.orig_link_settings_stored)
322 autoc = hw->mac.orig_autoc;
323 else
324 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
325
326 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
327 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
328 *speed = IXGBE_LINK_SPEED_1GB_FULL;
329 *negotiation = FALSE;
330 break;
386 out:
387 return status;
388 }
389
390 /**
391 * ixgbe_get_media_type_82599 - Get media type
392 * @hw: pointer to hardware structure
393 *
394 * Returns the media type (fiber, copper, backplane)
395 **/
396 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
397 {
398 enum ixgbe_media_type media_type;
399
400 DEBUGFUNC("ixgbe_get_media_type_82599");
401
402 /* Detect if there is a copper PHY attached. */
403 switch (hw->phy.type) {
404 case ixgbe_phy_cu_unknown:
405 case ixgbe_phy_tn:
406 media_type = ixgbe_media_type_copper;
407 goto out;
408 default:
409 break;
410 }
411
412 switch (hw->device_id) {
413 case IXGBE_DEV_ID_82599_KX4:
414 case IXGBE_DEV_ID_82599_KX4_MEZZ:
415 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
416 case IXGBE_DEV_ID_82599_KR:
417 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
418 case IXGBE_DEV_ID_82599_XAUI_LOM:
419 /* Default device ID is mezzanine card KX/KX4 */
420 media_type = ixgbe_media_type_backplane;
421 break;
422 case IXGBE_DEV_ID_82599_SFP:
423 case IXGBE_DEV_ID_82599_SFP_FCOE:
424 case IXGBE_DEV_ID_82599_SFP_EM:
425 case IXGBE_DEV_ID_82599_SFP_SF2:
936 * @hw: pointer to hardware structure
937 * @speed: new link speed
938 * @autoneg: TRUE if autonegotiation enabled
939 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
940 *
941 * Restarts link on PHY and MAC based on settings passed in.
942 **/
943 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
944 ixgbe_link_speed speed,
945 bool autoneg,
946 bool autoneg_wait_to_complete)
947 {
948 s32 status;
949
950 DEBUGFUNC("ixgbe_setup_copper_link_82599");
951
952 /* Setup the PHY according to input speed */
953 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
954 autoneg_wait_to_complete);
955 /* Set up MAC */
956 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
957
958 return status;
959 }
960
961 /**
962 * ixgbe_reset_hw_82599 - Perform hardware reset
963 * @hw: pointer to hardware structure
964 *
965 * Resets the hardware by resetting the transmit and receive units, masks
966 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
967 * reset.
968 **/
969 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
970 {
971 ixgbe_link_speed link_speed;
972 s32 status;
973 u32 ctrl, i, autoc, autoc2;
974 bool link_up = FALSE;
975
976 DEBUGFUNC("ixgbe_reset_hw_82599");
977
978 /* Call adapter stop to disable tx/rx and clear interrupts */
979 status = hw->mac.ops.stop_adapter(hw);
980 if (status != IXGBE_SUCCESS)
981 goto reset_hw_out;
982
983 /* flush pending Tx transactions */
984 ixgbe_clear_tx_pending(hw);
985
986 /* PHY ops must be identified and initialized prior to reset */
987
988 /* Identify PHY and related function pointers */
989 status = hw->phy.ops.init(hw);
990
991 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
992 goto reset_hw_out;
993
994 /* Setup SFP module if there is one present. */
995 if (hw->phy.sfp_setup_needed) {
996 status = hw->mac.ops.setup_sfp(hw);
997 hw->phy.sfp_setup_needed = FALSE;
998 }
999
1000 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1001 goto reset_hw_out;
1002
1003 /* Reset PHY */
1004 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
1005 hw->phy.ops.reset(hw);
1006
1007 mac_reset_top:
1008 /*
1009 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1010 * If link reset is used when link is up, it might reset the PHY when
1011 * mng is using it. If link is down or the flag to force full link
1012 * reset is set, then perform link reset.
1013 */
1014 ctrl = IXGBE_CTRL_LNK_RST;
1015 if (!hw->force_full_reset) {
1016 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
1017 if (link_up)
1018 ctrl = IXGBE_CTRL_RST;
1019 }
1020
1021 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1022 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1023 IXGBE_WRITE_FLUSH(hw);
1024
1025 /* Poll for reset bit to self-clear indicating reset is complete */
1026 for (i = 0; i < 10; i++) {
1027 usec_delay(1);
1028 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1029 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1030 break;
1031 }
1032
1033 if (ctrl & IXGBE_CTRL_RST_MASK) {
1034 status = IXGBE_ERR_RESET_FAILED;
1035 DEBUGOUT("Reset polling failed to complete.\n");
1036 }
1037
1038 msec_delay(50);
1039
1040 /*
1041 * Double resets are required for recovery from certain error
1042 * conditions. Between resets, it is necessary to stall to allow time
1043 * for any pending HW events to complete.
1044 */
1045 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1046 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1047 goto mac_reset_top;
1048 }
1049
1050 /*
1051 * Store the original AUTOC/AUTOC2 values if they have not been
1052 * stored off yet. Otherwise restore the stored original
1053 * values since the reset operation sets back to defaults.
1054 */
1055 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1056 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1057 if (hw->mac.orig_link_settings_stored == FALSE) {
1058 hw->mac.orig_autoc = autoc;
1059 hw->mac.orig_autoc2 = autoc2;
1060 hw->mac.orig_link_settings_stored = TRUE;
1061 } else {
1062 if (autoc != hw->mac.orig_autoc)
1063 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
1064 IXGBE_AUTOC_AN_RESTART));
1065
1066 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1067 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1068 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1069 autoc2 |= (hw->mac.orig_autoc2 &
1074
1075 /* Store the permanent mac address */
1076 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1077
1078 /*
1079 * Store MAC address from RAR0, clear receive address registers, and
1080 * clear the multicast table. Also reset num_rar_entries to 128,
1081 * since we modify this value when programming the SAN MAC address.
1082 */
1083 hw->mac.num_rar_entries = 128;
1084 hw->mac.ops.init_rx_addrs(hw);
1085
1086 /* Store the permanent SAN mac address */
1087 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1088
1089 /* Add the SAN MAC address to the RAR only if it's a valid address */
1090 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1091 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1092 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1093
1094 /* Save the SAN MAC RAR index */
1095 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1096
1097 /* Reserve the last RAR for the SAN MAC address */
1098 hw->mac.num_rar_entries--;
1099 }
1100
1101 /* Store the alternative WWNN/WWPN prefix */
1102 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1103 &hw->mac.wwpn_prefix);
1104
1105 reset_hw_out:
1106 return status;
1107 }
1108
1109 /**
1110 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1111 * @hw: pointer to hardware structure
1112 **/
1113 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1114 {
1115 int i;
1116 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1117 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1118
1119 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1120
1121 /*
1122 * Before starting reinitialization process,
1123 * FDIRCMD.CMD must be zero.
1124 */
1125 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1126 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1127 IXGBE_FDIRCMD_CMD_MASK))
1128 break;
1129 usec_delay(10);
1130 }
1131 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1132 DEBUGOUT("Flow Director previous command isn't complete, "
1133 "aborting table re-initialization.\n");
1134 return IXGBE_ERR_FDIR_REINIT_FAILED;
1135 }
1136
1137 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1138 IXGBE_WRITE_FLUSH(hw);
1139 /*
1140 * 82599 adapters flow director init flow cannot be restarted,
1141 * Workaround 82599 silicon errata by performing the following steps
1142 * before re-writing the FDIRCTRL control register with the same value.
1143 * - write 1 to bit 8 of FDIRCMD register &
1144 * - write 0 to bit 8 of FDIRCMD register
1145 */
1146 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1147 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1148 IXGBE_FDIRCMD_CLEARHT));
1149 IXGBE_WRITE_FLUSH(hw);
1150 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1151 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1152 ~IXGBE_FDIRCMD_CLEARHT));
1153 IXGBE_WRITE_FLUSH(hw);
1157 */
1158 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1159 IXGBE_WRITE_FLUSH(hw);
1160
1161 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1162 IXGBE_WRITE_FLUSH(hw);
1163
1164 /* Poll init-done after we write FDIRCTRL register */
1165 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1166 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1167 IXGBE_FDIRCTRL_INIT_DONE)
1168 break;
1169 usec_delay(10);
1170 }
1171 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1172 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1173 return IXGBE_ERR_FDIR_REINIT_FAILED;
1174 }
1175
1176 /* Clear FDIR statistics registers (read to clear) */
1177 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1178 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1179 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1180 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1181 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1182
1183 return IXGBE_SUCCESS;
1184 }
1185
1186 /**
1187 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1188 * @hw: pointer to hardware structure
1189 * @fdirctrl: value to write to flow director control register
1190 **/
1191 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1192 {
1193 int i;
1194
1195 DEBUGFUNC("ixgbe_fdir_enable_82599");
1196
1197 /* Prime the keys for hashing */
1198 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1199 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1200
1201 /*
1202 * Poll init-done after we write the register. Estimated times:
1203 * 10G: PBALLOC = 11b, timing is 60us
1204 * 1G: PBALLOC = 11b, timing is 600us
1205 * 100M: PBALLOC = 11b, timing is 6ms
1206 *
1207 * Multiple these timings by 4 if under full Rx load
1208 *
1209 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1210 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1211 * this might not finish in our poll time, but we can live with that
1212 * for now.
1213 */
1214 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1215 IXGBE_WRITE_FLUSH(hw);
1216 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1217 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1218 IXGBE_FDIRCTRL_INIT_DONE)
1219 break;
1220 msec_delay(1);
1221 }
1222
1223 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1224 DEBUGOUT("Flow Director poll time exceeded!\n");
1225 }
1226
1227 /**
1228 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1229 * @hw: pointer to hardware structure
1230 * @fdirctrl: value to write to flow director control register, initially
1231 * contains just the value of the Rx packet buffer allocation
1232 **/
1233 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1234 {
1235 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1236
1237 /*
1238 * Continue setup of fdirctrl register bits:
1239 * Move the flexible bytes to use the ethertype - shift 6 words
1240 * Set the maximum length per hash bucket to 0xA filters
1241 * Send interrupt when 64 filters are left
1242 */
1243 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1244 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1245 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1246
1247 /* write hashes and fdirctrl register, poll for completion */
1248 ixgbe_fdir_enable_82599(hw, fdirctrl);
1249
1250 return IXGBE_SUCCESS;
1251 }
1252
1253 /**
1254 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1255 * @hw: pointer to hardware structure
1256 * @fdirctrl: value to write to flow director control register, initially
1257 * contains just the value of the Rx packet buffer allocation
1258 **/
1259 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1260 {
1261 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1262
1263 /*
1264 * Continue setup of fdirctrl register bits:
1265 * Turn perfect match filtering on
1266 * Report hash in RSS field of Rx wb descriptor
1267 * Initialize the drop queue
1268 * Move the flexible bytes to use the ethertype - shift 6 words
1269 * Set the maximum length per hash bucket to 0xA filters
1270 * Send interrupt when 64 (0x4 * 16) filters are left
1271 */
1272 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1273 IXGBE_FDIRCTRL_REPORT_STATUS |
1274 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1275 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1276 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1277 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1278
1279 /* write hashes and fdirctrl register, poll for completion */
1280 ixgbe_fdir_enable_82599(hw, fdirctrl);
1281
1282 return IXGBE_SUCCESS;
1283 }
1284
1285 /*
1286 * These defines allow us to quickly generate all of the necessary instructions
1287 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1288 * for values 0 through 15
1289 */
1290 #define IXGBE_ATR_COMMON_HASH_KEY \
1291 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1292 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1293 do { \
1294 u32 n = (_n); \
1295 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1296 common_hash ^= lo_hash_dword >> n; \
1297 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1298 bucket_hash ^= lo_hash_dword >> n; \
1299 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1300 sig_hash ^= lo_hash_dword << (16 - n); \
1301 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1302 common_hash ^= hi_hash_dword >> n; \
1303 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1304 bucket_hash ^= hi_hash_dword >> n; \
1305 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1306 sig_hash ^= hi_hash_dword << (16 - n); \
1307 } while (0);
1308
1309 /**
1310 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1311 * @stream: input bitstream to compute the hash on
1312 *
1313 * This function is almost identical to the function above but contains
1314 * several optomizations such as unwinding all of the loops, letting the
1315 * compiler work out all of the conditional ifs since the keys are static
1316 * defines, and computing two keys at once since the hashed dword stream
1317 * will be the same for both keys.
1318 **/
1319 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1320 union ixgbe_atr_hash_dword common)
1321 {
1322 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1323 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1324
1325 /* record the flow_vm_vlan bits as they are a key part to the hash */
1326 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1327
1328 /* generate common hash dword */
1329 hi_hash_dword = IXGBE_NTOHL(common.dword);
1330
1331 /* low dword is word swapped version of common */
1332 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1333
1334 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1335 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1336
1337 /* Process bits 0 and 16 */
1338 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1339
1358 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1359 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1360 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1361 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1362 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1363
1364 /* combine common_hash result with signature and bucket hashes */
1365 bucket_hash ^= common_hash;
1366 bucket_hash &= IXGBE_ATR_HASH_MASK;
1367
1368 sig_hash ^= common_hash << 16;
1369 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1370
1371 /* return completed signature hash */
1372 return sig_hash ^ bucket_hash;
1373 }
1374
1375 /**
1376 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1377 * @hw: pointer to hardware structure
1378 * @input: unique input dword
1379 * @common: compressed common input dword
1380 * @queue: queue index to direct traffic to
1381 **/
1382 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1383 union ixgbe_atr_hash_dword input,
1384 union ixgbe_atr_hash_dword common,
1385 u8 queue)
1386 {
1387 u64 fdirhashcmd;
1388 u32 fdircmd;
1389
1390 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1391
1392 /*
1393 * Get the flow_type in order to program FDIRCMD properly
1394 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1395 */
1396 switch (input.formatted.flow_type) {
1397 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1398 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1399 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1408
1409 /* configure FDIRCMD register */
1410 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1411 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1412 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1413 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1414
1415 /*
1416 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1417 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1418 */
1419 fdirhashcmd = (u64)fdircmd << 32;
1420 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1421 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1422
1423 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1424
1425 return IXGBE_SUCCESS;
1426 }
1427
1428 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1429 do { \
1430 u32 n = (_n); \
1431 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1432 bucket_hash ^= lo_hash_dword >> n; \
1433 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1434 bucket_hash ^= hi_hash_dword >> n; \
1435 } while (0);
1436
1437 /**
1438 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1439 * @atr_input: input bitstream to compute the hash on
1440 * @input_mask: mask for the input bitstream
1441 *
1442 * This function serves two main purposes. First it applys the input_mask
1443 * to the atr_input resulting in a cleaned up atr_input data stream.
1444 * Secondly it computes the hash and stores it in the bkt_hash field at
1445 * the end of the input byte stream. This way it will be available for
1446 * future use without needing to recompute the hash.
1447 **/
1448 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1449 union ixgbe_atr_input *input_mask)
1450 {
1451
1452 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1453 u32 bucket_hash = 0;
1454
1455 /* Apply masks to input data */
1456 input->dword_stream[0] &= input_mask->dword_stream[0];
1457 input->dword_stream[1] &= input_mask->dword_stream[1];
1458 input->dword_stream[2] &= input_mask->dword_stream[2];
1459 input->dword_stream[3] &= input_mask->dword_stream[3];
1460 input->dword_stream[4] &= input_mask->dword_stream[4];
1461 input->dword_stream[5] &= input_mask->dword_stream[5];
1462 input->dword_stream[6] &= input_mask->dword_stream[6];
1463 input->dword_stream[7] &= input_mask->dword_stream[7];
1464 input->dword_stream[8] &= input_mask->dword_stream[8];
1465 input->dword_stream[9] &= input_mask->dword_stream[9];
1466 input->dword_stream[10] &= input_mask->dword_stream[10];
1467
1468 /* record the flow_vm_vlan bits as they are a key part to the hash */
1469 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1470
1471 /* generate common hash dword */
1472 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1473 input->dword_stream[2] ^
1474 input->dword_stream[3] ^
1475 input->dword_stream[4] ^
1476 input->dword_stream[5] ^
1477 input->dword_stream[6] ^
1478 input->dword_stream[7] ^
1479 input->dword_stream[8] ^
1480 input->dword_stream[9] ^
1481 input->dword_stream[10]);
1482
1483 /* low dword is word swapped version of common */
1484 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1485
1486 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1487 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1488
1489 /* Process bits 0 and 16 */
1490 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1491
1492 /*
1493 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1494 * delay this because bit 0 of the stream should not be processed
1495 * so we do not add the vlan until after bit 0 was processed
1496 */
1497 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1498
1499 /* Process remaining 30 bit of the key */
1500 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1501 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1502 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1503 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1504 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1505 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1506 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1507 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1508 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1509 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1510 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1511 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1512 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1513 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1514 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1515
1516 /*
1517 * Limit hash to 13 bits since max bucket count is 8K.
1518 * Store result at the end of the input stream.
1519 */
1520 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1521 }
1522
1523 /**
1524 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1525 * @input_mask: mask to be bit swapped
1526 *
1527 * The source and destination port masks for flow director are bit swapped
1528 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1529 * generate a correctly swapped value we need to bit swap the mask and that
1530 * is what is accomplished by this function.
1531 **/
1532 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1533 {
1534 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1535 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1536 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1537 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1538 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1539 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1540 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1541 }
1542
1543 /*
1544 * These two macros are meant to address the fact that we have registers
1545 * that are either all or in part big-endian. As a result on big-endian
1546 * systems we will end up byte swapping the value to little-endian before
1547 * it is byte swapped again and written to the hardware in the original
1548 * big-endian format.
1549 */
1550 #define IXGBE_STORE_AS_BE32(_value) \
1551 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1552 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1553
1554 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1555 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1556
1557 #define IXGBE_STORE_AS_BE16(_value) \
1558 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1559
1560 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1561 union ixgbe_atr_input *input_mask)
1562 {
1563 /* mask IPv6 since it is currently not supported */
1564 u32 fdirm = IXGBE_FDIRM_DIPv6;
1565 u32 fdirtcpm;
1566
1567 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1568
1569 /*
1570 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1571 * are zero, then assume a full mask for that field. Also assume that
1572 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1573 * cannot be masked out in this implementation.
1574 *
1575 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1576 * point in time.
1577 */
1578
1579 /* verify bucket hash is cleared on hash generation */
1580 if (input_mask->formatted.bkt_hash)
1581 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1582
1583 /* Program FDIRM and verify partial masks */
1584 switch (input_mask->formatted.vm_pool & 0x7F) {
1585 case 0x0:
1586 fdirm |= IXGBE_FDIRM_POOL;
1587 case 0x7F:
1588 break;
1589 default:
1590 DEBUGOUT(" Error on vm pool mask\n");
1591 return IXGBE_ERR_CONFIG;
1592 }
1593
1594 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1595 case 0x0:
1596 fdirm |= IXGBE_FDIRM_L4P;
1597 if (input_mask->formatted.dst_port ||
1598 input_mask->formatted.src_port) {
1599 DEBUGOUT(" Error on src/dst port mask\n");
1600 return IXGBE_ERR_CONFIG;
1601 }
1602 case IXGBE_ATR_L4TYPE_MASK:
1603 break;
1604 default:
1605 DEBUGOUT(" Error on flow type mask\n");
1606 return IXGBE_ERR_CONFIG;
1607 }
1608
1609 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1610 case 0x0000:
1611 /* mask VLAN ID, fall through to mask VLAN priority */
1612 fdirm |= IXGBE_FDIRM_VLANID;
1613 case 0x0FFF:
1614 /* mask VLAN priority */
1615 fdirm |= IXGBE_FDIRM_VLANP;
1616 break;
1617 case 0xE000:
1618 /* mask VLAN ID only, fall through */
1619 fdirm |= IXGBE_FDIRM_VLANID;
1620 case 0xEFFF:
1621 /* no VLAN fields masked */
1622 break;
1623 default:
1624 DEBUGOUT(" Error on VLAN mask\n");
1625 return IXGBE_ERR_CONFIG;
1626 }
1627
1628 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1629 case 0x0000:
1630 /* Mask Flex Bytes, fall through */
1631 fdirm |= IXGBE_FDIRM_FLEX;
1632 case 0xFFFF:
1633 break;
1634 default:
1635 DEBUGOUT(" Error on flexible byte mask\n");
1636 return IXGBE_ERR_CONFIG;
1637 }
1638
1639 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1640 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1641
1642 /* store the TCP/UDP port masks, bit reversed from port layout */
1643 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1644
1645 /* write both the same so that UDP and TCP use the same mask */
1646 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1647 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1648
1649 /* store source and destination IP masks (big-enian) */
1650 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1651 ~input_mask->formatted.src_ip[0]);
1652 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1653 ~input_mask->formatted.dst_ip[0]);
1654
1655 return IXGBE_SUCCESS;
1656 }
1657
1658 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1659 union ixgbe_atr_input *input,
1660 u16 soft_id, u8 queue)
1661 {
1662 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1663
1664 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1665
1666 /* currently IPv6 is not supported, must be programmed with 0 */
1667 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1668 input->formatted.src_ip[0]);
1669 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1670 input->formatted.src_ip[1]);
1671 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1672 input->formatted.src_ip[2]);
1673
1674 /* record the source address (big-endian) */
1675 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1676
1677 /* record the first 32 bits of the destination address (big-endian) */
1678 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1679
1680 /* record source and destination port (little-endian)*/
1681 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1682 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1683 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1684 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1685
1686 /* record vlan (little-endian) and flex_bytes(big-endian) */
1687 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1688 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1689 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1690 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1691
1692 /* configure FDIRHASH register */
1693 fdirhash = input->formatted.bkt_hash;
1694 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1695 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1696
1697 /*
1698 * flush all previous writes to make certain registers are
1699 * programmed prior to issuing the command
1700 */
1701 IXGBE_WRITE_FLUSH(hw);
1702
1703 /* configure FDIRCMD register */
1704 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1705 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1706 if (queue == IXGBE_FDIR_DROP_QUEUE)
1707 fdircmd |= IXGBE_FDIRCMD_DROP;
1708 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1709 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1710 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1711
1712 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1713
1714 return IXGBE_SUCCESS;
1715 }
1716
1717 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1718 union ixgbe_atr_input *input,
1719 u16 soft_id)
1720 {
1721 u32 fdirhash;
1722 u32 fdircmd = 0;
1723 u32 retry_count;
1724 s32 err = IXGBE_SUCCESS;
1725
1726 /* configure FDIRHASH register */
1727 fdirhash = input->formatted.bkt_hash;
1728 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1729 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1730
1731 /* flush hash to HW */
1732 IXGBE_WRITE_FLUSH(hw);
1733
1734 /* Query if filter is present */
1735 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1736
1737 for (retry_count = 10; retry_count; retry_count--) {
1738 /* allow 10us for query to process */
1739 usec_delay(10);
1740 /* verify query completed successfully */
1741 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1742 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1743 break;
1744 }
1745
1746 if (!retry_count)
1747 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1748
1749 /* if filter exists in hardware then remove it */
1750 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1751 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1752 IXGBE_WRITE_FLUSH(hw);
1753 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1754 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1755 }
1756
1757 return err;
1758 }
1759
1760 /**
1761 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1762 * @hw: pointer to hardware structure
1763 * @input: input bitstream
1764 * @input_mask: mask for the input bitstream
1765 * @soft_id: software index for the filters
1766 * @queue: queue index to direct traffic to
1767 *
1768 * Note that the caller to this function must lock before calling, since the
1769 * hardware writes must be protected from one another.
1770 **/
1771 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1772 union ixgbe_atr_input *input,
1773 union ixgbe_atr_input *input_mask,
1774 u16 soft_id, u8 queue)
1775 {
1776 s32 err = IXGBE_ERR_CONFIG;
1777
1778 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1779
1780 /*
1781 * Check flow_type formatting, and bail out before we touch the hardware
1782 * if there's a configuration issue
1783 */
1784 switch (input->formatted.flow_type) {
1785 case IXGBE_ATR_FLOW_TYPE_IPV4:
1786 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1787 if (input->formatted.dst_port || input->formatted.src_port) {
1788 DEBUGOUT(" Error on src/dst port\n");
1789 return IXGBE_ERR_CONFIG;
1790 }
1791 break;
1792 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1793 if (input->formatted.dst_port || input->formatted.src_port) {
1794 DEBUGOUT(" Error on src/dst port\n");
1795 return IXGBE_ERR_CONFIG;
1796 }
1797 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1798 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1799 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1800 IXGBE_ATR_L4TYPE_MASK;
1801 break;
1802 default:
1803 DEBUGOUT(" Error on flow type input\n");
1804 return err;
1805 }
1806
1807 /* program input mask into the HW */
1808 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1809 if (err)
1810 return err;
1811
1812 /* apply mask and compute/store hash */
1813 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1814
1815 /* program filters to filter memory */
1816 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1817 soft_id, queue);
1818 }
1819
1820 /**
1821 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1822 * @hw: pointer to hardware structure
1823 * @reg: analog register to read
1824 * @val: read value
1825 *
1826 * Performs read operation to Omer analog register specified.
1827 **/
1828 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1829 {
1830 u32 core_ctl;
1831
1832 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1833
1834 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1835 (reg << 8));
1836 IXGBE_WRITE_FLUSH(hw);
1837 usec_delay(10);
1838 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1839 *val = (u8)core_ctl;
1840
1847 * @reg: atlas register to write
1848 * @val: value to write
1849 *
1850 * Performs write operation to Omer analog register specified.
1851 **/
1852 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1853 {
1854 u32 core_ctl;
1855
1856 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
1857
1858 core_ctl = (reg << 8) | val;
1859 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1860 IXGBE_WRITE_FLUSH(hw);
1861 usec_delay(10);
1862
1863 return IXGBE_SUCCESS;
1864 }
1865
1866 /**
1867 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1868 * @hw: pointer to hardware structure
1869 *
1870 * Starts the hardware using the generic start_hw function
1871 * and the generation start_hw function.
1872 * Then performs revision-specific operations, if any.
1873 **/
1874 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1875 {
1876 s32 ret_val = IXGBE_SUCCESS;
1877
1878 DEBUGFUNC("ixgbe_start_hw_82599");
1879
1880 ret_val = ixgbe_start_hw_generic(hw);
1881 if (ret_val != IXGBE_SUCCESS)
1882 goto out;
1883
1884 ret_val = ixgbe_start_hw_gen2(hw);
1885 if (ret_val != IXGBE_SUCCESS)
1886 goto out;
1887
1888 /* We need to run link autotry after the driver loads */
1889 hw->mac.autotry_restart = TRUE;
1890
1891 if (ret_val == IXGBE_SUCCESS)
1892 ret_val = ixgbe_verify_fw_version_82599(hw);
1893 out:
1894 return ret_val;
1895 }
1896
1897 /**
1898 * ixgbe_identify_phy_82599 - Get physical layer module
1899 * @hw: pointer to hardware structure
1900 *
1901 * Determines the physical layer module found on the current adapter.
1902 * If PHY already detected, maintains current PHY type in hw struct,
1903 * otherwise executes the PHY detection routine.
1904 **/
1905 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1906 {
1907 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1908
1909 DEBUGFUNC("ixgbe_identify_phy_82599");
1910
1911 /* Detect PHY if not unknown - returns success if already detected. */
1912 status = ixgbe_identify_phy_generic(hw);
1913 if (status != IXGBE_SUCCESS) {
1914 /* 82599 10GBASE-T requires an external PHY */
1915 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1916 goto out;
1917 else
1918 status = ixgbe_identify_module_generic(hw);
1919 }
1920
1921 /* Set PHY type none if no PHY detected */
1922 if (hw->phy.type == ixgbe_phy_unknown) {
1923 hw->phy.type = ixgbe_phy_none;
1924 status = IXGBE_SUCCESS;
1925 }
1926
1927 /* Return error if SFP module has been detected but is not supported */
1928 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1929 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1930
1931 out:
1932 return status;
1933 }
1934
1935 /**
1936 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1937 * @hw: pointer to hardware structure
1938 *
1939 * Determines physical layer capabilities of the current configuration.
1940 **/
1941 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1942 {
1943 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1944 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1945 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1946 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1947 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1948 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1949 u16 ext_ability = 0;
1950 u8 comp_codes_10g = 0;
1951 u8 comp_codes_1g = 0;
1952
1953 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
1954
1955 hw->phy.ops.identify(hw);
1956
1957 switch (hw->phy.type) {
1958 case ixgbe_phy_tn:
1959 case ixgbe_phy_cu_unknown:
1960 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1961 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1962 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1963 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1964 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1965 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1966 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1967 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1968 goto out;
1969 default:
1970 break;
1971 }
1972
1973 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1974 case IXGBE_AUTOC_LMS_1G_AN:
1975 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1976 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1977 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1978 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2022 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2023 break;
2024 case ixgbe_phy_sfp_ftl_active:
2025 case ixgbe_phy_sfp_active_unknown:
2026 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2027 break;
2028 case ixgbe_phy_sfp_avago:
2029 case ixgbe_phy_sfp_ftl:
2030 case ixgbe_phy_sfp_intel:
2031 case ixgbe_phy_sfp_unknown:
2032 hw->phy.ops.read_i2c_eeprom(hw,
2033 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2034 hw->phy.ops.read_i2c_eeprom(hw,
2035 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2036 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2037 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2038 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2039 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2040 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2041 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2042 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2043 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2044 break;
2045 default:
2046 break;
2047 }
2048
2049 out:
2050 return physical_layer;
2051 }
2052
2053 /**
2054 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2055 * @hw: pointer to hardware structure
2056 * @regval: register value to write to RXCTRL
2057 *
2058 * Enables the Rx DMA unit for 82599
2059 **/
2060 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2061 {
2062
2063 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2064
2065 /*
2066 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2067 * If traffic is incoming before we enable the Rx unit, it could hang
2068 * the Rx DMA unit. Therefore, make sure the security engine is
2069 * completely disabled prior to enabling the Rx unit.
2070 */
2071
2072 hw->mac.ops.disable_sec_rx_path(hw);
2073
2074 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2075
2076 hw->mac.ops.enable_sec_rx_path(hw);
2077
2078 return IXGBE_SUCCESS;
2079 }
2080
2081 /**
2082 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2083 * @hw: pointer to hardware structure
2084 *
2085 * Verifies that installed the firmware version is 0.6 or higher
2086 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2087 *
2088 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2089 * if the FW version is not supported.
2090 **/
2091 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2092 {
2093 s32 status = IXGBE_ERR_EEPROM_VERSION;
2094 u16 fw_offset, fw_ptp_cfg_offset;
2095 u16 fw_version = 0;
2096
2097 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2101 status = IXGBE_SUCCESS;
2102 goto fw_version_out;
2103 }
2104
2105 /* get the offset to the Firmware Module block */
2106 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2107
2108 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2109 goto fw_version_out;
2110
2111 /* get the offset to the Pass Through Patch Configuration block */
2112 hw->eeprom.ops.read(hw, (fw_offset +
2113 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2114 &fw_ptp_cfg_offset);
2115
2116 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2117 goto fw_version_out;
2118
2119 /* get the firmware version */
2120 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2121 IXGBE_FW_PATCH_VERSION_4), &fw_version);
2122
2123 if (fw_version > 0x5)
2124 status = IXGBE_SUCCESS;
2125
2126 fw_version_out:
2127 return status;
2128 }
2129
2130 /**
2131 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2132 * @hw: pointer to hardware structure
2133 *
2134 * Returns TRUE if the LESM FW module is present and enabled. Otherwise
2135 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled.
2136 **/
2137 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2138 {
2139 bool lesm_enabled = FALSE;
2140 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2141 s32 status;
2154 IXGBE_FW_LESM_PARAMETERS_PTR),
2155 &fw_lesm_param_offset);
2156
2157 if ((status != IXGBE_SUCCESS) ||
2158 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2159 goto out;
2160
2161 /* get the lesm state word */
2162 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2163 IXGBE_FW_LESM_STATE_1),
2164 &fw_lesm_state);
2165
2166 if ((status == IXGBE_SUCCESS) &&
2167 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2168 lesm_enabled = TRUE;
2169
2170 out:
2171 return lesm_enabled;
2172 }
2173
2174 /**
2175 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2176 * fastest available method
2177 *
2178 * @hw: pointer to hardware structure
2179 * @offset: offset of word in EEPROM to read
2180 * @words: number of words
2181 * @data: word(s) read from the EEPROM
2182 *
2183 * Retrieves 16 bit word(s) read from EEPROM
2184 **/
2185 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2186 u16 words, u16 *data)
2187 {
2188 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2189 s32 ret_val = IXGBE_ERR_CONFIG;
2190
2191 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2192
2193 /*
2194 * If EEPROM is detected and can be addressed using 14 bits,
2195 * use EERD otherwise use bit bang
2196 */
2197 if ((eeprom->type == ixgbe_eeprom_spi) &&
2198 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2199 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2200 data);
2201 else
2202 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2203 words,
2204 data);
2205
2206 return ret_val;
2207 }
2208
2209 /**
2210 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2211 * fastest available method
2212 *
2213 * @hw: pointer to hardware structure
2214 * @offset: offset of word in the EEPROM to read
2215 * @data: word read from the EEPROM
2216 *
2217 * Reads a 16 bit word from the EEPROM
2218 **/
2219 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2220 u16 offset, u16 *data)
2221 {
2222 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2223 s32 ret_val = IXGBE_ERR_CONFIG;
2224
2225 DEBUGFUNC("ixgbe_read_eeprom_82599");
2226
2227 /*
2228 * If EEPROM is detected and can be addressed using 14 bits,
2229 * use EERD otherwise use bit bang
2230 */
2231 if ((eeprom->type == ixgbe_eeprom_spi) &&
2232 (offset <= IXGBE_EERD_MAX_ADDR))
2233 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2234 else
2235 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2236
2237 return ret_val;
2238 }
2239
2240
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