1061 ASSERT(tx_ring->work_list[tcb_index] == NULL);
1062 tx_ring->work_list[tcb_index] = tcb;
1063
1064 tcb_index = index;
1065 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list);
1066 }
1067
1068 if (load_context) {
1069 /*
1070 * Count the context descriptor for
1071 * the first tx control block.
1072 */
1073 first_tcb->desc_num++;
1074 }
1075 first_tcb->last_index = PREV_INDEX(index, 1, tx_ring->ring_size);
1076
1077 /*
1078 * The Insert Ethernet CRC (IFCS) bit and the checksum fields are only
1079 * valid in the first descriptor of the packet.
1080 * Setting paylen in every first_tbd for all parts.
1081 * 82599 requires the packet length in paylen field with or without
1082 * LSO and 82598 will ignore it in non-LSO mode.
1083 */
1084 ASSERT(first_tbd != NULL);
1085 first_tbd->read.cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS;
1086
1087 switch (hw->mac.type) {
1088 case ixgbe_mac_82598EB:
1089 if (ctx != NULL && ctx->lso_flag) {
1090 first_tbd->read.cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
1091 first_tbd->read.olinfo_status |=
1092 (mbsize - ctx->mac_hdr_len - ctx->ip_hdr_len
1093 - ctx->l4_hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT;
1094 }
1095 break;
1096
1097 case ixgbe_mac_82599EB:
1098 if (ctx != NULL && ctx->lso_flag) {
1099 first_tbd->read.cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
1100 first_tbd->read.olinfo_status |=
1101 (mbsize - ctx->mac_hdr_len - ctx->ip_hdr_len
1102 - ctx->l4_hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT;
1103 } else {
1104 first_tbd->read.olinfo_status |=
1105 (mbsize << IXGBE_ADVTXD_PAYLEN_SHIFT);
1106 }
1107 break;
1108
1109 default:
1110 break;
1111 }
1112
1113 /* Set hardware checksum bits */
1114 if (hcksum_flags != 0) {
1115 if (hcksum_flags & HCK_IPV4_HDRCKSUM)
1116 first_tbd->read.olinfo_status |=
1117 IXGBE_ADVTXD_POPTS_IXSM;
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1061 ASSERT(tx_ring->work_list[tcb_index] == NULL);
1062 tx_ring->work_list[tcb_index] = tcb;
1063
1064 tcb_index = index;
1065 tcb = (tx_control_block_t *)LIST_POP_HEAD(pending_list);
1066 }
1067
1068 if (load_context) {
1069 /*
1070 * Count the context descriptor for
1071 * the first tx control block.
1072 */
1073 first_tcb->desc_num++;
1074 }
1075 first_tcb->last_index = PREV_INDEX(index, 1, tx_ring->ring_size);
1076
1077 /*
1078 * The Insert Ethernet CRC (IFCS) bit and the checksum fields are only
1079 * valid in the first descriptor of the packet.
1080 * Setting paylen in every first_tbd for all parts.
1081 * 82599 and X540 require the packet length in paylen field with or
1082 * without LSO and 82598 will ignore it in non-LSO mode.
1083 */
1084 ASSERT(first_tbd != NULL);
1085 first_tbd->read.cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS;
1086
1087 switch (hw->mac.type) {
1088 case ixgbe_mac_82598EB:
1089 if (ctx != NULL && ctx->lso_flag) {
1090 first_tbd->read.cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
1091 first_tbd->read.olinfo_status |=
1092 (mbsize - ctx->mac_hdr_len - ctx->ip_hdr_len
1093 - ctx->l4_hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT;
1094 }
1095 break;
1096
1097 case ixgbe_mac_82599EB:
1098 case ixgbe_mac_X540:
1099 if (ctx != NULL && ctx->lso_flag) {
1100 first_tbd->read.cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
1101 first_tbd->read.olinfo_status |=
1102 (mbsize - ctx->mac_hdr_len - ctx->ip_hdr_len
1103 - ctx->l4_hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT;
1104 } else {
1105 first_tbd->read.olinfo_status |=
1106 (mbsize << IXGBE_ADVTXD_PAYLEN_SHIFT);
1107 }
1108 break;
1109
1110 default:
1111 break;
1112 }
1113
1114 /* Set hardware checksum bits */
1115 if (hcksum_flags != 0) {
1116 if (hcksum_flags & HCK_IPV4_HDRCKSUM)
1117 first_tbd->read.olinfo_status |=
1118 IXGBE_ADVTXD_POPTS_IXSM;
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