1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26 /*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30 #ifndef _IXGBE_OSDEP_H
31 #define _IXGBE_OSDEP_H
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 #include <sys/types.h>
38 #include <sys/byteorder.h>
39 #include <sys/conf.h>
40 #include <sys/debug.h>
41 #include <sys/stropts.h>
42 #include <sys/stream.h>
43 #include <sys/strlog.h>
44 #include <sys/kmem.h>
45 #include <sys/stat.h>
46 #include <sys/kstat.h>
47 #include <sys/modctl.h>
48 #include <sys/errno.h>
49 #include <sys/ddi.h>
50 #include <sys/dditypes.h>
51 #include <sys/sunddi.h>
52 #include <sys/pci.h>
53 #include <sys/atomic.h>
54 #include <sys/note.h>
55 #include "ixgbe_debug.h"
56
57 /* function declarations */
58 struct ixgbe_hw;
59 uint16_t ixgbe_read_pci_cfg(struct ixgbe_hw *, uint32_t);
60 void ixgbe_write_pci_cfg(struct ixgbe_hw *, uint32_t, uint32_t);
61
62 #define usec_delay(x) drv_usecwait(x)
63 #define msec_delay(x) drv_usecwait(x * 1000)
64
65 #define OS_DEP(hw) ((struct ixgbe_osdep *)((hw)->back))
66
67 #define false B_FALSE
68 #define true B_TRUE
69 #define FALSE B_FALSE
70 #define TRUE B_TRUE
71
72 #define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg
73 #define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg
74 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
75 #define PCI_COMMAND_REGISTER 0x04
76 #define PCI_EX_CONF_CAP 0xE0
77 #define SPEED_10GB 10000
78 #define SPEED_1GB 1000
79 #define SPEED_100 100
80 #define FULL_DUPLEX 2
81
82 #define IXGBE_WRITE_FLUSH(a) (void) IXGBE_READ_REG(a, IXGBE_STATUS)
83
84 #define IXGBE_WRITE_REG(a, reg, value) \
85 ddi_put32((OS_DEP(a))->reg_handle, \
86 (uint32_t *)((uintptr_t)(a)->hw_addr + reg), (value))
87
88 #define IXGBE_WRITE_REG_ARRAY(a, reg, index, value) \
89 IXGBE_WRITE_REG(a, ((reg) + ((index) << 2)), (value))
90
91 #define IXGBE_READ_REG(a, reg) \
92 ddi_get32((OS_DEP(a))->reg_handle, \
93 (uint32_t *)((uintptr_t)(a)->hw_addr + reg))
94
95 #define IXGBE_READ_REG_ARRAY(a, reg, index) \
96 IXGBE_READ_REG(a, ((reg) + ((index) << 2)))
97
98 #define msec_delay_irq msec_delay
99 #define IXGBE_HTONL htonl
100 #define IXGBE_NTOHL ntohl
101 #define IXGBE_NTOHS ntohs
102
103 #define UNREFERENCED_PARAMETER(x) _NOTE(ARGUNUSED(x))
104
105 typedef int8_t s8;
106 typedef int16_t s16;
107 typedef int32_t s32;
108 typedef int64_t s64;
109 typedef uint8_t u8;
110 typedef uint16_t u16;
111 typedef uint32_t u32;
112 typedef uint64_t u64;
113 typedef boolean_t bool;
114
115 struct ixgbe_osdep {
116 ddi_acc_handle_t reg_handle;
117 ddi_acc_handle_t cfg_handle;
118 struct ixgbe *ixgbe;
119 };
120
121 #ifdef __cplusplus
122 }
123 #endif
124
125 #endif /* _IXGBE_OSDEP_H */