1 /******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37 #include "ixgbe_api.h"
38
39 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
42 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
44 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
45 u16 count);
46 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
47 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
50
51 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
52 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
53 u16 *san_mac_offset);
54 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw);
55 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw);
56 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw);
57 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
58 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
59 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);
60
61 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan);
62
63 /**
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
66 *
67 * Initialize the function pointers.
68 **/
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 {
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
74
75 DEBUGFUNC("ixgbe_init_ops_generic");
76
77 /* EEPROM */
78 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & (1 << 8))
81 eeprom->ops.read = &ixgbe_read_eerd_generic;
82 else
83 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.write = &ixgbe_write_eeprom_generic;
85 eeprom->ops.validate_checksum =
86 &ixgbe_validate_eeprom_checksum_generic;
87 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
88 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
89
90 /* MAC */
91 mac->ops.init_hw = &ixgbe_init_hw_generic;
92 mac->ops.reset_hw = NULL;
93 mac->ops.start_hw = &ixgbe_start_hw_generic;
94 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
95 mac->ops.get_media_type = NULL;
96 mac->ops.get_supported_physical_layer = NULL;
97 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
98 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
99 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
100 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
101 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
102 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
103 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
104
105 /* LEDs */
106 mac->ops.led_on = &ixgbe_led_on_generic;
107 mac->ops.led_off = &ixgbe_led_off_generic;
108 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
109 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
110
111 /* RAR, Multicast, VLAN */
112 mac->ops.set_rar = &ixgbe_set_rar_generic;
113 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
114 mac->ops.insert_mac_addr = NULL;
115 mac->ops.set_vmdq = NULL;
116 mac->ops.clear_vmdq = NULL;
117 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
118 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
119 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
120 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
121 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
122 mac->ops.clear_vfta = NULL;
123 mac->ops.set_vfta = NULL;
124 mac->ops.init_uta_tables = NULL;
125
126 /* Flow Control */
127 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
128
129 /* Link */
130 mac->ops.get_link_capabilities = NULL;
131 mac->ops.setup_link = NULL;
132 mac->ops.check_link = NULL;
133
134 return IXGBE_SUCCESS;
135 }
136
137 /**
138 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
139 * @hw: pointer to hardware structure
140 *
141 * Starts the hardware by filling the bus info structure and media type, clears
142 * all on chip counters, initializes receive address registers, multicast
143 * table, VLAN filter table, calls routine to set up link and flow control
144 * settings, and leaves transmit and receive units disabled and uninitialized
145 **/
146 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
147 {
148 u32 ctrl_ext;
149
150 DEBUGFUNC("ixgbe_start_hw_generic");
151
152 /* Set the media type */
153 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
154
155 /* PHY ops initialization must be done in reset_hw() */
156
157 /* Clear the VLAN filter table */
158 hw->mac.ops.clear_vfta(hw);
159
160 /* Clear statistics registers */
161 hw->mac.ops.clear_hw_cntrs(hw);
162
163 /* Set No Snoop Disable */
164 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
165 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
166 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
167 IXGBE_WRITE_FLUSH(hw);
168
169 /* Setup flow control */
170 (void) ixgbe_setup_fc(hw, 0);
171
172 /* Clear adapter stopped flag */
173 hw->adapter_stopped = FALSE;
174
175 return IXGBE_SUCCESS;
176 }
177
178 /**
179 * ixgbe_start_hw_gen2 - Init sequence for common device family
180 * @hw: pointer to hw structure
181 *
182 * Performs the init sequence common to the second generation
183 * of 10 GbE devices.
184 * Devices in the second generation:
185 * 82599
186 * X540
187 **/
188 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
189 {
190 u32 i;
191 u32 regval;
192
193 /* Clear the rate limiters */
194 for (i = 0; i < hw->mac.max_tx_queues; i++) {
195 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
196 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
197 }
198 IXGBE_WRITE_FLUSH(hw);
199
200 /* Disable relaxed ordering */
201 for (i = 0; i < hw->mac.max_tx_queues; i++) {
202 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
203 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
204 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
205 }
206
207 for (i = 0; i < hw->mac.max_rx_queues; i++) {
208 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
209 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
210 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
211 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
212 }
213
214 return IXGBE_SUCCESS;
215 }
216
217 /**
218 * ixgbe_init_hw_generic - Generic hardware initialization
219 * @hw: pointer to hardware structure
220 *
221 * Initialize the hardware by resetting the hardware, filling the bus info
222 * structure and media type, clears all on chip counters, initializes receive
223 * address registers, multicast table, VLAN filter table, calls routine to set
224 * up link and flow control settings, and leaves transmit and receive units
225 * disabled and uninitialized
226 **/
227 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
228 {
229 s32 status;
230
237 /* Start the HW */
238 status = hw->mac.ops.start_hw(hw);
239 }
240
241 return status;
242 }
243
244 /**
245 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
246 * @hw: pointer to hardware structure
247 *
248 * Clears all hardware statistics counters by reading them from the hardware
249 * Statistics counters are clear on read.
250 **/
251 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
252 {
253 u16 i = 0;
254
255 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
256
257 (void) IXGBE_READ_REG(hw, IXGBE_CRCERRS);
258 (void) IXGBE_READ_REG(hw, IXGBE_ILLERRC);
259 (void) IXGBE_READ_REG(hw, IXGBE_ERRBC);
260 (void) IXGBE_READ_REG(hw, IXGBE_MSPDC);
261 for (i = 0; i < 8; i++)
262 (void) IXGBE_READ_REG(hw, IXGBE_MPC(i));
263
264 (void) IXGBE_READ_REG(hw, IXGBE_MLFC);
265 (void) IXGBE_READ_REG(hw, IXGBE_MRFC);
266 (void) IXGBE_READ_REG(hw, IXGBE_RLEC);
267 (void) IXGBE_READ_REG(hw, IXGBE_LXONTXC);
268 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
269 if (hw->mac.type >= ixgbe_mac_82599EB) {
270 (void) IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
271 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
272 } else {
273 (void) IXGBE_READ_REG(hw, IXGBE_LXONRXC);
274 (void) IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
275 }
276
277 for (i = 0; i < 8; i++) {
278 (void) IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
279 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
280 if (hw->mac.type >= ixgbe_mac_82599EB) {
281 (void) IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
282 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
283 } else {
284 (void) IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
285 (void) IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
286 }
287 }
288 if (hw->mac.type >= ixgbe_mac_82599EB)
289 for (i = 0; i < 8; i++)
290 (void) IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
291 (void) IXGBE_READ_REG(hw, IXGBE_PRC64);
292 (void) IXGBE_READ_REG(hw, IXGBE_PRC127);
293 (void) IXGBE_READ_REG(hw, IXGBE_PRC255);
294 (void) IXGBE_READ_REG(hw, IXGBE_PRC511);
295 (void) IXGBE_READ_REG(hw, IXGBE_PRC1023);
296 (void) IXGBE_READ_REG(hw, IXGBE_PRC1522);
297 (void) IXGBE_READ_REG(hw, IXGBE_GPRC);
298 (void) IXGBE_READ_REG(hw, IXGBE_BPRC);
299 (void) IXGBE_READ_REG(hw, IXGBE_MPRC);
300 (void) IXGBE_READ_REG(hw, IXGBE_GPTC);
301 (void) IXGBE_READ_REG(hw, IXGBE_GORCL);
302 (void) IXGBE_READ_REG(hw, IXGBE_GORCH);
303 (void) IXGBE_READ_REG(hw, IXGBE_GOTCL);
304 (void) IXGBE_READ_REG(hw, IXGBE_GOTCH);
305 for (i = 0; i < 8; i++)
306 (void) IXGBE_READ_REG(hw, IXGBE_RNBC(i));
307 (void) IXGBE_READ_REG(hw, IXGBE_RUC);
308 (void) IXGBE_READ_REG(hw, IXGBE_RFC);
309 (void) IXGBE_READ_REG(hw, IXGBE_ROC);
310 (void) IXGBE_READ_REG(hw, IXGBE_RJC);
311 (void) IXGBE_READ_REG(hw, IXGBE_MNGPRC);
312 (void) IXGBE_READ_REG(hw, IXGBE_MNGPDC);
313 (void) IXGBE_READ_REG(hw, IXGBE_MNGPTC);
314 (void) IXGBE_READ_REG(hw, IXGBE_TORL);
315 (void) IXGBE_READ_REG(hw, IXGBE_TORH);
316 (void) IXGBE_READ_REG(hw, IXGBE_TPR);
317 (void) IXGBE_READ_REG(hw, IXGBE_TPT);
318 (void) IXGBE_READ_REG(hw, IXGBE_PTC64);
319 (void) IXGBE_READ_REG(hw, IXGBE_PTC127);
320 (void) IXGBE_READ_REG(hw, IXGBE_PTC255);
321 (void) IXGBE_READ_REG(hw, IXGBE_PTC511);
322 (void) IXGBE_READ_REG(hw, IXGBE_PTC1023);
323 (void) IXGBE_READ_REG(hw, IXGBE_PTC1522);
324 (void) IXGBE_READ_REG(hw, IXGBE_MPTC);
325 (void) IXGBE_READ_REG(hw, IXGBE_BPTC);
326 for (i = 0; i < 16; i++) {
327 (void) IXGBE_READ_REG(hw, IXGBE_QPRC(i));
328 (void) IXGBE_READ_REG(hw, IXGBE_QPTC(i));
329 if (hw->mac.type >= ixgbe_mac_82599EB) {
330 (void) IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
331 (void) IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
332 (void) IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
333 (void) IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
334 (void) IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
335 } else {
336 (void) IXGBE_READ_REG(hw, IXGBE_QBRC(i));
337 (void) IXGBE_READ_REG(hw, IXGBE_QBTC(i));
338 }
339 }
340
341 return IXGBE_SUCCESS;
342 }
343
344 /**
345 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
346 * @hw: pointer to hardware structure
347 * @pba_num: stores the part number string from the EEPROM
348 * @pba_num_size: part number string buffer length
349 *
350 * Reads the part number string from the EEPROM.
351 **/
352 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
353 u32 pba_num_size)
354 {
355 s32 ret_val;
356 u16 data;
357 u16 pba_ptr;
358 u16 offset;
359 u16 length;
360
436
437 /* trim pba length from start of string */
438 pba_ptr++;
439 length--;
440
441 for (offset = 0; offset < length; offset++) {
442 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
443 if (ret_val) {
444 DEBUGOUT("NVM Read Error\n");
445 return ret_val;
446 }
447 pba_num[offset * 2] = (u8)(data >> 8);
448 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
449 }
450 pba_num[offset * 2] = '\0';
451
452 return IXGBE_SUCCESS;
453 }
454
455 /**
456 * ixgbe_read_pba_length_generic - Reads part number length from EEPROM
457 * @hw: pointer to hardware structure
458 * @pba_num_size: part number string buffer length
459 *
460 * Reads the part number length from the EEPROM.
461 * Returns expected buffer size in pba_num_size
462 **/
463 s32 ixgbe_read_pba_length_generic(struct ixgbe_hw *hw, u32 *pba_num_size)
464 {
465 s32 ret_val;
466 u16 data;
467 u16 pba_ptr;
468 u16 length;
469
470 DEBUGFUNC("ixgbe_read_pba_length_generic");
471
472 if (pba_num_size == NULL) {
473 DEBUGOUT("PBA buffer size was null\n");
474 return IXGBE_ERR_INVALID_ARGUMENT;
475 }
476
477 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
478 if (ret_val) {
479 DEBUGOUT("NVM Read Error\n");
480 return ret_val;
481 }
482
483 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
484 if (ret_val) {
485 DEBUGOUT("NVM Read Error\n");
486 return ret_val;
487 }
488
489 /* if data is not ptr guard the PBA must be in legacy format */
490 if (data != IXGBE_PBANUM_PTR_GUARD) {
491 *pba_num_size = 11;
492 return IXGBE_SUCCESS;
493 }
494
495 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
496 if (ret_val) {
497 DEBUGOUT("NVM Read Error\n");
498 return ret_val;
499 }
500
501 if (length == 0xFFFF || length == 0) {
502 DEBUGOUT("NVM PBA number section invalid length\n");
503 return IXGBE_ERR_PBA_SECTION;
504 }
505
506 /*
507 * Convert from length in u16 values to u8 chars, add 1 for NULL,
508 * and subtract 2 because length field is included in length.
509 */
510 *pba_num_size = ((u32)length * 2) - 1;
511
512 return IXGBE_SUCCESS;
513 }
514
515 /**
516 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
517 * @hw: pointer to hardware structure
518 * @pba_num: stores the part number from the EEPROM
519 *
520 * Reads the part number from the EEPROM.
521 **/
522 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
523 {
524 s32 ret_val;
525 u16 data;
526
527 DEBUGFUNC("ixgbe_read_pba_num_generic");
528
529 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
530 if (ret_val) {
531 DEBUGOUT("NVM Read Error\n");
532 return ret_val;
533 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
534 DEBUGOUT("NVM Not supported\n");
535 return IXGBE_NOT_IMPLEMENTED;
601 hw->bus.width = ixgbe_bus_width_pcie_x2;
602 break;
603 case IXGBE_PCI_LINK_WIDTH_4:
604 hw->bus.width = ixgbe_bus_width_pcie_x4;
605 break;
606 case IXGBE_PCI_LINK_WIDTH_8:
607 hw->bus.width = ixgbe_bus_width_pcie_x8;
608 break;
609 default:
610 hw->bus.width = ixgbe_bus_width_unknown;
611 break;
612 }
613
614 switch (link_status & IXGBE_PCI_LINK_SPEED) {
615 case IXGBE_PCI_LINK_SPEED_2500:
616 hw->bus.speed = ixgbe_bus_speed_2500;
617 break;
618 case IXGBE_PCI_LINK_SPEED_5000:
619 hw->bus.speed = ixgbe_bus_speed_5000;
620 break;
621 default:
622 hw->bus.speed = ixgbe_bus_speed_unknown;
623 break;
624 }
625
626 mac->ops.set_lan_id(hw);
627
628 return IXGBE_SUCCESS;
629 }
630
631 /**
632 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
633 * @hw: pointer to the HW structure
634 *
635 * Determines the LAN function id by reading memory-mapped registers
636 * and swaps the port value if requested.
637 **/
638 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
639 {
640 struct ixgbe_bus_info *bus = &hw->bus;
646 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
647 bus->lan_id = bus->func;
648
649 /* check for a port swap */
650 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
651 if (reg & IXGBE_FACTPS_LFS)
652 bus->func ^= 0x1;
653 }
654
655 /**
656 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
657 * @hw: pointer to hardware structure
658 *
659 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
660 * disables transmit and receive units. The adapter_stopped flag is used by
661 * the shared code and drivers to determine if the adapter is in a stopped
662 * state and should not touch the hardware.
663 **/
664 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
665 {
666 u32 number_of_queues;
667 u32 reg_val;
668 u16 i;
669
670 DEBUGFUNC("ixgbe_stop_adapter_generic");
671
672 /*
673 * Set the adapter_stopped flag so other driver functions stop touching
674 * the hardware
675 */
676 hw->adapter_stopped = TRUE;
677
678 /* Disable the receive unit */
679 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
680 reg_val &= ~(IXGBE_RXCTRL_RXEN);
681 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
682 IXGBE_WRITE_FLUSH(hw);
683 msec_delay(2);
684
685 /* Clear interrupt mask to stop from interrupts being generated */
686 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
687
688 /* Clear any pending interrupts */
689 (void) IXGBE_READ_REG(hw, IXGBE_EICR);
690
691 /* Disable the transmit unit. Each queue must be disabled. */
692 number_of_queues = hw->mac.max_tx_queues;
693 for (i = 0; i < number_of_queues; i++) {
694 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
695 if (reg_val & IXGBE_TXDCTL_ENABLE) {
696 reg_val &= ~IXGBE_TXDCTL_ENABLE;
697 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
698 }
699 }
700
701 /*
702 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
703 * access and verify no pending requests
704 */
705 (void) ixgbe_disable_pcie_master(hw);
706
707 return IXGBE_SUCCESS;
708 }
709
710 /**
711 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
712 * @hw: pointer to hardware structure
713 * @index: led number to turn on
714 **/
715 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
716 {
717 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
718
719 DEBUGFUNC("ixgbe_led_on_generic");
720
721 /* To turn on the LED, set mode to ON. */
722 led_reg &= ~IXGBE_LED_MODE_MASK(index);
723 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
724 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
725 IXGBE_WRITE_FLUSH(hw);
726
727 return IXGBE_SUCCESS;
750 /**
751 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
752 * @hw: pointer to hardware structure
753 *
754 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
755 * ixgbe_hw struct in order to set up EEPROM access.
756 **/
757 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
758 {
759 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
760 u32 eec;
761 u16 eeprom_size;
762
763 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
764
765 if (eeprom->type == ixgbe_eeprom_uninitialized) {
766 eeprom->type = ixgbe_eeprom_none;
767 /* Set default semaphore delay to 10ms which is a well
768 * tested value */
769 eeprom->semaphore_delay = 10;
770
771 /*
772 * Check for EEPROM present first.
773 * If not present leave as none
774 */
775 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
776 if (eec & IXGBE_EEC_PRES) {
777 eeprom->type = ixgbe_eeprom_spi;
778
779 /*
780 * SPI EEPROM is assumed here. This code would need to
781 * change if a future EEPROM is not SPI.
782 */
783 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
784 IXGBE_EEC_SIZE_SHIFT);
785 eeprom->word_size = 1 << (eeprom_size +
786 IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT);
787 }
788
789 if (eec & IXGBE_EEC_ADDR_SIZE)
790 eeprom->address_bits = 16;
791 else
792 eeprom->address_bits = 8;
793 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
794 "%d\n", eeprom->type, eeprom->word_size,
795 eeprom->address_bits);
796 }
797
798 return IXGBE_SUCCESS;
799 }
800
801 /**
802 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
803 * @hw: pointer to hardware structure
804 * @offset: offset within the EEPROM to be written to
805 * @data: 16 bit word to be written to the EEPROM
806 *
807 * If ixgbe_eeprom_update_checksum is not called after this function, the
808 * EEPROM will most likely contain an invalid checksum.
809 **/
810 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
811 {
812 s32 status;
813 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
814
815 DEBUGFUNC("ixgbe_write_eeprom_generic");
816
817 hw->eeprom.ops.init_params(hw);
818
819 if (offset >= hw->eeprom.word_size) {
820 status = IXGBE_ERR_EEPROM;
821 goto out;
822 }
823
824 /* Prepare the EEPROM for writing */
825 status = ixgbe_acquire_eeprom(hw);
826
827 if (status == IXGBE_SUCCESS) {
828 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
829 ixgbe_release_eeprom(hw);
830 status = IXGBE_ERR_EEPROM;
831 }
832 }
833
834 if (status == IXGBE_SUCCESS) {
835 ixgbe_standby_eeprom(hw);
836
837 /* Send the WRITE ENABLE command (8 bit opcode ) */
838 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
839 IXGBE_EEPROM_OPCODE_BITS);
840
841 ixgbe_standby_eeprom(hw);
842
843 /*
844 * Some SPI eeproms use the 8th address bit embedded in the
845 * opcode
846 */
847 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
848 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
849
850 /* Send the Write command (8-bit opcode + addr) */
851 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
852 IXGBE_EEPROM_OPCODE_BITS);
853 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
854 hw->eeprom.address_bits);
855
856 /* Send the data */
857 data = (data >> 8) | (data << 8);
858 ixgbe_shift_out_eeprom_bits(hw, data, 16);
859 ixgbe_standby_eeprom(hw);
860
861 /* Done with writing - release the EEPROM */
862 ixgbe_release_eeprom(hw);
863 }
864
865 out:
866 return status;
867 }
868
869 /**
870 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
871 * @hw: pointer to hardware structure
872 * @offset: offset within the EEPROM to be read
873 * @data: read 16 bit value from EEPROM
874 *
875 * Reads 16 bit value from EEPROM through bit-bang method
876 **/
877 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
878 u16 *data)
879 {
880 s32 status;
881 u16 word_in;
882 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
883
884 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
885
886 hw->eeprom.ops.init_params(hw);
887
888 if (offset >= hw->eeprom.word_size) {
889 status = IXGBE_ERR_EEPROM;
890 goto out;
891 }
892
893 /* Prepare the EEPROM for reading */
894 status = ixgbe_acquire_eeprom(hw);
895
896 if (status == IXGBE_SUCCESS) {
897 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
898 ixgbe_release_eeprom(hw);
899 status = IXGBE_ERR_EEPROM;
900 }
901 }
902
903 if (status == IXGBE_SUCCESS) {
904 ixgbe_standby_eeprom(hw);
905
906 /*
907 * Some SPI eeproms use the 8th address bit embedded in the
908 * opcode
909 */
910 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
911 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
912
913 /* Send the READ command (opcode + addr) */
914 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
915 IXGBE_EEPROM_OPCODE_BITS);
916 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
917 hw->eeprom.address_bits);
918
919 /* Read the data. */
920 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
921 *data = (word_in >> 8) | (word_in << 8);
922
923 /* End this read operation */
924 ixgbe_release_eeprom(hw);
925 }
926
927 out:
928 return status;
929 }
930
931 /**
932 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
933 * @hw: pointer to hardware structure
934 * @offset: offset of word in the EEPROM to read
935 * @data: word read from the EEPROM
936 *
937 * Reads a 16 bit word from the EEPROM using the EERD register.
938 **/
939 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
940 {
941 u32 eerd;
942 s32 status;
943
944 DEBUGFUNC("ixgbe_read_eerd_generic");
945
946 hw->eeprom.ops.init_params(hw);
947
948 if (offset >= hw->eeprom.word_size) {
949 status = IXGBE_ERR_EEPROM;
950 goto out;
951 }
952
953 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) +
954 IXGBE_EEPROM_RW_REG_START;
955
956 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
957 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
958
959 if (status == IXGBE_SUCCESS)
960 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
961 IXGBE_EEPROM_RW_REG_DATA);
962 else
963 DEBUGOUT("Eeprom read timed out\n");
964
965 out:
966 return status;
967 }
968
969 /**
970 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
971 * @hw: pointer to hardware structure
972 * @offset: offset of word in the EEPROM to write
973 * @data: word write to the EEPROM
974 *
975 * Write a 16 bit word to the EEPROM using the EEWR register.
976 **/
977 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
978 {
979 u32 eewr;
980 s32 status;
981
982 DEBUGFUNC("ixgbe_write_eewr_generic");
983
984 hw->eeprom.ops.init_params(hw);
985
986 if (offset >= hw->eeprom.word_size) {
987 status = IXGBE_ERR_EEPROM;
988 goto out;
989 }
990
991 eewr = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) |
992 (data << IXGBE_EEPROM_RW_REG_DATA) | IXGBE_EEPROM_RW_REG_START;
993
994 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
995 if (status != IXGBE_SUCCESS) {
996 DEBUGOUT("Eeprom write EEWR timed out\n");
997 goto out;
998 }
999
1000 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1001
1002 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1003 if (status != IXGBE_SUCCESS) {
1004 DEBUGOUT("Eeprom write EEWR timed out\n");
1005 goto out;
1006 }
1007
1008 out:
1009 return status;
1010 }
1011
1012 /**
1013 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1014 * @hw: pointer to hardware structure
1015 * @ee_reg: EEPROM flag for polling
1016 *
1017 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1018 * read or write is done respectively.
1019 **/
1020 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1021 {
1022 u32 i;
1023 u32 reg;
1024 s32 status = IXGBE_ERR_EEPROM;
1025
1026 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1027
1028 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1029 if (ee_reg == IXGBE_NVM_POLL_READ)
1030 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1031 else
1032 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1038 usec_delay(5);
1039 }
1040 return status;
1041 }
1042
1043 /**
1044 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1045 * @hw: pointer to hardware structure
1046 *
1047 * Prepares EEPROM for access using bit-bang method. This function should
1048 * be called before issuing a command to the EEPROM.
1049 **/
1050 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1051 {
1052 s32 status = IXGBE_SUCCESS;
1053 u32 eec;
1054 u32 i;
1055
1056 DEBUGFUNC("ixgbe_acquire_eeprom");
1057
1058 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS)
1059 status = IXGBE_ERR_SWFW_SYNC;
1060
1061 if (status == IXGBE_SUCCESS) {
1062 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1063
1064 /* Request EEPROM Access */
1065 eec |= IXGBE_EEC_REQ;
1066 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1067
1068 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1069 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1070 if (eec & IXGBE_EEC_GNT)
1071 break;
1072 usec_delay(5);
1073 }
1074
1075 /* Release if grant not acquired */
1076 if (!(eec & IXGBE_EEC_GNT)) {
1077 eec &= ~IXGBE_EEC_REQ;
1078 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1079 DEBUGOUT("Could not acquire EEPROM grant\n");
1080
1081 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1082 status = IXGBE_ERR_EEPROM;
1083 }
1084
1085 /* Setup EEPROM for Read/Write */
1086 if (status == IXGBE_SUCCESS) {
1087 /* Clear CS and SK */
1088 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1089 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1090 IXGBE_WRITE_FLUSH(hw);
1091 usec_delay(1);
1092 }
1093 }
1094 return status;
1095 }
1096
1097 /**
1098 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1099 * @hw: pointer to hardware structure
1100 *
1101 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1107 u32 i;
1108 u32 swsm;
1109
1110 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1111
1112
1113 /* Get SMBI software semaphore between device drivers first */
1114 for (i = 0; i < timeout; i++) {
1115 /*
1116 * If the SMBI bit is 0 when we read it, then the bit will be
1117 * set and we have the semaphore
1118 */
1119 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1120 if (!(swsm & IXGBE_SWSM_SMBI)) {
1121 status = IXGBE_SUCCESS;
1122 break;
1123 }
1124 usec_delay(50);
1125 }
1126
1127 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1128 if (status == IXGBE_SUCCESS) {
1129 for (i = 0; i < timeout; i++) {
1130 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1131
1132 /* Set the SW EEPROM semaphore bit to request access */
1133 swsm |= IXGBE_SWSM_SWESMBI;
1134 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1135
1136 /*
1137 * If we set the bit successfully then we got the
1138 * semaphore.
1139 */
1140 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1141 if (swsm & IXGBE_SWSM_SWESMBI)
1142 break;
1143
1144 usec_delay(50);
1145 }
1146
1387 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1388 {
1389 u32 eec;
1390
1391 DEBUGFUNC("ixgbe_release_eeprom");
1392
1393 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1394
1395 eec |= IXGBE_EEC_CS; /* Pull CS high */
1396 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1397
1398 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1399 IXGBE_WRITE_FLUSH(hw);
1400
1401 usec_delay(1);
1402
1403 /* Stop requesting EEPROM access */
1404 eec &= ~IXGBE_EEC_REQ;
1405 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1406
1407 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1408
1409 /* Delay before attempt to obtain semaphore again to allow FW access */
1410 msec_delay(hw->eeprom.semaphore_delay);
1411 }
1412
1413 /**
1414 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1415 * @hw: pointer to hardware structure
1416 **/
1417 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1418 {
1419 u16 i;
1420 u16 j;
1421 u16 checksum = 0;
1422 u16 length = 0;
1423 u16 pointer = 0;
1424 u16 word = 0;
1425
1426 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
1427
1696 }
1697 hw->addr_ctrl.overflow_promisc = 0;
1698
1699 hw->addr_ctrl.rar_used_count = 1;
1700
1701 /* Zero out the other receive addresses. */
1702 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
1703 for (i = 1; i < rar_entries; i++) {
1704 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1705 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1706 }
1707
1708 /* Clear the MTA */
1709 hw->addr_ctrl.mta_in_use = 0;
1710 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1711
1712 DEBUGOUT(" Clearing MTA\n");
1713 for (i = 0; i < hw->mac.mcft_size; i++)
1714 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1715
1716 (void) ixgbe_init_uta_tables(hw);
1717
1718 return IXGBE_SUCCESS;
1719 }
1720
1721 /**
1722 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1723 * @hw: pointer to hardware structure
1724 * @addr: new address
1725 *
1726 * Adds it to unused receive address register or goes into promiscuous mode.
1727 **/
1728 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1729 {
1730 u32 rar_entries = hw->mac.num_rar_entries;
1731 u32 rar;
1732
1733 DEBUGFUNC("ixgbe_add_uc_addr");
1734
1735 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1736 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1886 /*
1887 * The MTA is a register array of 128 32-bit registers. It is treated
1888 * like an array of 4096 bits. We want to set bit
1889 * BitArray[vector_value]. So we figure out what register the bit is
1890 * in, read it, OR in the new bit, then write back the new value. The
1891 * register is determined by the upper 7 bits of the vector value and
1892 * the bit within that register are determined by the lower 5 bits of
1893 * the value.
1894 */
1895 vector_reg = (vector >> 5) & 0x7F;
1896 vector_bit = vector & 0x1F;
1897 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
1898 }
1899
1900 /**
1901 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1902 * @hw: pointer to hardware structure
1903 * @mc_addr_list: the list of new multicast addresses
1904 * @mc_addr_count: number of addresses
1905 * @next: iterator function to walk the multicast address list
1906 *
1907 * The given list replaces any existing list. Clears the MC addrs from receive
1908 * address registers and the multicast table. Uses unused receive address
1909 * registers for the first multicast addresses, and hashes the rest into the
1910 * multicast table.
1911 **/
1912 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
1913 u32 mc_addr_count, ixgbe_mc_addr_itr next)
1914 {
1915 u32 i;
1916 u32 vmdq;
1917
1918 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
1919
1920 /*
1921 * Set the new number of MC addresses that we are being requested to
1922 * use.
1923 */
1924 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
1925 hw->addr_ctrl.mta_in_use = 0;
1926
1927 /* Clear mta_shadow */
1928 DEBUGOUT(" Clearing MTA\n");
1929 (void) memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
1930
1931 /* Update mta_shadow */
1932 for (i = 0; i < mc_addr_count; i++) {
1933 DEBUGOUT(" Adding the multicast addresses:\n");
1934 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
1935 }
1936
1937 /* Enable mta */
1938 for (i = 0; i < hw->mac.mcft_size; i++)
1939 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
1940 hw->mac.mta_shadow[i]);
1941
1942 if (hw->addr_ctrl.mta_in_use > 0)
1943 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1944 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1945
1946 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
1947 return IXGBE_SUCCESS;
1948 }
1949
1970 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1971 * @hw: pointer to hardware structure
1972 *
1973 * Disables multicast address in RAR and the use of the multicast hash table.
1974 **/
1975 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1976 {
1977 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1978
1979 DEBUGFUNC("ixgbe_disable_mc_generic");
1980
1981 if (a->mta_in_use > 0)
1982 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1983
1984 return IXGBE_SUCCESS;
1985 }
1986
1987 /**
1988 * ixgbe_fc_enable_generic - Enable flow control
1989 * @hw: pointer to hardware structure
1990 * @packetbuf_num: packet buffer number (0-7)
1991 *
1992 * Enable flow control according to the current settings.
1993 **/
1994 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1995 {
1996 s32 ret_val = IXGBE_SUCCESS;
1997 u32 mflcn_reg, fccfg_reg;
1998 u32 reg;
1999 u32 rx_pba_size;
2000 u32 fcrtl, fcrth;
2001
2002 DEBUGFUNC("ixgbe_fc_enable_generic");
2003
2004 /* Negotiate the fc mode to use */
2005 ret_val = ixgbe_fc_autoneg(hw);
2006 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
2007 goto out;
2008
2009 /* Disable any previous flow control settings */
2010 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2011 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
2012
2013 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2014 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2015
2016 /*
2017 * The possible values of fc.current_mode are:
2018 * 0: Flow control is completely disabled
2019 * 1: Rx flow control is enabled (we can receive pause frames,
2020 * but not send pause frames).
2021 * 2: Tx flow control is enabled (we can send pause frames but
2022 * we do not support receiving pause frames).
2023 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2024 * other: Invalid.
2025 */
2026 switch (hw->fc.current_mode) {
2027 case ixgbe_fc_none:
2028 /*
2029 * Flow control is disabled by software override or autoneg.
2030 * The code below will actually disable it in the HW.
2031 */
2047 * disabled by software override.
2048 */
2049 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2050 break;
2051 case ixgbe_fc_full:
2052 /* Flow control (both Rx and Tx) is enabled by SW override. */
2053 mflcn_reg |= IXGBE_MFLCN_RFCE;
2054 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2055 break;
2056 default:
2057 DEBUGOUT("Flow control param set incorrectly\n");
2058 ret_val = IXGBE_ERR_CONFIG;
2059 goto out;
2060 }
2061
2062 /* Set 802.3x based flow control settings. */
2063 mflcn_reg |= IXGBE_MFLCN_DPF;
2064 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2065 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2066
2067 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
2068 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
2069
2070 fcrth = (rx_pba_size - hw->fc.high_water) << 10;
2071 fcrtl = (rx_pba_size - hw->fc.low_water) << 10;
2072
2073 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2074 fcrth |= IXGBE_FCRTH_FCEN;
2075 if (hw->fc.send_xon)
2076 fcrtl |= IXGBE_FCRTL_XONE;
2077 }
2078
2079 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
2080 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
2081
2082 /* Configure pause time (2 TCs per register) */
2083 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
2084 if ((packetbuf_num & 1) == 0)
2085 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
2086 else
2087 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
2088 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
2089
2090 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
2091
2092 out:
2093 return ret_val;
2094 }
2095
2096 /**
2097 * ixgbe_fc_autoneg - Configure flow control
2098 * @hw: pointer to hardware structure
2099 *
2100 * Compares our advertised flow control capabilities to those advertised by
2101 * our link partner, and determines the proper flow control mode to use.
2102 **/
2103 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2104 {
2105 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2106 ixgbe_link_speed speed;
2107 bool link_up;
2108
2109 DEBUGFUNC("ixgbe_fc_autoneg");
2110
2111 if (hw->fc.disable_fc_autoneg)
2112 goto out;
2113
2114 /*
2115 * AN should have completed when the cable was plugged in.
2116 * Look for reasons to bail out. Bail out if:
2117 * - FC autoneg is disabled, or if
2118 * - link is not up.
2119 *
2120 * Since we're being called from an LSC, link is already known to be up.
2121 * So use link_up_wait_to_complete=FALSE.
2122 */
2123 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2124 if (!link_up) {
2125 ret_val = IXGBE_ERR_FLOW_CONTROL;
2126 goto out;
2127 }
2128
2129 switch (hw->phy.media_type) {
2130 /* Autoneg flow control on fiber adapters */
2131 case ixgbe_media_type_fiber:
2132 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2133 ret_val = ixgbe_fc_autoneg_fiber(hw);
2134 break;
2135
2136 /* Autoneg flow control on backplane adapters */
2137 case ixgbe_media_type_backplane:
2138 ret_val = ixgbe_fc_autoneg_backplane(hw);
2139 break;
2140
2141 /* Autoneg flow control on copper adapters */
2142 case ixgbe_media_type_copper:
2143 if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
2144 ret_val = ixgbe_fc_autoneg_copper(hw);
2145 break;
2146
2147 default:
2148 break;
2149 }
2150
2151 out:
2152 if (ret_val == IXGBE_SUCCESS) {
2153 hw->fc.fc_was_autonegged = TRUE;
2154 } else {
2155 hw->fc.fc_was_autonegged = FALSE;
2156 hw->fc.current_mode = hw->fc.requested_mode;
2157 }
2158 return ret_val;
2159 }
2160
2161 /**
2162 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2163 * @hw: pointer to hardware structure
2164 * @speed:
2165 * @link_up
2166 *
2167 * Enable flow control according on 1 gig fiber.
2168 **/
2169 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2170 {
2171 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2172 s32 ret_val;
2173
2174 /*
2175 * On multispeed fiber at 1g, bail out if
2176 * - link is up but AN did not complete, or if
2177 * - link is up and AN completed but timed out
2178 */
2179
2180 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2181 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2182 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2183 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2184 goto out;
2185 }
2186
2187 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2188 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2189
2190 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2191 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2192 IXGBE_PCS1GANA_ASM_PAUSE,
2193 IXGBE_PCS1GANA_SYM_PAUSE,
2194 IXGBE_PCS1GANA_ASM_PAUSE);
2195
2196 out:
2197 return ret_val;
2198 }
2199
2200 /**
2201 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2202 * @hw: pointer to hardware structure
2203 *
2204 * Enable flow control according to IEEE clause 37.
2205 **/
2206 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2207 {
2208 u32 links2, anlp1_reg, autoc_reg, links;
2209 s32 ret_val;
2210
2211 /*
2212 * On backplane, bail out if
2213 * - backplane autoneg was not completed, or if
2214 * - we are 82599 and link partner is not AN enabled
2215 */
2216 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2217 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2218 hw->fc.fc_was_autonegged = FALSE;
2219 hw->fc.current_mode = hw->fc.requested_mode;
2220 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2221 goto out;
2222 }
2223
2224 if (hw->mac.type == ixgbe_mac_82599EB) {
2225 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2226 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2227 hw->fc.fc_was_autonegged = FALSE;
2228 hw->fc.current_mode = hw->fc.requested_mode;
2229 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2230 goto out;
2231 }
2232 }
2233 /*
2234 * Read the 10g AN autoc and LP ability registers and resolve
2235 * local flow control settings accordingly
2236 */
2237 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2238 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2239
2240 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2241 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2242 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2243
2244 out:
2245 return ret_val;
2246 }
2247
2248 /**
2249 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2250 * @hw: pointer to hardware structure
2251 *
2252 * Enable flow control according to IEEE clause 37.
2253 **/
2254 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2255 {
2256 u16 technology_ability_reg = 0;
2257 u16 lp_technology_ability_reg = 0;
2258
2259 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2260 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2261 &technology_ability_reg);
2262 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2263 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2264 &lp_technology_ability_reg);
2265
2266 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2267 (u32)lp_technology_ability_reg,
2268 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2269 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2270 }
2271
2272 /**
2273 * ixgbe_negotiate_fc - Negotiate flow control
2274 * @hw: pointer to hardware structure
2275 * @adv_reg: flow control advertised settings
2276 * @lp_reg: link partner's flow control settings
2277 * @adv_sym: symmetric pause bit in advertisement
2278 * @adv_asm: asymmetric pause bit in advertisement
2279 * @lp_sym: symmetric pause bit in link partner advertisement
2280 * @lp_asm: asymmetric pause bit in link partner advertisement
2281 *
2282 * Find the intersection between advertised settings and link partner's
2283 * advertised settings
2284 **/
2285 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2286 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2287 {
2288 if ((!(adv_reg)) || (!(lp_reg)))
2289 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2290
2291 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2292 /*
2293 * Now we need to check if the user selected Rx ONLY
2294 * of pause frames. In this case, we had to advertise
2295 * FULL flow control because we could not advertise RX
2296 * ONLY. Hence, we must now check to see if we need to
2297 * turn OFF the TRANSMISSION of PAUSE frames.
2298 */
2299 if (hw->fc.requested_mode == ixgbe_fc_full) {
2300 hw->fc.current_mode = ixgbe_fc_full;
2301 DEBUGOUT("Flow Control = FULL.\n");
2302 } else {
2303 hw->fc.current_mode = ixgbe_fc_rx_pause;
2304 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2305 }
2306 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2307 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2308 hw->fc.current_mode = ixgbe_fc_tx_pause;
2309 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2310 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2311 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2312 hw->fc.current_mode = ixgbe_fc_rx_pause;
2313 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2314 } else {
2315 hw->fc.current_mode = ixgbe_fc_none;
2316 DEBUGOUT("Flow Control = NONE.\n");
2317 }
2318 return IXGBE_SUCCESS;
2319 }
2320
2321 /**
2322 * ixgbe_setup_fc - Set up flow control
2323 * @hw: pointer to hardware structure
2324 *
2325 * Called at init time to set up flow control.
2326 **/
2327 s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
2328 {
2329 s32 ret_val = IXGBE_SUCCESS;
2330 u32 reg = 0, reg_bp = 0;
2331 u16 reg_cu = 0;
2332
2333 DEBUGFUNC("ixgbe_setup_fc");
2334
2335 /* Validate the packetbuf configuration */
2336 if (packetbuf_num < 0 || packetbuf_num > 7) {
2337 DEBUGOUT1("Invalid packet buffer number [%d], expected range is"
2338 " 0-7\n", packetbuf_num);
2339 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2340 goto out;
2341 }
2342
2343 /*
2344 * Validate the water mark configuration. Zero water marks are invalid
2345 * because it causes the controller to just blast out fc packets.
2346 */
2347 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
2348 DEBUGOUT("Invalid water mark configuration\n");
2349 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2350 goto out;
2351 }
2352
2353 /*
2354 * Validate the requested mode. Strict IEEE mode does not allow
2355 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
2356 */
2357 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2358 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2359 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2360 goto out;
2361 }
2362
2363 /*
2364 * 10gig parts do not have a word in the EEPROM to determine the
2365 * default flow control setting, so we explicitly set it to full.
2366 */
2367 if (hw->fc.requested_mode == ixgbe_fc_default)
2368 hw->fc.requested_mode = ixgbe_fc_full;
2369
2370 /*
2371 * Set up the 1G and 10G flow control advertisement registers so the
2372 * HW will be able to do fc autoneg once the cable is plugged in. If
2373 * we link at 10G, the 1G advertisement is harmless and vice versa.
2374 */
2375
2376 switch (hw->phy.media_type) {
2377 case ixgbe_media_type_fiber:
2378 case ixgbe_media_type_backplane:
2379 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2380 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2381 break;
2382
2383 case ixgbe_media_type_copper:
2384 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2385 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
2386 break;
2387
2388 default:
2389 ;
2390 }
2391
2392 /*
2393 * The possible values of fc.requested_mode are:
2394 * 0: Flow control is completely disabled
2395 * 1: Rx flow control is enabled (we can receive pause frames,
2396 * but not send pause frames).
2397 * 2: Tx flow control is enabled (we can send pause frames but
2398 * we do not support receiving pause frames).
2399 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2400 * other: Invalid.
2401 */
2402 switch (hw->fc.requested_mode) {
2403 case ixgbe_fc_none:
2404 /* Flow control completely disabled by software override. */
2405 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2406 if (hw->phy.media_type == ixgbe_media_type_backplane)
2407 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
2408 IXGBE_AUTOC_ASM_PAUSE);
2409 else if (hw->phy.media_type == ixgbe_media_type_copper)
2410 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
2411 break;
2412 case ixgbe_fc_rx_pause:
2413 /*
2414 * Rx Flow control is enabled and Tx Flow control is
2415 * disabled by software override. Since there really
2416 * isn't a way to advertise that we are capable of RX
2417 * Pause ONLY, we will advertise that we support both
2418 * symmetric and asymmetric Rx PAUSE. Later, we will
2419 * disable the adapter's ability to send PAUSE frames.
2420 */
2421 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2422 if (hw->phy.media_type == ixgbe_media_type_backplane)
2423 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2424 IXGBE_AUTOC_ASM_PAUSE);
2425 else if (hw->phy.media_type == ixgbe_media_type_copper)
2426 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
2427 break;
2428 case ixgbe_fc_tx_pause:
2429 /*
2430 * Tx Flow control is enabled, and Rx Flow control is
2431 * disabled by software override.
2432 */
2433 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
2434 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
2435 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2436 reg_bp |= (IXGBE_AUTOC_ASM_PAUSE);
2437 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE);
2438 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
2439 reg_cu |= (IXGBE_TAF_ASM_PAUSE);
2440 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE);
2441 }
2442 break;
2443 case ixgbe_fc_full:
2444 /* Flow control (both Rx and Tx) is enabled by SW override. */
2445 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
2446 if (hw->phy.media_type == ixgbe_media_type_backplane)
2447 reg_bp |= (IXGBE_AUTOC_SYM_PAUSE |
2448 IXGBE_AUTOC_ASM_PAUSE);
2449 else if (hw->phy.media_type == ixgbe_media_type_copper)
2450 reg_cu |= (IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
2451 break;
2452 default:
2453 DEBUGOUT("Flow control param set incorrectly\n");
2454 ret_val = IXGBE_ERR_CONFIG;
2455 goto out;
2456 }
2457
2458 /*
2459 * Enable auto-negotiation between the MAC & PHY;
2460 * the MAC will advertise clause 37 flow control.
2461 */
2462 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
2463 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
2464
2465 /* Disable AN timeout */
2466 if (hw->fc.strict_ieee)
2467 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
2468
2469 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
2470 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
2471
2472 /*
2473 * AUTOC restart handles negotiation of 1G and 10G on backplane
2474 * and copper. There is no need to set the PCS1GCTL register.
2475 *
2476 */
2477 if (hw->phy.media_type == ixgbe_media_type_backplane) {
2478 reg_bp |= IXGBE_AUTOC_AN_RESTART;
2479 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
2480 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
2481 (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
2482 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2483 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
2484 }
2485
2486 DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
2487 out:
2488 return ret_val;
2489 }
2490
2491 /**
2492 * ixgbe_disable_pcie_master - Disable PCI-express master access
2493 * @hw: pointer to hardware structure
2494 *
2495 * Disables PCI-Express master access and verifies there are no pending
2496 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2497 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
2498 * is returned signifying master requests disabled.
2499 **/
2500 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2501 {
2502 u32 i;
2503 u32 reg_val;
2504 u32 number_of_queues;
2505 s32 status = IXGBE_SUCCESS;
2506
2507 DEBUGFUNC("ixgbe_disable_pcie_master");
2508
2509 /* Just jump out if bus mastering is already disabled */
2510 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2511 goto out;
2512
2513 /* Disable the receive unit by stopping each queue */
2514 number_of_queues = hw->mac.max_rx_queues;
2515 for (i = 0; i < number_of_queues; i++) {
2516 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
2517 if (reg_val & IXGBE_RXDCTL_ENABLE) {
2518 reg_val &= ~IXGBE_RXDCTL_ENABLE;
2519 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
2520 }
2521 }
2522
2523 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
2524 reg_val |= IXGBE_CTRL_GIO_DIS;
2525 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
2526
2527 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2528 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2529 goto check_device_status;
2530 usec_delay(100);
2531 }
2532
2533 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
2534 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2535
2536 /*
2537 * Before proceeding, make sure that the PCIe block does not have
2538 * transactions pending.
2539 */
2540 check_device_status:
2541 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2542 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
2543 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2544 break;
2545 usec_delay(100);
2546 }
2547
2548 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT)
2549 DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
2550 else
2551 goto out;
2552
2553 /*
2554 * Two consecutive resets are required via CTRL.RST per datasheet
2555 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2556 * of this need. The first reset prevents new master requests from
2557 * being issued by our device. We then must wait 1usec for any
2558 * remaining completions from the PCIe bus to trickle in, and then reset
2559 * again to clear out any effects they may have had on our device.
2560 */
2561 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2562
2563 out:
2564 return status;
2565 }
2566
2567
2568 /**
2569 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2570 * @hw: pointer to hardware structure
2571 * @mask: Mask to specify which semaphore to acquire
2572 *
2573 * Acquires the SWFW semaphore thought the GSSR register for the specified
2574 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2575 **/
2576 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2577 {
2578 u32 gssr;
2579 u32 swmask = mask;
2580 u32 fwmask = mask << 5;
2581 s32 timeout = 200;
2582
2583 DEBUGFUNC("ixgbe_acquire_swfw_sync");
2584
2585 while (timeout) {
2586 /*
2587 * SW EEPROM semaphore bit is used for access to all
2588 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2589 */
2590 if (ixgbe_get_eeprom_semaphore(hw))
2591 return IXGBE_ERR_SWFW_SYNC;
2592
2593 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2603 timeout--;
2604 }
2605
2606 if (!timeout) {
2607 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
2608 return IXGBE_ERR_SWFW_SYNC;
2609 }
2610
2611 gssr |= swmask;
2612 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2613
2614 ixgbe_release_eeprom_semaphore(hw);
2615 return IXGBE_SUCCESS;
2616 }
2617
2618 /**
2619 * ixgbe_release_swfw_sync - Release SWFW semaphore
2620 * @hw: pointer to hardware structure
2621 * @mask: Mask to specify which semaphore to release
2622 *
2623 * Releases the SWFW semaphore thought the GSSR register for the specified
2624 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2625 **/
2626 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2627 {
2628 u32 gssr;
2629 u32 swmask = mask;
2630
2631 DEBUGFUNC("ixgbe_release_swfw_sync");
2632
2633 (void) ixgbe_get_eeprom_semaphore(hw);
2634
2635 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2636 gssr &= ~swmask;
2637 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2638
2639 ixgbe_release_eeprom_semaphore(hw);
2640 }
2641
2642 /**
2643 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2644 * @hw: pointer to hardware structure
2645 * @regval: register value to write to RXCTRL
2646 *
2647 * Enables the Rx DMA unit
2648 **/
2649 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2650 {
2651 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
2652
2653 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2654
2655 return IXGBE_SUCCESS;
2656 }
2657
2658 /**
2659 * ixgbe_blink_led_start_generic - Blink LED based on index.
2660 * @hw: pointer to hardware structure
2661 * @index: led number to blink
2662 **/
2663 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2664 {
2665 ixgbe_link_speed speed = 0;
2666 bool link_up = 0;
2667 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2668 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2669
2670 DEBUGFUNC("ixgbe_blink_led_start_generic");
2671
2672 /*
2673 * Link must be up to auto-blink the LEDs;
2674 * Force it if link is down.
2675 */
2676 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2677
2678 if (!link_up) {
2679 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2680 autoc_reg |= IXGBE_AUTOC_FLU;
2681 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2682 msec_delay(10);
2683 }
2684
2685 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2686 led_reg |= IXGBE_LED_BLINK(index);
2687 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2688 IXGBE_WRITE_FLUSH(hw);
2689
2690 return IXGBE_SUCCESS;
2691 }
2692
2693 /**
2694 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2695 * @hw: pointer to hardware structure
2696 * @index: led number to stop blinking
2697 **/
2698 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2699 {
2700 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2701 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2743 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2744 * @hw: pointer to hardware structure
2745 * @san_mac_addr: SAN MAC address
2746 *
2747 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2748 * per-port, so set_lan_id() must be called before reading the addresses.
2749 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2750 * upon for non-SFP connections, so we must call it here.
2751 **/
2752 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2753 {
2754 u16 san_mac_data, san_mac_offset;
2755 u8 i;
2756
2757 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
2758
2759 /*
2760 * First read the EEPROM pointer to see if the MAC addresses are
2761 * available. If they're not, no point in calling set_lan_id() here.
2762 */
2763 (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2764
2765 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2766 /*
2767 * No addresses available in this EEPROM. It's not an
2768 * error though, so just wipe the local address and return.
2769 */
2770 for (i = 0; i < 6; i++)
2771 san_mac_addr[i] = 0xFF;
2772
2773 goto san_mac_addr_out;
2774 }
2775
2776 /* make sure we know which port we need to program */
2777 hw->mac.ops.set_lan_id(hw);
2778 /* apply the port offset to the address offset */
2779 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2780 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2781 for (i = 0; i < 3; i++) {
2782 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2783 san_mac_addr[i * 2] = (u8)(san_mac_data);
2788 san_mac_addr_out:
2789 return IXGBE_SUCCESS;
2790 }
2791
2792 /**
2793 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
2794 * @hw: pointer to hardware structure
2795 * @san_mac_addr: SAN MAC address
2796 *
2797 * Write a SAN MAC address to the EEPROM.
2798 **/
2799 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
2800 {
2801 s32 status = IXGBE_SUCCESS;
2802 u16 san_mac_data, san_mac_offset;
2803 u8 i;
2804
2805 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
2806
2807 /* Look for SAN mac address pointer. If not defined, return */
2808 (void) ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
2809
2810 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2811 status = IXGBE_ERR_NO_SAN_ADDR_PTR;
2812 goto san_mac_addr_out;
2813 }
2814
2815 /* Make sure we know which port we need to write */
2816 hw->mac.ops.set_lan_id(hw);
2817 /* Apply the port offset to the address offset */
2818 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2819 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2820
2821 for (i = 0; i < 3; i++) {
2822 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
2823 san_mac_data |= (u16)(san_mac_addr[i * 2]);
2824 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
2825 san_mac_offset++;
2826 }
2827
2828 san_mac_addr_out:
2829 return status;
2830 }
2831
2832 /**
2833 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2834 * @hw: pointer to hardware structure
2835 *
2836 * Read PCIe configuration space, and get the MSI-X vector count from
2837 * the capabilities table.
2838 **/
2839 u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
2840 {
2841 u32 msix_count = 64;
2842
2843 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
2844 if (hw->mac.msix_vectors_from_pcie) {
2845 msix_count = IXGBE_READ_PCIE_WORD(hw,
2846 IXGBE_PCIE_MSIX_82599_CAPS);
2847 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
2848
2849 /* MSI-X count is zero-based in HW, so increment to give
2850 * proper value */
2851 msix_count++;
2852 }
2853
2854 return msix_count;
2855 }
2856
2857 /**
2858 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
2859 * @hw: pointer to hardware structure
2860 * @addr: Address to put into receive address register
2861 * @vmdq: VMDq pool to assign
2862 *
2863 * Puts an ethernet address into a receive address register, or
2864 * finds the rar that it is aleady in; adds to the pool list
2865 **/
2866 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2867 {
2868 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
2869 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
2870 u32 rar;
2871 u32 rar_low, rar_high;
2872 u32 addr_low, addr_high;
2873
2883 * Either find the mac_id in rar or find the first empty space.
2884 * rar_highwater points to just after the highest currently used
2885 * rar in order to shorten the search. It grows when we add a new
2886 * rar to the top.
2887 */
2888 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
2889 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
2890
2891 if (((IXGBE_RAH_AV & rar_high) == 0)
2892 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
2893 first_empty_rar = rar;
2894 } else if ((rar_high & 0xFFFF) == addr_high) {
2895 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
2896 if (rar_low == addr_low)
2897 break; /* found it already in the rars */
2898 }
2899 }
2900
2901 if (rar < hw->mac.rar_highwater) {
2902 /* already there so just add to the pool bits */
2903 (void) ixgbe_set_vmdq(hw, rar, vmdq);
2904 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
2905 /* stick it into first empty RAR slot we found */
2906 rar = first_empty_rar;
2907 (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2908 } else if (rar == hw->mac.rar_highwater) {
2909 /* add it to the top of the list and inc the highwater mark */
2910 (void) ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2911 hw->mac.rar_highwater++;
2912 } else if (rar >= hw->mac.num_rar_entries) {
2913 return IXGBE_ERR_INVALID_MAC_ADDR;
2914 }
2915
2916 /*
2917 * If we found rar[0], make sure the default pool bit (we use pool 0)
2918 * remains cleared to be sure default pool packets will get delivered
2919 */
2920 if (rar == 0)
2921 (void) ixgbe_clear_vmdq(hw, rar, 0);
2922
2923 return rar;
2924 }
2925
2926 /**
2927 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2928 * @hw: pointer to hardware struct
2929 * @rar: receive address register index to disassociate
2930 * @vmdq: VMDq pool index to remove from the rar
2931 **/
2932 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
2933 {
2934 u32 mpsar_lo, mpsar_hi;
2935 u32 rar_entries = hw->mac.num_rar_entries;
2936
2937 DEBUGFUNC("ixgbe_clear_vmdq_generic");
2938
2939 /* Make sure we are using a valid rar index range */
2940 if (rar >= rar_entries) {
2941 DEBUGOUT1("RAR index %d is out of range.\n", rar);
2987
2988 /* Make sure we are using a valid rar index range */
2989 if (rar >= rar_entries) {
2990 DEBUGOUT1("RAR index %d is out of range.\n", rar);
2991 return IXGBE_ERR_INVALID_ARGUMENT;
2992 }
2993
2994 if (vmdq < 32) {
2995 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
2996 mpsar |= 1 << vmdq;
2997 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
2998 } else {
2999 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3000 mpsar |= 1 << (vmdq - 32);
3001 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3002 }
3003 return IXGBE_SUCCESS;
3004 }
3005
3006 /**
3007 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3008 * @hw: pointer to hardware structure
3009 **/
3010 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3011 {
3012 int i;
3013
3014 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3015 DEBUGOUT(" Clearing UTA\n");
3016
3017 for (i = 0; i < 128; i++)
3018 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3019
3020 return IXGBE_SUCCESS;
3021 }
3022
3023 /**
3024 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3025 * @hw: pointer to hardware structure
3026 * @vlan: VLAN id to write to VLAN filter
3065 }
3066
3067 return regindex;
3068 }
3069
3070 /**
3071 * ixgbe_set_vfta_generic - Set VLAN filter table
3072 * @hw: pointer to hardware structure
3073 * @vlan: VLAN id to write to VLAN filter
3074 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3075 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3076 *
3077 * Turn on/off specified VLAN in the VLAN filter table.
3078 **/
3079 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3080 bool vlan_on)
3081 {
3082 s32 regindex;
3083 u32 bitindex;
3084 u32 vfta;
3085 u32 bits;
3086 u32 vt;
3087 u32 targetbit;
3088 bool vfta_changed = FALSE;
3089
3090 DEBUGFUNC("ixgbe_set_vfta_generic");
3091
3092 if (vlan > 4095)
3093 return IXGBE_ERR_PARAM;
3094
3095 /*
3096 * this is a 2 part operation - first the VFTA, then the
3097 * VLVF and VLVFB if VT Mode is set
3098 * We don't write the VFTA until we know the VLVF part succeeded.
3099 */
3100
3101 /* Part 1
3102 * The VFTA is a bitstring made up of 128 32-bit registers
3103 * that enable the particular VLAN id, much like the MTA:
3104 * bits[11-5]: which register
3105 * bits[4-0]: which bit in the register
3106 */
3107 regindex = (vlan >> 5) & 0x7F;
3108 bitindex = vlan & 0x1F;
3109 targetbit = (1 << bitindex);
3110 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3111
3112 if (vlan_on) {
3113 if (!(vfta & targetbit)) {
3114 vfta |= targetbit;
3115 vfta_changed = TRUE;
3116 }
3117 } else {
3118 if ((vfta & targetbit)) {
3119 vfta &= ~targetbit;
3120 vfta_changed = TRUE;
3121 }
3122 }
3123
3124 /* Part 2
3125 * If VT Mode is set
3126 * Either vlan_on
3127 * make sure the vlan is in VLVF
3128 * set the vind bit in the matching VLVFB
3129 * Or !vlan_on
3130 * clear the pool bit and possibly the vind
3131 */
3132 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3133 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3134 s32 vlvf_index;
3135
3136 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3137 if (vlvf_index < 0)
3138 return vlvf_index;
3139
3140 if (vlan_on) {
3141 /* set the pool bit */
3142 if (vind < 32) {
3143 bits = IXGBE_READ_REG(hw,
3144 IXGBE_VLVFB(vlvf_index*2));
3145 bits |= (1 << vind);
3146 IXGBE_WRITE_REG(hw,
3147 IXGBE_VLVFB(vlvf_index*2),
3148 bits);
3149 } else {
3150 bits = IXGBE_READ_REG(hw,
3151 IXGBE_VLVFB((vlvf_index*2)+1));
3152 bits |= (1 << (vind-32));
3153 IXGBE_WRITE_REG(hw,
3154 IXGBE_VLVFB((vlvf_index*2)+1),
3155 bits);
3156 }
3157 } else {
3158 /* clear the pool bit */
3159 if (vind < 32) {
3160 bits = IXGBE_READ_REG(hw,
3161 IXGBE_VLVFB(vlvf_index*2));
3162 bits &= ~(1 << vind);
3163 IXGBE_WRITE_REG(hw,
3164 IXGBE_VLVFB(vlvf_index*2),
3165 bits);
3166 bits |= IXGBE_READ_REG(hw,
3167 IXGBE_VLVFB((vlvf_index*2)+1));
3168 } else {
3169 bits = IXGBE_READ_REG(hw,
3170 IXGBE_VLVFB((vlvf_index*2)+1));
3171 bits &= ~(1 << (vind-32));
3172 IXGBE_WRITE_REG(hw,
3173 IXGBE_VLVFB((vlvf_index*2)+1),
3174 bits);
3175 bits |= IXGBE_READ_REG(hw,
3176 IXGBE_VLVFB(vlvf_index*2));
3177 }
3178 }
3179
3180 /*
3181 * If there are still bits set in the VLVFB registers
3182 * for the VLAN ID indicated we need to see if the
3183 * caller is requesting that we clear the VFTA entry bit.
3184 * If the caller has requested that we clear the VFTA
3185 * entry bit but there are still pools/VFs using this VLAN
3186 * ID entry then ignore the request. We're not worried
3187 * about the case where we're turning the VFTA VLAN ID
3188 * entry bit on, only when requested to turn it off as
3189 * there may be multiple pools and/or VFs using the
3190 * VLAN ID entry. In that case we cannot clear the
3191 * VFTA bit until all pools/VFs using that VLAN ID have also
3192 * been cleared. This will be indicated by "bits" being
3193 * zero.
3194 */
3195 if (bits) {
3196 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3197 (IXGBE_VLVF_VIEN | vlan));
3198 if (!vlan_on) {
3199 /* someone wants to clear the vfta entry
3200 * but some pools/VFs are still using it.
3201 * Ignore it. */
3202 vfta_changed = FALSE;
3203 }
3204 }
3205 else
3206 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3207 }
3208
3209 if (vfta_changed)
3210 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3211
3212 return IXGBE_SUCCESS;
3213 }
3214
3215 /**
3216 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3217 * @hw: pointer to hardware structure
3218 *
3219 * Clears the VLAN filer table, and the VMDq index associated with the filter
3220 **/
3221 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3222 {
3223 u32 offset;
3224
3225 DEBUGFUNC("ixgbe_clear_vfta_generic");
3226
3227 for (offset = 0; offset < hw->mac.vft_size; offset++)
3228 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3229
3230 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3231 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3232 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
3233 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
3234 }
3235
3236 return IXGBE_SUCCESS;
3237 }
3238
3239 /**
3240 * ixgbe_check_mac_link_generic - Determine link and speed status
3241 * @hw: pointer to hardware structure
3242 * @speed: pointer to link speed
3243 * @link_up: TRUE when link is up
3244 * @link_up_wait_to_complete: bool used to wait for link up or not
3245 *
3246 * Reads the links register to determine if link is up and the current speed
3247 **/
3248 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3249 bool *link_up, bool link_up_wait_to_complete)
3250 {
3251 u32 links_reg, links_orig;
3252 u32 i;
3253
3276 }
3277 } else {
3278 if (links_reg & IXGBE_LINKS_UP)
3279 *link_up = TRUE;
3280 else
3281 *link_up = FALSE;
3282 }
3283
3284 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3285 IXGBE_LINKS_SPEED_10G_82599)
3286 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3287 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3288 IXGBE_LINKS_SPEED_1G_82599)
3289 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3290 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3291 IXGBE_LINKS_SPEED_100_82599)
3292 *speed = IXGBE_LINK_SPEED_100_FULL;
3293 else
3294 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3295
3296 /* if link is down, zero out the current_mode */
3297 if (*link_up == FALSE) {
3298 hw->fc.current_mode = ixgbe_fc_none;
3299 hw->fc.fc_was_autonegged = FALSE;
3300 }
3301
3302 return IXGBE_SUCCESS;
3303 }
3304
3305 /**
3306 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3307 * the EEPROM
3308 * @hw: pointer to hardware structure
3309 * @wwnn_prefix: the alternative WWNN prefix
3310 * @wwpn_prefix: the alternative WWPN prefix
3311 *
3312 * This function will read the EEPROM from the alternative SAN MAC address
3313 * block to check the support for the alternative WWNN/WWPN prefix support.
3314 **/
3315 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3316 u16 *wwpn_prefix)
3317 {
3318 u16 offset, caps;
3319 u16 alt_san_mac_blk_offset;
3320
3321 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
3382
3383 if ((offset == 0) || (offset == 0xFFFF))
3384 goto out;
3385
3386 /* read fcoe flags in iSCSI FCOE block */
3387 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
3388 status = hw->eeprom.ops.read(hw, offset, &flags);
3389 if (status != IXGBE_SUCCESS)
3390 goto out;
3391
3392 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
3393 *bs = ixgbe_fcoe_bootstatus_enabled;
3394 else
3395 *bs = ixgbe_fcoe_bootstatus_disabled;
3396
3397 out:
3398 return status;
3399 }
3400
3401 /**
3402 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
3403 * control
3404 * @hw: pointer to hardware structure
3405 *
3406 * There are several phys that do not support autoneg flow control. This
3407 * function check the device id to see if the associated phy supports
3408 * autoneg flow control.
3409 **/
3410 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
3411 {
3412
3413 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
3414
3415 switch (hw->device_id) {
3416 case IXGBE_DEV_ID_82599_T3_LOM:
3417 return IXGBE_SUCCESS;
3418 default:
3419 return IXGBE_ERR_FC_NOT_SUPPORTED;
3420 }
3421 }
3422
3423 /**
3424 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3425 * @hw: pointer to hardware structure
3426 * @enable: enable or disable switch for anti-spoofing
3427 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3428 *
3429 **/
3430 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3431 {
3432 int j;
3433 int pf_target_reg = pf >> 3;
3434 int pf_target_shift = pf % 8;
3435 u32 pfvfspoof = 0;
3436
3437 if (hw->mac.type == ixgbe_mac_82598EB)
3438 return;
3439
3440 if (enable)
3441 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3442
3443 /*
3444 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3445 * MAC anti-spoof enables in each register array element.
3446 */
3447 for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3448 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3449
3450 /* If not enabling anti-spoofing then done */
3451 if (!enable)
3452 return;
3453
3454 /*
3455 * The PF should be allowed to spoof so that it can support
3456 * emulation mode NICs. Reset the bit assigned to the PF
3457 */
3458 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
3459 pfvfspoof ^= (1 << pf_target_shift);
3460 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
3461 }
3462
3463 /**
3464 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3465 * @hw: pointer to hardware structure
3466 * @enable: enable or disable switch for VLAN anti-spoofing
3467 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3468 *
3469 **/
3470 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3471 {
3472 int vf_target_reg = vf >> 3;
3473 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3474 u32 pfvfspoof;
3475
3476 if (hw->mac.type == ixgbe_mac_82598EB)
3477 return;
3478
3479 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3480 if (enable)
3499 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3500
3501 return IXGBE_SUCCESS;
3502 }
3503
3504 /**
3505 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
3506 * @hw: pointer to hardware structure
3507 *
3508 **/
3509 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
3510 {
3511 u32 regval;
3512 u32 i;
3513
3514 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
3515
3516 /* Enable relaxed ordering */
3517 for (i = 0; i < hw->mac.max_tx_queues; i++) {
3518 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
3519 regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
3520 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
3521 }
3522
3523 for (i = 0; i < hw->mac.max_rx_queues; i++) {
3524 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
3525 regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
3526 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
3527 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
3528 }
3529
3530 }
|
1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_common.c,v 1.14 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
37 #include "ixgbe_api.h"
38
39 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
42 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
44 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
45 u16 count);
46 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
47 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
50
51 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
52 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
53 u16 *san_mac_offset);
54 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
59 u16 offset);
60
61 /**
62 * ixgbe_init_ops_generic - Inits function ptrs
63 * @hw: pointer to the hardware structure
64 *
65 * Initialize the function pointers.
66 **/
67 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
68 {
69 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
70 struct ixgbe_mac_info *mac = &hw->mac;
71 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
72
73 DEBUGFUNC("ixgbe_init_ops_generic");
74
75 /* EEPROM */
76 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
77 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
78 if (eec & IXGBE_EEC_PRES) {
79 eeprom->ops.read = &ixgbe_read_eerd_generic;
80 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
81 } else {
82 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
83 eeprom->ops.read_buffer =
84 &ixgbe_read_eeprom_buffer_bit_bang_generic;
85 }
86 eeprom->ops.write = &ixgbe_write_eeprom_generic;
87 eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
88 eeprom->ops.validate_checksum =
89 &ixgbe_validate_eeprom_checksum_generic;
90 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
91 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
92
93 /* MAC */
94 mac->ops.init_hw = &ixgbe_init_hw_generic;
95 mac->ops.reset_hw = NULL;
96 mac->ops.start_hw = &ixgbe_start_hw_generic;
97 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
98 mac->ops.get_media_type = NULL;
99 mac->ops.get_supported_physical_layer = NULL;
100 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
101 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
102 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
103 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
104 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
105 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
106 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
107
108 /* LEDs */
109 mac->ops.led_on = &ixgbe_led_on_generic;
110 mac->ops.led_off = &ixgbe_led_off_generic;
111 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
112 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
113
114 /* RAR, Multicast, VLAN */
115 mac->ops.set_rar = &ixgbe_set_rar_generic;
116 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
117 mac->ops.insert_mac_addr = NULL;
118 mac->ops.set_vmdq = NULL;
119 mac->ops.clear_vmdq = NULL;
120 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
121 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
122 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
123 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
124 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
125 mac->ops.clear_vfta = NULL;
126 mac->ops.set_vfta = NULL;
127 mac->ops.set_vlvf = NULL;
128 mac->ops.init_uta_tables = NULL;
129
130 /* Flow Control */
131 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
132
133 /* Link */
134 mac->ops.get_link_capabilities = NULL;
135 mac->ops.setup_link = NULL;
136 mac->ops.check_link = NULL;
137
138 return IXGBE_SUCCESS;
139 }
140
141 /**
142 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
143 * control
144 * @hw: pointer to hardware structure
145 *
146 * There are several phys that do not support autoneg flow control. This
147 * function check the device id to see if the associated phy supports
148 * autoneg flow control.
149 **/
150 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
151 {
152
153 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
154
155 switch (hw->device_id) {
156 case IXGBE_DEV_ID_X540T:
157 case IXGBE_DEV_ID_X540T1:
158 return IXGBE_SUCCESS;
159 case IXGBE_DEV_ID_82599_T3_LOM:
160 return IXGBE_SUCCESS;
161 default:
162 return IXGBE_ERR_FC_NOT_SUPPORTED;
163 }
164 }
165
166 /**
167 * ixgbe_setup_fc - Set up flow control
168 * @hw: pointer to hardware structure
169 *
170 * Called at init time to set up flow control.
171 **/
172 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
173 {
174 s32 ret_val = IXGBE_SUCCESS;
175 u32 reg = 0, reg_bp = 0;
176 u16 reg_cu = 0;
177
178 DEBUGFUNC("ixgbe_setup_fc");
179
180 /*
181 * Validate the requested mode. Strict IEEE mode does not allow
182 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
183 */
184 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
185 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
186 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
187 goto out;
188 }
189
190 /*
191 * 10gig parts do not have a word in the EEPROM to determine the
192 * default flow control setting, so we explicitly set it to full.
193 */
194 if (hw->fc.requested_mode == ixgbe_fc_default)
195 hw->fc.requested_mode = ixgbe_fc_full;
196
197 /*
198 * Set up the 1G and 10G flow control advertisement registers so the
199 * HW will be able to do fc autoneg once the cable is plugged in. If
200 * we link at 10G, the 1G advertisement is harmless and vice versa.
201 */
202 switch (hw->phy.media_type) {
203 case ixgbe_media_type_fiber:
204 case ixgbe_media_type_backplane:
205 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
206 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
207 break;
208 case ixgbe_media_type_copper:
209 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
210 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
211 break;
212 default:
213 break;
214 }
215
216 /*
217 * The possible values of fc.requested_mode are:
218 * 0: Flow control is completely disabled
219 * 1: Rx flow control is enabled (we can receive pause frames,
220 * but not send pause frames).
221 * 2: Tx flow control is enabled (we can send pause frames but
222 * we do not support receiving pause frames).
223 * 3: Both Rx and Tx flow control (symmetric) are enabled.
224 * other: Invalid.
225 */
226 switch (hw->fc.requested_mode) {
227 case ixgbe_fc_none:
228 /* Flow control completely disabled by software override. */
229 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
230 if (hw->phy.media_type == ixgbe_media_type_backplane)
231 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
232 IXGBE_AUTOC_ASM_PAUSE);
233 else if (hw->phy.media_type == ixgbe_media_type_copper)
234 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
235 break;
236 case ixgbe_fc_tx_pause:
237 /*
238 * Tx Flow control is enabled, and Rx Flow control is
239 * disabled by software override.
240 */
241 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
242 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
243 if (hw->phy.media_type == ixgbe_media_type_backplane) {
244 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
245 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
246 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
247 reg_cu |= IXGBE_TAF_ASM_PAUSE;
248 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
249 }
250 break;
251 case ixgbe_fc_rx_pause:
252 /*
253 * Rx Flow control is enabled and Tx Flow control is
254 * disabled by software override. Since there really
255 * isn't a way to advertise that we are capable of RX
256 * Pause ONLY, we will advertise that we support both
257 * symmetric and asymmetric Rx PAUSE, as such we fall
258 * through to the fc_full statement. Later, we will
259 * disable the adapter's ability to send PAUSE frames.
260 */
261 case ixgbe_fc_full:
262 /* Flow control (both Rx and Tx) is enabled by SW override. */
263 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
264 if (hw->phy.media_type == ixgbe_media_type_backplane)
265 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
266 IXGBE_AUTOC_ASM_PAUSE;
267 else if (hw->phy.media_type == ixgbe_media_type_copper)
268 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
269 break;
270 default:
271 DEBUGOUT("Flow control param set incorrectly\n");
272 ret_val = IXGBE_ERR_CONFIG;
273 goto out;
274 }
275
276 if (hw->mac.type != ixgbe_mac_X540) {
277 /*
278 * Enable auto-negotiation between the MAC & PHY;
279 * the MAC will advertise clause 37 flow control.
280 */
281 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
282 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
283
284 /* Disable AN timeout */
285 if (hw->fc.strict_ieee)
286 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
287
288 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
289 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
290 }
291
292 /*
293 * AUTOC restart handles negotiation of 1G and 10G on backplane
294 * and copper. There is no need to set the PCS1GCTL register.
295 *
296 */
297 if (hw->phy.media_type == ixgbe_media_type_backplane) {
298 reg_bp |= IXGBE_AUTOC_AN_RESTART;
299 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
300 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
301 (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
302 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
303 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
304 }
305
306 DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
307 out:
308 return ret_val;
309 }
310
311 /**
312 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
313 * @hw: pointer to hardware structure
314 *
315 * Starts the hardware by filling the bus info structure and media type, clears
316 * all on chip counters, initializes receive address registers, multicast
317 * table, VLAN filter table, calls routine to set up link and flow control
318 * settings, and leaves transmit and receive units disabled and uninitialized
319 **/
320 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
321 {
322 s32 ret_val;
323 u32 ctrl_ext;
324
325 DEBUGFUNC("ixgbe_start_hw_generic");
326
327 /* Set the media type */
328 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
329
330 /* PHY ops initialization must be done in reset_hw() */
331
332 /* Clear the VLAN filter table */
333 hw->mac.ops.clear_vfta(hw);
334
335 /* Clear statistics registers */
336 hw->mac.ops.clear_hw_cntrs(hw);
337
338 /* Set No Snoop Disable */
339 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
340 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
341 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
342 IXGBE_WRITE_FLUSH(hw);
343
344 /* Setup flow control */
345 ret_val = ixgbe_setup_fc(hw);
346 if (ret_val != IXGBE_SUCCESS)
347 goto out;
348
349 /* Clear adapter stopped flag */
350 hw->adapter_stopped = FALSE;
351
352 out:
353 return ret_val;
354 }
355
356 /**
357 * ixgbe_start_hw_gen2 - Init sequence for common device family
358 * @hw: pointer to hw structure
359 *
360 * Performs the init sequence common to the second generation
361 * of 10 GbE devices.
362 * Devices in the second generation:
363 * 82599
364 * X540
365 **/
366 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
367 {
368 u32 i;
369 u32 regval;
370
371 /* Clear the rate limiters */
372 for (i = 0; i < hw->mac.max_tx_queues; i++) {
373 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
374 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
375 }
376 IXGBE_WRITE_FLUSH(hw);
377
378 /* Disable relaxed ordering */
379 for (i = 0; i < hw->mac.max_tx_queues; i++) {
380 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
381 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
382 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
383 }
384
385 for (i = 0; i < hw->mac.max_rx_queues; i++) {
386 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
387 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
388 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
389 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
390 }
391
392 return IXGBE_SUCCESS;
393 }
394
395 /**
396 * ixgbe_init_hw_generic - Generic hardware initialization
397 * @hw: pointer to hardware structure
398 *
399 * Initialize the hardware by resetting the hardware, filling the bus info
400 * structure and media type, clears all on chip counters, initializes receive
401 * address registers, multicast table, VLAN filter table, calls routine to set
402 * up link and flow control settings, and leaves transmit and receive units
403 * disabled and uninitialized
404 **/
405 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
406 {
407 s32 status;
408
415 /* Start the HW */
416 status = hw->mac.ops.start_hw(hw);
417 }
418
419 return status;
420 }
421
422 /**
423 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
424 * @hw: pointer to hardware structure
425 *
426 * Clears all hardware statistics counters by reading them from the hardware
427 * Statistics counters are clear on read.
428 **/
429 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
430 {
431 u16 i = 0;
432
433 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
434
435 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
436 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
437 IXGBE_READ_REG(hw, IXGBE_ERRBC);
438 IXGBE_READ_REG(hw, IXGBE_MSPDC);
439 for (i = 0; i < 8; i++)
440 IXGBE_READ_REG(hw, IXGBE_MPC(i));
441
442 IXGBE_READ_REG(hw, IXGBE_MLFC);
443 IXGBE_READ_REG(hw, IXGBE_MRFC);
444 IXGBE_READ_REG(hw, IXGBE_RLEC);
445 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
446 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
447 if (hw->mac.type >= ixgbe_mac_82599EB) {
448 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
449 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
450 } else {
451 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
452 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
453 }
454
455 for (i = 0; i < 8; i++) {
456 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
457 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
458 if (hw->mac.type >= ixgbe_mac_82599EB) {
459 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
460 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
461 } else {
462 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
463 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
464 }
465 }
466 if (hw->mac.type >= ixgbe_mac_82599EB)
467 for (i = 0; i < 8; i++)
468 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
469 IXGBE_READ_REG(hw, IXGBE_PRC64);
470 IXGBE_READ_REG(hw, IXGBE_PRC127);
471 IXGBE_READ_REG(hw, IXGBE_PRC255);
472 IXGBE_READ_REG(hw, IXGBE_PRC511);
473 IXGBE_READ_REG(hw, IXGBE_PRC1023);
474 IXGBE_READ_REG(hw, IXGBE_PRC1522);
475 IXGBE_READ_REG(hw, IXGBE_GPRC);
476 IXGBE_READ_REG(hw, IXGBE_BPRC);
477 IXGBE_READ_REG(hw, IXGBE_MPRC);
478 IXGBE_READ_REG(hw, IXGBE_GPTC);
479 IXGBE_READ_REG(hw, IXGBE_GORCL);
480 IXGBE_READ_REG(hw, IXGBE_GORCH);
481 IXGBE_READ_REG(hw, IXGBE_GOTCL);
482 IXGBE_READ_REG(hw, IXGBE_GOTCH);
483 if (hw->mac.type == ixgbe_mac_82598EB)
484 for (i = 0; i < 8; i++)
485 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
486 IXGBE_READ_REG(hw, IXGBE_RUC);
487 IXGBE_READ_REG(hw, IXGBE_RFC);
488 IXGBE_READ_REG(hw, IXGBE_ROC);
489 IXGBE_READ_REG(hw, IXGBE_RJC);
490 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
491 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
492 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
493 IXGBE_READ_REG(hw, IXGBE_TORL);
494 IXGBE_READ_REG(hw, IXGBE_TORH);
495 IXGBE_READ_REG(hw, IXGBE_TPR);
496 IXGBE_READ_REG(hw, IXGBE_TPT);
497 IXGBE_READ_REG(hw, IXGBE_PTC64);
498 IXGBE_READ_REG(hw, IXGBE_PTC127);
499 IXGBE_READ_REG(hw, IXGBE_PTC255);
500 IXGBE_READ_REG(hw, IXGBE_PTC511);
501 IXGBE_READ_REG(hw, IXGBE_PTC1023);
502 IXGBE_READ_REG(hw, IXGBE_PTC1522);
503 IXGBE_READ_REG(hw, IXGBE_MPTC);
504 IXGBE_READ_REG(hw, IXGBE_BPTC);
505 for (i = 0; i < 16; i++) {
506 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
507 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
508 if (hw->mac.type >= ixgbe_mac_82599EB) {
509 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
510 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
511 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
512 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
513 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
514 } else {
515 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
516 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
517 }
518 }
519
520 if (hw->mac.type == ixgbe_mac_X540) {
521 if (hw->phy.id == 0)
522 ixgbe_identify_phy(hw);
523 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
524 IXGBE_MDIO_PCS_DEV_TYPE, &i);
525 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
526 IXGBE_MDIO_PCS_DEV_TYPE, &i);
527 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
528 IXGBE_MDIO_PCS_DEV_TYPE, &i);
529 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
530 IXGBE_MDIO_PCS_DEV_TYPE, &i);
531 }
532
533 return IXGBE_SUCCESS;
534 }
535
536 /**
537 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
538 * @hw: pointer to hardware structure
539 * @pba_num: stores the part number string from the EEPROM
540 * @pba_num_size: part number string buffer length
541 *
542 * Reads the part number string from the EEPROM.
543 **/
544 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
545 u32 pba_num_size)
546 {
547 s32 ret_val;
548 u16 data;
549 u16 pba_ptr;
550 u16 offset;
551 u16 length;
552
628
629 /* trim pba length from start of string */
630 pba_ptr++;
631 length--;
632
633 for (offset = 0; offset < length; offset++) {
634 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
635 if (ret_val) {
636 DEBUGOUT("NVM Read Error\n");
637 return ret_val;
638 }
639 pba_num[offset * 2] = (u8)(data >> 8);
640 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
641 }
642 pba_num[offset * 2] = '\0';
643
644 return IXGBE_SUCCESS;
645 }
646
647 /**
648 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
649 * @hw: pointer to hardware structure
650 * @pba_num: stores the part number from the EEPROM
651 *
652 * Reads the part number from the EEPROM.
653 **/
654 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
655 {
656 s32 ret_val;
657 u16 data;
658
659 DEBUGFUNC("ixgbe_read_pba_num_generic");
660
661 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
662 if (ret_val) {
663 DEBUGOUT("NVM Read Error\n");
664 return ret_val;
665 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
666 DEBUGOUT("NVM Not supported\n");
667 return IXGBE_NOT_IMPLEMENTED;
733 hw->bus.width = ixgbe_bus_width_pcie_x2;
734 break;
735 case IXGBE_PCI_LINK_WIDTH_4:
736 hw->bus.width = ixgbe_bus_width_pcie_x4;
737 break;
738 case IXGBE_PCI_LINK_WIDTH_8:
739 hw->bus.width = ixgbe_bus_width_pcie_x8;
740 break;
741 default:
742 hw->bus.width = ixgbe_bus_width_unknown;
743 break;
744 }
745
746 switch (link_status & IXGBE_PCI_LINK_SPEED) {
747 case IXGBE_PCI_LINK_SPEED_2500:
748 hw->bus.speed = ixgbe_bus_speed_2500;
749 break;
750 case IXGBE_PCI_LINK_SPEED_5000:
751 hw->bus.speed = ixgbe_bus_speed_5000;
752 break;
753 case IXGBE_PCI_LINK_SPEED_8000:
754 hw->bus.speed = ixgbe_bus_speed_8000;
755 break;
756 default:
757 hw->bus.speed = ixgbe_bus_speed_unknown;
758 break;
759 }
760
761 mac->ops.set_lan_id(hw);
762
763 return IXGBE_SUCCESS;
764 }
765
766 /**
767 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
768 * @hw: pointer to the HW structure
769 *
770 * Determines the LAN function id by reading memory-mapped registers
771 * and swaps the port value if requested.
772 **/
773 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
774 {
775 struct ixgbe_bus_info *bus = &hw->bus;
781 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
782 bus->lan_id = bus->func;
783
784 /* check for a port swap */
785 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
786 if (reg & IXGBE_FACTPS_LFS)
787 bus->func ^= 0x1;
788 }
789
790 /**
791 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
792 * @hw: pointer to hardware structure
793 *
794 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
795 * disables transmit and receive units. The adapter_stopped flag is used by
796 * the shared code and drivers to determine if the adapter is in a stopped
797 * state and should not touch the hardware.
798 **/
799 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
800 {
801 u32 reg_val;
802 u16 i;
803
804 DEBUGFUNC("ixgbe_stop_adapter_generic");
805
806 /*
807 * Set the adapter_stopped flag so other driver functions stop touching
808 * the hardware
809 */
810 hw->adapter_stopped = TRUE;
811
812 /* Disable the receive unit */
813 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
814
815 /* Clear interrupt mask to stop interrupts from being generated */
816 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
817
818 /* Clear any pending interrupts, flush previous writes */
819 IXGBE_READ_REG(hw, IXGBE_EICR);
820
821 /* Disable the transmit unit. Each queue must be disabled. */
822 for (i = 0; i < hw->mac.max_tx_queues; i++)
823 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
824
825 /* Disable the receive unit by stopping each queue */
826 for (i = 0; i < hw->mac.max_rx_queues; i++) {
827 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
828 reg_val &= ~IXGBE_RXDCTL_ENABLE;
829 reg_val |= IXGBE_RXDCTL_SWFLSH;
830 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
831 }
832
833 /* flush all queues disables */
834 IXGBE_WRITE_FLUSH(hw);
835 msec_delay(2);
836
837 /*
838 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
839 * access and verify no pending requests
840 */
841 return ixgbe_disable_pcie_master(hw);
842 }
843
844 /**
845 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
846 * @hw: pointer to hardware structure
847 * @index: led number to turn on
848 **/
849 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
850 {
851 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
852
853 DEBUGFUNC("ixgbe_led_on_generic");
854
855 /* To turn on the LED, set mode to ON. */
856 led_reg &= ~IXGBE_LED_MODE_MASK(index);
857 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
858 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
859 IXGBE_WRITE_FLUSH(hw);
860
861 return IXGBE_SUCCESS;
884 /**
885 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
886 * @hw: pointer to hardware structure
887 *
888 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
889 * ixgbe_hw struct in order to set up EEPROM access.
890 **/
891 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
892 {
893 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
894 u32 eec;
895 u16 eeprom_size;
896
897 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
898
899 if (eeprom->type == ixgbe_eeprom_uninitialized) {
900 eeprom->type = ixgbe_eeprom_none;
901 /* Set default semaphore delay to 10ms which is a well
902 * tested value */
903 eeprom->semaphore_delay = 10;
904 /* Clear EEPROM page size, it will be initialized as needed */
905 eeprom->word_page_size = 0;
906
907 /*
908 * Check for EEPROM present first.
909 * If not present leave as none
910 */
911 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
912 if (eec & IXGBE_EEC_PRES) {
913 eeprom->type = ixgbe_eeprom_spi;
914
915 /*
916 * SPI EEPROM is assumed here. This code would need to
917 * change if a future EEPROM is not SPI.
918 */
919 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
920 IXGBE_EEC_SIZE_SHIFT);
921 eeprom->word_size = 1 << (eeprom_size +
922 IXGBE_EEPROM_WORD_SIZE_SHIFT);
923 }
924
925 if (eec & IXGBE_EEC_ADDR_SIZE)
926 eeprom->address_bits = 16;
927 else
928 eeprom->address_bits = 8;
929 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
930 "%d\n", eeprom->type, eeprom->word_size,
931 eeprom->address_bits);
932 }
933
934 return IXGBE_SUCCESS;
935 }
936
937 /**
938 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
939 * @hw: pointer to hardware structure
940 * @offset: offset within the EEPROM to write
941 * @words: number of word(s)
942 * @data: 16 bit word(s) to write to EEPROM
943 *
944 * Reads 16 bit word(s) from EEPROM through bit-bang method
945 **/
946 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
947 u16 words, u16 *data)
948 {
949 s32 status = IXGBE_SUCCESS;
950 u16 i, count;
951
952 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
953
954 hw->eeprom.ops.init_params(hw);
955
956 if (words == 0) {
957 status = IXGBE_ERR_INVALID_ARGUMENT;
958 goto out;
959 }
960
961 if (offset + words > hw->eeprom.word_size) {
962 status = IXGBE_ERR_EEPROM;
963 goto out;
964 }
965
966 /*
967 * The EEPROM page size cannot be queried from the chip. We do lazy
968 * initialization. It is worth to do that when we write large buffer.
969 */
970 if ((hw->eeprom.word_page_size == 0) &&
971 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
972 ixgbe_detect_eeprom_page_size_generic(hw, offset);
973
974 /*
975 * We cannot hold synchronization semaphores for too long
976 * to avoid other entity starvation. However it is more efficient
977 * to read in bursts than synchronizing access for each word.
978 */
979 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
980 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
981 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
982 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
983 count, &data[i]);
984
985 if (status != IXGBE_SUCCESS)
986 break;
987 }
988
989 out:
990 return status;
991 }
992
993 /**
994 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
995 * @hw: pointer to hardware structure
996 * @offset: offset within the EEPROM to be written to
997 * @words: number of word(s)
998 * @data: 16 bit word(s) to be written to the EEPROM
999 *
1000 * If ixgbe_eeprom_update_checksum is not called after this function, the
1001 * EEPROM will most likely contain an invalid checksum.
1002 **/
1003 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1004 u16 words, u16 *data)
1005 {
1006 s32 status;
1007 u16 word;
1008 u16 page_size;
1009 u16 i;
1010 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1011
1012 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1013
1014 /* Prepare the EEPROM for writing */
1015 status = ixgbe_acquire_eeprom(hw);
1016
1017 if (status == IXGBE_SUCCESS) {
1018 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1019 ixgbe_release_eeprom(hw);
1020 status = IXGBE_ERR_EEPROM;
1021 }
1022 }
1023
1024 if (status == IXGBE_SUCCESS) {
1025 for (i = 0; i < words; i++) {
1026 ixgbe_standby_eeprom(hw);
1027
1028 /* Send the WRITE ENABLE command (8 bit opcode ) */
1029 ixgbe_shift_out_eeprom_bits(hw,
1030 IXGBE_EEPROM_WREN_OPCODE_SPI,
1031 IXGBE_EEPROM_OPCODE_BITS);
1032
1033 ixgbe_standby_eeprom(hw);
1034
1035 /*
1036 * Some SPI eeproms use the 8th address bit embedded
1037 * in the opcode
1038 */
1039 if ((hw->eeprom.address_bits == 8) &&
1040 ((offset + i) >= 128))
1041 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1042
1043 /* Send the Write command (8-bit opcode + addr) */
1044 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1045 IXGBE_EEPROM_OPCODE_BITS);
1046 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1047 hw->eeprom.address_bits);
1048
1049 page_size = hw->eeprom.word_page_size;
1050
1051 /* Send the data in burst via SPI*/
1052 do {
1053 word = data[i];
1054 word = (word >> 8) | (word << 8);
1055 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1056
1057 if (page_size == 0)
1058 break;
1059
1060 /* do not wrap around page */
1061 if (((offset + i) & (page_size - 1)) ==
1062 (page_size - 1))
1063 break;
1064 } while (++i < words);
1065
1066 ixgbe_standby_eeprom(hw);
1067 msec_delay(10);
1068 }
1069 /* Done with writing - release the EEPROM */
1070 ixgbe_release_eeprom(hw);
1071 }
1072
1073 return status;
1074 }
1075
1076 /**
1077 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1078 * @hw: pointer to hardware structure
1079 * @offset: offset within the EEPROM to be written to
1080 * @data: 16 bit word to be written to the EEPROM
1081 *
1082 * If ixgbe_eeprom_update_checksum is not called after this function, the
1083 * EEPROM will most likely contain an invalid checksum.
1084 **/
1085 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1086 {
1087 s32 status;
1088
1089 DEBUGFUNC("ixgbe_write_eeprom_generic");
1090
1091 hw->eeprom.ops.init_params(hw);
1092
1093 if (offset >= hw->eeprom.word_size) {
1094 status = IXGBE_ERR_EEPROM;
1095 goto out;
1096 }
1097
1098 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1099
1100 out:
1101 return status;
1102 }
1103
1104 /**
1105 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1106 * @hw: pointer to hardware structure
1107 * @offset: offset within the EEPROM to be read
1108 * @data: read 16 bit words(s) from EEPROM
1109 * @words: number of word(s)
1110 *
1111 * Reads 16 bit word(s) from EEPROM through bit-bang method
1112 **/
1113 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1114 u16 words, u16 *data)
1115 {
1116 s32 status = IXGBE_SUCCESS;
1117 u16 i, count;
1118
1119 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1120
1121 hw->eeprom.ops.init_params(hw);
1122
1123 if (words == 0) {
1124 status = IXGBE_ERR_INVALID_ARGUMENT;
1125 goto out;
1126 }
1127
1128 if (offset + words > hw->eeprom.word_size) {
1129 status = IXGBE_ERR_EEPROM;
1130 goto out;
1131 }
1132
1133 /*
1134 * We cannot hold synchronization semaphores for too long
1135 * to avoid other entity starvation. However it is more efficient
1136 * to read in bursts than synchronizing access for each word.
1137 */
1138 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1139 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1140 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1141
1142 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1143 count, &data[i]);
1144
1145 if (status != IXGBE_SUCCESS)
1146 break;
1147 }
1148
1149 out:
1150 return status;
1151 }
1152
1153 /**
1154 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1155 * @hw: pointer to hardware structure
1156 * @offset: offset within the EEPROM to be read
1157 * @words: number of word(s)
1158 * @data: read 16 bit word(s) from EEPROM
1159 *
1160 * Reads 16 bit word(s) from EEPROM through bit-bang method
1161 **/
1162 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1163 u16 words, u16 *data)
1164 {
1165 s32 status;
1166 u16 word_in;
1167 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1168 u16 i;
1169
1170 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1171
1172 /* Prepare the EEPROM for reading */
1173 status = ixgbe_acquire_eeprom(hw);
1174
1175 if (status == IXGBE_SUCCESS) {
1176 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1177 ixgbe_release_eeprom(hw);
1178 status = IXGBE_ERR_EEPROM;
1179 }
1180 }
1181
1182 if (status == IXGBE_SUCCESS) {
1183 for (i = 0; i < words; i++) {
1184 ixgbe_standby_eeprom(hw);
1185 /*
1186 * Some SPI eeproms use the 8th address bit embedded
1187 * in the opcode
1188 */
1189 if ((hw->eeprom.address_bits == 8) &&
1190 ((offset + i) >= 128))
1191 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1192
1193 /* Send the READ command (opcode + addr) */
1194 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1195 IXGBE_EEPROM_OPCODE_BITS);
1196 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1197 hw->eeprom.address_bits);
1198
1199 /* Read the data. */
1200 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1201 data[i] = (word_in >> 8) | (word_in << 8);
1202 }
1203
1204 /* End this read operation */
1205 ixgbe_release_eeprom(hw);
1206 }
1207
1208 return status;
1209 }
1210
1211 /**
1212 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1213 * @hw: pointer to hardware structure
1214 * @offset: offset within the EEPROM to be read
1215 * @data: read 16 bit value from EEPROM
1216 *
1217 * Reads 16 bit value from EEPROM through bit-bang method
1218 **/
1219 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1220 u16 *data)
1221 {
1222 s32 status;
1223
1224 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1225
1226 hw->eeprom.ops.init_params(hw);
1227
1228 if (offset >= hw->eeprom.word_size) {
1229 status = IXGBE_ERR_EEPROM;
1230 goto out;
1231 }
1232
1233 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1234
1235 out:
1236 return status;
1237 }
1238
1239 /**
1240 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1241 * @hw: pointer to hardware structure
1242 * @offset: offset of word in the EEPROM to read
1243 * @words: number of word(s)
1244 * @data: 16 bit word(s) from the EEPROM
1245 *
1246 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1247 **/
1248 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1249 u16 words, u16 *data)
1250 {
1251 u32 eerd;
1252 s32 status = IXGBE_SUCCESS;
1253 u32 i;
1254
1255 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1256
1257 hw->eeprom.ops.init_params(hw);
1258
1259 if (words == 0) {
1260 status = IXGBE_ERR_INVALID_ARGUMENT;
1261 goto out;
1262 }
1263
1264 if (offset >= hw->eeprom.word_size) {
1265 status = IXGBE_ERR_EEPROM;
1266 goto out;
1267 }
1268
1269 for (i = 0; i < words; i++) {
1270 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
1271 IXGBE_EEPROM_RW_REG_START;
1272
1273 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1274 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1275
1276 if (status == IXGBE_SUCCESS) {
1277 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1278 IXGBE_EEPROM_RW_REG_DATA);
1279 } else {
1280 DEBUGOUT("Eeprom read timed out\n");
1281 goto out;
1282 }
1283 }
1284 out:
1285 return status;
1286 }
1287
1288 /**
1289 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1290 * @hw: pointer to hardware structure
1291 * @offset: offset within the EEPROM to be used as a scratch pad
1292 *
1293 * Discover EEPROM page size by writing marching data at given offset.
1294 * This function is called only when we are writing a new large buffer
1295 * at given offset so the data would be overwritten anyway.
1296 **/
1297 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1298 u16 offset)
1299 {
1300 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1301 s32 status = IXGBE_SUCCESS;
1302 u16 i;
1303
1304 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1305
1306 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1307 data[i] = i;
1308
1309 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1310 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1311 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1312 hw->eeprom.word_page_size = 0;
1313 if (status != IXGBE_SUCCESS)
1314 goto out;
1315
1316 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1317 if (status != IXGBE_SUCCESS)
1318 goto out;
1319
1320 /*
1321 * When writing in burst more than the actual page size
1322 * EEPROM address wraps around current page.
1323 */
1324 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1325
1326 DEBUGOUT1("Detected EEPROM page size = %d words.",
1327 hw->eeprom.word_page_size);
1328 out:
1329 return status;
1330 }
1331
1332 /**
1333 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1334 * @hw: pointer to hardware structure
1335 * @offset: offset of word in the EEPROM to read
1336 * @data: word read from the EEPROM
1337 *
1338 * Reads a 16 bit word from the EEPROM using the EERD register.
1339 **/
1340 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1341 {
1342 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1343 }
1344
1345 /**
1346 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1347 * @hw: pointer to hardware structure
1348 * @offset: offset of word in the EEPROM to write
1349 * @words: number of word(s)
1350 * @data: word(s) write to the EEPROM
1351 *
1352 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1353 **/
1354 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1355 u16 words, u16 *data)
1356 {
1357 u32 eewr;
1358 s32 status = IXGBE_SUCCESS;
1359 u16 i;
1360
1361 DEBUGFUNC("ixgbe_write_eewr_generic");
1362
1363 hw->eeprom.ops.init_params(hw);
1364
1365 if (words == 0) {
1366 status = IXGBE_ERR_INVALID_ARGUMENT;
1367 goto out;
1368 }
1369
1370 if (offset >= hw->eeprom.word_size) {
1371 status = IXGBE_ERR_EEPROM;
1372 goto out;
1373 }
1374
1375 for (i = 0; i < words; i++) {
1376 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1377 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1378 IXGBE_EEPROM_RW_REG_START;
1379
1380 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1381 if (status != IXGBE_SUCCESS) {
1382 DEBUGOUT("Eeprom write EEWR timed out\n");
1383 goto out;
1384 }
1385
1386 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1387
1388 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1389 if (status != IXGBE_SUCCESS) {
1390 DEBUGOUT("Eeprom write EEWR timed out\n");
1391 goto out;
1392 }
1393 }
1394
1395 out:
1396 return status;
1397 }
1398
1399 /**
1400 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1401 * @hw: pointer to hardware structure
1402 * @offset: offset of word in the EEPROM to write
1403 * @data: word write to the EEPROM
1404 *
1405 * Write a 16 bit word to the EEPROM using the EEWR register.
1406 **/
1407 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1408 {
1409 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1410 }
1411
1412 /**
1413 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1414 * @hw: pointer to hardware structure
1415 * @ee_reg: EEPROM flag for polling
1416 *
1417 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1418 * read or write is done respectively.
1419 **/
1420 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1421 {
1422 u32 i;
1423 u32 reg;
1424 s32 status = IXGBE_ERR_EEPROM;
1425
1426 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1427
1428 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1429 if (ee_reg == IXGBE_NVM_POLL_READ)
1430 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1431 else
1432 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1438 usec_delay(5);
1439 }
1440 return status;
1441 }
1442
1443 /**
1444 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1445 * @hw: pointer to hardware structure
1446 *
1447 * Prepares EEPROM for access using bit-bang method. This function should
1448 * be called before issuing a command to the EEPROM.
1449 **/
1450 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1451 {
1452 s32 status = IXGBE_SUCCESS;
1453 u32 eec;
1454 u32 i;
1455
1456 DEBUGFUNC("ixgbe_acquire_eeprom");
1457
1458 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1459 != IXGBE_SUCCESS)
1460 status = IXGBE_ERR_SWFW_SYNC;
1461
1462 if (status == IXGBE_SUCCESS) {
1463 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1464
1465 /* Request EEPROM Access */
1466 eec |= IXGBE_EEC_REQ;
1467 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1468
1469 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1470 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1471 if (eec & IXGBE_EEC_GNT)
1472 break;
1473 usec_delay(5);
1474 }
1475
1476 /* Release if grant not acquired */
1477 if (!(eec & IXGBE_EEC_GNT)) {
1478 eec &= ~IXGBE_EEC_REQ;
1479 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1480 DEBUGOUT("Could not acquire EEPROM grant\n");
1481
1482 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1483 status = IXGBE_ERR_EEPROM;
1484 }
1485
1486 /* Setup EEPROM for Read/Write */
1487 if (status == IXGBE_SUCCESS) {
1488 /* Clear CS and SK */
1489 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1490 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1491 IXGBE_WRITE_FLUSH(hw);
1492 usec_delay(1);
1493 }
1494 }
1495 return status;
1496 }
1497
1498 /**
1499 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1500 * @hw: pointer to hardware structure
1501 *
1502 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1508 u32 i;
1509 u32 swsm;
1510
1511 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1512
1513
1514 /* Get SMBI software semaphore between device drivers first */
1515 for (i = 0; i < timeout; i++) {
1516 /*
1517 * If the SMBI bit is 0 when we read it, then the bit will be
1518 * set and we have the semaphore
1519 */
1520 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1521 if (!(swsm & IXGBE_SWSM_SMBI)) {
1522 status = IXGBE_SUCCESS;
1523 break;
1524 }
1525 usec_delay(50);
1526 }
1527
1528 if (i == timeout) {
1529 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1530 "not granted.\n");
1531 /*
1532 * this release is particularly important because our attempts
1533 * above to get the semaphore may have succeeded, and if there
1534 * was a timeout, we should unconditionally clear the semaphore
1535 * bits to free the driver to make progress
1536 */
1537 ixgbe_release_eeprom_semaphore(hw);
1538
1539 usec_delay(50);
1540 /*
1541 * one last try
1542 * If the SMBI bit is 0 when we read it, then the bit will be
1543 * set and we have the semaphore
1544 */
1545 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1546 if (!(swsm & IXGBE_SWSM_SMBI))
1547 status = IXGBE_SUCCESS;
1548 }
1549
1550 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1551 if (status == IXGBE_SUCCESS) {
1552 for (i = 0; i < timeout; i++) {
1553 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1554
1555 /* Set the SW EEPROM semaphore bit to request access */
1556 swsm |= IXGBE_SWSM_SWESMBI;
1557 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1558
1559 /*
1560 * If we set the bit successfully then we got the
1561 * semaphore.
1562 */
1563 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1564 if (swsm & IXGBE_SWSM_SWESMBI)
1565 break;
1566
1567 usec_delay(50);
1568 }
1569
1810 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
1811 {
1812 u32 eec;
1813
1814 DEBUGFUNC("ixgbe_release_eeprom");
1815
1816 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1817
1818 eec |= IXGBE_EEC_CS; /* Pull CS high */
1819 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
1820
1821 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1822 IXGBE_WRITE_FLUSH(hw);
1823
1824 usec_delay(1);
1825
1826 /* Stop requesting EEPROM access */
1827 eec &= ~IXGBE_EEC_REQ;
1828 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1829
1830 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1831
1832 /* Delay before attempt to obtain semaphore again to allow FW access */
1833 msec_delay(hw->eeprom.semaphore_delay);
1834 }
1835
1836 /**
1837 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
1838 * @hw: pointer to hardware structure
1839 **/
1840 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
1841 {
1842 u16 i;
1843 u16 j;
1844 u16 checksum = 0;
1845 u16 length = 0;
1846 u16 pointer = 0;
1847 u16 word = 0;
1848
1849 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
1850
2119 }
2120 hw->addr_ctrl.overflow_promisc = 0;
2121
2122 hw->addr_ctrl.rar_used_count = 1;
2123
2124 /* Zero out the other receive addresses. */
2125 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2126 for (i = 1; i < rar_entries; i++) {
2127 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2128 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2129 }
2130
2131 /* Clear the MTA */
2132 hw->addr_ctrl.mta_in_use = 0;
2133 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2134
2135 DEBUGOUT(" Clearing MTA\n");
2136 for (i = 0; i < hw->mac.mcft_size; i++)
2137 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2138
2139 ixgbe_init_uta_tables(hw);
2140
2141 return IXGBE_SUCCESS;
2142 }
2143
2144 /**
2145 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2146 * @hw: pointer to hardware structure
2147 * @addr: new address
2148 *
2149 * Adds it to unused receive address register or goes into promiscuous mode.
2150 **/
2151 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2152 {
2153 u32 rar_entries = hw->mac.num_rar_entries;
2154 u32 rar;
2155
2156 DEBUGFUNC("ixgbe_add_uc_addr");
2157
2158 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2159 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2309 /*
2310 * The MTA is a register array of 128 32-bit registers. It is treated
2311 * like an array of 4096 bits. We want to set bit
2312 * BitArray[vector_value]. So we figure out what register the bit is
2313 * in, read it, OR in the new bit, then write back the new value. The
2314 * register is determined by the upper 7 bits of the vector value and
2315 * the bit within that register are determined by the lower 5 bits of
2316 * the value.
2317 */
2318 vector_reg = (vector >> 5) & 0x7F;
2319 vector_bit = vector & 0x1F;
2320 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2321 }
2322
2323 /**
2324 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2325 * @hw: pointer to hardware structure
2326 * @mc_addr_list: the list of new multicast addresses
2327 * @mc_addr_count: number of addresses
2328 * @next: iterator function to walk the multicast address list
2329 * @clear: flag, when set clears the table beforehand
2330 *
2331 * When the clear flag is set, the given list replaces any existing list.
2332 * Hashes the given addresses into the multicast table.
2333 **/
2334 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2335 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2336 bool clear)
2337 {
2338 u32 i;
2339 u32 vmdq;
2340
2341 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2342
2343 /*
2344 * Set the new number of MC addresses that we are being requested to
2345 * use.
2346 */
2347 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2348 hw->addr_ctrl.mta_in_use = 0;
2349
2350 /* Clear mta_shadow */
2351 if (clear) {
2352 DEBUGOUT(" Clearing MTA\n");
2353 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2354 }
2355
2356 /* Update mta_shadow */
2357 for (i = 0; i < mc_addr_count; i++) {
2358 DEBUGOUT(" Adding the multicast addresses:\n");
2359 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2360 }
2361
2362 /* Enable mta */
2363 for (i = 0; i < hw->mac.mcft_size; i++)
2364 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2365 hw->mac.mta_shadow[i]);
2366
2367 if (hw->addr_ctrl.mta_in_use > 0)
2368 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2369 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2370
2371 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2372 return IXGBE_SUCCESS;
2373 }
2374
2395 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2396 * @hw: pointer to hardware structure
2397 *
2398 * Disables multicast address in RAR and the use of the multicast hash table.
2399 **/
2400 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2401 {
2402 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2403
2404 DEBUGFUNC("ixgbe_disable_mc_generic");
2405
2406 if (a->mta_in_use > 0)
2407 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2408
2409 return IXGBE_SUCCESS;
2410 }
2411
2412 /**
2413 * ixgbe_fc_enable_generic - Enable flow control
2414 * @hw: pointer to hardware structure
2415 *
2416 * Enable flow control according to the current settings.
2417 **/
2418 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2419 {
2420 s32 ret_val = IXGBE_SUCCESS;
2421 u32 mflcn_reg, fccfg_reg;
2422 u32 reg;
2423 u32 fcrtl, fcrth;
2424 int i;
2425
2426 DEBUGFUNC("ixgbe_fc_enable_generic");
2427
2428 /* Validate the water mark configuration */
2429 if (!hw->fc.pause_time) {
2430 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2431 goto out;
2432 }
2433
2434 /* Low water mark of zero causes XOFF floods */
2435 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2436 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2437 hw->fc.high_water[i]) {
2438 if (!hw->fc.low_water[i] ||
2439 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2440 DEBUGOUT("Invalid water mark configuration\n");
2441 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2442 goto out;
2443 }
2444 }
2445 }
2446
2447 /* Negotiate the fc mode to use */
2448 ixgbe_fc_autoneg(hw);
2449
2450 /* Disable any previous flow control settings */
2451 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2452 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2453
2454 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2455 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2456
2457 /*
2458 * The possible values of fc.current_mode are:
2459 * 0: Flow control is completely disabled
2460 * 1: Rx flow control is enabled (we can receive pause frames,
2461 * but not send pause frames).
2462 * 2: Tx flow control is enabled (we can send pause frames but
2463 * we do not support receiving pause frames).
2464 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2465 * other: Invalid.
2466 */
2467 switch (hw->fc.current_mode) {
2468 case ixgbe_fc_none:
2469 /*
2470 * Flow control is disabled by software override or autoneg.
2471 * The code below will actually disable it in the HW.
2472 */
2488 * disabled by software override.
2489 */
2490 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2491 break;
2492 case ixgbe_fc_full:
2493 /* Flow control (both Rx and Tx) is enabled by SW override. */
2494 mflcn_reg |= IXGBE_MFLCN_RFCE;
2495 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2496 break;
2497 default:
2498 DEBUGOUT("Flow control param set incorrectly\n");
2499 ret_val = IXGBE_ERR_CONFIG;
2500 goto out;
2501 }
2502
2503 /* Set 802.3x based flow control settings. */
2504 mflcn_reg |= IXGBE_MFLCN_DPF;
2505 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2506 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2507
2508
2509 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2510 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2511 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2512 hw->fc.high_water[i]) {
2513 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2514 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2515 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2516 } else {
2517 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2518 /*
2519 * In order to prevent Tx hangs when the internal Tx
2520 * switch is enabled we must set the high water mark
2521 * to the maximum FCRTH value. This allows the Tx
2522 * switch to function even under heavy Rx workloads.
2523 */
2524 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2525 }
2526
2527 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2528 }
2529
2530 /* Configure pause time (2 TCs per register) */
2531 reg = hw->fc.pause_time * 0x00010001;
2532 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2533 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2534
2535 /* Configure flow control refresh threshold value */
2536 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2537
2538 out:
2539 return ret_val;
2540 }
2541
2542 /**
2543 * ixgbe_negotiate_fc - Negotiate flow control
2544 * @hw: pointer to hardware structure
2545 * @adv_reg: flow control advertised settings
2546 * @lp_reg: link partner's flow control settings
2547 * @adv_sym: symmetric pause bit in advertisement
2548 * @adv_asm: asymmetric pause bit in advertisement
2549 * @lp_sym: symmetric pause bit in link partner advertisement
2550 * @lp_asm: asymmetric pause bit in link partner advertisement
2551 *
2552 * Find the intersection between advertised settings and link partner's
2553 * advertised settings
2554 **/
2555 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2556 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2557 {
2558 if ((!(adv_reg)) || (!(lp_reg)))
2559 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2560
2561 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2562 /*
2563 * Now we need to check if the user selected Rx ONLY
2564 * of pause frames. In this case, we had to advertise
2565 * FULL flow control because we could not advertise RX
2566 * ONLY. Hence, we must now check to see if we need to
2567 * turn OFF the TRANSMISSION of PAUSE frames.
2568 */
2569 if (hw->fc.requested_mode == ixgbe_fc_full) {
2570 hw->fc.current_mode = ixgbe_fc_full;
2571 DEBUGOUT("Flow Control = FULL.\n");
2572 } else {
2573 hw->fc.current_mode = ixgbe_fc_rx_pause;
2574 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2575 }
2576 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2577 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2578 hw->fc.current_mode = ixgbe_fc_tx_pause;
2579 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2580 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2581 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2582 hw->fc.current_mode = ixgbe_fc_rx_pause;
2583 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2584 } else {
2585 hw->fc.current_mode = ixgbe_fc_none;
2586 DEBUGOUT("Flow Control = NONE.\n");
2587 }
2588 return IXGBE_SUCCESS;
2589 }
2590
2591 /**
2592 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2593 * @hw: pointer to hardware structure
2594 *
2595 * Enable flow control according on 1 gig fiber.
2596 **/
2597 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2598 {
2599 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2600 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2601
2602 /*
2603 * On multispeed fiber at 1g, bail out if
2604 * - link is up but AN did not complete, or if
2605 * - link is up and AN completed but timed out
2606 */
2607
2608 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2609 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2610 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
2611 goto out;
2612
2613 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2614 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2615
2616 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2617 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2618 IXGBE_PCS1GANA_ASM_PAUSE,
2619 IXGBE_PCS1GANA_SYM_PAUSE,
2620 IXGBE_PCS1GANA_ASM_PAUSE);
2621
2622 out:
2623 return ret_val;
2624 }
2625
2626 /**
2627 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2628 * @hw: pointer to hardware structure
2629 *
2630 * Enable flow control according to IEEE clause 37.
2631 **/
2632 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2633 {
2634 u32 links2, anlp1_reg, autoc_reg, links;
2635 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2636
2637 /*
2638 * On backplane, bail out if
2639 * - backplane autoneg was not completed, or if
2640 * - we are 82599 and link partner is not AN enabled
2641 */
2642 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2643 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
2644 goto out;
2645
2646 if (hw->mac.type == ixgbe_mac_82599EB) {
2647 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2648 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
2649 goto out;
2650 }
2651 /*
2652 * Read the 10g AN autoc and LP ability registers and resolve
2653 * local flow control settings accordingly
2654 */
2655 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2656 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2657
2658 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2659 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2660 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2661
2662 out:
2663 return ret_val;
2664 }
2665
2666 /**
2667 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2668 * @hw: pointer to hardware structure
2669 *
2670 * Enable flow control according to IEEE clause 37.
2671 **/
2672 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2673 {
2674 u16 technology_ability_reg = 0;
2675 u16 lp_technology_ability_reg = 0;
2676
2677 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2678 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2679 &technology_ability_reg);
2680 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2681 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2682 &lp_technology_ability_reg);
2683
2684 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2685 (u32)lp_technology_ability_reg,
2686 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2687 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2688 }
2689
2690 /**
2691 * ixgbe_fc_autoneg - Configure flow control
2692 * @hw: pointer to hardware structure
2693 *
2694 * Compares our advertised flow control capabilities to those advertised by
2695 * our link partner, and determines the proper flow control mode to use.
2696 **/
2697 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2698 {
2699 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2700 ixgbe_link_speed speed;
2701 bool link_up;
2702
2703 DEBUGFUNC("ixgbe_fc_autoneg");
2704
2705 /*
2706 * AN should have completed when the cable was plugged in.
2707 * Look for reasons to bail out. Bail out if:
2708 * - FC autoneg is disabled, or if
2709 * - link is not up.
2710 */
2711 if (hw->fc.disable_fc_autoneg)
2712 goto out;
2713
2714 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2715 if (!link_up)
2716 goto out;
2717
2718 switch (hw->phy.media_type) {
2719 /* Autoneg flow control on fiber adapters */
2720 case ixgbe_media_type_fiber:
2721 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2722 ret_val = ixgbe_fc_autoneg_fiber(hw);
2723 break;
2724
2725 /* Autoneg flow control on backplane adapters */
2726 case ixgbe_media_type_backplane:
2727 ret_val = ixgbe_fc_autoneg_backplane(hw);
2728 break;
2729
2730 /* Autoneg flow control on copper adapters */
2731 case ixgbe_media_type_copper:
2732 if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
2733 ret_val = ixgbe_fc_autoneg_copper(hw);
2734 break;
2735
2736 default:
2737 break;
2738 }
2739
2740 out:
2741 if (ret_val == IXGBE_SUCCESS) {
2742 hw->fc.fc_was_autonegged = TRUE;
2743 } else {
2744 hw->fc.fc_was_autonegged = FALSE;
2745 hw->fc.current_mode = hw->fc.requested_mode;
2746 }
2747 }
2748
2749 /**
2750 * ixgbe_disable_pcie_master - Disable PCI-express master access
2751 * @hw: pointer to hardware structure
2752 *
2753 * Disables PCI-Express master access and verifies there are no pending
2754 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2755 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
2756 * is returned signifying master requests disabled.
2757 **/
2758 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
2759 {
2760 s32 status = IXGBE_SUCCESS;
2761 u32 i;
2762
2763 DEBUGFUNC("ixgbe_disable_pcie_master");
2764
2765 /* Always set this bit to ensure any future transactions are blocked */
2766 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
2767
2768 /* Exit if master requets are blocked */
2769 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2770 goto out;
2771
2772 /* Poll for master request bit to clear */
2773 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2774 usec_delay(100);
2775 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
2776 goto out;
2777 }
2778
2779 /*
2780 * Two consecutive resets are required via CTRL.RST per datasheet
2781 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
2782 * of this need. The first reset prevents new master requests from
2783 * being issued by our device. We then must wait 1usec or more for any
2784 * remaining completions from the PCIe bus to trickle in, and then reset
2785 * again to clear out any effects they may have had on our device.
2786 */
2787 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
2788 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2789
2790 /*
2791 * Before proceeding, make sure that the PCIe block does not have
2792 * transactions pending.
2793 */
2794 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
2795 usec_delay(100);
2796 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) &
2797 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
2798 goto out;
2799 }
2800
2801 DEBUGOUT("PCIe transaction pending bit also did not clear.\n");
2802 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
2803
2804 out:
2805 return status;
2806 }
2807
2808 /**
2809 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2810 * @hw: pointer to hardware structure
2811 * @mask: Mask to specify which semaphore to acquire
2812 *
2813 * Acquires the SWFW semaphore through the GSSR register for the specified
2814 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2815 **/
2816 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2817 {
2818 u32 gssr;
2819 u32 swmask = mask;
2820 u32 fwmask = mask << 5;
2821 s32 timeout = 200;
2822
2823 DEBUGFUNC("ixgbe_acquire_swfw_sync");
2824
2825 while (timeout) {
2826 /*
2827 * SW EEPROM semaphore bit is used for access to all
2828 * SW_FW_SYNC/GSSR bits (not just EEPROM)
2829 */
2830 if (ixgbe_get_eeprom_semaphore(hw))
2831 return IXGBE_ERR_SWFW_SYNC;
2832
2833 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2843 timeout--;
2844 }
2845
2846 if (!timeout) {
2847 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
2848 return IXGBE_ERR_SWFW_SYNC;
2849 }
2850
2851 gssr |= swmask;
2852 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2853
2854 ixgbe_release_eeprom_semaphore(hw);
2855 return IXGBE_SUCCESS;
2856 }
2857
2858 /**
2859 * ixgbe_release_swfw_sync - Release SWFW semaphore
2860 * @hw: pointer to hardware structure
2861 * @mask: Mask to specify which semaphore to release
2862 *
2863 * Releases the SWFW semaphore through the GSSR register for the specified
2864 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2865 **/
2866 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2867 {
2868 u32 gssr;
2869 u32 swmask = mask;
2870
2871 DEBUGFUNC("ixgbe_release_swfw_sync");
2872
2873 ixgbe_get_eeprom_semaphore(hw);
2874
2875 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2876 gssr &= ~swmask;
2877 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2878
2879 ixgbe_release_eeprom_semaphore(hw);
2880 }
2881
2882 /**
2883 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
2884 * @hw: pointer to hardware structure
2885 *
2886 * Stops the receive data path and waits for the HW to internally empty
2887 * the Rx security block
2888 **/
2889 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
2890 {
2891 #define IXGBE_MAX_SECRX_POLL 40
2892
2893 int i;
2894 int secrxreg;
2895
2896 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
2897
2898
2899 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2900 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2901 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2902 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2903 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2904 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2905 break;
2906 else
2907 /* Use interrupt-safe sleep just in case */
2908 usec_delay(1000);
2909 }
2910
2911 /* For informational purposes only */
2912 if (i >= IXGBE_MAX_SECRX_POLL)
2913 DEBUGOUT("Rx unit being enabled before security "
2914 "path fully disabled. Continuing with init.\n");
2915
2916 return IXGBE_SUCCESS;
2917 }
2918
2919 /**
2920 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
2921 * @hw: pointer to hardware structure
2922 *
2923 * Enables the receive data path.
2924 **/
2925 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
2926 {
2927 int secrxreg;
2928
2929 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
2930
2931 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2932 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2933 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2934 IXGBE_WRITE_FLUSH(hw);
2935
2936 return IXGBE_SUCCESS;
2937 }
2938
2939 /**
2940 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2941 * @hw: pointer to hardware structure
2942 * @regval: register value to write to RXCTRL
2943 *
2944 * Enables the Rx DMA unit
2945 **/
2946 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2947 {
2948 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
2949
2950 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2951
2952 return IXGBE_SUCCESS;
2953 }
2954
2955 /**
2956 * ixgbe_blink_led_start_generic - Blink LED based on index.
2957 * @hw: pointer to hardware structure
2958 * @index: led number to blink
2959 **/
2960 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2961 {
2962 ixgbe_link_speed speed = 0;
2963 bool link_up = 0;
2964 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2965 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2966
2967 DEBUGFUNC("ixgbe_blink_led_start_generic");
2968
2969 /*
2970 * Link must be up to auto-blink the LEDs;
2971 * Force it if link is down.
2972 */
2973 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2974
2975 if (!link_up) {
2976 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2977 autoc_reg |= IXGBE_AUTOC_FLU;
2978 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2979 IXGBE_WRITE_FLUSH(hw);
2980 msec_delay(10);
2981 }
2982
2983 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2984 led_reg |= IXGBE_LED_BLINK(index);
2985 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2986 IXGBE_WRITE_FLUSH(hw);
2987
2988 return IXGBE_SUCCESS;
2989 }
2990
2991 /**
2992 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2993 * @hw: pointer to hardware structure
2994 * @index: led number to stop blinking
2995 **/
2996 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2997 {
2998 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2999 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3041 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3042 * @hw: pointer to hardware structure
3043 * @san_mac_addr: SAN MAC address
3044 *
3045 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3046 * per-port, so set_lan_id() must be called before reading the addresses.
3047 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3048 * upon for non-SFP connections, so we must call it here.
3049 **/
3050 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3051 {
3052 u16 san_mac_data, san_mac_offset;
3053 u8 i;
3054
3055 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3056
3057 /*
3058 * First read the EEPROM pointer to see if the MAC addresses are
3059 * available. If they're not, no point in calling set_lan_id() here.
3060 */
3061 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3062
3063 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
3064 /*
3065 * No addresses available in this EEPROM. It's not an
3066 * error though, so just wipe the local address and return.
3067 */
3068 for (i = 0; i < 6; i++)
3069 san_mac_addr[i] = 0xFF;
3070
3071 goto san_mac_addr_out;
3072 }
3073
3074 /* make sure we know which port we need to program */
3075 hw->mac.ops.set_lan_id(hw);
3076 /* apply the port offset to the address offset */
3077 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3078 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3079 for (i = 0; i < 3; i++) {
3080 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
3081 san_mac_addr[i * 2] = (u8)(san_mac_data);
3086 san_mac_addr_out:
3087 return IXGBE_SUCCESS;
3088 }
3089
3090 /**
3091 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3092 * @hw: pointer to hardware structure
3093 * @san_mac_addr: SAN MAC address
3094 *
3095 * Write a SAN MAC address to the EEPROM.
3096 **/
3097 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3098 {
3099 s32 status = IXGBE_SUCCESS;
3100 u16 san_mac_data, san_mac_offset;
3101 u8 i;
3102
3103 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3104
3105 /* Look for SAN mac address pointer. If not defined, return */
3106 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3107
3108 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
3109 status = IXGBE_ERR_NO_SAN_ADDR_PTR;
3110 goto san_mac_addr_out;
3111 }
3112
3113 /* Make sure we know which port we need to write */
3114 hw->mac.ops.set_lan_id(hw);
3115 /* Apply the port offset to the address offset */
3116 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3117 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3118
3119 for (i = 0; i < 3; i++) {
3120 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3121 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3122 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3123 san_mac_offset++;
3124 }
3125
3126 san_mac_addr_out:
3127 return status;
3128 }
3129
3130 /**
3131 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3132 * @hw: pointer to hardware structure
3133 *
3134 * Read PCIe configuration space, and get the MSI-X vector count from
3135 * the capabilities table.
3136 **/
3137 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3138 {
3139 u16 msix_count = 1;
3140 u16 max_msix_count;
3141 u16 pcie_offset;
3142
3143 switch (hw->mac.type) {
3144 case ixgbe_mac_82598EB:
3145 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3146 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3147 break;
3148 case ixgbe_mac_82599EB:
3149 case ixgbe_mac_X540:
3150 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3151 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3152 break;
3153 default:
3154 return msix_count;
3155 }
3156
3157 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3158 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3159 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3160
3161 /* MSI-X count is zero-based in HW */
3162 msix_count++;
3163
3164 if (msix_count > max_msix_count)
3165 msix_count = max_msix_count;
3166
3167 return msix_count;
3168 }
3169
3170 /**
3171 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3172 * @hw: pointer to hardware structure
3173 * @addr: Address to put into receive address register
3174 * @vmdq: VMDq pool to assign
3175 *
3176 * Puts an ethernet address into a receive address register, or
3177 * finds the rar that it is aleady in; adds to the pool list
3178 **/
3179 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3180 {
3181 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3182 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3183 u32 rar;
3184 u32 rar_low, rar_high;
3185 u32 addr_low, addr_high;
3186
3196 * Either find the mac_id in rar or find the first empty space.
3197 * rar_highwater points to just after the highest currently used
3198 * rar in order to shorten the search. It grows when we add a new
3199 * rar to the top.
3200 */
3201 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3202 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3203
3204 if (((IXGBE_RAH_AV & rar_high) == 0)
3205 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3206 first_empty_rar = rar;
3207 } else if ((rar_high & 0xFFFF) == addr_high) {
3208 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3209 if (rar_low == addr_low)
3210 break; /* found it already in the rars */
3211 }
3212 }
3213
3214 if (rar < hw->mac.rar_highwater) {
3215 /* already there so just add to the pool bits */
3216 ixgbe_set_vmdq(hw, rar, vmdq);
3217 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3218 /* stick it into first empty RAR slot we found */
3219 rar = first_empty_rar;
3220 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3221 } else if (rar == hw->mac.rar_highwater) {
3222 /* add it to the top of the list and inc the highwater mark */
3223 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3224 hw->mac.rar_highwater++;
3225 } else if (rar >= hw->mac.num_rar_entries) {
3226 return IXGBE_ERR_INVALID_MAC_ADDR;
3227 }
3228
3229 /*
3230 * If we found rar[0], make sure the default pool bit (we use pool 0)
3231 * remains cleared to be sure default pool packets will get delivered
3232 */
3233 if (rar == 0)
3234 ixgbe_clear_vmdq(hw, rar, 0);
3235
3236 return rar;
3237 }
3238
3239 /**
3240 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3241 * @hw: pointer to hardware struct
3242 * @rar: receive address register index to disassociate
3243 * @vmdq: VMDq pool index to remove from the rar
3244 **/
3245 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3246 {
3247 u32 mpsar_lo, mpsar_hi;
3248 u32 rar_entries = hw->mac.num_rar_entries;
3249
3250 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3251
3252 /* Make sure we are using a valid rar index range */
3253 if (rar >= rar_entries) {
3254 DEBUGOUT1("RAR index %d is out of range.\n", rar);
3300
3301 /* Make sure we are using a valid rar index range */
3302 if (rar >= rar_entries) {
3303 DEBUGOUT1("RAR index %d is out of range.\n", rar);
3304 return IXGBE_ERR_INVALID_ARGUMENT;
3305 }
3306
3307 if (vmdq < 32) {
3308 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3309 mpsar |= 1 << vmdq;
3310 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3311 } else {
3312 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3313 mpsar |= 1 << (vmdq - 32);
3314 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3315 }
3316 return IXGBE_SUCCESS;
3317 }
3318
3319 /**
3320 * This function should only be involved in the IOV mode.
3321 * In IOV mode, Default pool is next pool after the number of
3322 * VFs advertized and not 0.
3323 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3324 *
3325 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3326 * @hw: pointer to hardware struct
3327 * @vmdq: VMDq pool index
3328 **/
3329 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3330 {
3331 u32 rar = hw->mac.san_mac_rar_index;
3332
3333 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3334
3335 if (vmdq < 32) {
3336 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3337 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3338 } else {
3339 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3340 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3341 }
3342
3343 return IXGBE_SUCCESS;
3344 }
3345
3346 /**
3347 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3348 * @hw: pointer to hardware structure
3349 **/
3350 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3351 {
3352 int i;
3353
3354 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3355 DEBUGOUT(" Clearing UTA\n");
3356
3357 for (i = 0; i < 128; i++)
3358 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3359
3360 return IXGBE_SUCCESS;
3361 }
3362
3363 /**
3364 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3365 * @hw: pointer to hardware structure
3366 * @vlan: VLAN id to write to VLAN filter
3405 }
3406
3407 return regindex;
3408 }
3409
3410 /**
3411 * ixgbe_set_vfta_generic - Set VLAN filter table
3412 * @hw: pointer to hardware structure
3413 * @vlan: VLAN id to write to VLAN filter
3414 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3415 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3416 *
3417 * Turn on/off specified VLAN in the VLAN filter table.
3418 **/
3419 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3420 bool vlan_on)
3421 {
3422 s32 regindex;
3423 u32 bitindex;
3424 u32 vfta;
3425 u32 targetbit;
3426 s32 ret_val = IXGBE_SUCCESS;
3427 bool vfta_changed = FALSE;
3428
3429 DEBUGFUNC("ixgbe_set_vfta_generic");
3430
3431 if (vlan > 4095)
3432 return IXGBE_ERR_PARAM;
3433
3434 /*
3435 * this is a 2 part operation - first the VFTA, then the
3436 * VLVF and VLVFB if VT Mode is set
3437 * We don't write the VFTA until we know the VLVF part succeeded.
3438 */
3439
3440 /* Part 1
3441 * The VFTA is a bitstring made up of 128 32-bit registers
3442 * that enable the particular VLAN id, much like the MTA:
3443 * bits[11-5]: which register
3444 * bits[4-0]: which bit in the register
3445 */
3446 regindex = (vlan >> 5) & 0x7F;
3447 bitindex = vlan & 0x1F;
3448 targetbit = (1 << bitindex);
3449 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3450
3451 if (vlan_on) {
3452 if (!(vfta & targetbit)) {
3453 vfta |= targetbit;
3454 vfta_changed = TRUE;
3455 }
3456 } else {
3457 if ((vfta & targetbit)) {
3458 vfta &= ~targetbit;
3459 vfta_changed = TRUE;
3460 }
3461 }
3462
3463 /* Part 2
3464 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3465 */
3466 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3467 &vfta_changed);
3468 if (ret_val != IXGBE_SUCCESS)
3469 return ret_val;
3470
3471 if (vfta_changed)
3472 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3473
3474 return IXGBE_SUCCESS;
3475 }
3476
3477 /**
3478 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3479 * @hw: pointer to hardware structure
3480 * @vlan: VLAN id to write to VLAN filter
3481 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3482 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3483 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3484 * should be changed
3485 *
3486 * Turn on/off specified bit in VLVF table.
3487 **/
3488 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3489 bool vlan_on, bool *vfta_changed)
3490 {
3491 u32 vt;
3492
3493 DEBUGFUNC("ixgbe_set_vlvf_generic");
3494
3495 if (vlan > 4095)
3496 return IXGBE_ERR_PARAM;
3497
3498 /* If VT Mode is set
3499 * Either vlan_on
3500 * make sure the vlan is in VLVF
3501 * set the vind bit in the matching VLVFB
3502 * Or !vlan_on
3503 * clear the pool bit and possibly the vind
3504 */
3505 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3506 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3507 s32 vlvf_index;
3508 u32 bits;
3509
3510 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3511 if (vlvf_index < 0)
3512 return vlvf_index;
3513
3514 if (vlan_on) {
3515 /* set the pool bit */
3516 if (vind < 32) {
3517 bits = IXGBE_READ_REG(hw,
3518 IXGBE_VLVFB(vlvf_index * 2));
3519 bits |= (1 << vind);
3520 IXGBE_WRITE_REG(hw,
3521 IXGBE_VLVFB(vlvf_index * 2),
3522 bits);
3523 } else {
3524 bits = IXGBE_READ_REG(hw,
3525 IXGBE_VLVFB((vlvf_index * 2) + 1));
3526 bits |= (1 << (vind - 32));
3527 IXGBE_WRITE_REG(hw,
3528 IXGBE_VLVFB((vlvf_index * 2) + 1),
3529 bits);
3530 }
3531 } else {
3532 /* clear the pool bit */
3533 if (vind < 32) {
3534 bits = IXGBE_READ_REG(hw,
3535 IXGBE_VLVFB(vlvf_index * 2));
3536 bits &= ~(1 << vind);
3537 IXGBE_WRITE_REG(hw,
3538 IXGBE_VLVFB(vlvf_index * 2),
3539 bits);
3540 bits |= IXGBE_READ_REG(hw,
3541 IXGBE_VLVFB((vlvf_index * 2) + 1));
3542 } else {
3543 bits = IXGBE_READ_REG(hw,
3544 IXGBE_VLVFB((vlvf_index * 2) + 1));
3545 bits &= ~(1 << (vind - 32));
3546 IXGBE_WRITE_REG(hw,
3547 IXGBE_VLVFB((vlvf_index * 2) + 1),
3548 bits);
3549 bits |= IXGBE_READ_REG(hw,
3550 IXGBE_VLVFB(vlvf_index * 2));
3551 }
3552 }
3553
3554 /*
3555 * If there are still bits set in the VLVFB registers
3556 * for the VLAN ID indicated we need to see if the
3557 * caller is requesting that we clear the VFTA entry bit.
3558 * If the caller has requested that we clear the VFTA
3559 * entry bit but there are still pools/VFs using this VLAN
3560 * ID entry then ignore the request. We're not worried
3561 * about the case where we're turning the VFTA VLAN ID
3562 * entry bit on, only when requested to turn it off as
3563 * there may be multiple pools and/or VFs using the
3564 * VLAN ID entry. In that case we cannot clear the
3565 * VFTA bit until all pools/VFs using that VLAN ID have also
3566 * been cleared. This will be indicated by "bits" being
3567 * zero.
3568 */
3569 if (bits) {
3570 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3571 (IXGBE_VLVF_VIEN | vlan));
3572 if ((!vlan_on) && (vfta_changed != NULL)) {
3573 /* someone wants to clear the vfta entry
3574 * but some pools/VFs are still using it.
3575 * Ignore it. */
3576 *vfta_changed = FALSE;
3577 }
3578 } else
3579 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3580 }
3581
3582 return IXGBE_SUCCESS;
3583 }
3584
3585 /**
3586 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3587 * @hw: pointer to hardware structure
3588 *
3589 * Clears the VLAN filer table, and the VMDq index associated with the filter
3590 **/
3591 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3592 {
3593 u32 offset;
3594
3595 DEBUGFUNC("ixgbe_clear_vfta_generic");
3596
3597 for (offset = 0; offset < hw->mac.vft_size; offset++)
3598 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3599
3600 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3601 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3602 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3603 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
3604 }
3605
3606 return IXGBE_SUCCESS;
3607 }
3608
3609 /**
3610 * ixgbe_check_mac_link_generic - Determine link and speed status
3611 * @hw: pointer to hardware structure
3612 * @speed: pointer to link speed
3613 * @link_up: TRUE when link is up
3614 * @link_up_wait_to_complete: bool used to wait for link up or not
3615 *
3616 * Reads the links register to determine if link is up and the current speed
3617 **/
3618 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3619 bool *link_up, bool link_up_wait_to_complete)
3620 {
3621 u32 links_reg, links_orig;
3622 u32 i;
3623
3646 }
3647 } else {
3648 if (links_reg & IXGBE_LINKS_UP)
3649 *link_up = TRUE;
3650 else
3651 *link_up = FALSE;
3652 }
3653
3654 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3655 IXGBE_LINKS_SPEED_10G_82599)
3656 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3657 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3658 IXGBE_LINKS_SPEED_1G_82599)
3659 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3660 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
3661 IXGBE_LINKS_SPEED_100_82599)
3662 *speed = IXGBE_LINK_SPEED_100_FULL;
3663 else
3664 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3665
3666 return IXGBE_SUCCESS;
3667 }
3668
3669 /**
3670 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
3671 * the EEPROM
3672 * @hw: pointer to hardware structure
3673 * @wwnn_prefix: the alternative WWNN prefix
3674 * @wwpn_prefix: the alternative WWPN prefix
3675 *
3676 * This function will read the EEPROM from the alternative SAN MAC address
3677 * block to check the support for the alternative WWNN/WWPN prefix support.
3678 **/
3679 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
3680 u16 *wwpn_prefix)
3681 {
3682 u16 offset, caps;
3683 u16 alt_san_mac_blk_offset;
3684
3685 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
3746
3747 if ((offset == 0) || (offset == 0xFFFF))
3748 goto out;
3749
3750 /* read fcoe flags in iSCSI FCOE block */
3751 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
3752 status = hw->eeprom.ops.read(hw, offset, &flags);
3753 if (status != IXGBE_SUCCESS)
3754 goto out;
3755
3756 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
3757 *bs = ixgbe_fcoe_bootstatus_enabled;
3758 else
3759 *bs = ixgbe_fcoe_bootstatus_disabled;
3760
3761 out:
3762 return status;
3763 }
3764
3765 /**
3766 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
3767 * @hw: pointer to hardware structure
3768 * @enable: enable or disable switch for anti-spoofing
3769 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
3770 *
3771 **/
3772 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
3773 {
3774 int j;
3775 int pf_target_reg = pf >> 3;
3776 int pf_target_shift = pf % 8;
3777 u32 pfvfspoof = 0;
3778
3779 if (hw->mac.type == ixgbe_mac_82598EB)
3780 return;
3781
3782 if (enable)
3783 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
3784
3785 /*
3786 * PFVFSPOOF register array is size 8 with 8 bits assigned to
3787 * MAC anti-spoof enables in each register array element.
3788 */
3789 for (j = 0; j < pf_target_reg; j++)
3790 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3791
3792 /*
3793 * The PF should be allowed to spoof so that it can support
3794 * emulation mode NICs. Do not set the bits assigned to the PF
3795 */
3796 pfvfspoof &= (1 << pf_target_shift) - 1;
3797 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
3798
3799 /*
3800 * Remaining pools belong to the PF so they do not need to have
3801 * anti-spoofing enabled.
3802 */
3803 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
3804 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
3805 }
3806
3807 /**
3808 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
3809 * @hw: pointer to hardware structure
3810 * @enable: enable or disable switch for VLAN anti-spoofing
3811 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
3812 *
3813 **/
3814 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
3815 {
3816 int vf_target_reg = vf >> 3;
3817 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
3818 u32 pfvfspoof;
3819
3820 if (hw->mac.type == ixgbe_mac_82598EB)
3821 return;
3822
3823 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3824 if (enable)
3843 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
3844
3845 return IXGBE_SUCCESS;
3846 }
3847
3848 /**
3849 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
3850 * @hw: pointer to hardware structure
3851 *
3852 **/
3853 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
3854 {
3855 u32 regval;
3856 u32 i;
3857
3858 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
3859
3860 /* Enable relaxed ordering */
3861 for (i = 0; i < hw->mac.max_tx_queues; i++) {
3862 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
3863 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3864 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
3865 }
3866
3867 for (i = 0; i < hw->mac.max_rx_queues; i++) {
3868 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
3869 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
3870 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
3871 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
3872 }
3873
3874 }
3875
3876 /**
3877 * ixgbe_calculate_checksum - Calculate checksum for buffer
3878 * @buffer: pointer to EEPROM
3879 * @length: size of EEPROM to calculate a checksum for
3880 * Calculates the checksum for some buffer on a specified length. The
3881 * checksum calculated is returned.
3882 **/
3883 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3884 {
3885 u32 i;
3886 u8 sum = 0;
3887
3888 DEBUGFUNC("ixgbe_calculate_checksum");
3889
3890 if (!buffer)
3891 return 0;
3892
3893 for (i = 0; i < length; i++)
3894 sum += buffer[i];
3895
3896 return (u8) (0 - sum);
3897 }
3898
3899 /**
3900 * ixgbe_host_interface_command - Issue command to manageability block
3901 * @hw: pointer to the HW structure
3902 * @buffer: contains the command to write and where the return status will
3903 * be placed
3904 * @length: length of buffer, must be multiple of 4 bytes
3905 *
3906 * Communicates with the manageability block. On success return IXGBE_SUCCESS
3907 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3908 **/
3909 static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3910 u32 length)
3911 {
3912 u32 hicr, i, bi;
3913 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3914 u8 buf_len, dword_len;
3915
3916 s32 ret_val = IXGBE_SUCCESS;
3917
3918 DEBUGFUNC("ixgbe_host_interface_command");
3919
3920 if (length == 0 || length & 0x3 ||
3921 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3922 DEBUGOUT("Buffer length failure.\n");
3923 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3924 goto out;
3925 }
3926
3927 /* Check that the host interface is enabled. */
3928 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3929 if ((hicr & IXGBE_HICR_EN) == 0) {
3930 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
3931 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3932 goto out;
3933 }
3934
3935 /* Calculate length in DWORDs */
3936 dword_len = length >> 2;
3937
3938 /*
3939 * The device driver writes the relevant command block
3940 * into the ram area.
3941 */
3942 for (i = 0; i < dword_len; i++)
3943 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
3944 i, IXGBE_CPU_TO_LE32(buffer[i]));
3945
3946 /* Setting this bit tells the ARC that a new command is pending. */
3947 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
3948
3949 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
3950 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3951 if (!(hicr & IXGBE_HICR_C))
3952 break;
3953 msec_delay(1);
3954 }
3955
3956 /* Check command successful completion. */
3957 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
3958 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
3959 DEBUGOUT("Command has failed with no status valid.\n");
3960 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3961 goto out;
3962 }
3963
3964 /* Calculate length in DWORDs */
3965 dword_len = hdr_size >> 2;
3966
3967 /* first pull in the header so we know the buffer length */
3968 for (bi = 0; bi < dword_len; bi++) {
3969 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3970 IXGBE_LE32_TO_CPUS(&buffer[bi]);
3971 }
3972
3973 /* If there is any thing in data position pull it in */
3974 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
3975 if (buf_len == 0)
3976 goto out;
3977
3978 if (length < (buf_len + hdr_size)) {
3979 DEBUGOUT("Buffer not large enough for reply message.\n");
3980 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3981 goto out;
3982 }
3983
3984 /* Calculate length in DWORDs, add 3 for odd lengths */
3985 dword_len = (buf_len + 3) >> 2;
3986
3987 /* Pull in the rest of the buffer (bi is where we left off)*/
3988 for (; bi <= dword_len; bi++) {
3989 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
3990 IXGBE_LE32_TO_CPUS(&buffer[bi]);
3991 }
3992
3993 out:
3994 return ret_val;
3995 }
3996
3997 /**
3998 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
3999 * @hw: pointer to the HW structure
4000 * @maj: driver version major number
4001 * @min: driver version minor number
4002 * @build: driver version build number
4003 * @sub: driver version sub build number
4004 *
4005 * Sends driver version number to firmware through the manageability
4006 * block. On success return IXGBE_SUCCESS
4007 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4008 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4009 **/
4010 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4011 u8 build, u8 sub)
4012 {
4013 struct ixgbe_hic_drv_info fw_cmd;
4014 int i;
4015 s32 ret_val = IXGBE_SUCCESS;
4016
4017 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4018
4019 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4020 != IXGBE_SUCCESS) {
4021 ret_val = IXGBE_ERR_SWFW_SYNC;
4022 goto out;
4023 }
4024
4025 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4026 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4027 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4028 fw_cmd.port_num = (u8)hw->bus.func;
4029 fw_cmd.ver_maj = maj;
4030 fw_cmd.ver_min = min;
4031 fw_cmd.ver_build = build;
4032 fw_cmd.ver_sub = sub;
4033 fw_cmd.hdr.checksum = 0;
4034 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4035 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4036 fw_cmd.pad = 0;
4037 fw_cmd.pad2 = 0;
4038
4039 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4040 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4041 sizeof(fw_cmd));
4042 if (ret_val != IXGBE_SUCCESS)
4043 continue;
4044
4045 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4046 FW_CEM_RESP_STATUS_SUCCESS)
4047 ret_val = IXGBE_SUCCESS;
4048 else
4049 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4050
4051 break;
4052 }
4053
4054 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4055 out:
4056 return ret_val;
4057 }
4058
4059 /**
4060 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4061 * @hw: pointer to hardware structure
4062 * @num_pb: number of packet buffers to allocate
4063 * @headroom: reserve n KB of headroom
4064 * @strategy: packet buffer allocation strategy
4065 **/
4066 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4067 int strategy)
4068 {
4069 u32 pbsize = hw->mac.rx_pb_size;
4070 int i = 0;
4071 u32 rxpktsize, txpktsize, txpbthresh;
4072
4073 /* Reserve headroom */
4074 pbsize -= headroom;
4075
4076 if (!num_pb)
4077 num_pb = 1;
4078
4079 /* Divide remaining packet buffer space amongst the number of packet
4080 * buffers requested using supplied strategy.
4081 */
4082 switch (strategy) {
4083 case PBA_STRATEGY_WEIGHTED:
4084 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4085 * buffer with 5/8 of the packet buffer space.
4086 */
4087 rxpktsize = (pbsize * 5) / (num_pb * 4);
4088 pbsize -= rxpktsize * (num_pb / 2);
4089 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4090 for (; i < (num_pb / 2); i++)
4091 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4092 /* Fall through to configure remaining packet buffers */
4093 case PBA_STRATEGY_EQUAL:
4094 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4095 for (; i < num_pb; i++)
4096 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4097 break;
4098 default:
4099 break;
4100 }
4101
4102 /* Only support an equally distributed Tx packet buffer strategy. */
4103 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4104 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4105 for (i = 0; i < num_pb; i++) {
4106 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4107 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4108 }
4109
4110 /* Clear unused TCs, if any, to zero buffer size*/
4111 for (; i < IXGBE_MAX_PB; i++) {
4112 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4113 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4114 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4115 }
4116 }
4117
4118 /**
4119 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4120 * @hw: pointer to the hardware structure
4121 *
4122 * The 82599 and x540 MACs can experience issues if TX work is still pending
4123 * when a reset occurs. This function prevents this by flushing the PCIe
4124 * buffers on the system.
4125 **/
4126 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4127 {
4128 u32 gcr_ext, hlreg0;
4129
4130 /*
4131 * If double reset is not requested then all transactions should
4132 * already be clear and as such there is no work to do
4133 */
4134 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4135 return;
4136
4137 /*
4138 * Set loopback enable to prevent any transmits from being sent
4139 * should the link come up. This assumes that the RXCTRL.RXEN bit
4140 * has already been cleared.
4141 */
4142 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4143 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4144
4145 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4146 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4147 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4148 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4149
4150 /* Flush all writes and allow 20usec for all transactions to clear */
4151 IXGBE_WRITE_FLUSH(hw);
4152 usec_delay(20);
4153
4154 /* restore previous register values */
4155 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4156 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4157 }
4158
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