Print this page
XXXX Intel X540 support
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/io/ixgbe/ixgbe_phy.h
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_phy.h
1 1 /******************************************************************************
2 2
3 - Copyright (c) 2001-2010, Intel Corporation
3 + Copyright (c) 2001-2012, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
|
↓ open down ↓ |
18 lines elided |
↑ open up ↑ |
32 32 ******************************************************************************/
33 33 /*$FreeBSD$*/
34 34
35 35 #ifndef _IXGBE_PHY_H_
36 36 #define _IXGBE_PHY_H_
37 37
38 38 #include "ixgbe_type.h"
39 39 #define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
40 40
41 41 /* EEPROM byte offsets */
42 -#define IXGBE_SFF_IDENTIFIER 0x0
43 -#define IXGBE_SFF_IDENTIFIER_SFP 0x3
44 -#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
45 -#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
46 -#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
47 -#define IXGBE_SFF_1GBE_COMP_CODES 0x6
48 -#define IXGBE_SFF_10GBE_COMP_CODES 0x3
49 -#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
50 -#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
42 +#define IXGBE_SFF_IDENTIFIER 0x0
43 +#define IXGBE_SFF_IDENTIFIER_SFP 0x3
44 +#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
45 +#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
46 +#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
47 +#define IXGBE_SFF_1GBE_COMP_CODES 0x6
48 +#define IXGBE_SFF_10GBE_COMP_CODES 0x3
49 +#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
50 +#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
51 51
52 52 /* Bitmasks */
53 -#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
54 -#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
55 -#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
56 -#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
57 -#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
58 -#define IXGBE_SFF_1GBASET_CAPABLE 0x8
59 -#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
60 -#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
61 -#define IXGBE_I2C_EEPROM_READ_MASK 0x100
62 -#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
63 -#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
64 -#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
65 -#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
66 -#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
53 +#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
54 +#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
55 +#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
56 +#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
57 +#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
58 +#define IXGBE_SFF_1GBASET_CAPABLE 0x8
59 +#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
60 +#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
61 +#define IXGBE_I2C_EEPROM_READ_MASK 0x100
62 +#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
63 +#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
64 +#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
65 +#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
66 +#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
67 67
68 68 /* Flow control defines */
69 -#define IXGBE_TAF_SYM_PAUSE 0x400
70 -#define IXGBE_TAF_ASM_PAUSE 0x800
69 +#define IXGBE_TAF_SYM_PAUSE 0x400
70 +#define IXGBE_TAF_ASM_PAUSE 0x800
71 71
72 72 /* Bit-shift macros */
73 -#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
74 -#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
75 -#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
73 +#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
74 +#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
75 +#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
76 76
77 77 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
78 -#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
79 -#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
80 -#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
81 -#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
78 +#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
79 +#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
80 +#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
81 +#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
82 82
83 83 /* I2C SDA and SCL timing parameters for standard mode */
84 -#define IXGBE_I2C_T_HD_STA 4
85 -#define IXGBE_I2C_T_LOW 5
86 -#define IXGBE_I2C_T_HIGH 4
87 -#define IXGBE_I2C_T_SU_STA 5
88 -#define IXGBE_I2C_T_HD_DATA 5
89 -#define IXGBE_I2C_T_SU_DATA 1
90 -#define IXGBE_I2C_T_RISE 1
91 -#define IXGBE_I2C_T_FALL 1
92 -#define IXGBE_I2C_T_SU_STO 4
93 -#define IXGBE_I2C_T_BUF 5
84 +#define IXGBE_I2C_T_HD_STA 4
85 +#define IXGBE_I2C_T_LOW 5
86 +#define IXGBE_I2C_T_HIGH 4
87 +#define IXGBE_I2C_T_SU_STA 5
88 +#define IXGBE_I2C_T_HD_DATA 5
89 +#define IXGBE_I2C_T_SU_DATA 1
90 +#define IXGBE_I2C_T_RISE 1
91 +#define IXGBE_I2C_T_FALL 1
92 +#define IXGBE_I2C_T_SU_STO 4
93 +#define IXGBE_I2C_T_BUF 5
94 94
95 -#define IXGBE_TN_LASI_STATUS_REG 0x9005
96 -#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
95 +#define IXGBE_TN_LASI_STATUS_REG 0x9005
96 +#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
97 97
98 98 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
99 99 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
100 100 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
101 101 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
102 102 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
103 103 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
104 104 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
105 - u32 device_type, u16 *phy_data);
105 + u32 device_type, u16 *phy_data);
106 106 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
107 - u32 device_type, u16 phy_data);
107 + u32 device_type, u16 phy_data);
108 108 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
109 109 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
110 - ixgbe_link_speed speed,
111 - bool autoneg,
112 - bool autoneg_wait_to_complete);
110 + ixgbe_link_speed speed,
111 + bool autoneg,
112 + bool autoneg_wait_to_complete);
113 113 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
114 - ixgbe_link_speed *speed,
115 - bool *autoneg);
114 + ixgbe_link_speed *speed,
115 + bool *autoneg);
116 116
117 117 /* PHY specific */
118 118 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
119 - ixgbe_link_speed *speed,
120 - bool *link_up);
119 + ixgbe_link_speed *speed,
120 + bool *link_up);
121 121 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
122 122 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
123 - u16 *firmware_version);
123 + u16 *firmware_version);
124 124 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
125 - u16 *firmware_version);
125 + u16 *firmware_version);
126 126
127 127 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
128 +s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
128 129 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
129 130 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
130 - u16 *list_offset,
131 - u16 *data_offset);
131 + u16 *list_offset,
132 + u16 *data_offset);
132 133 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
133 134 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
134 - u8 dev_addr, u8 *data);
135 + u8 dev_addr, u8 *data);
135 136 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
136 - u8 dev_addr, u8 data);
137 + u8 dev_addr, u8 data);
137 138 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
138 - u8 *eeprom_data);
139 + u8 *eeprom_data);
139 140 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
140 - u8 eeprom_data);
141 + u8 eeprom_data);
142 +void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
141 143 #endif /* _IXGBE_PHY_H_ */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX