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XXXX Intel X540 support
*** 28,45 ****
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
! /*$FreeBSD$*/
#include "ixgbe_api.h"
#include "ixgbe_common.h"
- extern s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
- extern s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
-
/**
* ixgbe_init_shared_code - Initialize the shared code
* @hw: pointer to hardware structure
*
* This will assign function pointers and assign the MAC type and PHY code.
--- 28,42 ----
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
! /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
#include "ixgbe_api.h"
#include "ixgbe_common.h"
/**
* ixgbe_init_shared_code - Initialize the shared code
* @hw: pointer to hardware structure
*
* This will assign function pointers and assign the MAC type and PHY code.
*** 57,75 ****
DEBUGFUNC("ixgbe_init_shared_code");
/*
* Set the mac type
*/
! (void) ixgbe_set_mac_type(hw);
switch (hw->mac.type) {
case ixgbe_mac_82598EB:
status = ixgbe_init_ops_82598(hw);
break;
case ixgbe_mac_82599EB:
status = ixgbe_init_ops_82599(hw);
break;
default:
status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
break;
}
--- 54,82 ----
DEBUGFUNC("ixgbe_init_shared_code");
/*
* Set the mac type
*/
! ixgbe_set_mac_type(hw);
switch (hw->mac.type) {
case ixgbe_mac_82598EB:
status = ixgbe_init_ops_82598(hw);
break;
case ixgbe_mac_82599EB:
status = ixgbe_init_ops_82599(hw);
break;
+ #if 0
+ /* XXX KEBE ASKS - nuke this? */
+ case ixgbe_mac_82599_vf:
+ case ixgbe_mac_X540_vf:
+ status = ixgbe_init_ops_vf(hw);
+ break;
+ #endif
+ case ixgbe_mac_X540:
+ status = ixgbe_init_ops_X540(hw);
+ break;
default:
status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
break;
}
*** 118,127 ****
--- 125,144 ----
case IXGBE_DEV_ID_82599EN_SFP:
case IXGBE_DEV_ID_82599_CX4:
case IXGBE_DEV_ID_82599_T3_LOM:
hw->mac.type = ixgbe_mac_82599EB;
break;
+ case IXGBE_DEV_ID_82599_VF:
+ hw->mac.type = ixgbe_mac_82599_vf;
+ break;
+ case IXGBE_DEV_ID_X540_VF:
+ hw->mac.type = ixgbe_mac_X540_vf;
+ break;
+ case IXGBE_DEV_ID_X540T:
+ case IXGBE_DEV_ID_X540T1:
+ hw->mac.type = ixgbe_mac_X540;
+ break;
default:
ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
break;
}
} else {
*** 361,383 ****
{
return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);
}
/**
- * ixgbe_read_pba_length - Reads part number string length from EEPROM
- * @hw: pointer to hardware structure
- * @pba_num_size: part number string buffer length
- *
- * Reads the part number length from the EEPROM.
- * Returns expected buffer size in pba_num_size.
- **/
- s32 ixgbe_read_pba_length(struct ixgbe_hw *hw, u32 *pba_num_size)
- {
- return ixgbe_read_pba_length_generic(hw, pba_num_size);
- }
-
- /**
* ixgbe_read_pba_num - Reads part number from EEPROM
* @hw: pointer to hardware structure
* @pba_num: stores the part number from the EEPROM
*
* Reads the part number from the EEPROM.
--- 378,387 ----
*** 450,460 ****
**/
s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 *phy_data)
{
if (hw->phy.id == 0)
! (void) ixgbe_identify_phy(hw);
return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
}
--- 454,464 ----
**/
s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 *phy_data)
{
if (hw->phy.id == 0)
! ixgbe_identify_phy(hw);
return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
}
*** 468,478 ****
**/
s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 phy_data)
{
if (hw->phy.id == 0)
! (void) ixgbe_identify_phy(hw);
return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
}
--- 472,482 ----
**/
s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
u16 phy_data)
{
if (hw->phy.id == 0)
! ixgbe_identify_phy(hw);
return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
}
*** 682,691 ****
--- 686,714 ----
return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),
IXGBE_NOT_IMPLEMENTED);
}
/**
+ * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM
+ * @hw: pointer to hardware structure
+ * @offset: offset within the EEPROM to be written to
+ * @data: 16 bit word(s) to be written to the EEPROM
+ * @words: number of words
+ *
+ * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not
+ * called after this function, the EEPROM will most likely contain an
+ * invalid checksum.
+ **/
+ s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,
+ u16 *data)
+ {
+ return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer,
+ (hw, offset, words, data),
+ IXGBE_NOT_IMPLEMENTED);
+ }
+
+ /**
* ixgbe_read_eeprom - Read word from EEPROM
* @hw: pointer to hardware structure
* @offset: offset within the EEPROM to be read
* @data: read 16 bit value from EEPROM
*
*** 696,705 ****
--- 719,745 ----
return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),
IXGBE_NOT_IMPLEMENTED);
}
/**
+ * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM
+ * @hw: pointer to hardware structure
+ * @offset: offset within the EEPROM to be read
+ * @data: read 16 bit word(s) from EEPROM
+ * @words: number of words
+ *
+ * Reads 16 bit word(s) from EEPROM
+ **/
+ s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
+ u16 words, u16 *data)
+ {
+ return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer,
+ (hw, offset, words, data),
+ IXGBE_NOT_IMPLEMENTED);
+ }
+
+ /**
* ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
* @hw: pointer to hardware structure
* @checksum_val: calculated checksum
*
* Performs checksum calculation and validates the EEPROM checksum
*** 774,786 ****
--- 814,838 ----
**/
s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
{
return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
IXGBE_NOT_IMPLEMENTED);
+
}
/**
+ * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
+ * @hw: pointer to hardware structure
+ * @vmdq: VMDq default pool index
+ **/
+ s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)
+ {
+ return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,
+ (hw, vmdq), IXGBE_NOT_IMPLEMENTED);
+ }
+
+ /**
* ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
* @hw: pointer to hardware structure
* @rar: receive address register index to disassociate with VMDq index
* @vmdq: VMDq set or pool index
**/
*** 843,856 ****
* address registers and the multicast table. Uses unused receive address
* registers for the first multicast addresses, and hashes the rest into the
* multicast table.
**/
s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
! u32 mc_addr_count, ixgbe_mc_addr_itr func)
{
return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
! mc_addr_list, mc_addr_count, func),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_enable_mc - Enable multicast address in RAR
--- 895,909 ----
* address registers and the multicast table. Uses unused receive address
* registers for the first multicast addresses, and hashes the rest into the
* multicast table.
**/
s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
! u32 mc_addr_count, ixgbe_mc_addr_itr func,
! bool clear)
{
return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
! mc_addr_list, mc_addr_count, func, clear),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_enable_mc - Enable multicast address in RAR
*** 902,924 ****
return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
vlan_on), IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_fc_enable - Enable flow control
* @hw: pointer to hardware structure
- * @packetbuf_num: packet buffer number (0-7)
*
* Configures the flow control settings based on SW configuration.
**/
! s32 ixgbe_fc_enable(struct ixgbe_hw *hw, s32 packetbuf_num)
{
! return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw, packetbuf_num),
IXGBE_NOT_IMPLEMENTED);
}
/**
* ixgbe_read_analog_reg8 - Reads 8 bit analog register
* @hw: pointer to hardware structure
* @reg: analog register to read
* @val: read value
*
--- 955,1010 ----
return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
vlan_on), IXGBE_NOT_IMPLEMENTED);
}
/**
+ * ixgbe_set_vlvf - Set VLAN Pool Filter
+ * @hw: pointer to hardware structure
+ * @vlan: VLAN id to write to VLAN filter
+ * @vind: VMDq output index that maps queue to VLAN id in VFVFB
+ * @vlan_on: boolean flag to turn on/off VLAN in VFVF
+ * @vfta_changed: pointer to boolean flag which indicates whether VFTA
+ * should be changed
+ *
+ * Turn on/off specified bit in VLVF table.
+ **/
+ s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
+ bool *vfta_changed)
+ {
+ return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
+ vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);
+ }
+
+ /**
* ixgbe_fc_enable - Enable flow control
* @hw: pointer to hardware structure
*
* Configures the flow control settings based on SW configuration.
**/
! s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
{
! return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
IXGBE_NOT_IMPLEMENTED);
}
/**
+ * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
+ * @hw: pointer to hardware structure
+ * @maj: driver major number to be sent to firmware
+ * @min: driver minor number to be sent to firmware
+ * @build: driver build number to be sent to firmware
+ * @ver: driver version number to be sent to firmware
+ **/
+ s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
+ u8 ver)
+ {
+ return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
+ build, ver), IXGBE_NOT_IMPLEMENTED);
+ }
+
+
+ /**
* ixgbe_read_analog_reg8 - Reads 8 bit analog register
* @hw: pointer to hardware structure
* @reg: analog register to read
* @val: read value
*
*** 1030,1040 ****
return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
(hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
}
/**
! * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependant on device specifics
* @hw: pointer to hardware structure
* @regval: bitfield to write to the Rx DMA register
*
* Enables the Rx DMA unit of the device.
**/
--- 1116,1126 ----
return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
(hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
}
/**
! * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
* @hw: pointer to hardware structure
* @regval: bitfield to write to the Rx DMA register
*
* Enables the Rx DMA unit of the device.
**/
*** 1042,1051 ****
--- 1128,1161 ----
{
return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
(hw, regval), IXGBE_NOT_IMPLEMENTED);
}
+ /**
+ * ixgbe_disable_sec_rx_path - Stops the receive data path
+ * @hw: pointer to hardware structure
+ *
+ * Stops the receive data path.
+ **/
+ s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)
+ {
+ return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path,
+ (hw), IXGBE_NOT_IMPLEMENTED);
+ }
+
+ /**
+ * ixgbe_enable_sec_rx_path - Enables the receive data path
+ * @hw: pointer to hardware structure
+ *
+ * Enables the receive data path.
+ **/
+ s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)
+ {
+ return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,
+ (hw), IXGBE_NOT_IMPLEMENTED);
+ }
+
/**
* ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
* @hw: pointer to hardware structure
* @mask: Mask to specify which semaphore to acquire
*