1 /******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39
40 u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw);
41 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw);
42 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
43 ixgbe_link_speed *speed,
44 bool *autoneg);
45 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
46 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num);
47 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
50 ixgbe_link_speed *speed, bool *link_up,
51 bool link_up_wait_to_complete);
52 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
53 ixgbe_link_speed speed,
54 bool autoneg,
55 bool autoneg_wait_to_complete);
56 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
58 bool autoneg,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
61 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw);
62 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw);
63 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
64 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
65 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan,
66 u32 vind, bool vlan_on);
67 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
68 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);
69 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);
70 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
71 u8 *eeprom_data);
72 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw);
73 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw);
74 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw);
75 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw);
76
77 /**
78 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
79 * @hw: pointer to the HW structure
80 *
81 * The defaults for 82598 should be in the range of 50us to 50ms,
82 * however the hardware default for these parts is 500us to 1ms which is less
83 * than the 10ms recommended by the pci-e spec. To address this we need to
84 * increase the value to either 10ms to 250ms for capability version 1 config,
85 * or 16ms to 55ms for version 2.
86 **/
87 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
88 {
89 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
90 u16 pcie_devctl2;
91
92 /* only take action if timeout value is defaulted to 0 */
93 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
94 goto out;
95
100 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
101 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
102 goto out;
103 }
104
105 /*
106 * for version 2 capabilities we need to write the config space
107 * directly in order to set the completion timeout value for
108 * 16ms to 55ms
109 */
110 pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
111 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
112 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
113 out:
114 /* disable completion timeout resend */
115 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
116 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
117 }
118
119 /**
120 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
121 * @hw: pointer to hardware structure
122 *
123 * Read PCIe configuration space, and get the MSI-X vector count from
124 * the capabilities table.
125 **/
126 u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
127 {
128 u32 msix_count = 18;
129
130 DEBUGFUNC("ixgbe_get_pcie_msix_count_82598");
131
132 if (hw->mac.msix_vectors_from_pcie) {
133 msix_count = IXGBE_READ_PCIE_WORD(hw,
134 IXGBE_PCIE_MSIX_82598_CAPS);
135 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
136
137 /* MSI-X count is zero-based in HW, so increment to give
138 * proper value */
139 msix_count++;
140 }
141 return msix_count;
142 }
143
144 /**
145 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
146 * @hw: pointer to hardware structure
147 *
148 * Initialize the function pointers and assign the MAC type for 82598.
149 * Does not touch the hardware.
150 **/
151 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
152 {
153 struct ixgbe_mac_info *mac = &hw->mac;
154 struct ixgbe_phy_info *phy = &hw->phy;
155 s32 ret_val;
156
157 DEBUGFUNC("ixgbe_init_ops_82598");
158
159 ret_val = ixgbe_init_phy_ops_generic(hw);
160 ret_val = ixgbe_init_ops_generic(hw);
161
162 /* PHY */
163 phy->ops.init = &ixgbe_init_phy_ops_82598;
164
165 /* MAC */
166 mac->ops.start_hw = &ixgbe_start_hw_82598;
167 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82598;
168 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
169 mac->ops.get_media_type = &ixgbe_get_media_type_82598;
170 mac->ops.get_supported_physical_layer =
171 &ixgbe_get_supported_physical_layer_82598;
172 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
173 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
174 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
175
176 /* RAR, Multicast, VLAN */
177 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
178 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
179 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
180 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
181
182 /* Flow Control */
183 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
184
185 mac->mcft_size = 128;
186 mac->vft_size = 128;
187 mac->num_rar_entries = 16;
188 mac->rx_pb_size = 512;
189 mac->max_tx_queues = 32;
190 mac->max_rx_queues = 64;
191 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
192
193 /* SFP+ Module */
194 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
195
196 /* Link */
197 mac->ops.check_link = &ixgbe_check_mac_link_82598;
198 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
199 mac->ops.flap_tx_laser = NULL;
200 mac->ops.get_link_capabilities =
201 &ixgbe_get_link_capabilities_82598;
202
203 return ret_val;
204 }
205
206 /**
207 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
208 * @hw: pointer to hardware structure
209 *
210 * Initialize any function pointers that were not able to be
211 * set during init_shared_code because the PHY/SFP type was
212 * not known. Perform the SFP init if necessary.
213 *
214 **/
215 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
216 {
217 struct ixgbe_mac_info *mac = &hw->mac;
218 struct ixgbe_phy_info *phy = &hw->phy;
219 s32 ret_val = IXGBE_SUCCESS;
220 u16 list_offset, data_offset;
221
222 DEBUGFUNC("ixgbe_init_phy_ops_82598");
223
224 /* Identify the PHY */
225 phy->ops.identify(hw);
226
227 /* Overwrite the link function pointers if copper PHY */
228 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
229 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
230 mac->ops.get_link_capabilities =
231 &ixgbe_get_copper_link_capabilities_generic;
232 }
233
234 switch (hw->phy.type) {
235 case ixgbe_phy_tn:
236 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
237 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
238 phy->ops.get_firmware_version =
239 &ixgbe_get_phy_firmware_version_tnx;
240 break;
241 case ixgbe_phy_aq:
242 phy->ops.get_firmware_version =
243 &ixgbe_get_phy_firmware_version_generic;
244 break;
245 case ixgbe_phy_nl:
246 phy->ops.reset = &ixgbe_reset_phy_nl;
247
248 /* Call SFP+ identify routine to get the SFP+ module type */
249 ret_val = phy->ops.identify_sfp(hw);
250 if (ret_val != IXGBE_SUCCESS)
251 goto out;
252 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
253 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
254 goto out;
255 }
256
257 /* Check to see if SFP+ module is supported */
258 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
259 &list_offset,
260 &data_offset);
261 if (ret_val != IXGBE_SUCCESS) {
262 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
263 goto out;
264 }
276 * @hw: pointer to hardware structure
277 *
278 * Starts the hardware using the generic start_hw function.
279 * Disables relaxed ordering Then set pcie completion timeout
280 *
281 **/
282 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
283 {
284 u32 regval;
285 u32 i;
286 s32 ret_val = IXGBE_SUCCESS;
287
288 DEBUGFUNC("ixgbe_start_hw_82598");
289
290 ret_val = ixgbe_start_hw_generic(hw);
291
292 /* Disable relaxed ordering */
293 for (i = 0; ((i < hw->mac.max_tx_queues) &&
294 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
295 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
296 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
297 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
298 }
299
300 for (i = 0; ((i < hw->mac.max_rx_queues) &&
301 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
302 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
303 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
304 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
305 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
306 }
307
308 /* set the completion timeout for interface */
309 if (ret_val == IXGBE_SUCCESS)
310 ixgbe_set_pcie_completion_timeout(hw);
311
312 return ret_val;
313 }
314
315 /**
316 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
317 * @hw: pointer to hardware structure
318 * @speed: pointer to link speed
319 * @autoneg: boolean auto-negotiation value
320 *
321 * Determines the link capabilities by reading the AUTOC register.
322 **/
323 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
324 ixgbe_link_speed *speed,
372
373 return status;
374 }
375
376 /**
377 * ixgbe_get_media_type_82598 - Determines media type
378 * @hw: pointer to hardware structure
379 *
380 * Returns the media type (fiber, copper, backplane)
381 **/
382 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
383 {
384 enum ixgbe_media_type media_type;
385
386 DEBUGFUNC("ixgbe_get_media_type_82598");
387
388 /* Detect if there is a copper PHY attached. */
389 switch (hw->phy.type) {
390 case ixgbe_phy_cu_unknown:
391 case ixgbe_phy_tn:
392 case ixgbe_phy_aq:
393 media_type = ixgbe_media_type_copper;
394 goto out;
395 default:
396 break;
397 }
398
399 /* Media type for I82598 is based on device ID */
400 switch (hw->device_id) {
401 case IXGBE_DEV_ID_82598:
402 case IXGBE_DEV_ID_82598_BX:
403 /* Default device ID is mezzanine card KX/KX4 */
404 media_type = ixgbe_media_type_backplane;
405 break;
406 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
407 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
408 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
409 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
410 case IXGBE_DEV_ID_82598EB_XF_LR:
411 case IXGBE_DEV_ID_82598EB_SFP_LOM:
412 media_type = ixgbe_media_type_fiber;
413 break;
414 case IXGBE_DEV_ID_82598EB_CX4:
415 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
416 media_type = ixgbe_media_type_cx4;
417 break;
418 case IXGBE_DEV_ID_82598AT:
419 case IXGBE_DEV_ID_82598AT2:
420 media_type = ixgbe_media_type_copper;
421 break;
422 default:
423 media_type = ixgbe_media_type_unknown;
424 break;
425 }
426 out:
427 return media_type;
428 }
429
430 /**
431 * ixgbe_fc_enable_82598 - Enable flow control
432 * @hw: pointer to hardware structure
433 * @packetbuf_num: packet buffer number (0-7)
434 *
435 * Enable flow control according to the current settings.
436 **/
437 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
438 {
439 s32 ret_val = IXGBE_SUCCESS;
440 u32 fctrl_reg;
441 u32 rmcs_reg;
442 u32 reg;
443 u32 rx_pba_size;
444 u32 link_speed = 0;
445 bool link_up;
446
447 DEBUGFUNC("ixgbe_fc_enable_82598");
448
449 /*
450 * On 82598 having Rx FC on causes resets while doing 1G
451 * so if it's on turn it off once we know link_speed. For
452 * more details see 82598 Specification update.
453 */
454 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
455 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
456 switch (hw->fc.requested_mode) {
457 case ixgbe_fc_full:
458 hw->fc.requested_mode = ixgbe_fc_tx_pause;
459 break;
460 case ixgbe_fc_rx_pause:
461 hw->fc.requested_mode = ixgbe_fc_none;
462 break;
463 default:
464 /* no change */
465 break;
466 }
467 }
468
469 /* Negotiate the fc mode to use */
470 ret_val = ixgbe_fc_autoneg(hw);
471 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
472 goto out;
473
474 /* Disable any previous flow control settings */
475 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
476 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
477
478 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
479 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
480
481 /*
482 * The possible values of fc.current_mode are:
483 * 0: Flow control is completely disabled
484 * 1: Rx flow control is enabled (we can receive pause frames,
485 * but not send pause frames).
486 * 2: Tx flow control is enabled (we can send pause frames but
487 * we do not support receiving pause frames).
488 * 3: Both Rx and Tx flow control (symmetric) are enabled.
489 * other: Invalid.
490 */
491 switch (hw->fc.current_mode) {
492 case ixgbe_fc_none:
513 */
514 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
515 break;
516 case ixgbe_fc_full:
517 /* Flow control (both Rx and Tx) is enabled by SW override. */
518 fctrl_reg |= IXGBE_FCTRL_RFCE;
519 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
520 break;
521 default:
522 DEBUGOUT("Flow control param set incorrectly\n");
523 ret_val = IXGBE_ERR_CONFIG;
524 goto out;
525 }
526
527 /* Set 802.3x based flow control settings. */
528 fctrl_reg |= IXGBE_FCTRL_DPF;
529 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
530 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
531
532 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
533 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
534 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
535 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
536
537 reg = (rx_pba_size - hw->fc.low_water) << 6;
538 if (hw->fc.send_xon)
539 reg |= IXGBE_FCRTL_XONE;
540
541 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
542
543 reg = (rx_pba_size - hw->fc.high_water) << 6;
544 reg |= IXGBE_FCRTH_FCEN;
545
546 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
547 }
548
549 /* Configure pause time (2 TCs per register) */
550 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
551 if ((packetbuf_num & 1) == 0)
552 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
553 else
554 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
555 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
556
557 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
558
559 out:
560 return ret_val;
561 }
562
563 /**
564 * ixgbe_start_mac_link_82598 - Configures MAC link settings
565 * @hw: pointer to hardware structure
566 *
567 * Configures link settings based on values in the ixgbe_hw struct.
568 * Restarts the link. Performs autonegotiation if needed.
569 **/
570 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
571 bool autoneg_wait_to_complete)
572 {
573 u32 autoc_reg;
574 u32 links_reg;
575 u32 i;
576 s32 status = IXGBE_SUCCESS;
577
712 }
713 msec_delay(100);
714 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
715 }
716 } else {
717 if (links_reg & IXGBE_LINKS_UP)
718 *link_up = TRUE;
719 else
720 *link_up = FALSE;
721 }
722
723 if (links_reg & IXGBE_LINKS_SPEED)
724 *speed = IXGBE_LINK_SPEED_10GB_FULL;
725 else
726 *speed = IXGBE_LINK_SPEED_1GB_FULL;
727
728 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) &&
729 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
730 *link_up = FALSE;
731
732 /* if link is down, zero out the current_mode */
733 if (*link_up == FALSE) {
734 hw->fc.current_mode = ixgbe_fc_none;
735 hw->fc.fc_was_autonegged = FALSE;
736 }
737 out:
738 return IXGBE_SUCCESS;
739 }
740
741 /**
742 * ixgbe_setup_mac_link_82598 - Set MAC link speed
743 * @hw: pointer to hardware structure
744 * @speed: new link speed
745 * @autoneg: TRUE if autonegotiation enabled
746 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
747 *
748 * Set the link speed in the AUTOC register and restarts link.
749 **/
750 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
751 ixgbe_link_speed speed, bool autoneg,
752 bool autoneg_wait_to_complete)
753 {
754 s32 status = IXGBE_SUCCESS;
755 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
756 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
757 u32 autoc = curr_autoc;
758 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
759
760 DEBUGFUNC("ixgbe_setup_mac_link_82598");
761
762 /* Check to see if speed passed in is supported. */
763 (void) ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
764 speed &= link_capabilities;
765
766 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
767 status = IXGBE_ERR_LINK_SETUP;
768
769 /* Set KX4/KX support according to speed requested */
770 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
771 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
772 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
773 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
774 autoc |= IXGBE_AUTOC_KX4_SUPP;
775 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
776 autoc |= IXGBE_AUTOC_KX_SUPP;
777 if (autoc != curr_autoc)
778 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
779 }
780
781 if (status == IXGBE_SUCCESS) {
782 /*
783 * Setup and restart the link based on the new values in
797 * @hw: pointer to hardware structure
798 * @speed: new link speed
799 * @autoneg: TRUE if autonegotiation enabled
800 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
801 *
802 * Sets the link speed in the AUTOC register in the MAC and restarts link.
803 **/
804 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
805 ixgbe_link_speed speed,
806 bool autoneg,
807 bool autoneg_wait_to_complete)
808 {
809 s32 status;
810
811 DEBUGFUNC("ixgbe_setup_copper_link_82598");
812
813 /* Setup the PHY according to input speed */
814 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
815 autoneg_wait_to_complete);
816 /* Set up MAC */
817 (void) ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
818
819 return status;
820 }
821
822 /**
823 * ixgbe_reset_hw_82598 - Performs hardware reset
824 * @hw: pointer to hardware structure
825 *
826 * Resets the hardware by resetting the transmit and receive units, masks and
827 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
828 * reset.
829 **/
830 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
831 {
832 s32 status = IXGBE_SUCCESS;
833 s32 phy_status = IXGBE_SUCCESS;
834 u32 ctrl;
835 u32 gheccr;
836 u32 i;
837 u32 autoc;
838 u8 analog_val;
839
840 DEBUGFUNC("ixgbe_reset_hw_82598");
841
842 /* Call adapter stop to disable tx/rx and clear interrupts */
843 hw->mac.ops.stop_adapter(hw);
844
845 /*
846 * Power up the Atlas Tx lanes if they are currently powered down.
847 * Atlas Tx lanes are powered down for MAC loopback tests, but
848 * they are not automatically restored on reset.
849 */
850 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
851 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
852 /* Enable Tx Atlas so packets can be transmitted again */
853 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
854 &analog_val);
855 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
856 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
857 analog_val);
858
859 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
860 &analog_val);
861 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
862 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
863 analog_val);
866 &analog_val);
867 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
868 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
869 analog_val);
870
871 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
872 &analog_val);
873 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
874 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
875 analog_val);
876 }
877
878 /* Reset PHY */
879 if (hw->phy.reset_disable == FALSE) {
880 /* PHY ops must be identified and initialized prior to reset */
881
882 /* Init PHY and function pointers, perform SFP setup */
883 phy_status = hw->phy.ops.init(hw);
884 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
885 goto reset_hw_out;
886 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
887 goto no_phy_reset;
888
889 hw->phy.ops.reset(hw);
890 }
891
892 no_phy_reset:
893 /*
894 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
895 * access and verify no pending requests before reset
896 */
897 (void) ixgbe_disable_pcie_master(hw);
898
899 mac_reset_top:
900 /*
901 * Issue global reset to the MAC. This needs to be a SW reset.
902 * If link reset is used, it might reset the MAC when mng is using it
903 */
904 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
905 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
906 IXGBE_WRITE_FLUSH(hw);
907
908 /* Poll for reset bit to self-clear indicating reset is complete */
909 for (i = 0; i < 10; i++) {
910 usec_delay(1);
911 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
912 if (!(ctrl & IXGBE_CTRL_RST))
913 break;
914 }
915 if (ctrl & IXGBE_CTRL_RST) {
916 status = IXGBE_ERR_RESET_FAILED;
917 DEBUGOUT("Reset polling failed to complete.\n");
918 }
919
920 /*
921 * Double resets are required for recovery from certain error
922 * conditions. Between resets, it is necessary to stall to allow time
923 * for any pending HW events to complete. We use 1usec since that is
924 * what is needed for ixgbe_disable_pcie_master(). The second reset
925 * then clears out any effects of those events.
926 */
927 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
928 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
929 usec_delay(1);
930 goto mac_reset_top;
931 }
932
933 msec_delay(50);
934
935 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
936 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
937 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
938
939 /*
940 * Store the original AUTOC value if it has not been
941 * stored off yet. Otherwise restore the stored original
942 * AUTOC value since the reset operation sets back to deaults.
943 */
944 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
945 if (hw->mac.orig_link_settings_stored == FALSE) {
946 hw->mac.orig_autoc = autoc;
947 hw->mac.orig_link_settings_stored = TRUE;
948 } else if (autoc != hw->mac.orig_autoc) {
949 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
950 }
951
952 /* Store the permanent mac address */
953 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
954
985 }
986
987 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
988 rar_high &= ~IXGBE_RAH_VIND_MASK;
989 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
990 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
991 return IXGBE_SUCCESS;
992 }
993
994 /**
995 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
996 * @hw: pointer to hardware struct
997 * @rar: receive address register index to associate with a VMDq index
998 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
999 **/
1000 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
1001 {
1002 u32 rar_high;
1003 u32 rar_entries = hw->mac.num_rar_entries;
1004
1005 UNREFERENCED_PARAMETER(vmdq);
1006
1007 /* Make sure we are using a valid rar index range */
1008 if (rar >= rar_entries) {
1009 DEBUGOUT1("RAR index %d is out of range.\n", rar);
1010 return IXGBE_ERR_INVALID_ARGUMENT;
1011 }
1012
1013 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
1014 if (rar_high & IXGBE_RAH_VIND_MASK) {
1015 rar_high &= ~IXGBE_RAH_VIND_MASK;
1016 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
1017 }
1018
1019 return IXGBE_SUCCESS;
1020 }
1021
1022 /**
1023 * ixgbe_set_vfta_82598 - Set VLAN filter table
1024 * @hw: pointer to hardware structure
1025 * @vlan: VLAN id to write to VLAN filter
1208 * @hw: pointer to hardware structure
1209 *
1210 * Determines physical layer capabilities of the current configuration.
1211 **/
1212 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1213 {
1214 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1215 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1216 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1217 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1218 u16 ext_ability = 0;
1219
1220 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1221
1222 hw->phy.ops.identify(hw);
1223
1224 /* Copper PHY must be checked before AUTOC LMS to determine correct
1225 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1226 switch (hw->phy.type) {
1227 case ixgbe_phy_tn:
1228 case ixgbe_phy_aq:
1229 case ixgbe_phy_cu_unknown:
1230 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1231 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1232 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1233 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1234 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1235 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1236 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1237 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1238 goto out;
1239 default:
1240 break;
1241 }
1242
1243 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1244 case IXGBE_AUTOC_LMS_1G_AN:
1245 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1246 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1247 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1248 else
1339 }
1340 }
1341 }
1342
1343 /**
1344 * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering
1345 * @hw: pointer to hardware structure
1346 *
1347 **/
1348 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
1349 {
1350 u32 regval;
1351 u32 i;
1352
1353 DEBUGFUNC("ixgbe_enable_relaxed_ordering_82598");
1354
1355 /* Enable relaxed ordering */
1356 for (i = 0; ((i < hw->mac.max_tx_queues) &&
1357 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1358 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1359 regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1360 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
1361 }
1362
1363 for (i = 0; ((i < hw->mac.max_rx_queues) &&
1364 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1365 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
1366 regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
1367 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
1368 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
1369 }
1370
1371 }
|
1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82598.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_type.h"
36 #include "ixgbe_82598.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
40
41 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
43 bool *autoneg);
44 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
45 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
46 bool autoneg_wait_to_complete);
47 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
48 ixgbe_link_speed *speed, bool *link_up,
49 bool link_up_wait_to_complete);
50 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
52 bool autoneg,
53 bool autoneg_wait_to_complete);
54 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg,
57 bool autoneg_wait_to_complete);
58 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
59 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
60 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
61 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
62 u32 headroom, int strategy);
63
64 /**
65 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
66 * @hw: pointer to the HW structure
67 *
68 * The defaults for 82598 should be in the range of 50us to 50ms,
69 * however the hardware default for these parts is 500us to 1ms which is less
70 * than the 10ms recommended by the pci-e spec. To address this we need to
71 * increase the value to either 10ms to 250ms for capability version 1 config,
72 * or 16ms to 55ms for version 2.
73 **/
74 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
75 {
76 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
77 u16 pcie_devctl2;
78
79 /* only take action if timeout value is defaulted to 0 */
80 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
81 goto out;
82
87 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
88 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
89 goto out;
90 }
91
92 /*
93 * for version 2 capabilities we need to write the config space
94 * directly in order to set the completion timeout value for
95 * 16ms to 55ms
96 */
97 pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
98 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
99 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
100 out:
101 /* disable completion timeout resend */
102 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
103 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
104 }
105
106 /**
107 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
108 * @hw: pointer to hardware structure
109 *
110 * Initialize the function pointers and assign the MAC type for 82598.
111 * Does not touch the hardware.
112 **/
113 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
114 {
115 struct ixgbe_mac_info *mac = &hw->mac;
116 struct ixgbe_phy_info *phy = &hw->phy;
117 s32 ret_val;
118
119 DEBUGFUNC("ixgbe_init_ops_82598");
120
121 ret_val = ixgbe_init_phy_ops_generic(hw);
122 ret_val = ixgbe_init_ops_generic(hw);
123
124 /* PHY */
125 phy->ops.init = &ixgbe_init_phy_ops_82598;
126
127 /* MAC */
128 mac->ops.start_hw = &ixgbe_start_hw_82598;
129 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82598;
130 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
131 mac->ops.get_media_type = &ixgbe_get_media_type_82598;
132 mac->ops.get_supported_physical_layer =
133 &ixgbe_get_supported_physical_layer_82598;
134 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
135 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
136 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
137
138 /* RAR, Multicast, VLAN */
139 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
140 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
141 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
142 mac->ops.set_vlvf = NULL;
143 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
144
145 /* Flow Control */
146 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
147
148 mac->mcft_size = 128;
149 mac->vft_size = 128;
150 mac->num_rar_entries = 16;
151 mac->rx_pb_size = 512;
152 mac->max_tx_queues = 32;
153 mac->max_rx_queues = 64;
154 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
155
156 /* SFP+ Module */
157 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
158
159 /* Link */
160 mac->ops.check_link = &ixgbe_check_mac_link_82598;
161 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
162 mac->ops.flap_tx_laser = NULL;
163 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;
164 mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;
165
166 /* Manageability interface */
167 mac->ops.set_fw_drv_ver = NULL;
168
169 return ret_val;
170 }
171
172 /**
173 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
174 * @hw: pointer to hardware structure
175 *
176 * Initialize any function pointers that were not able to be
177 * set during init_shared_code because the PHY/SFP type was
178 * not known. Perform the SFP init if necessary.
179 *
180 **/
181 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
182 {
183 struct ixgbe_mac_info *mac = &hw->mac;
184 struct ixgbe_phy_info *phy = &hw->phy;
185 s32 ret_val = IXGBE_SUCCESS;
186 u16 list_offset, data_offset;
187
188 DEBUGFUNC("ixgbe_init_phy_ops_82598");
189
190 /* Identify the PHY */
191 phy->ops.identify(hw);
192
193 /* Overwrite the link function pointers if copper PHY */
194 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
195 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
196 mac->ops.get_link_capabilities =
197 &ixgbe_get_copper_link_capabilities_generic;
198 }
199
200 switch (hw->phy.type) {
201 case ixgbe_phy_tn:
202 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
203 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
204 phy->ops.get_firmware_version =
205 &ixgbe_get_phy_firmware_version_tnx;
206 break;
207 case ixgbe_phy_nl:
208 phy->ops.reset = &ixgbe_reset_phy_nl;
209
210 /* Call SFP+ identify routine to get the SFP+ module type */
211 ret_val = phy->ops.identify_sfp(hw);
212 if (ret_val != IXGBE_SUCCESS)
213 goto out;
214 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
215 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
216 goto out;
217 }
218
219 /* Check to see if SFP+ module is supported */
220 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
221 &list_offset,
222 &data_offset);
223 if (ret_val != IXGBE_SUCCESS) {
224 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
225 goto out;
226 }
238 * @hw: pointer to hardware structure
239 *
240 * Starts the hardware using the generic start_hw function.
241 * Disables relaxed ordering Then set pcie completion timeout
242 *
243 **/
244 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
245 {
246 u32 regval;
247 u32 i;
248 s32 ret_val = IXGBE_SUCCESS;
249
250 DEBUGFUNC("ixgbe_start_hw_82598");
251
252 ret_val = ixgbe_start_hw_generic(hw);
253
254 /* Disable relaxed ordering */
255 for (i = 0; ((i < hw->mac.max_tx_queues) &&
256 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
257 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
258 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
259 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
260 }
261
262 for (i = 0; ((i < hw->mac.max_rx_queues) &&
263 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
264 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
265 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
266 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
267 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
268 }
269
270 /* set the completion timeout for interface */
271 if (ret_val == IXGBE_SUCCESS)
272 ixgbe_set_pcie_completion_timeout(hw);
273
274 return ret_val;
275 }
276
277 /**
278 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
279 * @hw: pointer to hardware structure
280 * @speed: pointer to link speed
281 * @autoneg: boolean auto-negotiation value
282 *
283 * Determines the link capabilities by reading the AUTOC register.
284 **/
285 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
286 ixgbe_link_speed *speed,
334
335 return status;
336 }
337
338 /**
339 * ixgbe_get_media_type_82598 - Determines media type
340 * @hw: pointer to hardware structure
341 *
342 * Returns the media type (fiber, copper, backplane)
343 **/
344 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
345 {
346 enum ixgbe_media_type media_type;
347
348 DEBUGFUNC("ixgbe_get_media_type_82598");
349
350 /* Detect if there is a copper PHY attached. */
351 switch (hw->phy.type) {
352 case ixgbe_phy_cu_unknown:
353 case ixgbe_phy_tn:
354 media_type = ixgbe_media_type_copper;
355 goto out;
356 default:
357 break;
358 }
359
360 /* Media type for I82598 is based on device ID */
361 switch (hw->device_id) {
362 case IXGBE_DEV_ID_82598:
363 case IXGBE_DEV_ID_82598_BX:
364 /* Default device ID is mezzanine card KX/KX4 */
365 media_type = ixgbe_media_type_backplane;
366 break;
367 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
368 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
369 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
370 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
371 case IXGBE_DEV_ID_82598EB_XF_LR:
372 case IXGBE_DEV_ID_82598EB_SFP_LOM:
373 media_type = ixgbe_media_type_fiber;
374 break;
375 case IXGBE_DEV_ID_82598EB_CX4:
376 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
377 media_type = ixgbe_media_type_cx4;
378 break;
379 case IXGBE_DEV_ID_82598AT:
380 case IXGBE_DEV_ID_82598AT2:
381 media_type = ixgbe_media_type_copper;
382 break;
383 default:
384 media_type = ixgbe_media_type_unknown;
385 break;
386 }
387 out:
388 return media_type;
389 }
390
391 /**
392 * ixgbe_fc_enable_82598 - Enable flow control
393 * @hw: pointer to hardware structure
394 *
395 * Enable flow control according to the current settings.
396 **/
397 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
398 {
399 s32 ret_val = IXGBE_SUCCESS;
400 u32 fctrl_reg;
401 u32 rmcs_reg;
402 u32 reg;
403 u32 fcrtl, fcrth;
404 u32 link_speed = 0;
405 int i;
406 bool link_up;
407
408 DEBUGFUNC("ixgbe_fc_enable_82598");
409
410 /* Validate the water mark configuration */
411 if (!hw->fc.pause_time) {
412 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
413 goto out;
414 }
415
416 /* Low water mark of zero causes XOFF floods */
417 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
418 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
419 hw->fc.high_water[i]) {
420 if (!hw->fc.low_water[i] ||
421 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
422 DEBUGOUT("Invalid water mark configuration\n");
423 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
424 goto out;
425 }
426 }
427 }
428
429 /*
430 * On 82598 having Rx FC on causes resets while doing 1G
431 * so if it's on turn it off once we know link_speed. For
432 * more details see 82598 Specification update.
433 */
434 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
435 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
436 switch (hw->fc.requested_mode) {
437 case ixgbe_fc_full:
438 hw->fc.requested_mode = ixgbe_fc_tx_pause;
439 break;
440 case ixgbe_fc_rx_pause:
441 hw->fc.requested_mode = ixgbe_fc_none;
442 break;
443 default:
444 /* no change */
445 break;
446 }
447 }
448
449 /* Negotiate the fc mode to use */
450 ixgbe_fc_autoneg(hw);
451
452 /* Disable any previous flow control settings */
453 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
454 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
455
456 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
457 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
458
459 /*
460 * The possible values of fc.current_mode are:
461 * 0: Flow control is completely disabled
462 * 1: Rx flow control is enabled (we can receive pause frames,
463 * but not send pause frames).
464 * 2: Tx flow control is enabled (we can send pause frames but
465 * we do not support receiving pause frames).
466 * 3: Both Rx and Tx flow control (symmetric) are enabled.
467 * other: Invalid.
468 */
469 switch (hw->fc.current_mode) {
470 case ixgbe_fc_none:
491 */
492 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
493 break;
494 case ixgbe_fc_full:
495 /* Flow control (both Rx and Tx) is enabled by SW override. */
496 fctrl_reg |= IXGBE_FCTRL_RFCE;
497 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
498 break;
499 default:
500 DEBUGOUT("Flow control param set incorrectly\n");
501 ret_val = IXGBE_ERR_CONFIG;
502 goto out;
503 }
504
505 /* Set 802.3x based flow control settings. */
506 fctrl_reg |= IXGBE_FCTRL_DPF;
507 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
508 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
509
510 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
511 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
512 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
513 hw->fc.high_water[i]) {
514 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
515 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
516 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
517 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
518 } else {
519 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
520 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
521 }
522
523 }
524
525 /* Configure pause time (2 TCs per register) */
526 reg = hw->fc.pause_time * 0x00010001;
527 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
528 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
529
530 /* Configure flow control refresh threshold value */
531 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
532
533 out:
534 return ret_val;
535 }
536
537 /**
538 * ixgbe_start_mac_link_82598 - Configures MAC link settings
539 * @hw: pointer to hardware structure
540 *
541 * Configures link settings based on values in the ixgbe_hw struct.
542 * Restarts the link. Performs autonegotiation if needed.
543 **/
544 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
545 bool autoneg_wait_to_complete)
546 {
547 u32 autoc_reg;
548 u32 links_reg;
549 u32 i;
550 s32 status = IXGBE_SUCCESS;
551
686 }
687 msec_delay(100);
688 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
689 }
690 } else {
691 if (links_reg & IXGBE_LINKS_UP)
692 *link_up = TRUE;
693 else
694 *link_up = FALSE;
695 }
696
697 if (links_reg & IXGBE_LINKS_SPEED)
698 *speed = IXGBE_LINK_SPEED_10GB_FULL;
699 else
700 *speed = IXGBE_LINK_SPEED_1GB_FULL;
701
702 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == TRUE) &&
703 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
704 *link_up = FALSE;
705
706 out:
707 return IXGBE_SUCCESS;
708 }
709
710 /**
711 * ixgbe_setup_mac_link_82598 - Set MAC link speed
712 * @hw: pointer to hardware structure
713 * @speed: new link speed
714 * @autoneg: TRUE if autonegotiation enabled
715 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
716 *
717 * Set the link speed in the AUTOC register and restarts link.
718 **/
719 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
720 ixgbe_link_speed speed, bool autoneg,
721 bool autoneg_wait_to_complete)
722 {
723 s32 status = IXGBE_SUCCESS;
724 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
725 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
726 u32 autoc = curr_autoc;
727 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
728
729 DEBUGFUNC("ixgbe_setup_mac_link_82598");
730
731 /* Check to see if speed passed in is supported. */
732 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
733 speed &= link_capabilities;
734
735 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
736 status = IXGBE_ERR_LINK_SETUP;
737
738 /* Set KX4/KX support according to speed requested */
739 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
740 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
741 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
742 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
743 autoc |= IXGBE_AUTOC_KX4_SUPP;
744 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
745 autoc |= IXGBE_AUTOC_KX_SUPP;
746 if (autoc != curr_autoc)
747 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
748 }
749
750 if (status == IXGBE_SUCCESS) {
751 /*
752 * Setup and restart the link based on the new values in
766 * @hw: pointer to hardware structure
767 * @speed: new link speed
768 * @autoneg: TRUE if autonegotiation enabled
769 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
770 *
771 * Sets the link speed in the AUTOC register in the MAC and restarts link.
772 **/
773 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
774 ixgbe_link_speed speed,
775 bool autoneg,
776 bool autoneg_wait_to_complete)
777 {
778 s32 status;
779
780 DEBUGFUNC("ixgbe_setup_copper_link_82598");
781
782 /* Setup the PHY according to input speed */
783 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
784 autoneg_wait_to_complete);
785 /* Set up MAC */
786 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
787
788 return status;
789 }
790
791 /**
792 * ixgbe_reset_hw_82598 - Performs hardware reset
793 * @hw: pointer to hardware structure
794 *
795 * Resets the hardware by resetting the transmit and receive units, masks and
796 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
797 * reset.
798 **/
799 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
800 {
801 s32 status = IXGBE_SUCCESS;
802 s32 phy_status = IXGBE_SUCCESS;
803 u32 ctrl;
804 u32 gheccr;
805 u32 i;
806 u32 autoc;
807 u8 analog_val;
808
809 DEBUGFUNC("ixgbe_reset_hw_82598");
810
811 /* Call adapter stop to disable tx/rx and clear interrupts */
812 status = hw->mac.ops.stop_adapter(hw);
813 if (status != IXGBE_SUCCESS)
814 goto reset_hw_out;
815
816 /*
817 * Power up the Atlas Tx lanes if they are currently powered down.
818 * Atlas Tx lanes are powered down for MAC loopback tests, but
819 * they are not automatically restored on reset.
820 */
821 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
822 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
823 /* Enable Tx Atlas so packets can be transmitted again */
824 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
825 &analog_val);
826 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
827 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
828 analog_val);
829
830 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
831 &analog_val);
832 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
833 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
834 analog_val);
837 &analog_val);
838 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
839 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
840 analog_val);
841
842 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
843 &analog_val);
844 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
845 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
846 analog_val);
847 }
848
849 /* Reset PHY */
850 if (hw->phy.reset_disable == FALSE) {
851 /* PHY ops must be identified and initialized prior to reset */
852
853 /* Init PHY and function pointers, perform SFP setup */
854 phy_status = hw->phy.ops.init(hw);
855 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
856 goto reset_hw_out;
857 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
858 goto mac_reset_top;
859
860 hw->phy.ops.reset(hw);
861 }
862
863 mac_reset_top:
864 /*
865 * Issue global reset to the MAC. This needs to be a SW reset.
866 * If link reset is used, it might reset the MAC when mng is using it
867 */
868 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
869 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
870 IXGBE_WRITE_FLUSH(hw);
871
872 /* Poll for reset bit to self-clear indicating reset is complete */
873 for (i = 0; i < 10; i++) {
874 usec_delay(1);
875 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
876 if (!(ctrl & IXGBE_CTRL_RST))
877 break;
878 }
879 if (ctrl & IXGBE_CTRL_RST) {
880 status = IXGBE_ERR_RESET_FAILED;
881 DEBUGOUT("Reset polling failed to complete.\n");
882 }
883
884 msec_delay(50);
885
886 /*
887 * Double resets are required for recovery from certain error
888 * conditions. Between resets, it is necessary to stall to allow time
889 * for any pending HW events to complete.
890 */
891 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
892 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
893 goto mac_reset_top;
894 }
895
896 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
897 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
898 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
899
900 /*
901 * Store the original AUTOC value if it has not been
902 * stored off yet. Otherwise restore the stored original
903 * AUTOC value since the reset operation sets back to deaults.
904 */
905 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
906 if (hw->mac.orig_link_settings_stored == FALSE) {
907 hw->mac.orig_autoc = autoc;
908 hw->mac.orig_link_settings_stored = TRUE;
909 } else if (autoc != hw->mac.orig_autoc) {
910 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
911 }
912
913 /* Store the permanent mac address */
914 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
915
946 }
947
948 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
949 rar_high &= ~IXGBE_RAH_VIND_MASK;
950 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
951 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
952 return IXGBE_SUCCESS;
953 }
954
955 /**
956 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
957 * @hw: pointer to hardware struct
958 * @rar: receive address register index to associate with a VMDq index
959 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
960 **/
961 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
962 {
963 u32 rar_high;
964 u32 rar_entries = hw->mac.num_rar_entries;
965
966 UNREFERENCED_1PARAMETER(vmdq);
967
968 /* Make sure we are using a valid rar index range */
969 if (rar >= rar_entries) {
970 DEBUGOUT1("RAR index %d is out of range.\n", rar);
971 return IXGBE_ERR_INVALID_ARGUMENT;
972 }
973
974 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
975 if (rar_high & IXGBE_RAH_VIND_MASK) {
976 rar_high &= ~IXGBE_RAH_VIND_MASK;
977 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
978 }
979
980 return IXGBE_SUCCESS;
981 }
982
983 /**
984 * ixgbe_set_vfta_82598 - Set VLAN filter table
985 * @hw: pointer to hardware structure
986 * @vlan: VLAN id to write to VLAN filter
1169 * @hw: pointer to hardware structure
1170 *
1171 * Determines physical layer capabilities of the current configuration.
1172 **/
1173 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1174 {
1175 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1176 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1177 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1178 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1179 u16 ext_ability = 0;
1180
1181 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1182
1183 hw->phy.ops.identify(hw);
1184
1185 /* Copper PHY must be checked before AUTOC LMS to determine correct
1186 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1187 switch (hw->phy.type) {
1188 case ixgbe_phy_tn:
1189 case ixgbe_phy_cu_unknown:
1190 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1191 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1192 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1193 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1194 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1195 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1196 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1197 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1198 goto out;
1199 default:
1200 break;
1201 }
1202
1203 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1204 case IXGBE_AUTOC_LMS_1G_AN:
1205 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1206 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1207 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1208 else
1299 }
1300 }
1301 }
1302
1303 /**
1304 * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering
1305 * @hw: pointer to hardware structure
1306 *
1307 **/
1308 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
1309 {
1310 u32 regval;
1311 u32 i;
1312
1313 DEBUGFUNC("ixgbe_enable_relaxed_ordering_82598");
1314
1315 /* Enable relaxed ordering */
1316 for (i = 0; ((i < hw->mac.max_tx_queues) &&
1317 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1318 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1319 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
1320 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
1321 }
1322
1323 for (i = 0; ((i < hw->mac.max_rx_queues) &&
1324 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1325 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
1326 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
1327 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
1328 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
1329 }
1330
1331 }
1332
1333 /**
1334 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1335 * @hw: pointer to hardware structure
1336 * @num_pb: number of packet buffers to allocate
1337 * @headroom: reserve n KB of headroom
1338 * @strategy: packet buffer allocation strategy
1339 **/
1340 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
1341 u32 headroom, int strategy)
1342 {
1343 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1344 u8 i = 0;
1345 UNREFERENCED_1PARAMETER(headroom);
1346
1347 if (!num_pb)
1348 return;
1349
1350 /* Setup Rx packet buffer sizes */
1351 switch (strategy) {
1352 case PBA_STRATEGY_WEIGHTED:
1353 /* Setup the first four at 80KB */
1354 rxpktsize = IXGBE_RXPBSIZE_80KB;
1355 for (; i < 4; i++)
1356 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1357 /* Setup the last four at 48KB...don't re-init i */
1358 rxpktsize = IXGBE_RXPBSIZE_48KB;
1359 /* Fall Through */
1360 case PBA_STRATEGY_EQUAL:
1361 default:
1362 /* Divide the remaining Rx packet buffer evenly among the TCs */
1363 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1364 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1365 break;
1366 }
1367
1368 /* Setup Tx packet buffer sizes */
1369 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1370 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1371
1372 return;
1373 }
|