Print this page
XXXX Intel X540 support
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/io/ixgbe/ixgbe_phy.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_phy.c
1 1 /******************************************************************************
2 2
3 - Copyright (c) 2001-2010, Intel Corporation
3 + Copyright (c) 2001-2012, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
↓ open down ↓ |
9 lines elided |
↑ open up ↑ |
23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 -/*$FreeBSD$*/
33 +/*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34 34
35 35 #include "ixgbe_api.h"
36 36 #include "ixgbe_common.h"
37 37 #include "ixgbe_phy.h"
38 38
39 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 -static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 +static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
50 -void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
51 50
52 51 /**
53 52 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
54 53 * @hw: pointer to the hardware structure
55 54 *
56 55 * Initialize the function pointers.
57 56 **/
58 57 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
59 58 {
60 59 struct ixgbe_phy_info *phy = &hw->phy;
61 60
62 61 DEBUGFUNC("ixgbe_init_phy_ops_generic");
63 62
64 63 /* PHY */
65 64 phy->ops.identify = &ixgbe_identify_phy_generic;
66 65 phy->ops.reset = &ixgbe_reset_phy_generic;
67 66 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
|
↓ open down ↓ |
7 lines elided |
↑ open up ↑ |
68 67 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
69 68 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
70 69 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
71 70 phy->ops.check_link = NULL;
72 71 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
73 72 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
74 73 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
75 74 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
76 75 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
77 76 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
78 - phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic;
77 + phy->ops.identify_sfp = &ixgbe_identify_module_generic;
79 78 phy->sfp_type = ixgbe_sfp_type_unknown;
80 79 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
81 80 return IXGBE_SUCCESS;
82 81 }
83 82
84 83 /**
85 84 * ixgbe_identify_phy_generic - Get physical layer module
86 85 * @hw: pointer to hardware structure
87 86 *
88 87 * Determines the physical layer module found on the current adapter.
89 88 **/
90 89 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
91 90 {
|
↓ open down ↓ |
3 lines elided |
↑ open up ↑ |
92 91 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
93 92 u32 phy_addr;
94 93 u16 ext_ability = 0;
95 94
96 95 DEBUGFUNC("ixgbe_identify_phy_generic");
97 96
98 97 if (hw->phy.type == ixgbe_phy_unknown) {
99 98 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
100 99 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
101 100 hw->phy.addr = phy_addr;
102 - (void) ixgbe_get_phy_id(hw);
101 + ixgbe_get_phy_id(hw);
103 102 hw->phy.type =
104 - ixgbe_get_phy_type_from_id(hw->phy.id);
103 + ixgbe_get_phy_type_from_id(hw->phy.id);
105 104
106 105 if (hw->phy.type == ixgbe_phy_unknown) {
107 106 hw->phy.ops.read_reg(hw,
108 107 IXGBE_MDIO_PHY_EXT_ABILITY,
109 - IXGBE_MDIO_PMA_PMD_DEV_TYPE,
110 - &ext_ability);
108 + IXGBE_MDIO_PMA_PMD_DEV_TYPE,
109 + &ext_ability);
111 110 if (ext_ability &
112 111 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
113 112 IXGBE_MDIO_PHY_1000BASET_ABILITY))
114 113 hw->phy.type =
115 - ixgbe_phy_cu_unknown;
114 + ixgbe_phy_cu_unknown;
116 115 else
117 116 hw->phy.type =
118 - ixgbe_phy_generic;
117 + ixgbe_phy_generic;
119 118 }
120 119
121 120 status = IXGBE_SUCCESS;
122 121 break;
123 122 }
124 123 }
125 124 /* clear value if nothing found */
126 125 if (status != IXGBE_SUCCESS)
127 126 hw->phy.addr = 0;
128 127 } else {
129 128 status = IXGBE_SUCCESS;
130 129 }
131 130
132 131 return status;
133 132 }
134 133
135 134 /**
136 135 * ixgbe_validate_phy_addr - Determines phy address is valid
137 136 * @hw: pointer to hardware structure
138 137 *
|
↓ open down ↓ |
10 lines elided |
↑ open up ↑ |
139 138 **/
140 139 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
141 140 {
142 141 u16 phy_id = 0;
143 142 bool valid = FALSE;
144 143
145 144 DEBUGFUNC("ixgbe_validate_phy_addr");
146 145
147 146 hw->phy.addr = phy_addr;
148 147 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
149 - IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
148 + IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
150 149
151 150 if (phy_id != 0xFFFF && phy_id != 0x0)
152 151 valid = TRUE;
153 152
154 153 return valid;
155 154 }
156 155
157 156 /**
158 157 * ixgbe_get_phy_id - Get the phy type
159 158 * @hw: pointer to hardware structure
160 159 *
|
↓ open down ↓ |
1 lines elided |
↑ open up ↑ |
161 160 **/
162 161 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
163 162 {
164 163 u32 status;
165 164 u16 phy_id_high = 0;
166 165 u16 phy_id_low = 0;
167 166
168 167 DEBUGFUNC("ixgbe_get_phy_id");
169 168
170 169 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
171 - IXGBE_MDIO_PMA_PMD_DEV_TYPE,
172 - &phy_id_high);
170 + IXGBE_MDIO_PMA_PMD_DEV_TYPE,
171 + &phy_id_high);
173 172
174 173 if (status == IXGBE_SUCCESS) {
175 174 hw->phy.id = (u32)(phy_id_high << 16);
176 175 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
177 - IXGBE_MDIO_PMA_PMD_DEV_TYPE,
178 - &phy_id_low);
176 + IXGBE_MDIO_PMA_PMD_DEV_TYPE,
177 + &phy_id_low);
179 178 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
180 179 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
181 180 }
182 181 return status;
183 182 }
184 183
185 184 /**
186 185 * ixgbe_get_phy_type_from_id - Get the phy type
187 186 * @hw: pointer to hardware structure
188 187 *
189 188 **/
|
↓ open down ↓ |
1 lines elided |
↑ open up ↑ |
190 189 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
191 190 {
192 191 enum ixgbe_phy_type phy_type;
193 192
194 193 DEBUGFUNC("ixgbe_get_phy_type_from_id");
195 194
196 195 switch (phy_id) {
197 196 case TN1010_PHY_ID:
198 197 phy_type = ixgbe_phy_tn;
199 198 break;
200 - case AQ1002_PHY_ID:
199 + case X540_PHY_ID:
201 200 phy_type = ixgbe_phy_aq;
202 201 break;
203 202 case QT2022_PHY_ID:
204 203 phy_type = ixgbe_phy_qt;
205 204 break;
206 205 case ATH_PHY_ID:
207 206 phy_type = ixgbe_phy_nl;
208 207 break;
209 208 default:
210 209 phy_type = ixgbe_phy_unknown;
211 210 break;
212 211 }
213 212
214 213 DEBUGOUT1("phy type found is %d\n", phy_type);
215 214 return phy_type;
216 215 }
217 216
218 217 /**
219 218 * ixgbe_reset_phy_generic - Performs a PHY reset
220 219 * @hw: pointer to hardware structure
221 220 **/
222 221 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
223 222 {
224 223 u32 i;
225 224 u16 ctrl = 0;
226 225 s32 status = IXGBE_SUCCESS;
227 226
228 227 DEBUGFUNC("ixgbe_reset_phy_generic");
229 228
230 229 if (hw->phy.type == ixgbe_phy_unknown)
231 230 status = ixgbe_identify_phy_generic(hw);
232 231
233 232 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
234 233 goto out;
235 234
|
↓ open down ↓ |
25 lines elided |
↑ open up ↑ |
236 235 /* Don't reset PHY if it's shut down due to overtemp. */
237 236 if (!hw->phy.reset_if_overtemp &&
238 237 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
239 238 goto out;
240 239
241 240 /*
242 241 * Perform soft PHY reset to the PHY_XS.
243 242 * This will cause a soft reset to the PHY
244 243 */
245 244 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
246 - IXGBE_MDIO_PHY_XS_DEV_TYPE,
247 - IXGBE_MDIO_PHY_XS_RESET);
245 + IXGBE_MDIO_PHY_XS_DEV_TYPE,
246 + IXGBE_MDIO_PHY_XS_RESET);
248 247
249 248 /*
250 249 * Poll for reset bit to self-clear indicating reset is complete.
251 250 * Some PHYs could take up to 3 seconds to complete and need about
252 251 * 1.7 usec delay after the reset is complete.
253 252 */
254 253 for (i = 0; i < 30; i++) {
255 254 msec_delay(100);
256 255 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
257 - IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
256 + IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
258 257 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
259 258 usec_delay(2);
260 259 break;
261 260 }
262 261 }
263 262
264 263 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
265 264 status = IXGBE_ERR_RESET_FAILED;
266 265 DEBUGOUT("PHY reset polling failed to complete.\n");
267 266 }
268 267
269 268 out:
|
↓ open down ↓ |
2 lines elided |
↑ open up ↑ |
270 269 return status;
271 270 }
272 271
273 272 /**
274 273 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
275 274 * @hw: pointer to hardware structure
276 275 * @reg_addr: 32 bit address of PHY register to read
277 276 * @phy_data: Pointer to read data from PHY register
278 277 **/
279 278 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
280 - u32 device_type, u16 *phy_data)
279 + u32 device_type, u16 *phy_data)
281 280 {
282 281 u32 command;
283 282 u32 i;
284 283 u32 data;
285 284 s32 status = IXGBE_SUCCESS;
286 285 u16 gssr;
287 286
288 287 DEBUGFUNC("ixgbe_read_phy_reg_generic");
289 288
290 289 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
291 290 gssr = IXGBE_GSSR_PHY1_SM;
292 291 else
293 292 gssr = IXGBE_GSSR_PHY0_SM;
294 293
295 - if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
294 + if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
296 295 status = IXGBE_ERR_SWFW_SYNC;
297 296
298 297 if (status == IXGBE_SUCCESS) {
299 298 /* Setup and write the address cycle command */
300 299 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
301 - (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
302 - (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
303 - (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
300 + (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
301 + (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
302 + (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
304 303
305 304 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
306 305
307 306 /*
308 307 * Check every 10 usec to see if the address cycle completed.
309 308 * The MDI Command bit will clear when the operation is
310 309 * complete
311 310 */
312 311 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
313 312 usec_delay(10);
314 313
315 314 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
316 315
317 316 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
318 317 break;
319 318 }
320 319
321 320 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
|
↓ open down ↓ |
8 lines elided |
↑ open up ↑ |
322 321 DEBUGOUT("PHY address command did not complete.\n");
323 322 status = IXGBE_ERR_PHY;
324 323 }
325 324
326 325 if (status == IXGBE_SUCCESS) {
327 326 /*
328 327 * Address cycle complete, setup and write the read
329 328 * command
330 329 */
331 330 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
332 - (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
333 - (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
334 - (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
331 + (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
332 + (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
333 + (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
335 334
336 335 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
337 336
338 337 /*
339 338 * Check every 10 usec to see if the address cycle
340 339 * completed. The MDI Command bit will clear when the
341 340 * operation is complete
342 341 */
343 342 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
344 343 usec_delay(10);
345 344
346 345 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
347 346
348 347 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
349 348 break;
350 349 }
351 350
352 351 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
353 352 DEBUGOUT("PHY read command didn't complete\n");
354 353 status = IXGBE_ERR_PHY;
355 354 } else {
|
↓ open down ↓ |
11 lines elided |
↑ open up ↑ |
356 355 /*
357 356 * Read operation is complete. Get the data
358 357 * from MSRWD
359 358 */
360 359 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
361 360 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
362 361 *phy_data = (u16)(data);
363 362 }
364 363 }
365 364
366 - ixgbe_release_swfw_sync(hw, gssr);
365 + hw->mac.ops.release_swfw_sync(hw, gssr);
367 366 }
368 367
369 368 return status;
370 369 }
371 370
372 371 /**
373 372 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
374 373 * @hw: pointer to hardware structure
375 374 * @reg_addr: 32 bit PHY register to write
376 375 * @device_type: 5 bit device type
377 376 * @phy_data: Data to write to the PHY register
378 377 **/
379 378 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
380 - u32 device_type, u16 phy_data)
379 + u32 device_type, u16 phy_data)
381 380 {
382 381 u32 command;
383 382 u32 i;
384 383 s32 status = IXGBE_SUCCESS;
385 384 u16 gssr;
386 385
387 386 DEBUGFUNC("ixgbe_write_phy_reg_generic");
388 387
389 388 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
390 389 gssr = IXGBE_GSSR_PHY1_SM;
391 390 else
392 391 gssr = IXGBE_GSSR_PHY0_SM;
393 392
394 - if (ixgbe_acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
393 + if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
395 394 status = IXGBE_ERR_SWFW_SYNC;
396 395
397 396 if (status == IXGBE_SUCCESS) {
398 397 /* Put the data in the MDI single read and write data register*/
399 398 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
400 399
401 400 /* Setup and write the address cycle command */
402 401 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
403 - (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
404 - (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
405 - (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
402 + (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
403 + (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
404 + (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
406 405
407 406 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
408 407
409 408 /*
410 409 * Check every 10 usec to see if the address cycle completed.
411 410 * The MDI Command bit will clear when the operation is
412 411 * complete
413 412 */
414 413 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
415 414 usec_delay(10);
416 415
417 416 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
418 417
419 418 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
420 419 break;
421 420 }
422 421
423 422 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
|
↓ open down ↓ |
8 lines elided |
↑ open up ↑ |
424 423 DEBUGOUT("PHY address cmd didn't complete\n");
425 424 status = IXGBE_ERR_PHY;
426 425 }
427 426
428 427 if (status == IXGBE_SUCCESS) {
429 428 /*
430 429 * Address cycle complete, setup and write the write
431 430 * command
432 431 */
433 432 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
434 - (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
435 - (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
436 - (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
433 + (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
434 + (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
435 + (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
437 436
438 437 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
439 438
440 439 /*
441 440 * Check every 10 usec to see if the address cycle
442 441 * completed. The MDI Command bit will clear when the
443 442 * operation is complete
444 443 */
445 444 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
446 445 usec_delay(10);
447 446
448 447 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
449 448
|
↓ open down ↓ |
3 lines elided |
↑ open up ↑ |
450 449 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
451 450 break;
452 451 }
453 452
454 453 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
455 454 DEBUGOUT("PHY address cmd didn't complete\n");
456 455 status = IXGBE_ERR_PHY;
457 456 }
458 457 }
459 458
460 - ixgbe_release_swfw_sync(hw, gssr);
459 + hw->mac.ops.release_swfw_sync(hw, gssr);
461 460 }
462 461
463 462 return status;
464 463 }
465 464
466 465 /**
467 466 * ixgbe_setup_phy_link_generic - Set and restart autoneg
468 467 * @hw: pointer to hardware structure
469 468 *
470 469 * Restart autonegotiation and PHY and waits for completion.
471 470 **/
472 471 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
|
↓ open down ↓ |
2 lines elided |
↑ open up ↑ |
473 472 {
474 473 s32 status = IXGBE_SUCCESS;
475 474 u32 time_out;
476 475 u32 max_time_out = 10;
477 476 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
478 477 bool autoneg = FALSE;
479 478 ixgbe_link_speed speed;
480 479
481 480 DEBUGFUNC("ixgbe_setup_phy_link_generic");
482 481
483 - (void) ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
482 + ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
484 483
485 484 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
486 485 /* Set or unset auto-negotiation 10G advertisement */
487 486 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
488 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
489 - &autoneg_reg);
487 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
488 + &autoneg_reg);
490 489
491 490 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
492 491 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
493 492 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
494 493
495 494 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
496 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
497 - autoneg_reg);
495 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
496 + autoneg_reg);
498 497 }
499 498
500 499 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
501 500 /* Set or unset auto-negotiation 1G advertisement */
502 501 hw->phy.ops.read_reg(hw,
503 - IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
504 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
505 - &autoneg_reg);
502 + IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
503 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
504 + &autoneg_reg);
506 505
507 506 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
508 507 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
509 508 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
510 509
511 510 hw->phy.ops.write_reg(hw,
512 - IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
513 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
514 - autoneg_reg);
511 + IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
512 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
513 + autoneg_reg);
515 514 }
516 515
517 516 if (speed & IXGBE_LINK_SPEED_100_FULL) {
518 517 /* Set or unset auto-negotiation 100M advertisement */
519 518 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
520 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
521 - &autoneg_reg);
519 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
520 + &autoneg_reg);
522 521
523 - autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
522 + autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
523 + IXGBE_MII_100BASE_T_ADVERTISE_HALF);
524 524 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
525 525 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
526 526
527 527 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
528 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
529 - autoneg_reg);
528 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
529 + autoneg_reg);
530 530 }
531 531
532 532 /* Restart PHY autonegotiation and wait for completion */
533 533 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
534 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
534 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
535 535
536 536 autoneg_reg |= IXGBE_MII_RESTART;
537 537
538 538 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
539 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
539 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
540 540
541 541 /* Wait for autonegotiation to finish */
542 542 for (time_out = 0; time_out < max_time_out; time_out++) {
543 543 usec_delay(10);
544 544 /* Restart PHY autonegotiation and wait for completion */
545 545 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
546 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
547 - &autoneg_reg);
546 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
547 + &autoneg_reg);
548 548
549 549 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
550 - if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
550 + if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
551 551 break;
552 - }
553 552 }
554 553
555 554 if (time_out == max_time_out) {
556 555 status = IXGBE_ERR_LINK_SETUP;
557 556 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
558 557 }
559 558
560 559 return status;
561 560 }
562 561
563 562 /**
564 563 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
565 564 * @hw: pointer to hardware structure
566 565 * @speed: new link speed
567 566 * @autoneg: TRUE if autonegotiation enabled
568 567 **/
569 568 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
570 - ixgbe_link_speed speed,
571 - bool autoneg,
572 - bool autoneg_wait_to_complete)
569 + ixgbe_link_speed speed,
570 + bool autoneg,
571 + bool autoneg_wait_to_complete)
573 572 {
574 - UNREFERENCED_PARAMETER(autoneg);
575 - UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
573 + UNREFERENCED_2PARAMETER(autoneg, autoneg_wait_to_complete);
576 574
577 575 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
578 576
579 577 /*
580 578 * Clear autoneg_advertised and set new values based on input link
581 579 * speed.
582 580 */
583 581 hw->phy.autoneg_advertised = 0;
584 582
585 583 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
586 584 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
587 585
588 586 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
589 587 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
590 588
591 589 if (speed & IXGBE_LINK_SPEED_100_FULL)
592 590 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
593 591
594 592 /* Setup link based on the new speed settings */
595 593 hw->phy.ops.setup_link(hw);
596 594
597 595 return IXGBE_SUCCESS;
598 596 }
|
↓ open down ↓ |
13 lines elided |
↑ open up ↑ |
599 597
600 598 /**
601 599 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
602 600 * @hw: pointer to hardware structure
603 601 * @speed: pointer to link speed
604 602 * @autoneg: boolean auto-negotiation value
605 603 *
606 604 * Determines the link capabilities by reading the AUTOC register.
607 605 **/
608 606 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
609 - ixgbe_link_speed *speed,
610 - bool *autoneg)
607 + ixgbe_link_speed *speed,
608 + bool *autoneg)
611 609 {
612 610 s32 status = IXGBE_ERR_LINK_SETUP;
613 611 u16 speed_ability;
614 612
615 613 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
616 614
617 615 *speed = 0;
618 616 *autoneg = TRUE;
619 617
620 618 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
621 - IXGBE_MDIO_PMA_PMD_DEV_TYPE,
622 - &speed_ability);
619 + IXGBE_MDIO_PMA_PMD_DEV_TYPE,
620 + &speed_ability);
623 621
624 622 if (status == IXGBE_SUCCESS) {
625 623 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
626 624 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
627 625 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
628 626 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
629 627 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
630 628 *speed |= IXGBE_LINK_SPEED_100_FULL;
631 629 }
632 630
633 631 return status;
|
↓ open down ↓ |
1 lines elided |
↑ open up ↑ |
634 632 }
635 633
636 634 /**
637 635 * ixgbe_check_phy_link_tnx - Determine link and speed status
638 636 * @hw: pointer to hardware structure
639 637 *
640 638 * Reads the VS1 register to determine if link is up and the current speed for
641 639 * the PHY.
642 640 **/
643 641 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
644 - bool *link_up)
642 + bool *link_up)
645 643 {
646 644 s32 status = IXGBE_SUCCESS;
647 645 u32 time_out;
648 646 u32 max_time_out = 10;
649 647 u16 phy_link = 0;
650 648 u16 phy_speed = 0;
651 649 u16 phy_data = 0;
652 650
653 651 DEBUGFUNC("ixgbe_check_phy_link_tnx");
654 652
655 653 /* Initialize speed and link to default case */
656 654 *link_up = FALSE;
|
↓ open down ↓ |
2 lines elided |
↑ open up ↑ |
657 655 *speed = IXGBE_LINK_SPEED_10GB_FULL;
658 656
659 657 /*
660 658 * Check current speed and link status of the PHY register.
661 659 * This is a vendor specific register and may have to
662 660 * be changed for other copper PHYs.
663 661 */
664 662 for (time_out = 0; time_out < max_time_out; time_out++) {
665 663 usec_delay(10);
666 664 status = hw->phy.ops.read_reg(hw,
667 - IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
668 - IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
669 - &phy_data);
670 - phy_link = phy_data &
671 - IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
665 + IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
666 + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
667 + &phy_data);
668 + phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
672 669 phy_speed = phy_data &
673 - IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
670 + IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
674 671 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
675 672 *link_up = TRUE;
676 673 if (phy_speed ==
677 674 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
678 675 *speed = IXGBE_LINK_SPEED_1GB_FULL;
679 676 break;
680 677 }
681 678 }
682 679
683 680 return status;
684 681 }
685 682
686 683 /**
687 684 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
688 685 * @hw: pointer to hardware structure
689 686 *
690 687 * Restart autonegotiation and PHY and waits for completion.
691 688 **/
692 689 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
|
↓ open down ↓ |
9 lines elided |
↑ open up ↑ |
693 690 {
694 691 s32 status = IXGBE_SUCCESS;
695 692 u32 time_out;
696 693 u32 max_time_out = 10;
697 694 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
698 695 bool autoneg = FALSE;
699 696 ixgbe_link_speed speed;
700 697
701 698 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
702 699
703 - (void) ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
700 + ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
704 701
705 702 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
706 703 /* Set or unset auto-negotiation 10G advertisement */
707 704 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
708 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
709 - &autoneg_reg);
705 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
706 + &autoneg_reg);
710 707
711 708 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
712 709 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
713 710 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
714 711
715 712 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
716 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
717 - autoneg_reg);
713 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
714 + autoneg_reg);
718 715 }
719 716
720 717 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
721 718 /* Set or unset auto-negotiation 1G advertisement */
722 719 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
723 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
724 - &autoneg_reg);
720 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
721 + &autoneg_reg);
725 722
726 723 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
727 724 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
728 725 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
729 726
730 727 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
731 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
732 - autoneg_reg);
728 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
729 + autoneg_reg);
733 730 }
734 731
735 732 if (speed & IXGBE_LINK_SPEED_100_FULL) {
736 733 /* Set or unset auto-negotiation 100M advertisement */
737 734 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
738 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
739 - &autoneg_reg);
735 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
736 + &autoneg_reg);
740 737
741 738 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
742 739 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
743 740 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
744 741
745 742 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
746 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
747 - autoneg_reg);
743 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
744 + autoneg_reg);
748 745 }
749 746
750 747 /* Restart PHY autonegotiation and wait for completion */
751 748 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
752 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
749 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
753 750
754 751 autoneg_reg |= IXGBE_MII_RESTART;
755 752
756 753 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
757 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
754 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
758 755
759 756 /* Wait for autonegotiation to finish */
760 757 for (time_out = 0; time_out < max_time_out; time_out++) {
761 758 usec_delay(10);
762 759 /* Restart PHY autonegotiation and wait for completion */
763 760 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
764 - IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
765 - &autoneg_reg);
761 + IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
762 + &autoneg_reg);
766 763
767 764 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
768 - if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
765 + if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
769 766 break;
770 - }
771 767 }
772 768
773 769 if (time_out == max_time_out) {
774 770 status = IXGBE_ERR_LINK_SETUP;
775 771 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
776 772 }
777 773
778 774 return status;
779 775 }
780 776
781 777 /**
782 778 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
783 779 * @hw: pointer to hardware structure
784 780 * @firmware_version: pointer to the PHY Firmware Version
785 781 **/
786 782 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
787 - u16 *firmware_version)
783 + u16 *firmware_version)
788 784 {
789 785 s32 status = IXGBE_SUCCESS;
790 786
791 787 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
792 788
793 789 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
794 - IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
795 - firmware_version);
790 + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
791 + firmware_version);
796 792
797 793 return status;
798 794 }
799 795
800 796 /**
801 797 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
802 798 * @hw: pointer to hardware structure
803 799 * @firmware_version: pointer to the PHY Firmware Version
804 800 **/
805 801 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
806 - u16 *firmware_version)
802 + u16 *firmware_version)
807 803 {
808 804 s32 status = IXGBE_SUCCESS;
809 805
810 806 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
811 807
812 808 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
813 - IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
814 - firmware_version);
809 + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
810 + firmware_version);
815 811
816 812 return status;
817 813 }
818 814
819 815 /**
820 816 * ixgbe_reset_phy_nl - Performs a PHY reset
821 817 * @hw: pointer to hardware structure
822 818 **/
823 819 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
824 820 {
825 821 u16 phy_offset, control, eword, edata, block_crc;
826 822 bool end_data = FALSE;
827 823 u16 list_offset, data_offset;
828 824 u16 phy_data = 0;
829 825 s32 ret_val = IXGBE_SUCCESS;
830 826 u32 i;
831 827
832 828 DEBUGFUNC("ixgbe_reset_phy_nl");
833 829
834 830 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
835 - IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
831 + IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
836 832
837 833 /* reset the PHY and poll for completion */
838 834 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
839 - IXGBE_MDIO_PHY_XS_DEV_TYPE,
840 - (phy_data | IXGBE_MDIO_PHY_XS_RESET));
835 + IXGBE_MDIO_PHY_XS_DEV_TYPE,
836 + (phy_data | IXGBE_MDIO_PHY_XS_RESET));
841 837
842 838 for (i = 0; i < 100; i++) {
843 839 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
844 - IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
840 + IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
845 841 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
846 842 break;
847 843 msec_delay(10);
848 844 }
849 845
850 846 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
851 847 DEBUGOUT("PHY reset did not complete.\n");
852 848 ret_val = IXGBE_ERR_PHY;
853 849 goto out;
854 850 }
855 851
856 852 /* Get init offsets */
857 853 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
858 - &data_offset);
854 + &data_offset);
859 855 if (ret_val != IXGBE_SUCCESS)
860 856 goto out;
861 857
862 858 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
863 859 data_offset++;
864 860 while (!end_data) {
865 861 /*
866 862 * Read control word from PHY init contents offset
867 863 */
868 864 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
869 865 control = (eword & IXGBE_CONTROL_MASK_NL) >>
870 - IXGBE_CONTROL_SHIFT_NL;
866 + IXGBE_CONTROL_SHIFT_NL;
871 867 edata = eword & IXGBE_DATA_MASK_NL;
872 868 switch (control) {
873 869 case IXGBE_DELAY_NL:
874 870 data_offset++;
875 871 DEBUGOUT1("DELAY: %d MS\n", edata);
876 872 msec_delay(edata);
877 873 break;
878 874 case IXGBE_DATA_NL:
879 - DEBUGOUT("DATA: \n");
875 + DEBUGOUT("DATA:\n");
880 876 data_offset++;
881 877 hw->eeprom.ops.read(hw, data_offset++,
882 - &phy_offset);
878 + &phy_offset);
883 879 for (i = 0; i < edata; i++) {
884 880 hw->eeprom.ops.read(hw, data_offset, &eword);
885 881 hw->phy.ops.write_reg(hw, phy_offset,
886 - IXGBE_TWINAX_DEV, eword);
882 + IXGBE_TWINAX_DEV, eword);
887 883 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
888 - phy_offset);
884 + phy_offset);
889 885 data_offset++;
890 886 phy_offset++;
891 887 }
892 888 break;
893 889 case IXGBE_CONTROL_NL:
894 890 data_offset++;
895 - DEBUGOUT("CONTROL: \n");
891 + DEBUGOUT("CONTROL:\n");
896 892 if (edata == IXGBE_CONTROL_EOL_NL) {
897 893 DEBUGOUT("EOL\n");
898 894 end_data = TRUE;
899 895 } else if (edata == IXGBE_CONTROL_SOL_NL) {
900 896 DEBUGOUT("SOL\n");
901 897 } else {
902 898 DEBUGOUT("Bad control value\n");
903 899 ret_val = IXGBE_ERR_PHY;
904 900 goto out;
905 901 }
906 902 break;
907 903 default:
908 904 DEBUGOUT("Bad control type\n");
|
↓ open down ↓ |
3 lines elided |
↑ open up ↑ |
909 905 ret_val = IXGBE_ERR_PHY;
910 906 goto out;
911 907 }
912 908 }
913 909
914 910 out:
915 911 return ret_val;
916 912 }
917 913
918 914 /**
915 + * ixgbe_identify_module_generic - Identifies module type
916 + * @hw: pointer to hardware structure
917 + *
918 + * Determines HW type and calls appropriate function.
919 + **/
920 +s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
921 +{
922 + s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
923 +
924 + DEBUGFUNC("ixgbe_identify_module_generic");
925 +
926 + switch (hw->mac.ops.get_media_type(hw)) {
927 + case ixgbe_media_type_fiber:
928 + status = ixgbe_identify_sfp_module_generic(hw);
929 + break;
930 +
931 +
932 + default:
933 + hw->phy.sfp_type = ixgbe_sfp_type_not_present;
934 + status = IXGBE_ERR_SFP_NOT_PRESENT;
935 + break;
936 + }
937 +
938 + return status;
939 +}
940 +
941 +/**
919 942 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
920 943 * @hw: pointer to hardware structure
921 944 *
922 945 * Searches for and identifies the SFP module and assigns appropriate PHY type.
923 946 **/
924 947 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
925 948 {
926 949 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
927 950 u32 vendor_oui = 0;
928 951 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
929 952 u8 identifier = 0;
930 953 u8 comp_codes_1g = 0;
931 954 u8 comp_codes_10g = 0;
932 955 u8 oui_bytes[3] = {0, 0, 0};
933 956 u8 cable_tech = 0;
934 957 u8 cable_spec = 0;
935 958 u16 enforce_sfp = 0;
|
↓ open down ↓ |
7 lines elided |
↑ open up ↑ |
936 959
937 960 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
938 961
939 962 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
940 963 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
941 964 status = IXGBE_ERR_SFP_NOT_PRESENT;
942 965 goto out;
943 966 }
944 967
945 968 status = hw->phy.ops.read_i2c_eeprom(hw,
946 - IXGBE_SFF_IDENTIFIER,
947 - &identifier);
969 + IXGBE_SFF_IDENTIFIER,
970 + &identifier);
948 971
949 972 if (status == IXGBE_ERR_SWFW_SYNC ||
950 973 status == IXGBE_ERR_I2C ||
951 974 status == IXGBE_ERR_SFP_NOT_PRESENT)
952 975 goto err_read_i2c_eeprom;
953 976
954 977 /* LAN ID is needed for sfp_type determination */
955 978 hw->mac.ops.set_lan_id(hw);
956 979
957 980 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
958 981 hw->phy.type = ixgbe_phy_sfp_unsupported;
959 982 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
960 983 } else {
961 984 status = hw->phy.ops.read_i2c_eeprom(hw,
962 - IXGBE_SFF_1GBE_COMP_CODES,
963 - &comp_codes_1g);
985 + IXGBE_SFF_1GBE_COMP_CODES,
986 + &comp_codes_1g);
964 987
965 988 if (status == IXGBE_ERR_SWFW_SYNC ||
966 989 status == IXGBE_ERR_I2C ||
967 990 status == IXGBE_ERR_SFP_NOT_PRESENT)
968 991 goto err_read_i2c_eeprom;
969 992
970 993 status = hw->phy.ops.read_i2c_eeprom(hw,
971 - IXGBE_SFF_10GBE_COMP_CODES,
972 - &comp_codes_10g);
994 + IXGBE_SFF_10GBE_COMP_CODES,
995 + &comp_codes_10g);
973 996
974 997 if (status == IXGBE_ERR_SWFW_SYNC ||
975 998 status == IXGBE_ERR_I2C ||
976 999 status == IXGBE_ERR_SFP_NOT_PRESENT)
977 1000 goto err_read_i2c_eeprom;
978 1001 status = hw->phy.ops.read_i2c_eeprom(hw,
979 - IXGBE_SFF_CABLE_TECHNOLOGY,
980 - &cable_tech);
1002 + IXGBE_SFF_CABLE_TECHNOLOGY,
1003 + &cable_tech);
981 1004
982 1005 if (status == IXGBE_ERR_SWFW_SYNC ||
983 1006 status == IXGBE_ERR_I2C ||
984 1007 status == IXGBE_ERR_SFP_NOT_PRESENT)
985 1008 goto err_read_i2c_eeprom;
986 1009
987 1010 /* ID Module
988 1011 * =========
989 1012 * 0 SFP_DA_CU
990 1013 * 1 SFP_SR
991 1014 * 2 SFP_LR
992 1015 * 3 SFP_DA_CORE0 - 82599-specific
993 1016 * 4 SFP_DA_CORE1 - 82599-specific
994 1017 * 5 SFP_SR/LR_CORE0 - 82599-specific
995 1018 * 6 SFP_SR/LR_CORE1 - 82599-specific
996 1019 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
997 1020 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
998 1021 * 9 SFP_1g_cu_CORE0 - 82599-specific
999 1022 * 10 SFP_1g_cu_CORE1 - 82599-specific
1023 + * 11 SFP_1g_sx_CORE0 - 82599-specific
1024 + * 12 SFP_1g_sx_CORE1 - 82599-specific
1000 1025 */
1001 1026 if (hw->mac.type == ixgbe_mac_82598EB) {
1002 1027 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1003 1028 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1004 1029 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1005 1030 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1006 1031 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1007 1032 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1008 1033 else
1009 1034 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1010 1035 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1011 1036 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1012 1037 if (hw->bus.lan_id == 0)
1013 1038 hw->phy.sfp_type =
1014 - ixgbe_sfp_type_da_cu_core0;
1039 + ixgbe_sfp_type_da_cu_core0;
1015 1040 else
1016 1041 hw->phy.sfp_type =
1017 - ixgbe_sfp_type_da_cu_core1;
1042 + ixgbe_sfp_type_da_cu_core1;
1018 1043 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1019 1044 hw->phy.ops.read_i2c_eeprom(
1020 1045 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1021 1046 &cable_spec);
1022 1047 if (cable_spec &
1023 1048 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1024 1049 if (hw->bus.lan_id == 0)
1025 1050 hw->phy.sfp_type =
1026 1051 ixgbe_sfp_type_da_act_lmt_core0;
1027 1052 else
1028 1053 hw->phy.sfp_type =
1029 1054 ixgbe_sfp_type_da_act_lmt_core1;
1030 1055 } else {
1031 1056 hw->phy.sfp_type =
1032 - ixgbe_sfp_type_unknown;
1057 + ixgbe_sfp_type_unknown;
1033 1058 }
1034 1059 } else if (comp_codes_10g &
1035 1060 (IXGBE_SFF_10GBASESR_CAPABLE |
1036 1061 IXGBE_SFF_10GBASELR_CAPABLE)) {
1037 1062 if (hw->bus.lan_id == 0)
1038 1063 hw->phy.sfp_type =
1039 - ixgbe_sfp_type_srlr_core0;
1064 + ixgbe_sfp_type_srlr_core0;
1040 1065 else
1041 1066 hw->phy.sfp_type =
1042 - ixgbe_sfp_type_srlr_core1;
1067 + ixgbe_sfp_type_srlr_core1;
1043 1068 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1044 1069 if (hw->bus.lan_id == 0)
1045 1070 hw->phy.sfp_type =
1046 1071 ixgbe_sfp_type_1g_cu_core0;
1047 1072 else
1048 1073 hw->phy.sfp_type =
1049 1074 ixgbe_sfp_type_1g_cu_core1;
1075 + } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1076 + if (hw->bus.lan_id == 0)
1077 + hw->phy.sfp_type =
1078 + ixgbe_sfp_type_1g_sx_core0;
1079 + else
1080 + hw->phy.sfp_type =
1081 + ixgbe_sfp_type_1g_sx_core1;
1050 1082 } else {
1051 1083 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1052 1084 }
1053 1085 }
1054 1086
1055 1087 if (hw->phy.sfp_type != stored_sfp_type)
1056 1088 hw->phy.sfp_setup_needed = TRUE;
1057 1089
1058 1090 /* Determine if the SFP+ PHY is dual speed or not. */
1059 1091 hw->phy.multispeed_fiber = FALSE;
1060 1092 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1061 1093 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1062 1094 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1063 1095 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1064 1096 hw->phy.multispeed_fiber = TRUE;
1065 1097
1066 1098 /* Determine PHY vendor */
1067 1099 if (hw->phy.type != ixgbe_phy_nl) {
1068 1100 hw->phy.id = identifier;
1069 1101 status = hw->phy.ops.read_i2c_eeprom(hw,
1070 - IXGBE_SFF_VENDOR_OUI_BYTE0,
1071 - &oui_bytes[0]);
1102 + IXGBE_SFF_VENDOR_OUI_BYTE0,
1103 + &oui_bytes[0]);
1072 1104
1073 1105 if (status == IXGBE_ERR_SWFW_SYNC ||
1074 1106 status == IXGBE_ERR_I2C ||
1075 1107 status == IXGBE_ERR_SFP_NOT_PRESENT)
1076 1108 goto err_read_i2c_eeprom;
1077 1109
1078 1110 status = hw->phy.ops.read_i2c_eeprom(hw,
1079 - IXGBE_SFF_VENDOR_OUI_BYTE1,
1080 - &oui_bytes[1]);
1111 + IXGBE_SFF_VENDOR_OUI_BYTE1,
1112 + &oui_bytes[1]);
1081 1113
1082 1114 if (status == IXGBE_ERR_SWFW_SYNC ||
1083 1115 status == IXGBE_ERR_I2C ||
1084 1116 status == IXGBE_ERR_SFP_NOT_PRESENT)
1085 1117 goto err_read_i2c_eeprom;
1086 1118
1087 1119 status = hw->phy.ops.read_i2c_eeprom(hw,
1088 - IXGBE_SFF_VENDOR_OUI_BYTE2,
1089 - &oui_bytes[2]);
1120 + IXGBE_SFF_VENDOR_OUI_BYTE2,
1121 + &oui_bytes[2]);
1090 1122
1091 1123 if (status == IXGBE_ERR_SWFW_SYNC ||
1092 1124 status == IXGBE_ERR_I2C ||
1093 1125 status == IXGBE_ERR_SFP_NOT_PRESENT)
1094 1126 goto err_read_i2c_eeprom;
1095 1127
1096 1128 vendor_oui =
1097 1129 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1098 1130 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1099 1131 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1100 1132
1101 1133 switch (vendor_oui) {
1102 1134 case IXGBE_SFF_VENDOR_OUI_TYCO:
1103 1135 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1104 1136 hw->phy.type =
1105 - ixgbe_phy_sfp_passive_tyco;
1137 + ixgbe_phy_sfp_passive_tyco;
1106 1138 break;
1107 1139 case IXGBE_SFF_VENDOR_OUI_FTL:
1108 1140 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1109 1141 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1110 1142 else
1111 1143 hw->phy.type = ixgbe_phy_sfp_ftl;
1112 1144 break;
1113 1145 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1114 1146 hw->phy.type = ixgbe_phy_sfp_avago;
1115 1147 break;
1116 1148 case IXGBE_SFF_VENDOR_OUI_INTEL:
1117 1149 hw->phy.type = ixgbe_phy_sfp_intel;
1118 1150 break;
1119 1151 default:
1120 1152 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1121 1153 hw->phy.type =
1122 - ixgbe_phy_sfp_passive_unknown;
1154 + ixgbe_phy_sfp_passive_unknown;
1123 1155 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1124 1156 hw->phy.type =
1125 1157 ixgbe_phy_sfp_active_unknown;
1126 1158 else
1127 1159 hw->phy.type = ixgbe_phy_sfp_unknown;
1128 1160 break;
1129 1161 }
1130 1162 }
1131 1163
1132 1164 /* Allow any DA cable vendor */
1133 1165 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1134 1166 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1135 1167 status = IXGBE_SUCCESS;
1136 1168 goto out;
1137 1169 }
1138 1170
1139 1171 /* Verify supported 1G SFP modules */
1140 1172 if (comp_codes_10g == 0 &&
1141 1173 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1142 - hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
1174 + hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1175 + hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1176 + hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1143 1177 hw->phy.type = ixgbe_phy_sfp_unsupported;
1144 1178 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1145 1179 goto out;
1146 1180 }
1147 1181
1148 1182 /* Anything else 82598-based is supported */
1149 1183 if (hw->mac.type == ixgbe_mac_82598EB) {
1150 1184 status = IXGBE_SUCCESS;
1151 1185 goto out;
1152 1186 }
1153 1187
1154 - (void) ixgbe_get_device_caps(hw, &enforce_sfp);
1188 + ixgbe_get_device_caps(hw, &enforce_sfp);
1155 1189 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1156 1190 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1157 - (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
1191 + (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1192 + (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
1193 + (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1158 1194 /* Make sure we're a supported PHY type */
1159 1195 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1160 1196 status = IXGBE_SUCCESS;
1161 1197 } else {
1162 - DEBUGOUT("SFP+ module not supported\n");
1163 - hw->phy.type = ixgbe_phy_sfp_unsupported;
1164 - status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1198 + if (hw->allow_unsupported_sfp == TRUE) {
1199 + EWARN(hw, "WARNING: Intel (R) Network "
1200 + "Connections are quality tested "
1201 + "using Intel (R) Ethernet Optics."
1202 + " Using untested modules is not "
1203 + "supported and may cause unstable"
1204 + " operation or damage to the "
1205 + "module or the adapter. Intel "
1206 + "Corporation is not responsible "
1207 + "for any harm caused by using "
1208 + "untested modules.\n", status);
1209 + status = IXGBE_SUCCESS;
1210 + } else {
1211 + DEBUGOUT("SFP+ module not supported\n");
1212 + hw->phy.type =
1213 + ixgbe_phy_sfp_unsupported;
1214 + status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1215 + }
1165 1216 }
1166 1217 } else {
1167 1218 status = IXGBE_SUCCESS;
1168 1219 }
1169 1220 }
1170 1221
1171 1222 out:
1172 1223 return status;
1173 1224
1174 1225 err_read_i2c_eeprom:
1175 1226 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1176 1227 if (hw->phy.type != ixgbe_phy_nl) {
1177 1228 hw->phy.id = 0;
1178 1229 hw->phy.type = ixgbe_phy_unknown;
1179 1230 }
1180 1231 return IXGBE_ERR_SFP_NOT_PRESENT;
1181 1232 }
1182 1233
1234 +
1235 +
1183 1236 /**
1184 1237 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1185 1238 * @hw: pointer to hardware structure
1186 1239 * @list_offset: offset to the SFP ID list
1187 1240 * @data_offset: offset to the SFP data block
1188 1241 *
1189 1242 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1190 1243 * so it returns the offsets to the phy init sequence block.
1191 1244 **/
1192 1245 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1193 - u16 *list_offset,
1194 - u16 *data_offset)
1246 + u16 *list_offset,
1247 + u16 *data_offset)
1195 1248 {
1196 1249 u16 sfp_id;
1197 1250 u16 sfp_type = hw->phy.sfp_type;
1198 1251
1199 1252 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1200 1253
1201 1254 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1202 1255 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1203 1256
1204 1257 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1205 1258 return IXGBE_ERR_SFP_NOT_PRESENT;
|
↓ open down ↓ |
1 lines elided |
↑ open up ↑ |
1206 1259
1207 1260 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1208 1261 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1209 1262 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1210 1263
1211 1264 /*
1212 1265 * Limiting active cables and 1G Phys must be initialized as
1213 1266 * SR modules
1214 1267 */
1215 1268 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1216 - sfp_type == ixgbe_sfp_type_1g_cu_core0)
1269 + sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1270 + sfp_type == ixgbe_sfp_type_1g_sx_core0)
1217 1271 sfp_type = ixgbe_sfp_type_srlr_core0;
1218 1272 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1219 - sfp_type == ixgbe_sfp_type_1g_cu_core1)
1273 + sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1274 + sfp_type == ixgbe_sfp_type_1g_sx_core1)
1220 1275 sfp_type = ixgbe_sfp_type_srlr_core1;
1221 1276
1222 1277 /* Read offset to PHY init contents */
1223 1278 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1224 1279
1225 1280 if ((!*list_offset) || (*list_offset == 0xFFFF))
1226 1281 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1227 1282
1228 1283 /* Shift offset to first ID word */
1229 1284 (*list_offset)++;
1230 1285
1231 1286 /*
1232 1287 * Find the matching SFP ID in the EEPROM
1233 1288 * and program the init sequence
1234 1289 */
1235 1290 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1236 1291
1237 1292 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1238 1293 if (sfp_id == sfp_type) {
1239 1294 (*list_offset)++;
1240 1295 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1241 1296 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1242 1297 DEBUGOUT("SFP+ module not supported\n");
1243 1298 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1244 1299 } else {
1245 1300 break;
1246 1301 }
1247 1302 } else {
1248 1303 (*list_offset) += 2;
1249 1304 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1250 1305 return IXGBE_ERR_PHY;
1251 1306 }
1252 1307 }
1253 1308
1254 1309 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1255 1310 DEBUGOUT("No matching SFP+ module found\n");
1256 1311 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1257 1312 }
1258 1313
1259 1314 return IXGBE_SUCCESS;
1260 1315 }
|
↓ open down ↓ |
31 lines elided |
↑ open up ↑ |
1261 1316
1262 1317 /**
1263 1318 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1264 1319 * @hw: pointer to hardware structure
1265 1320 * @byte_offset: EEPROM byte offset to read
1266 1321 * @eeprom_data: value read
1267 1322 *
1268 1323 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1269 1324 **/
1270 1325 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1271 - u8 *eeprom_data)
1326 + u8 *eeprom_data)
1272 1327 {
1273 1328 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1274 1329
1275 1330 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1276 - IXGBE_I2C_EEPROM_DEV_ADDR,
1277 - eeprom_data);
1331 + IXGBE_I2C_EEPROM_DEV_ADDR,
1332 + eeprom_data);
1278 1333 }
1279 1334
1280 1335 /**
1281 1336 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1282 1337 * @hw: pointer to hardware structure
1283 1338 * @byte_offset: EEPROM byte offset to write
1284 1339 * @eeprom_data: value to write
1285 1340 *
1286 1341 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1287 1342 **/
1288 1343 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1289 - u8 eeprom_data)
1344 + u8 eeprom_data)
1290 1345 {
1291 1346 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1292 1347
1293 1348 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1294 - IXGBE_I2C_EEPROM_DEV_ADDR,
1295 - eeprom_data);
1349 + IXGBE_I2C_EEPROM_DEV_ADDR,
1350 + eeprom_data);
1296 1351 }
1297 1352
1298 1353 /**
1299 1354 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1300 1355 * @hw: pointer to hardware structure
1301 1356 * @byte_offset: byte offset to read
1302 1357 * @data: value read
1303 1358 *
1304 1359 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1305 - * a specified deivce address.
1360 + * a specified device address.
1306 1361 **/
1307 1362 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1308 - u8 dev_addr, u8 *data)
1363 + u8 dev_addr, u8 *data)
1309 1364 {
1310 1365 s32 status = IXGBE_SUCCESS;
1311 1366 u32 max_retry = 10;
1312 1367 u32 retry = 0;
1313 1368 u16 swfw_mask = 0;
1314 1369 bool nack = 1;
1370 + *data = 0;
1315 1371
1316 1372 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1317 1373
1318 1374 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1319 1375 swfw_mask = IXGBE_GSSR_PHY1_SM;
1320 1376 else
1321 1377 swfw_mask = IXGBE_GSSR_PHY0_SM;
1322 1378
1323 1379 do {
1324 - if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1380 + if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1381 + != IXGBE_SUCCESS) {
1325 1382 status = IXGBE_ERR_SWFW_SYNC;
1326 1383 goto read_byte_out;
1327 1384 }
1328 1385
1329 1386 ixgbe_i2c_start(hw);
1330 1387
1331 1388 /* Device Address and write indication */
1332 1389 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1333 1390 if (status != IXGBE_SUCCESS)
1334 1391 goto fail;
1335 1392
1336 1393 status = ixgbe_get_i2c_ack(hw);
1337 1394 if (status != IXGBE_SUCCESS)
1338 1395 goto fail;
1339 1396
1340 1397 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1341 1398 if (status != IXGBE_SUCCESS)
1342 1399 goto fail;
1343 1400
1344 1401 status = ixgbe_get_i2c_ack(hw);
1345 1402 if (status != IXGBE_SUCCESS)
1346 1403 goto fail;
1347 1404
1348 1405 ixgbe_i2c_start(hw);
1349 1406
1350 1407 /* Device Address and read indication */
1351 1408 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1352 1409 if (status != IXGBE_SUCCESS)
1353 1410 goto fail;
1354 1411
1355 1412 status = ixgbe_get_i2c_ack(hw);
1356 1413 if (status != IXGBE_SUCCESS)
1357 1414 goto fail;
1358 1415
1359 1416 status = ixgbe_clock_in_i2c_byte(hw, data);
1360 1417 if (status != IXGBE_SUCCESS)
|
↓ open down ↓ |
26 lines elided |
↑ open up ↑ |
1361 1418 goto fail;
1362 1419
1363 1420 status = ixgbe_clock_out_i2c_bit(hw, nack);
1364 1421 if (status != IXGBE_SUCCESS)
1365 1422 goto fail;
1366 1423
1367 1424 ixgbe_i2c_stop(hw);
1368 1425 break;
1369 1426
1370 1427 fail:
1371 - ixgbe_release_swfw_sync(hw, swfw_mask);
1428 + hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1372 1429 msec_delay(100);
1373 1430 ixgbe_i2c_bus_clear(hw);
1374 1431 retry++;
1375 1432 if (retry < max_retry)
1376 1433 DEBUGOUT("I2C byte read error - Retrying.\n");
1377 1434 else
1378 1435 DEBUGOUT("I2C byte read error.\n");
1379 1436
1380 1437 } while (retry < max_retry);
1381 1438
1382 - ixgbe_release_swfw_sync(hw, swfw_mask);
1439 + hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1383 1440
1384 1441 read_byte_out:
1385 1442 return status;
1386 1443 }
1387 1444
1388 1445 /**
1389 1446 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1390 1447 * @hw: pointer to hardware structure
1391 1448 * @byte_offset: byte offset to write
1392 1449 * @data: value to write
1393 1450 *
1394 1451 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1395 1452 * a specified device address.
1396 1453 **/
1397 1454 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1398 - u8 dev_addr, u8 data)
1455 + u8 dev_addr, u8 data)
1399 1456 {
1400 1457 s32 status = IXGBE_SUCCESS;
1401 1458 u32 max_retry = 1;
1402 1459 u32 retry = 0;
1403 1460 u16 swfw_mask = 0;
1404 1461
1405 1462 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1406 1463
1407 1464 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1408 1465 swfw_mask = IXGBE_GSSR_PHY1_SM;
1409 1466 else
1410 1467 swfw_mask = IXGBE_GSSR_PHY0_SM;
1411 1468
1412 - if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1469 + if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1413 1470 status = IXGBE_ERR_SWFW_SYNC;
1414 1471 goto write_byte_out;
1415 1472 }
1416 1473
1417 1474 do {
1418 1475 ixgbe_i2c_start(hw);
1419 1476
1420 1477 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1421 1478 if (status != IXGBE_SUCCESS)
1422 1479 goto fail;
1423 1480
1424 1481 status = ixgbe_get_i2c_ack(hw);
1425 1482 if (status != IXGBE_SUCCESS)
1426 1483 goto fail;
1427 1484
1428 1485 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1429 1486 if (status != IXGBE_SUCCESS)
1430 1487 goto fail;
1431 1488
1432 1489 status = ixgbe_get_i2c_ack(hw);
1433 1490 if (status != IXGBE_SUCCESS)
1434 1491 goto fail;
1435 1492
1436 1493 status = ixgbe_clock_out_i2c_byte(hw, data);
1437 1494 if (status != IXGBE_SUCCESS)
1438 1495 goto fail;
1439 1496
1440 1497 status = ixgbe_get_i2c_ack(hw);
1441 1498 if (status != IXGBE_SUCCESS)
1442 1499 goto fail;
1443 1500
1444 1501 ixgbe_i2c_stop(hw);
1445 1502 break;
|
↓ open down ↓ |
23 lines elided |
↑ open up ↑ |
1446 1503
1447 1504 fail:
1448 1505 ixgbe_i2c_bus_clear(hw);
1449 1506 retry++;
1450 1507 if (retry < max_retry)
1451 1508 DEBUGOUT("I2C byte write error - Retrying.\n");
1452 1509 else
1453 1510 DEBUGOUT("I2C byte write error.\n");
1454 1511 } while (retry < max_retry);
1455 1512
1456 - ixgbe_release_swfw_sync(hw, swfw_mask);
1513 + hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1457 1514
1458 1515 write_byte_out:
1459 1516 return status;
1460 1517 }
1461 1518
1462 1519 /**
1463 1520 * ixgbe_i2c_start - Sets I2C start condition
1464 1521 * @hw: pointer to hardware structure
1465 1522 *
1466 1523 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1467 1524 **/
1468 1525 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1469 1526 {
1470 1527 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1471 1528
1472 1529 DEBUGFUNC("ixgbe_i2c_start");
1473 1530
1474 1531 /* Start condition must begin with data and clock high */
1475 - (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1476 - (void) ixgbe_raise_i2c_clk(hw, &i2cctl);
1532 + ixgbe_set_i2c_data(hw, &i2cctl, 1);
1533 + ixgbe_raise_i2c_clk(hw, &i2cctl);
1477 1534
1478 1535 /* Setup time for start condition (4.7us) */
1479 1536 usec_delay(IXGBE_I2C_T_SU_STA);
1480 1537
1481 - (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1538 + ixgbe_set_i2c_data(hw, &i2cctl, 0);
1482 1539
1483 1540 /* Hold time for start condition (4us) */
1484 1541 usec_delay(IXGBE_I2C_T_HD_STA);
1485 1542
1486 1543 ixgbe_lower_i2c_clk(hw, &i2cctl);
1487 1544
1488 1545 /* Minimum low period of clock is 4.7 us */
1489 1546 usec_delay(IXGBE_I2C_T_LOW);
1490 1547
1491 1548 }
1492 1549
1493 1550 /**
1494 1551 * ixgbe_i2c_stop - Sets I2C stop condition
1495 1552 * @hw: pointer to hardware structure
|
↓ open down ↓ |
4 lines elided |
↑ open up ↑ |
1496 1553 *
1497 1554 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1498 1555 **/
1499 1556 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1500 1557 {
1501 1558 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1502 1559
1503 1560 DEBUGFUNC("ixgbe_i2c_stop");
1504 1561
1505 1562 /* Stop condition must begin with data low and clock high */
1506 - (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1507 - (void) ixgbe_raise_i2c_clk(hw, &i2cctl);
1563 + ixgbe_set_i2c_data(hw, &i2cctl, 0);
1564 + ixgbe_raise_i2c_clk(hw, &i2cctl);
1508 1565
1509 1566 /* Setup time for stop condition (4us) */
1510 1567 usec_delay(IXGBE_I2C_T_SU_STO);
1511 1568
1512 - (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1569 + ixgbe_set_i2c_data(hw, &i2cctl, 1);
1513 1570
1514 1571 /* bus free time between stop and start (4.7us)*/
1515 1572 usec_delay(IXGBE_I2C_T_BUF);
1516 1573 }
1517 1574
1518 1575 /**
1519 1576 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1520 1577 * @hw: pointer to hardware structure
1521 1578 * @data: data byte to clock in
1522 1579 *
1523 1580 * Clocks in one byte data via I2C data/clock
1524 1581 **/
1525 1582 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1526 1583 {
1527 - s32 status = IXGBE_SUCCESS;
1528 1584 s32 i;
1529 1585 bool bit = 0;
1530 1586
1531 1587 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1532 1588
1533 1589 for (i = 7; i >= 0; i--) {
1534 - status = ixgbe_clock_in_i2c_bit(hw, &bit);
1590 + ixgbe_clock_in_i2c_bit(hw, &bit);
1535 1591 *data |= bit << i;
1536 -
1537 - if (status != IXGBE_SUCCESS)
1538 - break;
1539 1592 }
1540 1593
1541 - return status;
1594 + return IXGBE_SUCCESS;
1542 1595 }
1543 1596
1544 1597 /**
1545 1598 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1546 1599 * @hw: pointer to hardware structure
1547 1600 * @data: data byte clocked out
1548 1601 *
1549 1602 * Clocks out one byte data via I2C data/clock
1550 1603 **/
1551 1604 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1552 1605 {
1553 1606 s32 status = IXGBE_SUCCESS;
1554 1607 s32 i;
1555 1608 u32 i2cctl;
1556 1609 bool bit = 0;
1557 1610
1558 1611 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1559 1612
1560 1613 for (i = 7; i >= 0; i--) {
1561 1614 bit = (data >> i) & 0x1;
|
↓ open down ↓ |
10 lines elided |
↑ open up ↑ |
1562 1615 status = ixgbe_clock_out_i2c_bit(hw, bit);
1563 1616
1564 1617 if (status != IXGBE_SUCCESS)
1565 1618 break;
1566 1619 }
1567 1620
1568 1621 /* Release SDA line (set high) */
1569 1622 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1570 1623 i2cctl |= IXGBE_I2C_DATA_OUT;
1571 1624 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1625 + IXGBE_WRITE_FLUSH(hw);
1572 1626
1573 1627 return status;
1574 1628 }
1575 1629
1576 1630 /**
1577 1631 * ixgbe_get_i2c_ack - Polls for I2C ACK
1578 1632 * @hw: pointer to hardware structure
1579 1633 *
1580 1634 * Clocks in/out one bit via I2C data/clock
1581 1635 **/
1582 1636 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1583 1637 {
1584 - s32 status;
1638 + s32 status = IXGBE_SUCCESS;
1585 1639 u32 i = 0;
1586 1640 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1587 1641 u32 timeout = 10;
1588 1642 bool ack = 1;
1589 1643
1590 1644 DEBUGFUNC("ixgbe_get_i2c_ack");
1591 1645
1592 - status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1646 + ixgbe_raise_i2c_clk(hw, &i2cctl);
1593 1647
1594 - if (status != IXGBE_SUCCESS)
1595 - goto out;
1596 1648
1597 1649 /* Minimum high period of clock is 4us */
1598 1650 usec_delay(IXGBE_I2C_T_HIGH);
1599 1651
1600 1652 /* Poll for ACK. Note that ACK in I2C spec is
1601 1653 * transition from 1 to 0 */
1602 1654 for (i = 0; i < timeout; i++) {
1603 1655 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1604 1656 ack = ixgbe_get_i2c_data(&i2cctl);
1605 1657
1606 1658 usec_delay(1);
1607 1659 if (ack == 0)
1608 1660 break;
1609 1661 }
1610 1662
|
↓ open down ↓ |
5 lines elided |
↑ open up ↑ |
1611 1663 if (ack == 1) {
1612 1664 DEBUGOUT("I2C ack was not received.\n");
1613 1665 status = IXGBE_ERR_I2C;
1614 1666 }
1615 1667
1616 1668 ixgbe_lower_i2c_clk(hw, &i2cctl);
1617 1669
1618 1670 /* Minimum low period of clock is 4.7 us */
1619 1671 usec_delay(IXGBE_I2C_T_LOW);
1620 1672
1621 -out:
1622 1673 return status;
1623 1674 }
1624 1675
1625 1676 /**
1626 1677 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1627 1678 * @hw: pointer to hardware structure
1628 1679 * @data: read data value
1629 1680 *
1630 1681 * Clocks in one bit via I2C data/clock
1631 1682 **/
1632 1683 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1633 1684 {
1634 - s32 status;
1635 1685 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1636 1686
1637 1687 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1638 1688
1639 - status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1689 + ixgbe_raise_i2c_clk(hw, &i2cctl);
1640 1690
1641 1691 /* Minimum high period of clock is 4us */
1642 1692 usec_delay(IXGBE_I2C_T_HIGH);
1643 1693
1644 1694 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1645 1695 *data = ixgbe_get_i2c_data(&i2cctl);
1646 1696
1647 1697 ixgbe_lower_i2c_clk(hw, &i2cctl);
1648 1698
1649 1699 /* Minimum low period of clock is 4.7 us */
1650 1700 usec_delay(IXGBE_I2C_T_LOW);
1651 1701
1652 - return status;
1702 + return IXGBE_SUCCESS;
1653 1703 }
1654 1704
1655 1705 /**
1656 1706 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1657 1707 * @hw: pointer to hardware structure
1658 1708 * @data: data value to write
1659 1709 *
1660 1710 * Clocks out one bit via I2C data/clock
1661 1711 **/
1662 1712 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1663 1713 {
1664 1714 s32 status;
1665 1715 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1666 1716
1667 1717 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1668 1718
1669 1719 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1670 1720 if (status == IXGBE_SUCCESS) {
1671 - status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1721 + ixgbe_raise_i2c_clk(hw, &i2cctl);
1672 1722
1673 1723 /* Minimum high period of clock is 4us */
1674 1724 usec_delay(IXGBE_I2C_T_HIGH);
1675 1725
1676 1726 ixgbe_lower_i2c_clk(hw, &i2cctl);
1677 1727
1678 1728 /* Minimum low period of clock is 4.7 us.
1679 1729 * This also takes care of the data hold time.
1680 1730 */
1681 1731 usec_delay(IXGBE_I2C_T_LOW);
1682 1732 } else {
1683 1733 status = IXGBE_ERR_I2C;
1684 1734 DEBUGOUT1("I2C data was not set to %X\n", data);
1685 1735 }
|
↓ open down ↓ |
4 lines elided |
↑ open up ↑ |
1686 1736
1687 1737 return status;
1688 1738 }
1689 1739 /**
1690 1740 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1691 1741 * @hw: pointer to hardware structure
1692 1742 * @i2cctl: Current value of I2CCTL register
1693 1743 *
1694 1744 * Raises the I2C clock line '0'->'1'
1695 1745 **/
1696 -static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1746 +static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1697 1747 {
1698 - s32 status = IXGBE_SUCCESS;
1748 + u32 i = 0;
1749 + u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1750 + u32 i2cctl_r = 0;
1699 1751
1700 1752 DEBUGFUNC("ixgbe_raise_i2c_clk");
1701 1753
1702 - *i2cctl |= IXGBE_I2C_CLK_OUT;
1754 + for (i = 0; i < timeout; i++) {
1755 + *i2cctl |= IXGBE_I2C_CLK_OUT;
1703 1756
1704 - IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1757 + IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1758 + IXGBE_WRITE_FLUSH(hw);
1759 + /* SCL rise time (1000ns) */
1760 + usec_delay(IXGBE_I2C_T_RISE);
1705 1761
1706 - /* SCL rise time (1000ns) */
1707 - usec_delay(IXGBE_I2C_T_RISE);
1708 -
1709 - return status;
1762 + i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1763 + if (i2cctl_r & IXGBE_I2C_CLK_IN)
1764 + break;
1765 + }
1710 1766 }
1711 1767
1712 1768 /**
1713 1769 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1714 1770 * @hw: pointer to hardware structure
1715 1771 * @i2cctl: Current value of I2CCTL register
1716 1772 *
1717 1773 * Lowers the I2C clock line '1'->'0'
1718 1774 **/
1719 1775 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1720 1776 {
1721 1777
1722 1778 DEBUGFUNC("ixgbe_lower_i2c_clk");
1723 1779
1724 1780 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1725 1781
1726 1782 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1783 + IXGBE_WRITE_FLUSH(hw);
1727 1784
1728 1785 /* SCL fall time (300ns) */
1729 1786 usec_delay(IXGBE_I2C_T_FALL);
1730 1787 }
1731 1788
1732 1789 /**
1733 1790 * ixgbe_set_i2c_data - Sets the I2C data bit
1734 1791 * @hw: pointer to hardware structure
1735 1792 * @i2cctl: Current value of I2CCTL register
1736 1793 * @data: I2C data value (0 or 1) to set
1737 1794 *
1738 1795 * Sets the I2C data bit
1739 1796 **/
1740 1797 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1741 1798 {
|
↓ open down ↓ |
5 lines elided |
↑ open up ↑ |
1742 1799 s32 status = IXGBE_SUCCESS;
1743 1800
1744 1801 DEBUGFUNC("ixgbe_set_i2c_data");
1745 1802
1746 1803 if (data)
1747 1804 *i2cctl |= IXGBE_I2C_DATA_OUT;
1748 1805 else
1749 1806 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1750 1807
1751 1808 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1809 + IXGBE_WRITE_FLUSH(hw);
1752 1810
1753 1811 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1754 1812 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1755 1813
1756 1814 /* Verify data was set correctly */
1757 1815 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1758 1816 if (data != ixgbe_get_i2c_data(i2cctl)) {
1759 1817 status = IXGBE_ERR_I2C;
1760 1818 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1761 1819 }
1762 1820
1763 1821 return status;
1764 1822 }
1765 1823
1766 1824 /**
1767 1825 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1768 1826 * @hw: pointer to hardware structure
1769 1827 * @i2cctl: Current value of I2CCTL register
1770 1828 *
1771 1829 * Returns the I2C data bit value
1772 1830 **/
1773 1831 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1774 1832 {
1775 1833 bool data;
1776 1834
1777 1835 DEBUGFUNC("ixgbe_get_i2c_data");
1778 1836
1779 1837 if (*i2cctl & IXGBE_I2C_DATA_IN)
1780 1838 data = 1;
1781 1839 else
1782 1840 data = 0;
1783 1841
1784 1842 return data;
1785 1843 }
1786 1844
1787 1845 /**
1788 1846 * ixgbe_i2c_bus_clear - Clears the I2C bus
1789 1847 * @hw: pointer to hardware structure
1790 1848 *
1791 1849 * Clears the I2C bus by sending nine clock pulses.
1792 1850 * Used when data line is stuck low.
|
↓ open down ↓ |
31 lines elided |
↑ open up ↑ |
1793 1851 **/
1794 1852 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1795 1853 {
1796 1854 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1797 1855 u32 i;
1798 1856
1799 1857 DEBUGFUNC("ixgbe_i2c_bus_clear");
1800 1858
1801 1859 ixgbe_i2c_start(hw);
1802 1860
1803 - (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1861 + ixgbe_set_i2c_data(hw, &i2cctl, 1);
1804 1862
1805 1863 for (i = 0; i < 9; i++) {
1806 - (void) ixgbe_raise_i2c_clk(hw, &i2cctl);
1864 + ixgbe_raise_i2c_clk(hw, &i2cctl);
1807 1865
1808 1866 /* Min high period of clock is 4us */
1809 1867 usec_delay(IXGBE_I2C_T_HIGH);
1810 1868
1811 1869 ixgbe_lower_i2c_clk(hw, &i2cctl);
1812 1870
1813 1871 /* Min low period of clock is 4.7us*/
1814 1872 usec_delay(IXGBE_I2C_T_LOW);
1815 1873 }
1816 1874
1817 1875 ixgbe_i2c_start(hw);
1818 1876
1819 1877 /* Put the i2c bus back to default state */
1820 1878 ixgbe_i2c_stop(hw);
1821 1879 }
1822 1880
1823 1881 /**
1824 - * ixgbe_tn_check_overtemp - Checks if an overtemp occured.
1882 + * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1825 1883 * @hw: pointer to hardware structure
1826 1884 *
1827 1885 * Checks if the LASI temp alarm status was triggered due to overtemp
1828 1886 **/
1829 1887 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1830 1888 {
1831 1889 s32 status = IXGBE_SUCCESS;
1832 1890 u16 phy_data = 0;
1833 1891
1834 1892 DEBUGFUNC("ixgbe_tn_check_overtemp");
1835 1893
1836 1894 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1837 1895 goto out;
1838 1896
1839 1897 /* Check that the LASI temp alarm status was triggered */
1840 1898 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1841 1899 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1842 1900
1843 1901 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1844 1902 goto out;
1845 1903
1846 1904 status = IXGBE_ERR_OVERTEMP;
1847 1905 out:
1848 1906 return status;
1849 1907 }
|
↓ open down ↓ |
15 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX