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--- old/usr/src/uts/common/io/ixgbe/ixgbe_main.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_main.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
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18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 24 */
25 25
26 26 /*
27 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 + * Copyright (c) 2012, Joyent, Inc. All rights reserved.
29 + * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
28 30 */
29 31
30 32 #include "ixgbe_sw.h"
31 33
32 34 static char ixgbe_ident[] = "Intel 10Gb Ethernet";
33 35 static char ixgbe_version[] = "ixgbe 1.1.7";
34 36
35 37 /*
36 38 * Local function protoypes
37 39 */
38 40 static int ixgbe_register_mac(ixgbe_t *);
39 41 static int ixgbe_identify_hardware(ixgbe_t *);
40 42 static int ixgbe_regs_map(ixgbe_t *);
41 43 static void ixgbe_init_properties(ixgbe_t *);
42 44 static int ixgbe_init_driver_settings(ixgbe_t *);
43 45 static void ixgbe_init_locks(ixgbe_t *);
44 46 static void ixgbe_destroy_locks(ixgbe_t *);
45 47 static int ixgbe_init(ixgbe_t *);
46 48 static int ixgbe_chip_start(ixgbe_t *);
47 49 static void ixgbe_chip_stop(ixgbe_t *);
48 50 static int ixgbe_reset(ixgbe_t *);
49 51 static void ixgbe_tx_clean(ixgbe_t *);
50 52 static boolean_t ixgbe_tx_drain(ixgbe_t *);
51 53 static boolean_t ixgbe_rx_drain(ixgbe_t *);
52 54 static int ixgbe_alloc_rings(ixgbe_t *);
53 55 static void ixgbe_free_rings(ixgbe_t *);
54 56 static int ixgbe_alloc_rx_data(ixgbe_t *);
55 57 static void ixgbe_free_rx_data(ixgbe_t *);
56 58 static void ixgbe_setup_rings(ixgbe_t *);
57 59 static void ixgbe_setup_rx(ixgbe_t *);
58 60 static void ixgbe_setup_tx(ixgbe_t *);
59 61 static void ixgbe_setup_rx_ring(ixgbe_rx_ring_t *);
60 62 static void ixgbe_setup_tx_ring(ixgbe_tx_ring_t *);
61 63 static void ixgbe_setup_rss(ixgbe_t *);
62 64 static void ixgbe_setup_vmdq(ixgbe_t *);
63 65 static void ixgbe_setup_vmdq_rss(ixgbe_t *);
64 66 static void ixgbe_init_unicst(ixgbe_t *);
65 67 static int ixgbe_unicst_find(ixgbe_t *, const uint8_t *);
66 68 static void ixgbe_setup_multicst(ixgbe_t *);
67 69 static void ixgbe_get_hw_state(ixgbe_t *);
68 70 static void ixgbe_setup_vmdq_rss_conf(ixgbe_t *ixgbe);
69 71 static void ixgbe_get_conf(ixgbe_t *);
70 72 static void ixgbe_init_params(ixgbe_t *);
71 73 static int ixgbe_get_prop(ixgbe_t *, char *, int, int, int);
72 74 static void ixgbe_driver_link_check(ixgbe_t *);
73 75 static void ixgbe_sfp_check(void *);
74 76 static void ixgbe_overtemp_check(void *);
75 77 static void ixgbe_link_timer(void *);
76 78 static void ixgbe_local_timer(void *);
77 79 static void ixgbe_arm_watchdog_timer(ixgbe_t *);
78 80 static void ixgbe_restart_watchdog_timer(ixgbe_t *);
79 81 static void ixgbe_disable_adapter_interrupts(ixgbe_t *);
80 82 static void ixgbe_enable_adapter_interrupts(ixgbe_t *);
81 83 static boolean_t is_valid_mac_addr(uint8_t *);
82 84 static boolean_t ixgbe_stall_check(ixgbe_t *);
83 85 static boolean_t ixgbe_set_loopback_mode(ixgbe_t *, uint32_t);
84 86 static void ixgbe_set_internal_mac_loopback(ixgbe_t *);
85 87 static boolean_t ixgbe_find_mac_address(ixgbe_t *);
86 88 static int ixgbe_alloc_intrs(ixgbe_t *);
87 89 static int ixgbe_alloc_intr_handles(ixgbe_t *, int);
88 90 static int ixgbe_add_intr_handlers(ixgbe_t *);
89 91 static void ixgbe_map_rxring_to_vector(ixgbe_t *, int, int);
90 92 static void ixgbe_map_txring_to_vector(ixgbe_t *, int, int);
91 93 static void ixgbe_setup_ivar(ixgbe_t *, uint16_t, uint8_t, int8_t);
92 94 static void ixgbe_enable_ivar(ixgbe_t *, uint16_t, int8_t);
93 95 static void ixgbe_disable_ivar(ixgbe_t *, uint16_t, int8_t);
94 96 static uint32_t ixgbe_get_hw_rx_index(ixgbe_t *ixgbe, uint32_t sw_rx_index);
95 97 static int ixgbe_map_intrs_to_vectors(ixgbe_t *);
96 98 static void ixgbe_setup_adapter_vector(ixgbe_t *);
97 99 static void ixgbe_rem_intr_handlers(ixgbe_t *);
98 100 static void ixgbe_rem_intrs(ixgbe_t *);
99 101 static int ixgbe_enable_intrs(ixgbe_t *);
100 102 static int ixgbe_disable_intrs(ixgbe_t *);
101 103 static uint_t ixgbe_intr_legacy(void *, void *);
102 104 static uint_t ixgbe_intr_msi(void *, void *);
103 105 static uint_t ixgbe_intr_msix(void *, void *);
104 106 static void ixgbe_intr_rx_work(ixgbe_rx_ring_t *);
105 107 static void ixgbe_intr_tx_work(ixgbe_tx_ring_t *);
106 108 static void ixgbe_intr_other_work(ixgbe_t *, uint32_t);
107 109 static void ixgbe_get_driver_control(struct ixgbe_hw *);
108 110 static int ixgbe_addmac(void *, const uint8_t *);
109 111 static int ixgbe_remmac(void *, const uint8_t *);
110 112 static void ixgbe_release_driver_control(struct ixgbe_hw *);
111 113
112 114 static int ixgbe_attach(dev_info_t *, ddi_attach_cmd_t);
113 115 static int ixgbe_detach(dev_info_t *, ddi_detach_cmd_t);
114 116 static int ixgbe_resume(dev_info_t *);
115 117 static int ixgbe_suspend(dev_info_t *);
116 118 static void ixgbe_unconfigure(dev_info_t *, ixgbe_t *);
117 119 static uint8_t *ixgbe_mc_table_itr(struct ixgbe_hw *, uint8_t **, uint32_t *);
118 120 static int ixgbe_cbfunc(dev_info_t *, ddi_cb_action_t, void *, void *, void *);
119 121 static int ixgbe_intr_cb_register(ixgbe_t *);
120 122 static int ixgbe_intr_adjust(ixgbe_t *, ddi_cb_action_t, int);
121 123
122 124 static int ixgbe_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err,
123 125 const void *impl_data);
124 126 static void ixgbe_fm_init(ixgbe_t *);
125 127 static void ixgbe_fm_fini(ixgbe_t *);
126 128
127 129 char *ixgbe_priv_props[] = {
128 130 "_tx_copy_thresh",
129 131 "_tx_recycle_thresh",
130 132 "_tx_overload_thresh",
131 133 "_tx_resched_thresh",
132 134 "_rx_copy_thresh",
133 135 "_rx_limit_per_intr",
134 136 "_intr_throttling",
135 137 "_adv_pause_cap",
136 138 "_adv_asym_pause_cap",
137 139 NULL
138 140 };
139 141
140 142 #define IXGBE_MAX_PRIV_PROPS \
141 143 (sizeof (ixgbe_priv_props) / sizeof (mac_priv_prop_t))
142 144
143 145 static struct cb_ops ixgbe_cb_ops = {
144 146 nulldev, /* cb_open */
145 147 nulldev, /* cb_close */
146 148 nodev, /* cb_strategy */
147 149 nodev, /* cb_print */
148 150 nodev, /* cb_dump */
149 151 nodev, /* cb_read */
150 152 nodev, /* cb_write */
151 153 nodev, /* cb_ioctl */
152 154 nodev, /* cb_devmap */
153 155 nodev, /* cb_mmap */
154 156 nodev, /* cb_segmap */
155 157 nochpoll, /* cb_chpoll */
156 158 ddi_prop_op, /* cb_prop_op */
157 159 NULL, /* cb_stream */
158 160 D_MP | D_HOTPLUG, /* cb_flag */
159 161 CB_REV, /* cb_rev */
160 162 nodev, /* cb_aread */
161 163 nodev /* cb_awrite */
162 164 };
163 165
164 166 static struct dev_ops ixgbe_dev_ops = {
165 167 DEVO_REV, /* devo_rev */
166 168 0, /* devo_refcnt */
167 169 NULL, /* devo_getinfo */
168 170 nulldev, /* devo_identify */
169 171 nulldev, /* devo_probe */
170 172 ixgbe_attach, /* devo_attach */
171 173 ixgbe_detach, /* devo_detach */
172 174 nodev, /* devo_reset */
173 175 &ixgbe_cb_ops, /* devo_cb_ops */
174 176 NULL, /* devo_bus_ops */
175 177 ddi_power, /* devo_power */
176 178 ddi_quiesce_not_supported, /* devo_quiesce */
177 179 };
178 180
179 181 static struct modldrv ixgbe_modldrv = {
180 182 &mod_driverops, /* Type of module. This one is a driver */
181 183 ixgbe_ident, /* Discription string */
182 184 &ixgbe_dev_ops /* driver ops */
183 185 };
184 186
185 187 static struct modlinkage ixgbe_modlinkage = {
186 188 MODREV_1, &ixgbe_modldrv, NULL
187 189 };
188 190
189 191 /*
190 192 * Access attributes for register mapping
191 193 */
192 194 ddi_device_acc_attr_t ixgbe_regs_acc_attr = {
193 195 DDI_DEVICE_ATTR_V1,
194 196 DDI_STRUCTURE_LE_ACC,
195 197 DDI_STRICTORDER_ACC,
196 198 DDI_FLAGERR_ACC
197 199 };
198 200
199 201 /*
200 202 * Loopback property
201 203 */
202 204 static lb_property_t lb_normal = {
203 205 normal, "normal", IXGBE_LB_NONE
204 206 };
205 207
206 208 static lb_property_t lb_mac = {
207 209 internal, "MAC", IXGBE_LB_INTERNAL_MAC
208 210 };
209 211
210 212 static lb_property_t lb_external = {
211 213 external, "External", IXGBE_LB_EXTERNAL
212 214 };
213 215
214 216 #define IXGBE_M_CALLBACK_FLAGS \
215 217 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO)
216 218
217 219 static mac_callbacks_t ixgbe_m_callbacks = {
218 220 IXGBE_M_CALLBACK_FLAGS,
219 221 ixgbe_m_stat,
220 222 ixgbe_m_start,
221 223 ixgbe_m_stop,
222 224 ixgbe_m_promisc,
223 225 ixgbe_m_multicst,
224 226 NULL,
225 227 NULL,
226 228 NULL,
227 229 ixgbe_m_ioctl,
228 230 ixgbe_m_getcapab,
229 231 NULL,
230 232 NULL,
231 233 ixgbe_m_setprop,
232 234 ixgbe_m_getprop,
233 235 ixgbe_m_propinfo
234 236 };
235 237
236 238 /*
237 239 * Initialize capabilities of each supported adapter type
238 240 */
239 241 static adapter_info_t ixgbe_82598eb_cap = {
240 242 64, /* maximum number of rx queues */
241 243 1, /* minimum number of rx queues */
242 244 64, /* default number of rx queues */
243 245 16, /* maximum number of rx groups */
244 246 1, /* minimum number of rx groups */
245 247 1, /* default number of rx groups */
246 248 32, /* maximum number of tx queues */
247 249 1, /* minimum number of tx queues */
248 250 8, /* default number of tx queues */
249 251 16366, /* maximum MTU size */
250 252 0xFFFF, /* maximum interrupt throttle rate */
251 253 0, /* minimum interrupt throttle rate */
252 254 200, /* default interrupt throttle rate */
253 255 18, /* maximum total msix vectors */
254 256 16, /* maximum number of ring vectors */
255 257 2, /* maximum number of other vectors */
256 258 IXGBE_EICR_LSC, /* "other" interrupt types handled */
257 259 0, /* "other" interrupt types enable mask */
258 260 (IXGBE_FLAG_DCA_CAPABLE /* capability flags */
259 261 | IXGBE_FLAG_RSS_CAPABLE
260 262 | IXGBE_FLAG_VMDQ_CAPABLE)
261 263 };
262 264
263 265 static adapter_info_t ixgbe_82599eb_cap = {
264 266 128, /* maximum number of rx queues */
265 267 1, /* minimum number of rx queues */
266 268 128, /* default number of rx queues */
267 269 64, /* maximum number of rx groups */
268 270 1, /* minimum number of rx groups */
269 271 1, /* default number of rx groups */
270 272 128, /* maximum number of tx queues */
271 273 1, /* minimum number of tx queues */
272 274 8, /* default number of tx queues */
273 275 15500, /* maximum MTU size */
274 276 0xFF8, /* maximum interrupt throttle rate */
275 277 0, /* minimum interrupt throttle rate */
276 278 200, /* default interrupt throttle rate */
277 279 64, /* maximum total msix vectors */
278 280 16, /* maximum number of ring vectors */
279 281 2, /* maximum number of other vectors */
280 282 (IXGBE_EICR_LSC
281 283 | IXGBE_EICR_GPI_SDP1
282 284 | IXGBE_EICR_GPI_SDP2), /* "other" interrupt types handled */
283 285
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284 286 (IXGBE_SDP1_GPIEN
285 287 | IXGBE_SDP2_GPIEN), /* "other" interrupt types enable mask */
286 288
287 289 (IXGBE_FLAG_DCA_CAPABLE
288 290 | IXGBE_FLAG_RSS_CAPABLE
289 291 | IXGBE_FLAG_VMDQ_CAPABLE
290 292 | IXGBE_FLAG_RSC_CAPABLE
291 293 | IXGBE_FLAG_SFP_PLUG_CAPABLE) /* capability flags */
292 294 };
293 295
296 +static adapter_info_t ixgbe_X540_cap = {
297 + 128, /* maximum number of rx queues */
298 + 1, /* minimum number of rx queues */
299 + 128, /* default number of rx queues */
300 + 64, /* maximum number of rx groups */
301 + 1, /* minimum number of rx groups */
302 + 1, /* default number of rx groups */
303 + 128, /* maximum number of tx queues */
304 + 1, /* minimum number of tx queues */
305 + 8, /* default number of tx queues */
306 + 15500, /* maximum MTU size */
307 + 0xFF8, /* maximum interrupt throttle rate */
308 + 0, /* minimum interrupt throttle rate */
309 + 200, /* default interrupt throttle rate */
310 + 64, /* maximum total msix vectors */
311 + 16, /* maximum number of ring vectors */
312 + 2, /* maximum number of other vectors */
313 + (IXGBE_EICR_LSC
314 + | IXGBE_EICR_GPI_SDP1
315 + | IXGBE_EICR_GPI_SDP2), /* "other" interrupt types handled */
316 +
317 + (IXGBE_SDP1_GPIEN
318 + | IXGBE_SDP2_GPIEN), /* "other" interrupt types enable mask */
319 +
320 + (IXGBE_FLAG_DCA_CAPABLE
321 + | IXGBE_FLAG_RSS_CAPABLE
322 + | IXGBE_FLAG_VMDQ_CAPABLE
323 + | IXGBE_FLAG_RSC_CAPABLE) /* capability flags */
324 +};
325 +
294 326 /*
295 327 * Module Initialization Functions.
296 328 */
297 329
298 330 int
299 331 _init(void)
300 332 {
301 333 int status;
302 334
303 335 mac_init_ops(&ixgbe_dev_ops, MODULE_NAME);
304 336
305 337 status = mod_install(&ixgbe_modlinkage);
306 338
307 339 if (status != DDI_SUCCESS) {
308 340 mac_fini_ops(&ixgbe_dev_ops);
309 341 }
310 342
311 343 return (status);
312 344 }
313 345
314 346 int
315 347 _fini(void)
316 348 {
317 349 int status;
318 350
319 351 status = mod_remove(&ixgbe_modlinkage);
320 352
321 353 if (status == DDI_SUCCESS) {
322 354 mac_fini_ops(&ixgbe_dev_ops);
323 355 }
324 356
325 357 return (status);
326 358 }
327 359
328 360 int
329 361 _info(struct modinfo *modinfop)
330 362 {
331 363 int status;
332 364
333 365 status = mod_info(&ixgbe_modlinkage, modinfop);
334 366
335 367 return (status);
336 368 }
337 369
338 370 /*
339 371 * ixgbe_attach - Driver attach.
340 372 *
341 373 * This function is the device specific initialization entry
342 374 * point. This entry point is required and must be written.
343 375 * The DDI_ATTACH command must be provided in the attach entry
344 376 * point. When attach() is called with cmd set to DDI_ATTACH,
345 377 * all normal kernel services (such as kmem_alloc(9F)) are
346 378 * available for use by the driver.
347 379 *
348 380 * The attach() function will be called once for each instance
349 381 * of the device on the system with cmd set to DDI_ATTACH.
350 382 * Until attach() succeeds, the only driver entry points which
351 383 * may be called are open(9E) and getinfo(9E).
352 384 */
353 385 static int
354 386 ixgbe_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
355 387 {
356 388 ixgbe_t *ixgbe;
357 389 struct ixgbe_osdep *osdep;
358 390 struct ixgbe_hw *hw;
359 391 int instance;
360 392 char taskqname[32];
361 393
362 394 /*
363 395 * Check the command and perform corresponding operations
364 396 */
365 397 switch (cmd) {
366 398 default:
367 399 return (DDI_FAILURE);
368 400
369 401 case DDI_RESUME:
370 402 return (ixgbe_resume(devinfo));
371 403
372 404 case DDI_ATTACH:
373 405 break;
374 406 }
375 407
376 408 /* Get the device instance */
377 409 instance = ddi_get_instance(devinfo);
378 410
379 411 /* Allocate memory for the instance data structure */
380 412 ixgbe = kmem_zalloc(sizeof (ixgbe_t), KM_SLEEP);
381 413
382 414 ixgbe->dip = devinfo;
383 415 ixgbe->instance = instance;
384 416
385 417 hw = &ixgbe->hw;
386 418 osdep = &ixgbe->osdep;
387 419 hw->back = osdep;
388 420 osdep->ixgbe = ixgbe;
389 421
390 422 /* Attach the instance pointer to the dev_info data structure */
391 423 ddi_set_driver_private(devinfo, ixgbe);
392 424
393 425 /*
394 426 * Initialize for fma support
395 427 */
396 428 ixgbe->fm_capabilities = ixgbe_get_prop(ixgbe, PROP_FM_CAPABLE,
397 429 0, 0x0f, DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
398 430 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
399 431 ixgbe_fm_init(ixgbe);
400 432 ixgbe->attach_progress |= ATTACH_PROGRESS_FM_INIT;
401 433
402 434 /*
403 435 * Map PCI config space registers
404 436 */
405 437 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) {
406 438 ixgbe_error(ixgbe, "Failed to map PCI configurations");
407 439 goto attach_fail;
408 440 }
409 441 ixgbe->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG;
410 442
411 443 /*
412 444 * Identify the chipset family
413 445 */
414 446 if (ixgbe_identify_hardware(ixgbe) != IXGBE_SUCCESS) {
415 447 ixgbe_error(ixgbe, "Failed to identify hardware");
416 448 goto attach_fail;
417 449 }
418 450
419 451 /*
420 452 * Map device registers
421 453 */
422 454 if (ixgbe_regs_map(ixgbe) != IXGBE_SUCCESS) {
423 455 ixgbe_error(ixgbe, "Failed to map device registers");
424 456 goto attach_fail;
425 457 }
426 458 ixgbe->attach_progress |= ATTACH_PROGRESS_REGS_MAP;
427 459
428 460 /*
429 461 * Initialize driver parameters
430 462 */
431 463 ixgbe_init_properties(ixgbe);
432 464 ixgbe->attach_progress |= ATTACH_PROGRESS_PROPS;
433 465
434 466 /*
435 467 * Register interrupt callback
436 468 */
437 469 if (ixgbe_intr_cb_register(ixgbe) != IXGBE_SUCCESS) {
438 470 ixgbe_error(ixgbe, "Failed to register interrupt callback");
439 471 goto attach_fail;
440 472 }
441 473
442 474 /*
443 475 * Allocate interrupts
444 476 */
445 477 if (ixgbe_alloc_intrs(ixgbe) != IXGBE_SUCCESS) {
446 478 ixgbe_error(ixgbe, "Failed to allocate interrupts");
447 479 goto attach_fail;
448 480 }
449 481 ixgbe->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR;
450 482
451 483 /*
452 484 * Allocate rx/tx rings based on the ring numbers.
453 485 * The actual numbers of rx/tx rings are decided by the number of
454 486 * allocated interrupt vectors, so we should allocate the rings after
455 487 * interrupts are allocated.
456 488 */
457 489 if (ixgbe_alloc_rings(ixgbe) != IXGBE_SUCCESS) {
458 490 ixgbe_error(ixgbe, "Failed to allocate rx and tx rings");
459 491 goto attach_fail;
460 492 }
461 493 ixgbe->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS;
462 494
463 495 /*
464 496 * Map rings to interrupt vectors
465 497 */
466 498 if (ixgbe_map_intrs_to_vectors(ixgbe) != IXGBE_SUCCESS) {
467 499 ixgbe_error(ixgbe, "Failed to map interrupts to vectors");
468 500 goto attach_fail;
469 501 }
470 502
471 503 /*
472 504 * Add interrupt handlers
473 505 */
474 506 if (ixgbe_add_intr_handlers(ixgbe) != IXGBE_SUCCESS) {
475 507 ixgbe_error(ixgbe, "Failed to add interrupt handlers");
476 508 goto attach_fail;
477 509 }
478 510 ixgbe->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
479 511
480 512 /*
481 513 * Create a taskq for sfp-change
482 514 */
483 515 (void) sprintf(taskqname, "ixgbe%d_sfp_taskq", instance);
484 516 if ((ixgbe->sfp_taskq = ddi_taskq_create(devinfo, taskqname,
485 517 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
486 518 ixgbe_error(ixgbe, "sfp_taskq create failed");
487 519 goto attach_fail;
488 520 }
489 521 ixgbe->attach_progress |= ATTACH_PROGRESS_SFP_TASKQ;
490 522
491 523 /*
492 524 * Create a taskq for over-temp
493 525 */
494 526 (void) sprintf(taskqname, "ixgbe%d_overtemp_taskq", instance);
495 527 if ((ixgbe->overtemp_taskq = ddi_taskq_create(devinfo, taskqname,
496 528 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
497 529 ixgbe_error(ixgbe, "overtemp_taskq create failed");
498 530 goto attach_fail;
499 531 }
500 532 ixgbe->attach_progress |= ATTACH_PROGRESS_OVERTEMP_TASKQ;
501 533
502 534 /*
503 535 * Initialize driver parameters
504 536 */
505 537 if (ixgbe_init_driver_settings(ixgbe) != IXGBE_SUCCESS) {
506 538 ixgbe_error(ixgbe, "Failed to initialize driver settings");
507 539 goto attach_fail;
508 540 }
509 541
510 542 /*
511 543 * Initialize mutexes for this device.
512 544 * Do this before enabling the interrupt handler and
513 545 * register the softint to avoid the condition where
514 546 * interrupt handler can try using uninitialized mutex.
515 547 */
516 548 ixgbe_init_locks(ixgbe);
517 549 ixgbe->attach_progress |= ATTACH_PROGRESS_LOCKS;
518 550
519 551 /*
520 552 * Initialize chipset hardware
521 553 */
522 554 if (ixgbe_init(ixgbe) != IXGBE_SUCCESS) {
523 555 ixgbe_error(ixgbe, "Failed to initialize adapter");
524 556 goto attach_fail;
525 557 }
526 558 ixgbe->link_check_complete = B_FALSE;
527 559 ixgbe->link_check_hrtime = gethrtime() +
528 560 (IXGBE_LINK_UP_TIME * 100000000ULL);
529 561 ixgbe->attach_progress |= ATTACH_PROGRESS_INIT;
530 562
531 563 if (ixgbe_check_acc_handle(ixgbe->osdep.cfg_handle) != DDI_FM_OK) {
532 564 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
533 565 goto attach_fail;
534 566 }
535 567
536 568 /*
537 569 * Initialize statistics
538 570 */
539 571 if (ixgbe_init_stats(ixgbe) != IXGBE_SUCCESS) {
540 572 ixgbe_error(ixgbe, "Failed to initialize statistics");
541 573 goto attach_fail;
542 574 }
543 575 ixgbe->attach_progress |= ATTACH_PROGRESS_STATS;
544 576
545 577 /*
546 578 * Register the driver to the MAC
547 579 */
548 580 if (ixgbe_register_mac(ixgbe) != IXGBE_SUCCESS) {
549 581 ixgbe_error(ixgbe, "Failed to register MAC");
550 582 goto attach_fail;
551 583 }
552 584 mac_link_update(ixgbe->mac_hdl, LINK_STATE_UNKNOWN);
553 585 ixgbe->attach_progress |= ATTACH_PROGRESS_MAC;
554 586
555 587 ixgbe->periodic_id = ddi_periodic_add(ixgbe_link_timer, ixgbe,
556 588 IXGBE_CYCLIC_PERIOD, DDI_IPL_0);
557 589 if (ixgbe->periodic_id == 0) {
558 590 ixgbe_error(ixgbe, "Failed to add the link check timer");
559 591 goto attach_fail;
560 592 }
561 593 ixgbe->attach_progress |= ATTACH_PROGRESS_LINK_TIMER;
562 594
563 595 /*
564 596 * Now that mutex locks are initialized, and the chip is also
565 597 * initialized, enable interrupts.
566 598 */
567 599 if (ixgbe_enable_intrs(ixgbe) != IXGBE_SUCCESS) {
568 600 ixgbe_error(ixgbe, "Failed to enable DDI interrupts");
569 601 goto attach_fail;
570 602 }
571 603 ixgbe->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
572 604
573 605 ixgbe_log(ixgbe, "%s, %s", ixgbe_ident, ixgbe_version);
574 606 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_INITIALIZED);
575 607
576 608 return (DDI_SUCCESS);
577 609
578 610 attach_fail:
579 611 ixgbe_unconfigure(devinfo, ixgbe);
580 612 return (DDI_FAILURE);
581 613 }
582 614
583 615 /*
584 616 * ixgbe_detach - Driver detach.
585 617 *
586 618 * The detach() function is the complement of the attach routine.
587 619 * If cmd is set to DDI_DETACH, detach() is used to remove the
588 620 * state associated with a given instance of a device node
589 621 * prior to the removal of that instance from the system.
590 622 *
591 623 * The detach() function will be called once for each instance
592 624 * of the device for which there has been a successful attach()
593 625 * once there are no longer any opens on the device.
594 626 *
595 627 * Interrupts routine are disabled, All memory allocated by this
596 628 * driver are freed.
597 629 */
598 630 static int
599 631 ixgbe_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
600 632 {
601 633 ixgbe_t *ixgbe;
602 634
603 635 /*
604 636 * Check detach command
605 637 */
606 638 switch (cmd) {
607 639 default:
608 640 return (DDI_FAILURE);
609 641
610 642 case DDI_SUSPEND:
611 643 return (ixgbe_suspend(devinfo));
612 644
613 645 case DDI_DETACH:
614 646 break;
615 647 }
616 648
617 649 /*
618 650 * Get the pointer to the driver private data structure
619 651 */
620 652 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo);
621 653 if (ixgbe == NULL)
622 654 return (DDI_FAILURE);
623 655
624 656 /*
625 657 * If the device is still running, it needs to be stopped first.
626 658 * This check is necessary because under some specific circumstances,
627 659 * the detach routine can be called without stopping the interface
628 660 * first.
629 661 */
630 662 if (ixgbe->ixgbe_state & IXGBE_STARTED) {
631 663 atomic_and_32(&ixgbe->ixgbe_state, ~IXGBE_STARTED);
632 664 mutex_enter(&ixgbe->gen_lock);
633 665 ixgbe_stop(ixgbe, B_TRUE);
634 666 mutex_exit(&ixgbe->gen_lock);
635 667 /* Disable and stop the watchdog timer */
636 668 ixgbe_disable_watchdog_timer(ixgbe);
637 669 }
638 670
639 671 /*
640 672 * Check if there are still rx buffers held by the upper layer.
641 673 * If so, fail the detach.
642 674 */
643 675 if (!ixgbe_rx_drain(ixgbe))
644 676 return (DDI_FAILURE);
645 677
646 678 /*
647 679 * Do the remaining unconfigure routines
648 680 */
649 681 ixgbe_unconfigure(devinfo, ixgbe);
650 682
651 683 return (DDI_SUCCESS);
652 684 }
653 685
654 686 static void
655 687 ixgbe_unconfigure(dev_info_t *devinfo, ixgbe_t *ixgbe)
656 688 {
657 689 /*
658 690 * Disable interrupt
659 691 */
660 692 if (ixgbe->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
661 693 (void) ixgbe_disable_intrs(ixgbe);
662 694 }
663 695
664 696 /*
665 697 * remove the link check timer
666 698 */
667 699 if (ixgbe->attach_progress & ATTACH_PROGRESS_LINK_TIMER) {
668 700 if (ixgbe->periodic_id != NULL) {
669 701 ddi_periodic_delete(ixgbe->periodic_id);
670 702 ixgbe->periodic_id = NULL;
671 703 }
672 704 }
673 705
674 706 /*
675 707 * Unregister MAC
676 708 */
677 709 if (ixgbe->attach_progress & ATTACH_PROGRESS_MAC) {
678 710 (void) mac_unregister(ixgbe->mac_hdl);
679 711 }
680 712
681 713 /*
682 714 * Free statistics
683 715 */
684 716 if (ixgbe->attach_progress & ATTACH_PROGRESS_STATS) {
685 717 kstat_delete((kstat_t *)ixgbe->ixgbe_ks);
686 718 }
687 719
688 720 /*
689 721 * Remove interrupt handlers
690 722 */
691 723 if (ixgbe->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
692 724 ixgbe_rem_intr_handlers(ixgbe);
693 725 }
694 726
695 727 /*
696 728 * Remove taskq for sfp-status-change
697 729 */
698 730 if (ixgbe->attach_progress & ATTACH_PROGRESS_SFP_TASKQ) {
699 731 ddi_taskq_destroy(ixgbe->sfp_taskq);
700 732 }
701 733
702 734 /*
703 735 * Remove taskq for over-temp
704 736 */
705 737 if (ixgbe->attach_progress & ATTACH_PROGRESS_OVERTEMP_TASKQ) {
706 738 ddi_taskq_destroy(ixgbe->overtemp_taskq);
707 739 }
708 740
709 741 /*
710 742 * Remove interrupts
711 743 */
712 744 if (ixgbe->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) {
713 745 ixgbe_rem_intrs(ixgbe);
714 746 }
715 747
716 748 /*
717 749 * Unregister interrupt callback handler
718 750 */
719 751 (void) ddi_cb_unregister(ixgbe->cb_hdl);
720 752
721 753 /*
722 754 * Remove driver properties
723 755 */
724 756 if (ixgbe->attach_progress & ATTACH_PROGRESS_PROPS) {
725 757 (void) ddi_prop_remove_all(devinfo);
726 758 }
727 759
728 760 /*
729 761 * Stop the chipset
730 762 */
731 763 if (ixgbe->attach_progress & ATTACH_PROGRESS_INIT) {
732 764 mutex_enter(&ixgbe->gen_lock);
733 765 ixgbe_chip_stop(ixgbe);
734 766 mutex_exit(&ixgbe->gen_lock);
735 767 }
736 768
737 769 /*
738 770 * Free register handle
739 771 */
740 772 if (ixgbe->attach_progress & ATTACH_PROGRESS_REGS_MAP) {
741 773 if (ixgbe->osdep.reg_handle != NULL)
742 774 ddi_regs_map_free(&ixgbe->osdep.reg_handle);
743 775 }
744 776
745 777 /*
746 778 * Free PCI config handle
747 779 */
748 780 if (ixgbe->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) {
749 781 if (ixgbe->osdep.cfg_handle != NULL)
750 782 pci_config_teardown(&ixgbe->osdep.cfg_handle);
751 783 }
752 784
753 785 /*
754 786 * Free locks
755 787 */
756 788 if (ixgbe->attach_progress & ATTACH_PROGRESS_LOCKS) {
757 789 ixgbe_destroy_locks(ixgbe);
758 790 }
759 791
760 792 /*
761 793 * Free the rx/tx rings
762 794 */
763 795 if (ixgbe->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) {
764 796 ixgbe_free_rings(ixgbe);
765 797 }
766 798
767 799 /*
768 800 * Unregister FMA capabilities
769 801 */
770 802 if (ixgbe->attach_progress & ATTACH_PROGRESS_FM_INIT) {
771 803 ixgbe_fm_fini(ixgbe);
772 804 }
773 805
774 806 /*
775 807 * Free the driver data structure
776 808 */
777 809 kmem_free(ixgbe, sizeof (ixgbe_t));
778 810
779 811 ddi_set_driver_private(devinfo, NULL);
780 812 }
781 813
782 814 /*
783 815 * ixgbe_register_mac - Register the driver and its function pointers with
784 816 * the GLD interface.
785 817 */
786 818 static int
787 819 ixgbe_register_mac(ixgbe_t *ixgbe)
788 820 {
789 821 struct ixgbe_hw *hw = &ixgbe->hw;
790 822 mac_register_t *mac;
791 823 int status;
792 824
793 825 if ((mac = mac_alloc(MAC_VERSION)) == NULL)
794 826 return (IXGBE_FAILURE);
795 827
796 828 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
797 829 mac->m_driver = ixgbe;
798 830 mac->m_dip = ixgbe->dip;
799 831 mac->m_src_addr = hw->mac.addr;
800 832 mac->m_callbacks = &ixgbe_m_callbacks;
801 833 mac->m_min_sdu = 0;
802 834 mac->m_max_sdu = ixgbe->default_mtu;
803 835 mac->m_margin = VLAN_TAGSZ;
804 836 mac->m_priv_props = ixgbe_priv_props;
805 837 mac->m_v12n = MAC_VIRT_LEVEL1;
806 838
807 839 status = mac_register(mac, &ixgbe->mac_hdl);
808 840
809 841 mac_free(mac);
810 842
811 843 return ((status == 0) ? IXGBE_SUCCESS : IXGBE_FAILURE);
812 844 }
813 845
814 846 /*
815 847 * ixgbe_identify_hardware - Identify the type of the chipset.
816 848 */
817 849 static int
818 850 ixgbe_identify_hardware(ixgbe_t *ixgbe)
819 851 {
820 852 struct ixgbe_hw *hw = &ixgbe->hw;
821 853 struct ixgbe_osdep *osdep = &ixgbe->osdep;
822 854
823 855 /*
824 856 * Get the device id
825 857 */
826 858 hw->vendor_id =
827 859 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID);
828 860 hw->device_id =
829 861 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID);
830 862 hw->revision_id =
831 863 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID);
832 864 hw->subsystem_device_id =
833 865 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID);
834 866 hw->subsystem_vendor_id =
835 867 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID);
836 868
837 869 /*
838 870 * Set the mac type of the adapter based on the device id
839 871 */
840 872 if (ixgbe_set_mac_type(hw) != IXGBE_SUCCESS) {
841 873 return (IXGBE_FAILURE);
842 874 }
843 875
844 876 /*
845 877 * Install adapter capabilities
846 878 */
847 879 switch (hw->mac.type) {
848 880 case ixgbe_mac_82598EB:
849 881 IXGBE_DEBUGLOG_0(ixgbe, "identify 82598 adapter\n");
850 882 ixgbe->capab = &ixgbe_82598eb_cap;
851 883
852 884 if (ixgbe_get_media_type(hw) == ixgbe_media_type_copper) {
853 885 ixgbe->capab->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
854 886 ixgbe->capab->other_intr |= IXGBE_EICR_GPI_SDP1;
855 887 ixgbe->capab->other_gpie |= IXGBE_SDP1_GPIEN;
856 888 }
857 889 break;
858 890
859 891 case ixgbe_mac_82599EB:
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860 892 IXGBE_DEBUGLOG_0(ixgbe, "identify 82599 adapter\n");
861 893 ixgbe->capab = &ixgbe_82599eb_cap;
862 894
863 895 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) {
864 896 ixgbe->capab->flags |= IXGBE_FLAG_TEMP_SENSOR_CAPABLE;
865 897 ixgbe->capab->other_intr |= IXGBE_EICR_GPI_SDP0;
866 898 ixgbe->capab->other_gpie |= IXGBE_SDP0_GPIEN;
867 899 }
868 900 break;
869 901
902 + case ixgbe_mac_X540:
903 + IXGBE_DEBUGLOG_0(ixgbe, "identify X540 adapter\n");
904 + ixgbe->capab = &ixgbe_X540_cap;
905 + /*
906 + * For now, X540 is all set in its capab structure.
907 + * As other X540 variants show up, things can change here.
908 + */
909 + break;
910 +
870 911 default:
871 912 IXGBE_DEBUGLOG_1(ixgbe,
872 913 "adapter not supported in ixgbe_identify_hardware(): %d\n",
873 914 hw->mac.type);
874 915 return (IXGBE_FAILURE);
875 916 }
876 917
877 918 return (IXGBE_SUCCESS);
878 919 }
879 920
880 921 /*
881 922 * ixgbe_regs_map - Map the device registers.
882 923 *
883 924 */
884 925 static int
885 926 ixgbe_regs_map(ixgbe_t *ixgbe)
886 927 {
887 928 dev_info_t *devinfo = ixgbe->dip;
888 929 struct ixgbe_hw *hw = &ixgbe->hw;
889 930 struct ixgbe_osdep *osdep = &ixgbe->osdep;
890 931 off_t mem_size;
891 932
892 933 /*
893 934 * First get the size of device registers to be mapped.
894 935 */
895 936 if (ddi_dev_regsize(devinfo, IXGBE_ADAPTER_REGSET, &mem_size)
896 937 != DDI_SUCCESS) {
897 938 return (IXGBE_FAILURE);
898 939 }
899 940
900 941 /*
901 942 * Call ddi_regs_map_setup() to map registers
902 943 */
903 944 if ((ddi_regs_map_setup(devinfo, IXGBE_ADAPTER_REGSET,
904 945 (caddr_t *)&hw->hw_addr, 0,
905 946 mem_size, &ixgbe_regs_acc_attr,
906 947 &osdep->reg_handle)) != DDI_SUCCESS) {
907 948 return (IXGBE_FAILURE);
908 949 }
909 950
910 951 return (IXGBE_SUCCESS);
911 952 }
912 953
913 954 /*
914 955 * ixgbe_init_properties - Initialize driver properties.
915 956 */
916 957 static void
917 958 ixgbe_init_properties(ixgbe_t *ixgbe)
918 959 {
919 960 /*
920 961 * Get conf file properties, including link settings
921 962 * jumbo frames, ring number, descriptor number, etc.
922 963 */
923 964 ixgbe_get_conf(ixgbe);
924 965
925 966 ixgbe_init_params(ixgbe);
926 967 }
927 968
928 969 /*
929 970 * ixgbe_init_driver_settings - Initialize driver settings.
930 971 *
931 972 * The settings include hardware function pointers, bus information,
932 973 * rx/tx rings settings, link state, and any other parameters that
933 974 * need to be setup during driver initialization.
934 975 */
935 976 static int
936 977 ixgbe_init_driver_settings(ixgbe_t *ixgbe)
937 978 {
938 979 struct ixgbe_hw *hw = &ixgbe->hw;
939 980 dev_info_t *devinfo = ixgbe->dip;
940 981 ixgbe_rx_ring_t *rx_ring;
941 982 ixgbe_rx_group_t *rx_group;
942 983 ixgbe_tx_ring_t *tx_ring;
943 984 uint32_t rx_size;
944 985 uint32_t tx_size;
945 986 uint32_t ring_per_group;
946 987 int i;
947 988
948 989 /*
949 990 * Initialize chipset specific hardware function pointers
950 991 */
951 992 if (ixgbe_init_shared_code(hw) != IXGBE_SUCCESS) {
952 993 return (IXGBE_FAILURE);
953 994 }
954 995
955 996 /*
956 997 * Get the system page size
957 998 */
958 999 ixgbe->sys_page_size = ddi_ptob(devinfo, (ulong_t)1);
959 1000
960 1001 /*
961 1002 * Set rx buffer size
962 1003 *
963 1004 * The IP header alignment room is counted in the calculation.
964 1005 * The rx buffer size is in unit of 1K that is required by the
965 1006 * chipset hardware.
966 1007 */
967 1008 rx_size = ixgbe->max_frame_size + IPHDR_ALIGN_ROOM;
968 1009 ixgbe->rx_buf_size = ((rx_size >> 10) +
969 1010 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
970 1011
971 1012 /*
972 1013 * Set tx buffer size
973 1014 */
974 1015 tx_size = ixgbe->max_frame_size;
975 1016 ixgbe->tx_buf_size = ((tx_size >> 10) +
976 1017 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10;
977 1018
978 1019 /*
979 1020 * Initialize rx/tx rings/groups parameters
980 1021 */
981 1022 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
982 1023 for (i = 0; i < ixgbe->num_rx_rings; i++) {
983 1024 rx_ring = &ixgbe->rx_rings[i];
984 1025 rx_ring->index = i;
985 1026 rx_ring->ixgbe = ixgbe;
986 1027 rx_ring->group_index = i / ring_per_group;
987 1028 rx_ring->hw_index = ixgbe_get_hw_rx_index(ixgbe, i);
988 1029 }
989 1030
990 1031 for (i = 0; i < ixgbe->num_rx_groups; i++) {
991 1032 rx_group = &ixgbe->rx_groups[i];
992 1033 rx_group->index = i;
993 1034 rx_group->ixgbe = ixgbe;
994 1035 }
995 1036
996 1037 for (i = 0; i < ixgbe->num_tx_rings; i++) {
997 1038 tx_ring = &ixgbe->tx_rings[i];
998 1039 tx_ring->index = i;
999 1040 tx_ring->ixgbe = ixgbe;
1000 1041 if (ixgbe->tx_head_wb_enable)
1001 1042 tx_ring->tx_recycle = ixgbe_tx_recycle_head_wb;
1002 1043 else
1003 1044 tx_ring->tx_recycle = ixgbe_tx_recycle_legacy;
1004 1045
1005 1046 tx_ring->ring_size = ixgbe->tx_ring_size;
1006 1047 tx_ring->free_list_size = ixgbe->tx_ring_size +
1007 1048 (ixgbe->tx_ring_size >> 1);
1008 1049 }
1009 1050
1010 1051 /*
1011 1052 * Initialize values of interrupt throttling rate
1012 1053 */
1013 1054 for (i = 1; i < MAX_INTR_VECTOR; i++)
1014 1055 ixgbe->intr_throttling[i] = ixgbe->intr_throttling[0];
1015 1056
1016 1057 /*
1017 1058 * The initial link state should be "unknown"
1018 1059 */
1019 1060 ixgbe->link_state = LINK_STATE_UNKNOWN;
1020 1061
1021 1062 return (IXGBE_SUCCESS);
1022 1063 }
1023 1064
1024 1065 /*
1025 1066 * ixgbe_init_locks - Initialize locks.
1026 1067 */
1027 1068 static void
1028 1069 ixgbe_init_locks(ixgbe_t *ixgbe)
1029 1070 {
1030 1071 ixgbe_rx_ring_t *rx_ring;
1031 1072 ixgbe_tx_ring_t *tx_ring;
1032 1073 int i;
1033 1074
1034 1075 for (i = 0; i < ixgbe->num_rx_rings; i++) {
1035 1076 rx_ring = &ixgbe->rx_rings[i];
1036 1077 mutex_init(&rx_ring->rx_lock, NULL,
1037 1078 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1038 1079 }
1039 1080
1040 1081 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1041 1082 tx_ring = &ixgbe->tx_rings[i];
1042 1083 mutex_init(&tx_ring->tx_lock, NULL,
1043 1084 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1044 1085 mutex_init(&tx_ring->recycle_lock, NULL,
1045 1086 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1046 1087 mutex_init(&tx_ring->tcb_head_lock, NULL,
1047 1088 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1048 1089 mutex_init(&tx_ring->tcb_tail_lock, NULL,
1049 1090 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1050 1091 }
1051 1092
1052 1093 mutex_init(&ixgbe->gen_lock, NULL,
1053 1094 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1054 1095
1055 1096 mutex_init(&ixgbe->watchdog_lock, NULL,
1056 1097 MUTEX_DRIVER, DDI_INTR_PRI(ixgbe->intr_pri));
1057 1098 }
1058 1099
1059 1100 /*
1060 1101 * ixgbe_destroy_locks - Destroy locks.
1061 1102 */
1062 1103 static void
1063 1104 ixgbe_destroy_locks(ixgbe_t *ixgbe)
1064 1105 {
1065 1106 ixgbe_rx_ring_t *rx_ring;
1066 1107 ixgbe_tx_ring_t *tx_ring;
1067 1108 int i;
1068 1109
1069 1110 for (i = 0; i < ixgbe->num_rx_rings; i++) {
1070 1111 rx_ring = &ixgbe->rx_rings[i];
1071 1112 mutex_destroy(&rx_ring->rx_lock);
1072 1113 }
1073 1114
1074 1115 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1075 1116 tx_ring = &ixgbe->tx_rings[i];
1076 1117 mutex_destroy(&tx_ring->tx_lock);
1077 1118 mutex_destroy(&tx_ring->recycle_lock);
1078 1119 mutex_destroy(&tx_ring->tcb_head_lock);
1079 1120 mutex_destroy(&tx_ring->tcb_tail_lock);
1080 1121 }
1081 1122
1082 1123 mutex_destroy(&ixgbe->gen_lock);
1083 1124 mutex_destroy(&ixgbe->watchdog_lock);
1084 1125 }
1085 1126
1086 1127 static int
1087 1128 ixgbe_resume(dev_info_t *devinfo)
1088 1129 {
1089 1130 ixgbe_t *ixgbe;
1090 1131 int i;
1091 1132
1092 1133 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo);
1093 1134 if (ixgbe == NULL)
1094 1135 return (DDI_FAILURE);
1095 1136
1096 1137 mutex_enter(&ixgbe->gen_lock);
1097 1138
1098 1139 if (ixgbe->ixgbe_state & IXGBE_STARTED) {
1099 1140 if (ixgbe_start(ixgbe, B_FALSE) != IXGBE_SUCCESS) {
1100 1141 mutex_exit(&ixgbe->gen_lock);
1101 1142 return (DDI_FAILURE);
1102 1143 }
1103 1144
1104 1145 /*
1105 1146 * Enable and start the watchdog timer
1106 1147 */
1107 1148 ixgbe_enable_watchdog_timer(ixgbe);
1108 1149 }
1109 1150
1110 1151 atomic_and_32(&ixgbe->ixgbe_state, ~IXGBE_SUSPENDED);
1111 1152
1112 1153 if (ixgbe->ixgbe_state & IXGBE_STARTED) {
1113 1154 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1114 1155 mac_tx_ring_update(ixgbe->mac_hdl,
1115 1156 ixgbe->tx_rings[i].ring_handle);
1116 1157 }
1117 1158 }
1118 1159
1119 1160 mutex_exit(&ixgbe->gen_lock);
1120 1161
1121 1162 return (DDI_SUCCESS);
1122 1163 }
1123 1164
1124 1165 static int
1125 1166 ixgbe_suspend(dev_info_t *devinfo)
1126 1167 {
1127 1168 ixgbe_t *ixgbe;
1128 1169
1129 1170 ixgbe = (ixgbe_t *)ddi_get_driver_private(devinfo);
1130 1171 if (ixgbe == NULL)
1131 1172 return (DDI_FAILURE);
1132 1173
1133 1174 mutex_enter(&ixgbe->gen_lock);
1134 1175
1135 1176 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_SUSPENDED);
1136 1177 if (!(ixgbe->ixgbe_state & IXGBE_STARTED)) {
1137 1178 mutex_exit(&ixgbe->gen_lock);
1138 1179 return (DDI_SUCCESS);
1139 1180 }
1140 1181 ixgbe_stop(ixgbe, B_FALSE);
1141 1182
1142 1183 mutex_exit(&ixgbe->gen_lock);
1143 1184
1144 1185 /*
1145 1186 * Disable and stop the watchdog timer
1146 1187 */
1147 1188 ixgbe_disable_watchdog_timer(ixgbe);
1148 1189
1149 1190 return (DDI_SUCCESS);
1150 1191 }
1151 1192
1152 1193 /*
1153 1194 * ixgbe_init - Initialize the device.
1154 1195 */
1155 1196 static int
1156 1197 ixgbe_init(ixgbe_t *ixgbe)
1157 1198 {
1158 1199 struct ixgbe_hw *hw = &ixgbe->hw;
1159 1200
1160 1201 mutex_enter(&ixgbe->gen_lock);
1161 1202
1162 1203 /*
1163 1204 * Reset chipset to put the hardware in a known state
1164 1205 * before we try to do anything with the eeprom.
1165 1206 */
1166 1207 if (ixgbe_reset_hw(hw) != IXGBE_SUCCESS) {
1167 1208 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1168 1209 goto init_fail;
1169 1210 }
1170 1211
1171 1212 /*
1172 1213 * Need to init eeprom before validating the checksum.
1173 1214 */
1174 1215 if (ixgbe_init_eeprom_params(hw) < 0) {
1175 1216 ixgbe_error(ixgbe,
1176 1217 "Unable to intitialize the eeprom interface.");
1177 1218 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1178 1219 goto init_fail;
1179 1220 }
1180 1221
1181 1222 /*
1182 1223 * NVM validation
1183 1224 */
1184 1225 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
1185 1226 /*
1186 1227 * Some PCI-E parts fail the first check due to
1187 1228 * the link being in sleep state. Call it again,
1188 1229 * if it fails a second time it's a real issue.
1189 1230 */
1190 1231 if (ixgbe_validate_eeprom_checksum(hw, NULL) < 0) {
1191 1232 ixgbe_error(ixgbe,
1192 1233 "Invalid NVM checksum. Please contact "
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1193 1234 "the vendor to update the NVM.");
1194 1235 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1195 1236 goto init_fail;
1196 1237 }
1197 1238 }
1198 1239
1199 1240 /*
1200 1241 * Setup default flow control thresholds - enable/disable
1201 1242 * & flow control type is controlled by ixgbe.conf
1202 1243 */
1203 - hw->fc.high_water = DEFAULT_FCRTH;
1204 - hw->fc.low_water = DEFAULT_FCRTL;
1244 + hw->fc.high_water[0] = DEFAULT_FCRTH;
1245 + hw->fc.low_water[0] = DEFAULT_FCRTL;
1205 1246 hw->fc.pause_time = DEFAULT_FCPAUSE;
1206 1247 hw->fc.send_xon = B_TRUE;
1207 1248
1208 1249 /*
1209 1250 * Initialize link settings
1210 1251 */
1211 1252 (void) ixgbe_driver_setup_link(ixgbe, B_FALSE);
1212 1253
1213 1254 /*
1214 1255 * Initialize the chipset hardware
1215 1256 */
1216 1257 if (ixgbe_chip_start(ixgbe) != IXGBE_SUCCESS) {
1217 1258 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1218 1259 goto init_fail;
1219 1260 }
1220 1261
1221 1262 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
1222 1263 goto init_fail;
1223 1264 }
1224 1265
1225 1266 mutex_exit(&ixgbe->gen_lock);
1226 1267 return (IXGBE_SUCCESS);
1227 1268
1228 1269 init_fail:
1229 1270 /*
1230 1271 * Reset PHY
1231 1272 */
1232 1273 (void) ixgbe_reset_phy(hw);
1233 1274
1234 1275 mutex_exit(&ixgbe->gen_lock);
1235 1276 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
1236 1277 return (IXGBE_FAILURE);
1237 1278 }
1238 1279
1239 1280 /*
1240 1281 * ixgbe_chip_start - Initialize and start the chipset hardware.
1241 1282 */
1242 1283 static int
1243 1284 ixgbe_chip_start(ixgbe_t *ixgbe)
1244 1285 {
1245 1286 struct ixgbe_hw *hw = &ixgbe->hw;
1246 1287 int ret_val, i;
1247 1288
1248 1289 ASSERT(mutex_owned(&ixgbe->gen_lock));
1249 1290
1250 1291 /*
1251 1292 * Get the mac address
1252 1293 * This function should handle SPARC case correctly.
1253 1294 */
1254 1295 if (!ixgbe_find_mac_address(ixgbe)) {
1255 1296 ixgbe_error(ixgbe, "Failed to get the mac address");
1256 1297 return (IXGBE_FAILURE);
1257 1298 }
1258 1299
1259 1300 /*
1260 1301 * Validate the mac address
1261 1302 */
1262 1303 (void) ixgbe_init_rx_addrs(hw);
1263 1304 if (!is_valid_mac_addr(hw->mac.addr)) {
1264 1305 ixgbe_error(ixgbe, "Invalid mac address");
1265 1306 return (IXGBE_FAILURE);
1266 1307 }
1267 1308
1268 1309 /*
1269 1310 * Configure/Initialize hardware
1270 1311 */
1271 1312 ret_val = ixgbe_init_hw(hw);
1272 1313 if (ret_val != IXGBE_SUCCESS) {
1273 1314 if (ret_val == IXGBE_ERR_EEPROM_VERSION) {
1274 1315 ixgbe_error(ixgbe,
1275 1316 "This 82599 device is pre-release and contains"
1276 1317 " outdated firmware, please contact your hardware"
1277 1318 " vendor for a replacement.");
1278 1319 } else {
1279 1320 ixgbe_error(ixgbe, "Failed to initialize hardware");
1280 1321 return (IXGBE_FAILURE);
1281 1322 }
1282 1323 }
1283 1324
1284 1325 /*
1285 1326 * Re-enable relaxed ordering for performance. It is disabled
1286 1327 * by default in the hardware init.
1287 1328 */
1288 1329 if (ixgbe->relax_order_enable == B_TRUE)
1289 1330 ixgbe_enable_relaxed_ordering(hw);
1290 1331
1291 1332 /*
1292 1333 * Setup adapter interrupt vectors
1293 1334 */
1294 1335 ixgbe_setup_adapter_vector(ixgbe);
1295 1336
1296 1337 /*
1297 1338 * Initialize unicast addresses.
1298 1339 */
1299 1340 ixgbe_init_unicst(ixgbe);
1300 1341
1301 1342 /*
1302 1343 * Setup and initialize the mctable structures.
1303 1344 */
1304 1345 ixgbe_setup_multicst(ixgbe);
1305 1346
1306 1347 /*
1307 1348 * Set interrupt throttling rate
1308 1349 */
1309 1350 for (i = 0; i < ixgbe->intr_cnt; i++) {
1310 1351 IXGBE_WRITE_REG(hw, IXGBE_EITR(i), ixgbe->intr_throttling[i]);
1311 1352 }
1312 1353
1313 1354 /*
1314 1355 * Save the state of the phy
1315 1356 */
1316 1357 ixgbe_get_hw_state(ixgbe);
1317 1358
1318 1359 /*
1319 1360 * Make sure driver has control
1320 1361 */
1321 1362 ixgbe_get_driver_control(hw);
1322 1363
1323 1364 return (IXGBE_SUCCESS);
1324 1365 }
1325 1366
1326 1367 /*
1327 1368 * ixgbe_chip_stop - Stop the chipset hardware
1328 1369 */
1329 1370 static void
1330 1371 ixgbe_chip_stop(ixgbe_t *ixgbe)
1331 1372 {
1332 1373 struct ixgbe_hw *hw = &ixgbe->hw;
1333 1374
1334 1375 ASSERT(mutex_owned(&ixgbe->gen_lock));
1335 1376
1336 1377 /*
1337 1378 * Tell firmware driver is no longer in control
1338 1379 */
1339 1380 ixgbe_release_driver_control(hw);
1340 1381
1341 1382 /*
1342 1383 * Reset the chipset
1343 1384 */
1344 1385 (void) ixgbe_reset_hw(hw);
1345 1386
1346 1387 /*
1347 1388 * Reset PHY
1348 1389 */
1349 1390 (void) ixgbe_reset_phy(hw);
1350 1391 }
1351 1392
1352 1393 /*
1353 1394 * ixgbe_reset - Reset the chipset and re-start the driver.
1354 1395 *
1355 1396 * It involves stopping and re-starting the chipset,
1356 1397 * and re-configuring the rx/tx rings.
1357 1398 */
1358 1399 static int
1359 1400 ixgbe_reset(ixgbe_t *ixgbe)
1360 1401 {
1361 1402 int i;
1362 1403
1363 1404 /*
1364 1405 * Disable and stop the watchdog timer
1365 1406 */
1366 1407 ixgbe_disable_watchdog_timer(ixgbe);
1367 1408
1368 1409 mutex_enter(&ixgbe->gen_lock);
1369 1410
1370 1411 ASSERT(ixgbe->ixgbe_state & IXGBE_STARTED);
1371 1412 atomic_and_32(&ixgbe->ixgbe_state, ~IXGBE_STARTED);
1372 1413
1373 1414 ixgbe_stop(ixgbe, B_FALSE);
1374 1415
1375 1416 if (ixgbe_start(ixgbe, B_FALSE) != IXGBE_SUCCESS) {
1376 1417 mutex_exit(&ixgbe->gen_lock);
1377 1418 return (IXGBE_FAILURE);
1378 1419 }
1379 1420
1380 1421 /*
1381 1422 * After resetting, need to recheck the link status.
1382 1423 */
1383 1424 ixgbe->link_check_complete = B_FALSE;
1384 1425 ixgbe->link_check_hrtime = gethrtime() +
1385 1426 (IXGBE_LINK_UP_TIME * 100000000ULL);
1386 1427
1387 1428 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_STARTED);
1388 1429
1389 1430 if (!(ixgbe->ixgbe_state & IXGBE_SUSPENDED)) {
1390 1431 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1391 1432 mac_tx_ring_update(ixgbe->mac_hdl,
1392 1433 ixgbe->tx_rings[i].ring_handle);
1393 1434 }
1394 1435 }
1395 1436
1396 1437 mutex_exit(&ixgbe->gen_lock);
1397 1438
1398 1439 /*
1399 1440 * Enable and start the watchdog timer
1400 1441 */
1401 1442 ixgbe_enable_watchdog_timer(ixgbe);
1402 1443
1403 1444 return (IXGBE_SUCCESS);
1404 1445 }
1405 1446
1406 1447 /*
1407 1448 * ixgbe_tx_clean - Clean the pending transmit packets and DMA resources.
1408 1449 */
1409 1450 static void
1410 1451 ixgbe_tx_clean(ixgbe_t *ixgbe)
1411 1452 {
1412 1453 ixgbe_tx_ring_t *tx_ring;
1413 1454 tx_control_block_t *tcb;
1414 1455 link_list_t pending_list;
1415 1456 uint32_t desc_num;
1416 1457 int i, j;
1417 1458
1418 1459 LINK_LIST_INIT(&pending_list);
1419 1460
1420 1461 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1421 1462 tx_ring = &ixgbe->tx_rings[i];
1422 1463
1423 1464 mutex_enter(&tx_ring->recycle_lock);
1424 1465
1425 1466 /*
1426 1467 * Clean the pending tx data - the pending packets in the
1427 1468 * work_list that have no chances to be transmitted again.
1428 1469 *
1429 1470 * We must ensure the chipset is stopped or the link is down
1430 1471 * before cleaning the transmit packets.
1431 1472 */
1432 1473 desc_num = 0;
1433 1474 for (j = 0; j < tx_ring->ring_size; j++) {
1434 1475 tcb = tx_ring->work_list[j];
1435 1476 if (tcb != NULL) {
1436 1477 desc_num += tcb->desc_num;
1437 1478
1438 1479 tx_ring->work_list[j] = NULL;
1439 1480
1440 1481 ixgbe_free_tcb(tcb);
1441 1482
1442 1483 LIST_PUSH_TAIL(&pending_list, &tcb->link);
1443 1484 }
1444 1485 }
1445 1486
1446 1487 if (desc_num > 0) {
1447 1488 atomic_add_32(&tx_ring->tbd_free, desc_num);
1448 1489 ASSERT(tx_ring->tbd_free == tx_ring->ring_size);
1449 1490
1450 1491 /*
1451 1492 * Reset the head and tail pointers of the tbd ring;
1452 1493 * Reset the writeback head if it's enable.
1453 1494 */
1454 1495 tx_ring->tbd_head = 0;
1455 1496 tx_ring->tbd_tail = 0;
1456 1497 if (ixgbe->tx_head_wb_enable)
1457 1498 *tx_ring->tbd_head_wb = 0;
1458 1499
1459 1500 IXGBE_WRITE_REG(&ixgbe->hw,
1460 1501 IXGBE_TDH(tx_ring->index), 0);
1461 1502 IXGBE_WRITE_REG(&ixgbe->hw,
1462 1503 IXGBE_TDT(tx_ring->index), 0);
1463 1504 }
1464 1505
1465 1506 mutex_exit(&tx_ring->recycle_lock);
1466 1507
1467 1508 /*
1468 1509 * Add the tx control blocks in the pending list to
1469 1510 * the free list.
1470 1511 */
1471 1512 ixgbe_put_free_list(tx_ring, &pending_list);
1472 1513 }
1473 1514 }
1474 1515
1475 1516 /*
1476 1517 * ixgbe_tx_drain - Drain the tx rings to allow pending packets to be
1477 1518 * transmitted.
1478 1519 */
1479 1520 static boolean_t
1480 1521 ixgbe_tx_drain(ixgbe_t *ixgbe)
1481 1522 {
1482 1523 ixgbe_tx_ring_t *tx_ring;
1483 1524 boolean_t done;
1484 1525 int i, j;
1485 1526
1486 1527 /*
1487 1528 * Wait for a specific time to allow pending tx packets
1488 1529 * to be transmitted.
1489 1530 *
1490 1531 * Check the counter tbd_free to see if transmission is done.
1491 1532 * No lock protection is needed here.
1492 1533 *
1493 1534 * Return B_TRUE if all pending packets have been transmitted;
1494 1535 * Otherwise return B_FALSE;
1495 1536 */
1496 1537 for (i = 0; i < TX_DRAIN_TIME; i++) {
1497 1538
1498 1539 done = B_TRUE;
1499 1540 for (j = 0; j < ixgbe->num_tx_rings; j++) {
1500 1541 tx_ring = &ixgbe->tx_rings[j];
1501 1542 done = done &&
1502 1543 (tx_ring->tbd_free == tx_ring->ring_size);
1503 1544 }
1504 1545
1505 1546 if (done)
1506 1547 break;
1507 1548
1508 1549 msec_delay(1);
1509 1550 }
1510 1551
1511 1552 return (done);
1512 1553 }
1513 1554
1514 1555 /*
1515 1556 * ixgbe_rx_drain - Wait for all rx buffers to be released by upper layer.
1516 1557 */
1517 1558 static boolean_t
1518 1559 ixgbe_rx_drain(ixgbe_t *ixgbe)
1519 1560 {
1520 1561 boolean_t done = B_TRUE;
1521 1562 int i;
1522 1563
1523 1564 /*
1524 1565 * Polling the rx free list to check if those rx buffers held by
1525 1566 * the upper layer are released.
1526 1567 *
1527 1568 * Check the counter rcb_free to see if all pending buffers are
1528 1569 * released. No lock protection is needed here.
1529 1570 *
1530 1571 * Return B_TRUE if all pending buffers have been released;
1531 1572 * Otherwise return B_FALSE;
1532 1573 */
1533 1574 for (i = 0; i < RX_DRAIN_TIME; i++) {
1534 1575 done = (ixgbe->rcb_pending == 0);
1535 1576
1536 1577 if (done)
1537 1578 break;
1538 1579
1539 1580 msec_delay(1);
1540 1581 }
1541 1582
1542 1583 return (done);
1543 1584 }
1544 1585
1545 1586 /*
1546 1587 * ixgbe_start - Start the driver/chipset.
1547 1588 */
1548 1589 int
1549 1590 ixgbe_start(ixgbe_t *ixgbe, boolean_t alloc_buffer)
1550 1591 {
1551 1592 int i;
1552 1593
1553 1594 ASSERT(mutex_owned(&ixgbe->gen_lock));
1554 1595
1555 1596 if (alloc_buffer) {
1556 1597 if (ixgbe_alloc_rx_data(ixgbe) != IXGBE_SUCCESS) {
1557 1598 ixgbe_error(ixgbe,
1558 1599 "Failed to allocate software receive rings");
1559 1600 return (IXGBE_FAILURE);
1560 1601 }
1561 1602
1562 1603 /* Allocate buffers for all the rx/tx rings */
1563 1604 if (ixgbe_alloc_dma(ixgbe) != IXGBE_SUCCESS) {
1564 1605 ixgbe_error(ixgbe, "Failed to allocate DMA resource");
1565 1606 return (IXGBE_FAILURE);
1566 1607 }
1567 1608
1568 1609 ixgbe->tx_ring_init = B_TRUE;
1569 1610 } else {
1570 1611 ixgbe->tx_ring_init = B_FALSE;
1571 1612 }
1572 1613
1573 1614 for (i = 0; i < ixgbe->num_rx_rings; i++)
1574 1615 mutex_enter(&ixgbe->rx_rings[i].rx_lock);
1575 1616 for (i = 0; i < ixgbe->num_tx_rings; i++)
1576 1617 mutex_enter(&ixgbe->tx_rings[i].tx_lock);
1577 1618
1578 1619 /*
1579 1620 * Start the chipset hardware
1580 1621 */
1581 1622 if (ixgbe_chip_start(ixgbe) != IXGBE_SUCCESS) {
1582 1623 ixgbe_fm_ereport(ixgbe, DDI_FM_DEVICE_INVAL_STATE);
1583 1624 goto start_failure;
1584 1625 }
1585 1626
1586 1627 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
1587 1628 goto start_failure;
1588 1629 }
1589 1630
1590 1631 /*
1591 1632 * Setup the rx/tx rings
1592 1633 */
1593 1634 ixgbe_setup_rings(ixgbe);
1594 1635
1595 1636 /*
1596 1637 * ixgbe_start() will be called when resetting, however if reset
1597 1638 * happens, we need to clear the ERROR, STALL and OVERTEMP flags
1598 1639 * before enabling the interrupts.
1599 1640 */
1600 1641 atomic_and_32(&ixgbe->ixgbe_state, ~(IXGBE_ERROR
1601 1642 | IXGBE_STALL| IXGBE_OVERTEMP));
1602 1643
1603 1644 /*
1604 1645 * Enable adapter interrupts
1605 1646 * The interrupts must be enabled after the driver state is START
1606 1647 */
1607 1648 ixgbe_enable_adapter_interrupts(ixgbe);
1608 1649
1609 1650 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--)
1610 1651 mutex_exit(&ixgbe->tx_rings[i].tx_lock);
1611 1652 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--)
1612 1653 mutex_exit(&ixgbe->rx_rings[i].rx_lock);
1613 1654
1614 1655 return (IXGBE_SUCCESS);
1615 1656
1616 1657 start_failure:
1617 1658 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--)
1618 1659 mutex_exit(&ixgbe->tx_rings[i].tx_lock);
1619 1660 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--)
1620 1661 mutex_exit(&ixgbe->rx_rings[i].rx_lock);
1621 1662
1622 1663 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
1623 1664
1624 1665 return (IXGBE_FAILURE);
1625 1666 }
1626 1667
1627 1668 /*
1628 1669 * ixgbe_stop - Stop the driver/chipset.
1629 1670 */
1630 1671 void
1631 1672 ixgbe_stop(ixgbe_t *ixgbe, boolean_t free_buffer)
1632 1673 {
1633 1674 int i;
1634 1675
1635 1676 ASSERT(mutex_owned(&ixgbe->gen_lock));
1636 1677
1637 1678 /*
1638 1679 * Disable the adapter interrupts
1639 1680 */
1640 1681 ixgbe_disable_adapter_interrupts(ixgbe);
1641 1682
1642 1683 /*
1643 1684 * Drain the pending tx packets
1644 1685 */
1645 1686 (void) ixgbe_tx_drain(ixgbe);
1646 1687
1647 1688 for (i = 0; i < ixgbe->num_rx_rings; i++)
1648 1689 mutex_enter(&ixgbe->rx_rings[i].rx_lock);
1649 1690 for (i = 0; i < ixgbe->num_tx_rings; i++)
1650 1691 mutex_enter(&ixgbe->tx_rings[i].tx_lock);
1651 1692
1652 1693 /*
1653 1694 * Stop the chipset hardware
1654 1695 */
1655 1696 ixgbe_chip_stop(ixgbe);
1656 1697
1657 1698 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
1658 1699 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
1659 1700 }
1660 1701
1661 1702 /*
1662 1703 * Clean the pending tx data/resources
1663 1704 */
1664 1705 ixgbe_tx_clean(ixgbe);
1665 1706
1666 1707 for (i = ixgbe->num_tx_rings - 1; i >= 0; i--)
1667 1708 mutex_exit(&ixgbe->tx_rings[i].tx_lock);
1668 1709 for (i = ixgbe->num_rx_rings - 1; i >= 0; i--)
1669 1710 mutex_exit(&ixgbe->rx_rings[i].rx_lock);
1670 1711
1671 1712 if (ixgbe->link_state == LINK_STATE_UP) {
1672 1713 ixgbe->link_state = LINK_STATE_UNKNOWN;
1673 1714 mac_link_update(ixgbe->mac_hdl, ixgbe->link_state);
1674 1715 }
1675 1716
1676 1717 if (free_buffer) {
1677 1718 /*
1678 1719 * Release the DMA/memory resources of rx/tx rings
1679 1720 */
1680 1721 ixgbe_free_dma(ixgbe);
1681 1722 ixgbe_free_rx_data(ixgbe);
1682 1723 }
1683 1724 }
1684 1725
1685 1726 /*
1686 1727 * ixgbe_cbfunc - Driver interface for generic DDI callbacks
1687 1728 */
1688 1729 /* ARGSUSED */
1689 1730 static int
1690 1731 ixgbe_cbfunc(dev_info_t *dip, ddi_cb_action_t cbaction, void *cbarg,
1691 1732 void *arg1, void *arg2)
1692 1733 {
1693 1734 ixgbe_t *ixgbe = (ixgbe_t *)arg1;
1694 1735
1695 1736 switch (cbaction) {
1696 1737 /* IRM callback */
1697 1738 int count;
1698 1739 case DDI_CB_INTR_ADD:
1699 1740 case DDI_CB_INTR_REMOVE:
1700 1741 count = (int)(uintptr_t)cbarg;
1701 1742 ASSERT(ixgbe->intr_type == DDI_INTR_TYPE_MSIX);
1702 1743 DTRACE_PROBE2(ixgbe__irm__callback, int, count,
1703 1744 int, ixgbe->intr_cnt);
1704 1745 if (ixgbe_intr_adjust(ixgbe, cbaction, count) !=
1705 1746 DDI_SUCCESS) {
1706 1747 ixgbe_error(ixgbe,
1707 1748 "IRM CB: Failed to adjust interrupts");
1708 1749 goto cb_fail;
1709 1750 }
1710 1751 break;
1711 1752 default:
1712 1753 IXGBE_DEBUGLOG_1(ixgbe, "DDI CB: action 0x%x NOT supported",
1713 1754 cbaction);
1714 1755 return (DDI_ENOTSUP);
1715 1756 }
1716 1757 return (DDI_SUCCESS);
1717 1758 cb_fail:
1718 1759 return (DDI_FAILURE);
1719 1760 }
1720 1761
1721 1762 /*
1722 1763 * ixgbe_intr_adjust - Adjust interrupt to respond to IRM request.
1723 1764 */
1724 1765 static int
1725 1766 ixgbe_intr_adjust(ixgbe_t *ixgbe, ddi_cb_action_t cbaction, int count)
1726 1767 {
1727 1768 int i, rc, actual;
1728 1769
1729 1770 if (count == 0)
1730 1771 return (DDI_SUCCESS);
1731 1772
1732 1773 if ((cbaction == DDI_CB_INTR_ADD &&
1733 1774 ixgbe->intr_cnt + count > ixgbe->intr_cnt_max) ||
1734 1775 (cbaction == DDI_CB_INTR_REMOVE &&
1735 1776 ixgbe->intr_cnt - count < ixgbe->intr_cnt_min))
1736 1777 return (DDI_FAILURE);
1737 1778
1738 1779 if (!(ixgbe->ixgbe_state & IXGBE_STARTED)) {
1739 1780 return (DDI_FAILURE);
1740 1781 }
1741 1782
1742 1783 for (i = 0; i < ixgbe->num_rx_rings; i++)
1743 1784 mac_ring_intr_set(ixgbe->rx_rings[i].ring_handle, NULL);
1744 1785 for (i = 0; i < ixgbe->num_tx_rings; i++)
1745 1786 mac_ring_intr_set(ixgbe->tx_rings[i].ring_handle, NULL);
1746 1787
1747 1788 mutex_enter(&ixgbe->gen_lock);
1748 1789 ixgbe->ixgbe_state &= ~IXGBE_STARTED;
1749 1790 ixgbe->ixgbe_state |= IXGBE_INTR_ADJUST;
1750 1791 ixgbe->ixgbe_state |= IXGBE_SUSPENDED;
1751 1792 mac_link_update(ixgbe->mac_hdl, LINK_STATE_UNKNOWN);
1752 1793
1753 1794 ixgbe_stop(ixgbe, B_FALSE);
1754 1795 /*
1755 1796 * Disable interrupts
1756 1797 */
1757 1798 if (ixgbe->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) {
1758 1799 rc = ixgbe_disable_intrs(ixgbe);
1759 1800 ASSERT(rc == IXGBE_SUCCESS);
1760 1801 }
1761 1802 ixgbe->attach_progress &= ~ATTACH_PROGRESS_ENABLE_INTR;
1762 1803
1763 1804 /*
1764 1805 * Remove interrupt handlers
1765 1806 */
1766 1807 if (ixgbe->attach_progress & ATTACH_PROGRESS_ADD_INTR) {
1767 1808 ixgbe_rem_intr_handlers(ixgbe);
1768 1809 }
1769 1810 ixgbe->attach_progress &= ~ATTACH_PROGRESS_ADD_INTR;
1770 1811
1771 1812 /*
1772 1813 * Clear vect_map
1773 1814 */
1774 1815 bzero(&ixgbe->vect_map, sizeof (ixgbe->vect_map));
1775 1816 switch (cbaction) {
1776 1817 case DDI_CB_INTR_ADD:
1777 1818 rc = ddi_intr_alloc(ixgbe->dip, ixgbe->htable,
1778 1819 DDI_INTR_TYPE_MSIX, ixgbe->intr_cnt, count, &actual,
1779 1820 DDI_INTR_ALLOC_NORMAL);
1780 1821 if (rc != DDI_SUCCESS || actual != count) {
1781 1822 ixgbe_log(ixgbe, "Adjust interrupts failed."
1782 1823 "return: %d, irm cb size: %d, actual: %d",
1783 1824 rc, count, actual);
1784 1825 goto intr_adjust_fail;
1785 1826 }
1786 1827 ixgbe->intr_cnt += count;
1787 1828 break;
1788 1829
1789 1830 case DDI_CB_INTR_REMOVE:
1790 1831 for (i = ixgbe->intr_cnt - count;
1791 1832 i < ixgbe->intr_cnt; i ++) {
1792 1833 rc = ddi_intr_free(ixgbe->htable[i]);
1793 1834 ixgbe->htable[i] = NULL;
1794 1835 if (rc != DDI_SUCCESS) {
1795 1836 ixgbe_log(ixgbe, "Adjust interrupts failed."
1796 1837 "return: %d, irm cb size: %d, actual: %d",
1797 1838 rc, count, actual);
1798 1839 goto intr_adjust_fail;
1799 1840 }
1800 1841 }
1801 1842 ixgbe->intr_cnt -= count;
1802 1843 break;
1803 1844 }
1804 1845
1805 1846 /*
1806 1847 * Get priority for first vector, assume remaining are all the same
1807 1848 */
1808 1849 rc = ddi_intr_get_pri(ixgbe->htable[0], &ixgbe->intr_pri);
1809 1850 if (rc != DDI_SUCCESS) {
1810 1851 ixgbe_log(ixgbe,
1811 1852 "Get interrupt priority failed: %d", rc);
1812 1853 goto intr_adjust_fail;
1813 1854 }
1814 1855 rc = ddi_intr_get_cap(ixgbe->htable[0], &ixgbe->intr_cap);
1815 1856 if (rc != DDI_SUCCESS) {
1816 1857 ixgbe_log(ixgbe, "Get interrupt cap failed: %d", rc);
1817 1858 goto intr_adjust_fail;
1818 1859 }
1819 1860 ixgbe->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR;
1820 1861
1821 1862 /*
1822 1863 * Map rings to interrupt vectors
1823 1864 */
1824 1865 if (ixgbe_map_intrs_to_vectors(ixgbe) != IXGBE_SUCCESS) {
1825 1866 ixgbe_error(ixgbe,
1826 1867 "IRM CB: Failed to map interrupts to vectors");
1827 1868 goto intr_adjust_fail;
1828 1869 }
1829 1870
1830 1871 /*
1831 1872 * Add interrupt handlers
1832 1873 */
1833 1874 if (ixgbe_add_intr_handlers(ixgbe) != IXGBE_SUCCESS) {
1834 1875 ixgbe_error(ixgbe, "IRM CB: Failed to add interrupt handlers");
1835 1876 goto intr_adjust_fail;
1836 1877 }
1837 1878 ixgbe->attach_progress |= ATTACH_PROGRESS_ADD_INTR;
1838 1879
1839 1880 /*
1840 1881 * Now that mutex locks are initialized, and the chip is also
1841 1882 * initialized, enable interrupts.
1842 1883 */
1843 1884 if (ixgbe_enable_intrs(ixgbe) != IXGBE_SUCCESS) {
1844 1885 ixgbe_error(ixgbe, "IRM CB: Failed to enable DDI interrupts");
1845 1886 goto intr_adjust_fail;
1846 1887 }
1847 1888 ixgbe->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR;
1848 1889 if (ixgbe_start(ixgbe, B_FALSE) != IXGBE_SUCCESS) {
1849 1890 ixgbe_error(ixgbe, "IRM CB: Failed to start");
1850 1891 goto intr_adjust_fail;
1851 1892 }
1852 1893 ixgbe->ixgbe_state &= ~IXGBE_INTR_ADJUST;
1853 1894 ixgbe->ixgbe_state &= ~IXGBE_SUSPENDED;
1854 1895 ixgbe->ixgbe_state |= IXGBE_STARTED;
1855 1896 mutex_exit(&ixgbe->gen_lock);
1856 1897
1857 1898 for (i = 0; i < ixgbe->num_rx_rings; i++) {
1858 1899 mac_ring_intr_set(ixgbe->rx_rings[i].ring_handle,
1859 1900 ixgbe->htable[ixgbe->rx_rings[i].intr_vector]);
1860 1901 }
1861 1902 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1862 1903 mac_ring_intr_set(ixgbe->tx_rings[i].ring_handle,
1863 1904 ixgbe->htable[ixgbe->tx_rings[i].intr_vector]);
1864 1905 }
1865 1906
1866 1907 /* Wakeup all Tx rings */
1867 1908 for (i = 0; i < ixgbe->num_tx_rings; i++) {
1868 1909 mac_tx_ring_update(ixgbe->mac_hdl,
1869 1910 ixgbe->tx_rings[i].ring_handle);
1870 1911 }
1871 1912
1872 1913 IXGBE_DEBUGLOG_3(ixgbe,
1873 1914 "IRM CB: interrupts new value: 0x%x(0x%x:0x%x).",
1874 1915 ixgbe->intr_cnt, ixgbe->intr_cnt_min, ixgbe->intr_cnt_max);
1875 1916 return (DDI_SUCCESS);
1876 1917
1877 1918 intr_adjust_fail:
1878 1919 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
1879 1920 mutex_exit(&ixgbe->gen_lock);
1880 1921 return (DDI_FAILURE);
1881 1922 }
1882 1923
1883 1924 /*
1884 1925 * ixgbe_intr_cb_register - Register interrupt callback function.
1885 1926 */
1886 1927 static int
1887 1928 ixgbe_intr_cb_register(ixgbe_t *ixgbe)
1888 1929 {
1889 1930 if (ddi_cb_register(ixgbe->dip, DDI_CB_FLAG_INTR, ixgbe_cbfunc,
1890 1931 ixgbe, NULL, &ixgbe->cb_hdl) != DDI_SUCCESS) {
1891 1932 return (IXGBE_FAILURE);
1892 1933 }
1893 1934 IXGBE_DEBUGLOG_0(ixgbe, "Interrupt callback function registered.");
1894 1935 return (IXGBE_SUCCESS);
1895 1936 }
1896 1937
1897 1938 /*
1898 1939 * ixgbe_alloc_rings - Allocate memory space for rx/tx rings.
1899 1940 */
1900 1941 static int
1901 1942 ixgbe_alloc_rings(ixgbe_t *ixgbe)
1902 1943 {
1903 1944 /*
1904 1945 * Allocate memory space for rx rings
1905 1946 */
1906 1947 ixgbe->rx_rings = kmem_zalloc(
1907 1948 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings,
1908 1949 KM_NOSLEEP);
1909 1950
1910 1951 if (ixgbe->rx_rings == NULL) {
1911 1952 return (IXGBE_FAILURE);
1912 1953 }
1913 1954
1914 1955 /*
1915 1956 * Allocate memory space for tx rings
1916 1957 */
1917 1958 ixgbe->tx_rings = kmem_zalloc(
1918 1959 sizeof (ixgbe_tx_ring_t) * ixgbe->num_tx_rings,
1919 1960 KM_NOSLEEP);
1920 1961
1921 1962 if (ixgbe->tx_rings == NULL) {
1922 1963 kmem_free(ixgbe->rx_rings,
1923 1964 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings);
1924 1965 ixgbe->rx_rings = NULL;
1925 1966 return (IXGBE_FAILURE);
1926 1967 }
1927 1968
1928 1969 /*
1929 1970 * Allocate memory space for rx ring groups
1930 1971 */
1931 1972 ixgbe->rx_groups = kmem_zalloc(
1932 1973 sizeof (ixgbe_rx_group_t) * ixgbe->num_rx_groups,
1933 1974 KM_NOSLEEP);
1934 1975
1935 1976 if (ixgbe->rx_groups == NULL) {
1936 1977 kmem_free(ixgbe->rx_rings,
1937 1978 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings);
1938 1979 kmem_free(ixgbe->tx_rings,
1939 1980 sizeof (ixgbe_tx_ring_t) * ixgbe->num_tx_rings);
1940 1981 ixgbe->rx_rings = NULL;
1941 1982 ixgbe->tx_rings = NULL;
1942 1983 return (IXGBE_FAILURE);
1943 1984 }
1944 1985
1945 1986 return (IXGBE_SUCCESS);
1946 1987 }
1947 1988
1948 1989 /*
1949 1990 * ixgbe_free_rings - Free the memory space of rx/tx rings.
1950 1991 */
1951 1992 static void
1952 1993 ixgbe_free_rings(ixgbe_t *ixgbe)
1953 1994 {
1954 1995 if (ixgbe->rx_rings != NULL) {
1955 1996 kmem_free(ixgbe->rx_rings,
1956 1997 sizeof (ixgbe_rx_ring_t) * ixgbe->num_rx_rings);
1957 1998 ixgbe->rx_rings = NULL;
1958 1999 }
1959 2000
1960 2001 if (ixgbe->tx_rings != NULL) {
1961 2002 kmem_free(ixgbe->tx_rings,
1962 2003 sizeof (ixgbe_tx_ring_t) * ixgbe->num_tx_rings);
1963 2004 ixgbe->tx_rings = NULL;
1964 2005 }
1965 2006
1966 2007 if (ixgbe->rx_groups != NULL) {
1967 2008 kmem_free(ixgbe->rx_groups,
1968 2009 sizeof (ixgbe_rx_group_t) * ixgbe->num_rx_groups);
1969 2010 ixgbe->rx_groups = NULL;
1970 2011 }
1971 2012 }
1972 2013
1973 2014 static int
1974 2015 ixgbe_alloc_rx_data(ixgbe_t *ixgbe)
1975 2016 {
1976 2017 ixgbe_rx_ring_t *rx_ring;
1977 2018 int i;
1978 2019
1979 2020 for (i = 0; i < ixgbe->num_rx_rings; i++) {
1980 2021 rx_ring = &ixgbe->rx_rings[i];
1981 2022 if (ixgbe_alloc_rx_ring_data(rx_ring) != IXGBE_SUCCESS)
1982 2023 goto alloc_rx_rings_failure;
1983 2024 }
1984 2025 return (IXGBE_SUCCESS);
1985 2026
1986 2027 alloc_rx_rings_failure:
1987 2028 ixgbe_free_rx_data(ixgbe);
1988 2029 return (IXGBE_FAILURE);
1989 2030 }
1990 2031
1991 2032 static void
1992 2033 ixgbe_free_rx_data(ixgbe_t *ixgbe)
1993 2034 {
1994 2035 ixgbe_rx_ring_t *rx_ring;
1995 2036 ixgbe_rx_data_t *rx_data;
1996 2037 int i;
1997 2038
1998 2039 for (i = 0; i < ixgbe->num_rx_rings; i++) {
1999 2040 rx_ring = &ixgbe->rx_rings[i];
2000 2041
2001 2042 mutex_enter(&ixgbe->rx_pending_lock);
2002 2043 rx_data = rx_ring->rx_data;
2003 2044
2004 2045 if (rx_data != NULL) {
2005 2046 rx_data->flag |= IXGBE_RX_STOPPED;
2006 2047
2007 2048 if (rx_data->rcb_pending == 0) {
2008 2049 ixgbe_free_rx_ring_data(rx_data);
2009 2050 rx_ring->rx_data = NULL;
2010 2051 }
2011 2052 }
2012 2053
2013 2054 mutex_exit(&ixgbe->rx_pending_lock);
2014 2055 }
2015 2056 }
2016 2057
2017 2058 /*
2018 2059 * ixgbe_setup_rings - Setup rx/tx rings.
2019 2060 */
2020 2061 static void
2021 2062 ixgbe_setup_rings(ixgbe_t *ixgbe)
2022 2063 {
2023 2064 /*
2024 2065 * Setup the rx/tx rings, including the following:
2025 2066 *
2026 2067 * 1. Setup the descriptor ring and the control block buffers;
2027 2068 * 2. Initialize necessary registers for receive/transmit;
2028 2069 * 3. Initialize software pointers/parameters for receive/transmit;
2029 2070 */
2030 2071 ixgbe_setup_rx(ixgbe);
2031 2072
2032 2073 ixgbe_setup_tx(ixgbe);
2033 2074 }
2034 2075
2035 2076 static void
2036 2077 ixgbe_setup_rx_ring(ixgbe_rx_ring_t *rx_ring)
2037 2078 {
2038 2079 ixgbe_t *ixgbe = rx_ring->ixgbe;
2039 2080 ixgbe_rx_data_t *rx_data = rx_ring->rx_data;
2040 2081 struct ixgbe_hw *hw = &ixgbe->hw;
2041 2082 rx_control_block_t *rcb;
2042 2083 union ixgbe_adv_rx_desc *rbd;
2043 2084 uint32_t size;
2044 2085 uint32_t buf_low;
2045 2086 uint32_t buf_high;
2046 2087 uint32_t reg_val;
2047 2088 int i;
2048 2089
2049 2090 ASSERT(mutex_owned(&rx_ring->rx_lock));
2050 2091 ASSERT(mutex_owned(&ixgbe->gen_lock));
2051 2092
2052 2093 for (i = 0; i < ixgbe->rx_ring_size; i++) {
2053 2094 rcb = rx_data->work_list[i];
2054 2095 rbd = &rx_data->rbd_ring[i];
2055 2096
2056 2097 rbd->read.pkt_addr = rcb->rx_buf.dma_address;
2057 2098 rbd->read.hdr_addr = NULL;
2058 2099 }
2059 2100
2060 2101 /*
2061 2102 * Initialize the length register
2062 2103 */
2063 2104 size = rx_data->ring_size * sizeof (union ixgbe_adv_rx_desc);
2064 2105 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rx_ring->hw_index), size);
2065 2106
2066 2107 /*
2067 2108 * Initialize the base address registers
2068 2109 */
2069 2110 buf_low = (uint32_t)rx_data->rbd_area.dma_address;
2070 2111 buf_high = (uint32_t)(rx_data->rbd_area.dma_address >> 32);
2071 2112 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rx_ring->hw_index), buf_high);
2072 2113 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rx_ring->hw_index), buf_low);
2073 2114
2074 2115 /*
2075 2116 * Setup head & tail pointers
2076 2117 */
2077 2118 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->hw_index),
2078 2119 rx_data->ring_size - 1);
2079 2120 IXGBE_WRITE_REG(hw, IXGBE_RDH(rx_ring->hw_index), 0);
2080 2121
2081 2122 rx_data->rbd_next = 0;
2082 2123 rx_data->lro_first = 0;
2083 2124
2084 2125 /*
2085 2126 * Setup the Receive Descriptor Control Register (RXDCTL)
2086 2127 * PTHRESH=32 descriptors (half the internal cache)
2087 2128 * HTHRESH=0 descriptors (to minimize latency on fetch)
2088 2129 * WTHRESH defaults to 1 (writeback each descriptor)
|
↓ open down ↓ |
874 lines elided |
↑ open up ↑ |
2089 2130 */
2090 2131 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->hw_index));
2091 2132 reg_val |= IXGBE_RXDCTL_ENABLE; /* enable queue */
2092 2133
2093 2134 /* Not a valid value for 82599 */
2094 2135 if (hw->mac.type < ixgbe_mac_82599EB) {
2095 2136 reg_val |= 0x0020; /* pthresh */
2096 2137 }
2097 2138 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->hw_index), reg_val);
2098 2139
2099 - if (hw->mac.type == ixgbe_mac_82599EB) {
2140 + if (hw->mac.type >= ixgbe_mac_82599EB) {
2100 2141 reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2101 2142 reg_val |= (IXGBE_RDRXCTL_CRCSTRIP | IXGBE_RDRXCTL_AGGDIS);
2102 2143 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg_val);
2103 2144 }
2104 2145
2105 2146 /*
2106 2147 * Setup the Split and Replication Receive Control Register.
2107 2148 * Set the rx buffer size and the advanced descriptor type.
2108 2149 */
2109 2150 reg_val = (ixgbe->rx_buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) |
2110 2151 IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2111 2152 reg_val |= IXGBE_SRRCTL_DROP_EN;
2112 2153 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rx_ring->hw_index), reg_val);
2113 2154 }
2114 2155
2115 2156 static void
2116 2157 ixgbe_setup_rx(ixgbe_t *ixgbe)
2117 2158 {
2118 2159 ixgbe_rx_ring_t *rx_ring;
2119 2160 struct ixgbe_hw *hw = &ixgbe->hw;
2120 2161 uint32_t reg_val;
2121 2162 uint32_t ring_mapping;
2122 2163 uint32_t i, index;
2123 2164 uint32_t psrtype_rss_bit;
2124 2165
2125 2166 /* PSRTYPE must be configured for 82599 */
2126 2167 if (ixgbe->classify_mode != IXGBE_CLASSIFY_VMDQ &&
2127 2168 ixgbe->classify_mode != IXGBE_CLASSIFY_VMDQ_RSS) {
2128 2169 reg_val = IXGBE_PSRTYPE_TCPHDR | IXGBE_PSRTYPE_UDPHDR |
2129 2170 IXGBE_PSRTYPE_IPV4HDR | IXGBE_PSRTYPE_IPV6HDR;
2130 2171 reg_val |= IXGBE_PSRTYPE_L2HDR;
2131 2172 reg_val |= 0x80000000;
2132 2173 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), reg_val);
2133 2174 } else {
2134 2175 if (ixgbe->num_rx_groups > 32) {
2135 2176 psrtype_rss_bit = 0x20000000;
2136 2177 } else {
2137 2178 psrtype_rss_bit = 0x40000000;
2138 2179 }
2139 2180 for (i = 0; i < ixgbe->capab->max_rx_grp_num; i++) {
2140 2181 reg_val = IXGBE_PSRTYPE_TCPHDR | IXGBE_PSRTYPE_UDPHDR |
2141 2182 IXGBE_PSRTYPE_IPV4HDR | IXGBE_PSRTYPE_IPV6HDR;
2142 2183 reg_val |= IXGBE_PSRTYPE_L2HDR;
2143 2184 reg_val |= psrtype_rss_bit;
2144 2185 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(i), reg_val);
2145 2186 }
2146 2187 }
2147 2188
2148 2189 /*
2149 2190 * Set filter control in FCTRL to accept broadcast packets and do
2150 2191 * not pass pause frames to host. Flow control settings are already
2151 2192 * in this register, so preserve them.
2152 2193 */
2153 2194 reg_val = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2154 2195 reg_val |= IXGBE_FCTRL_BAM; /* broadcast accept mode */
2155 2196 reg_val |= IXGBE_FCTRL_DPF; /* discard pause frames */
2156 2197 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_val);
2157 2198
2158 2199 /*
2159 2200 * Hardware checksum settings
2160 2201 */
2161 2202 if (ixgbe->rx_hcksum_enable) {
2162 2203 reg_val = IXGBE_RXCSUM_IPPCSE; /* IP checksum */
2163 2204 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, reg_val);
2164 2205 }
2165 2206
2166 2207 /*
2167 2208 * Setup VMDq and RSS for multiple receive queues
2168 2209 */
2169 2210 switch (ixgbe->classify_mode) {
2170 2211 case IXGBE_CLASSIFY_RSS:
2171 2212 /*
2172 2213 * One group, only RSS is needed when more than
2173 2214 * one ring enabled.
2174 2215 */
2175 2216 ixgbe_setup_rss(ixgbe);
2176 2217 break;
2177 2218
2178 2219 case IXGBE_CLASSIFY_VMDQ:
2179 2220 /*
2180 2221 * Multiple groups, each group has one ring,
2181 2222 * only VMDq is needed.
2182 2223 */
2183 2224 ixgbe_setup_vmdq(ixgbe);
2184 2225 break;
2185 2226
2186 2227 case IXGBE_CLASSIFY_VMDQ_RSS:
2187 2228 /*
2188 2229 * Multiple groups and multiple rings, both
2189 2230 * VMDq and RSS are needed.
2190 2231 */
2191 2232 ixgbe_setup_vmdq_rss(ixgbe);
2192 2233 break;
2193 2234
2194 2235 default:
2195 2236 break;
2196 2237 }
2197 2238
2198 2239 /*
2199 2240 * Enable the receive unit. This must be done after filter
2200 2241 * control is set in FCTRL.
2201 2242 */
2202 2243 reg_val = (IXGBE_RXCTRL_RXEN /* Enable Receive Unit */
2203 2244 | IXGBE_RXCTRL_DMBYPS); /* descriptor monitor bypass */
2204 2245 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
2205 2246
2206 2247 /*
2207 2248 * ixgbe_setup_rx_ring must be called after configuring RXCTRL
2208 2249 */
2209 2250 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2210 2251 rx_ring = &ixgbe->rx_rings[i];
2211 2252 ixgbe_setup_rx_ring(rx_ring);
2212 2253 }
2213 2254
2214 2255 /*
2215 2256 * Setup the per-ring statistics mapping.
2216 2257 */
2217 2258 ring_mapping = 0;
2218 2259 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2219 2260 index = ixgbe->rx_rings[i].hw_index;
2220 2261 ring_mapping = IXGBE_READ_REG(hw, IXGBE_RQSMR(index >> 2));
2221 2262 ring_mapping |= (i & 0xF) << (8 * (index & 0x3));
2222 2263 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(index >> 2), ring_mapping);
2223 2264 }
2224 2265
2225 2266 /*
2226 2267 * The Max Frame Size in MHADD/MAXFRS will be internally increased
2227 2268 * by four bytes if the packet has a VLAN field, so includes MTU,
2228 2269 * ethernet header and frame check sequence.
2229 2270 * Register is MAXFRS in 82599.
2230 2271 */
2231 2272 reg_val = (ixgbe->default_mtu + sizeof (struct ether_header)
2232 2273 + ETHERFCSL) << IXGBE_MHADD_MFS_SHIFT;
2233 2274 IXGBE_WRITE_REG(hw, IXGBE_MHADD, reg_val);
2234 2275
2235 2276 /*
2236 2277 * Setup Jumbo Frame enable bit
2237 2278 */
2238 2279 if (ixgbe->default_mtu > ETHERMTU) {
2239 2280 reg_val = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2240 2281 reg_val |= IXGBE_HLREG0_JUMBOEN;
2241 2282 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_val);
2242 2283 }
2243 2284
2244 2285 /*
2245 2286 * Setup RSC for multiple receive queues.
2246 2287 */
2247 2288 if (ixgbe->lro_enable) {
2248 2289 for (i = 0; i < ixgbe->num_rx_rings; i++) {
2249 2290 /*
2250 2291 * Make sure rx_buf_size * MAXDESC not greater
2251 2292 * than 65535.
2252 2293 * Intel recommends 4 for MAXDESC field value.
2253 2294 */
2254 2295 reg_val = IXGBE_READ_REG(hw, IXGBE_RSCCTL(i));
2255 2296 reg_val |= IXGBE_RSCCTL_RSCEN;
2256 2297 if (ixgbe->rx_buf_size == IXGBE_PKG_BUF_16k)
2257 2298 reg_val |= IXGBE_RSCCTL_MAXDESC_1;
2258 2299 else
2259 2300 reg_val |= IXGBE_RSCCTL_MAXDESC_4;
2260 2301 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(i), reg_val);
2261 2302 }
2262 2303
2263 2304 reg_val = IXGBE_READ_REG(hw, IXGBE_RSCDBU);
2264 2305 reg_val |= IXGBE_RSCDBU_RSCACKDIS;
2265 2306 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, reg_val);
2266 2307
2267 2308 reg_val = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2268 2309 reg_val |= IXGBE_RDRXCTL_RSCACKC;
2269 2310 reg_val |= IXGBE_RDRXCTL_FCOE_WRFIX;
2270 2311 reg_val &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2271 2312
2272 2313 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg_val);
2273 2314 }
2274 2315 }
2275 2316
2276 2317 static void
2277 2318 ixgbe_setup_tx_ring(ixgbe_tx_ring_t *tx_ring)
2278 2319 {
2279 2320 ixgbe_t *ixgbe = tx_ring->ixgbe;
2280 2321 struct ixgbe_hw *hw = &ixgbe->hw;
2281 2322 uint32_t size;
2282 2323 uint32_t buf_low;
2283 2324 uint32_t buf_high;
2284 2325 uint32_t reg_val;
2285 2326
2286 2327 ASSERT(mutex_owned(&tx_ring->tx_lock));
2287 2328 ASSERT(mutex_owned(&ixgbe->gen_lock));
2288 2329
2289 2330 /*
2290 2331 * Initialize the length register
2291 2332 */
2292 2333 size = tx_ring->ring_size * sizeof (union ixgbe_adv_tx_desc);
2293 2334 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(tx_ring->index), size);
2294 2335
2295 2336 /*
2296 2337 * Initialize the base address registers
2297 2338 */
2298 2339 buf_low = (uint32_t)tx_ring->tbd_area.dma_address;
2299 2340 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32);
2300 2341 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(tx_ring->index), buf_low);
2301 2342 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(tx_ring->index), buf_high);
2302 2343
2303 2344 /*
2304 2345 * Setup head & tail pointers
2305 2346 */
2306 2347 IXGBE_WRITE_REG(hw, IXGBE_TDH(tx_ring->index), 0);
2307 2348 IXGBE_WRITE_REG(hw, IXGBE_TDT(tx_ring->index), 0);
2308 2349
2309 2350 /*
2310 2351 * Setup head write-back
2311 2352 */
2312 2353 if (ixgbe->tx_head_wb_enable) {
2313 2354 /*
2314 2355 * The memory of the head write-back is allocated using
2315 2356 * the extra tbd beyond the tail of the tbd ring.
2316 2357 */
2317 2358 tx_ring->tbd_head_wb = (uint32_t *)
2318 2359 ((uintptr_t)tx_ring->tbd_area.address + size);
2319 2360 *tx_ring->tbd_head_wb = 0;
2320 2361
2321 2362 buf_low = (uint32_t)
2322 2363 (tx_ring->tbd_area.dma_address + size);
2323 2364 buf_high = (uint32_t)
2324 2365 ((tx_ring->tbd_area.dma_address + size) >> 32);
2325 2366
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2326 2367 /* Set the head write-back enable bit */
2327 2368 buf_low |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
2328 2369
2329 2370 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(tx_ring->index), buf_low);
2330 2371 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(tx_ring->index), buf_high);
2331 2372
2332 2373 /*
2333 2374 * Turn off relaxed ordering for head write back or it will
2334 2375 * cause problems with the tx recycling
2335 2376 */
2336 - reg_val = IXGBE_READ_REG(hw,
2337 - IXGBE_DCA_TXCTRL(tx_ring->index));
2338 - reg_val &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
2339 - IXGBE_WRITE_REG(hw,
2340 - IXGBE_DCA_TXCTRL(tx_ring->index), reg_val);
2377 +
2378 + reg_val = (hw->mac.type == ixgbe_mac_82598EB) ?
2379 + IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(tx_ring->index)) :
2380 + IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(tx_ring->index));
2381 + reg_val &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
2382 + if (hw->mac.type == ixgbe_mac_82598EB) {
2383 + IXGBE_WRITE_REG(hw,
2384 + IXGBE_DCA_TXCTRL(tx_ring->index), reg_val);
2385 + } else {
2386 + IXGBE_WRITE_REG(hw,
2387 + IXGBE_DCA_TXCTRL_82599(tx_ring->index), reg_val);
2388 + }
2341 2389 } else {
2342 2390 tx_ring->tbd_head_wb = NULL;
2343 2391 }
2344 2392
2345 2393 tx_ring->tbd_head = 0;
2346 2394 tx_ring->tbd_tail = 0;
2347 2395 tx_ring->tbd_free = tx_ring->ring_size;
2348 2396
2349 2397 if (ixgbe->tx_ring_init == B_TRUE) {
2350 2398 tx_ring->tcb_head = 0;
2351 2399 tx_ring->tcb_tail = 0;
2352 2400 tx_ring->tcb_free = tx_ring->free_list_size;
2353 2401 }
2354 2402
2355 2403 /*
2356 2404 * Initialize the s/w context structure
2357 2405 */
2358 2406 bzero(&tx_ring->tx_context, sizeof (ixgbe_tx_context_t));
2359 2407 }
2360 2408
2361 2409 static void
2362 2410 ixgbe_setup_tx(ixgbe_t *ixgbe)
2363 2411 {
2364 2412 struct ixgbe_hw *hw = &ixgbe->hw;
2365 2413 ixgbe_tx_ring_t *tx_ring;
2366 2414 uint32_t reg_val;
2367 2415 uint32_t ring_mapping;
2368 2416 int i;
2369 2417
2370 2418 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2371 2419 tx_ring = &ixgbe->tx_rings[i];
2372 2420 ixgbe_setup_tx_ring(tx_ring);
2373 2421 }
2374 2422
2375 2423 /*
2376 2424 * Setup the per-ring statistics mapping.
2377 2425 */
2378 2426 ring_mapping = 0;
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2379 2427 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2380 2428 ring_mapping |= (i & 0xF) << (8 * (i & 0x3));
2381 2429 if ((i & 0x3) == 0x3) {
2382 2430 switch (hw->mac.type) {
2383 2431 case ixgbe_mac_82598EB:
2384 2432 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i >> 2),
2385 2433 ring_mapping);
2386 2434 break;
2387 2435
2388 2436 case ixgbe_mac_82599EB:
2437 + case ixgbe_mac_X540:
2389 2438 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i >> 2),
2390 2439 ring_mapping);
2391 2440 break;
2392 2441
2393 2442 default:
2394 2443 break;
2395 2444 }
2396 2445
2397 2446 ring_mapping = 0;
2398 2447 }
2399 2448 }
2400 2449 if (i & 0x3) {
2401 2450 switch (hw->mac.type) {
2402 2451 case ixgbe_mac_82598EB:
2403 2452 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i >> 2), ring_mapping);
2404 2453 break;
2405 2454
2406 2455 case ixgbe_mac_82599EB:
2456 + case ixgbe_mac_X540:
2407 2457 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i >> 2), ring_mapping);
2408 2458 break;
2409 2459
2410 2460 default:
2411 2461 break;
2412 2462 }
2413 2463 }
2414 2464
2415 2465 /*
2416 2466 * Enable CRC appending and TX padding (for short tx frames)
2417 2467 */
2418 2468 reg_val = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2419 2469 reg_val |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN;
2420 2470 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_val);
2421 2471
2422 2472 /*
2423 - * enable DMA for 82599 parts
2473 + * enable DMA for 82599 and X540 parts
2424 2474 */
2425 - if (hw->mac.type == ixgbe_mac_82599EB) {
2426 - /* DMATXCTL.TE must be set after all Tx config is complete */
2475 + if (hw->mac.type >= ixgbe_mac_82599EB) {
2476 + /* DMATXCTL.TE must be set after all Tx config is complete */
2427 2477 reg_val = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2428 2478 reg_val |= IXGBE_DMATXCTL_TE;
2429 2479 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_val);
2480 +
2481 + /* Disable arbiter to set MTQC */
2482 + reg_val = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2483 + reg_val |= IXGBE_RTTDCS_ARBDIS;
2484 + IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg_val);
2485 + IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2486 + reg_val &= ~IXGBE_RTTDCS_ARBDIS;
2487 + IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg_val);
2430 2488 }
2431 2489
2432 2490 /*
2433 2491 * Enabling tx queues ..
2434 2492 * For 82599 must be done after DMATXCTL.TE is set
2435 2493 */
2436 2494 for (i = 0; i < ixgbe->num_tx_rings; i++) {
2437 2495 tx_ring = &ixgbe->tx_rings[i];
2438 2496 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->index));
2439 2497 reg_val |= IXGBE_TXDCTL_ENABLE;
2440 2498 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->index), reg_val);
2441 2499 }
2442 2500 }
2443 2501
2444 2502 /*
2445 2503 * ixgbe_setup_rss - Setup receive-side scaling feature.
2446 2504 */
2447 2505 static void
2448 2506 ixgbe_setup_rss(ixgbe_t *ixgbe)
2449 2507 {
2450 2508 struct ixgbe_hw *hw = &ixgbe->hw;
2451 2509 uint32_t i, mrqc, rxcsum;
2452 2510 uint32_t random;
2453 2511 uint32_t reta;
2454 2512 uint32_t ring_per_group;
2455 2513
2456 2514 /*
2457 2515 * Fill out redirection table
2458 2516 */
2459 2517 reta = 0;
2460 2518 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
2461 2519
2462 2520 for (i = 0; i < 128; i++) {
2463 2521 reta = (reta << 8) | (i % ring_per_group) |
2464 2522 ((i % ring_per_group) << 4);
2465 2523 if ((i & 3) == 3)
2466 2524 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2467 2525 }
2468 2526
2469 2527 /*
2470 2528 * Fill out hash function seeds with a random constant
2471 2529 */
2472 2530 for (i = 0; i < 10; i++) {
2473 2531 (void) random_get_pseudo_bytes((uint8_t *)&random,
2474 2532 sizeof (uint32_t));
2475 2533 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), random);
2476 2534 }
2477 2535
2478 2536 /*
2479 2537 * Enable RSS & perform hash on these packet types
2480 2538 */
2481 2539 mrqc = IXGBE_MRQC_RSSEN |
2482 2540 IXGBE_MRQC_RSS_FIELD_IPV4 |
2483 2541 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
2484 2542 IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2485 2543 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP |
2486 2544 IXGBE_MRQC_RSS_FIELD_IPV6_EX |
2487 2545 IXGBE_MRQC_RSS_FIELD_IPV6 |
2488 2546 IXGBE_MRQC_RSS_FIELD_IPV6_TCP |
2489 2547 IXGBE_MRQC_RSS_FIELD_IPV6_UDP |
2490 2548 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2491 2549 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2492 2550
2493 2551 /*
2494 2552 * Disable Packet Checksum to enable RSS for multiple receive queues.
2495 2553 * It is an adapter hardware limitation that Packet Checksum is
2496 2554 * mutually exclusive with RSS.
2497 2555 */
2498 2556 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2499 2557 rxcsum |= IXGBE_RXCSUM_PCSD;
2500 2558 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
2501 2559 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2502 2560 }
2503 2561
2504 2562 /*
2505 2563 * ixgbe_setup_vmdq - Setup MAC classification feature
2506 2564 */
2507 2565 static void
2508 2566 ixgbe_setup_vmdq(ixgbe_t *ixgbe)
2509 2567 {
2510 2568 struct ixgbe_hw *hw = &ixgbe->hw;
2511 2569 uint32_t vmdctl, i, vtctl;
2512 2570
2513 2571 /*
2514 2572 * Setup the VMDq Control register, enable VMDq based on
2515 2573 * packet destination MAC address:
2516 2574 */
2517 2575 switch (hw->mac.type) {
2518 2576 case ixgbe_mac_82598EB:
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2519 2577 /*
2520 2578 * VMDq Enable = 1;
2521 2579 * VMDq Filter = 0; MAC filtering
2522 2580 * Default VMDq output index = 0;
2523 2581 */
2524 2582 vmdctl = IXGBE_VMD_CTL_VMDQ_EN;
2525 2583 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
2526 2584 break;
2527 2585
2528 2586 case ixgbe_mac_82599EB:
2587 + case ixgbe_mac_X540:
2529 2588 /*
2530 2589 * Enable VMDq-only.
2531 2590 */
2532 2591 vmdctl = IXGBE_MRQC_VMDQEN;
2533 2592 IXGBE_WRITE_REG(hw, IXGBE_MRQC, vmdctl);
2534 2593
2535 2594 for (i = 0; i < hw->mac.num_rar_entries; i++) {
2536 2595 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(i), 0);
2537 2596 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(i), 0);
2538 2597 }
2539 2598
2540 2599 /*
2541 2600 * Enable Virtualization and Replication.
2542 2601 */
2543 2602 vtctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2544 2603 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
2545 2604
2546 2605 /*
2547 2606 * Enable receiving packets to all VFs
2548 2607 */
2549 2608 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), IXGBE_VFRE_ENABLE_ALL);
2550 2609 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), IXGBE_VFRE_ENABLE_ALL);
2551 2610 break;
2552 2611
2553 2612 default:
2554 2613 break;
2555 2614 }
2556 2615 }
2557 2616
2558 2617 /*
2559 2618 * ixgbe_setup_vmdq_rss - Setup both vmdq feature and rss feature.
2560 2619 */
2561 2620 static void
2562 2621 ixgbe_setup_vmdq_rss(ixgbe_t *ixgbe)
2563 2622 {
2564 2623 struct ixgbe_hw *hw = &ixgbe->hw;
2565 2624 uint32_t i, mrqc, rxcsum;
2566 2625 uint32_t random;
2567 2626 uint32_t reta;
2568 2627 uint32_t ring_per_group;
2569 2628 uint32_t vmdctl, vtctl;
2570 2629
2571 2630 /*
2572 2631 * Fill out redirection table
2573 2632 */
2574 2633 reta = 0;
2575 2634 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
2576 2635 for (i = 0; i < 128; i++) {
2577 2636 reta = (reta << 8) | (i % ring_per_group) |
2578 2637 ((i % ring_per_group) << 4);
2579 2638 if ((i & 3) == 3)
2580 2639 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2581 2640 }
2582 2641
2583 2642 /*
2584 2643 * Fill out hash function seeds with a random constant
2585 2644 */
2586 2645 for (i = 0; i < 10; i++) {
2587 2646 (void) random_get_pseudo_bytes((uint8_t *)&random,
2588 2647 sizeof (uint32_t));
2589 2648 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), random);
2590 2649 }
2591 2650
2592 2651 /*
2593 2652 * Enable and setup RSS and VMDq
2594 2653 */
2595 2654 switch (hw->mac.type) {
2596 2655 case ixgbe_mac_82598EB:
2597 2656 /*
2598 2657 * Enable RSS & Setup RSS Hash functions
2599 2658 */
2600 2659 mrqc = IXGBE_MRQC_RSSEN |
2601 2660 IXGBE_MRQC_RSS_FIELD_IPV4 |
2602 2661 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
2603 2662 IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2604 2663 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP |
2605 2664 IXGBE_MRQC_RSS_FIELD_IPV6_EX |
2606 2665 IXGBE_MRQC_RSS_FIELD_IPV6 |
2607 2666 IXGBE_MRQC_RSS_FIELD_IPV6_TCP |
2608 2667 IXGBE_MRQC_RSS_FIELD_IPV6_UDP |
2609 2668 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2610 2669 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2611 2670
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2612 2671 /*
2613 2672 * Enable and Setup VMDq
2614 2673 * VMDq Filter = 0; MAC filtering
2615 2674 * Default VMDq output index = 0;
2616 2675 */
2617 2676 vmdctl = IXGBE_VMD_CTL_VMDQ_EN;
2618 2677 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
2619 2678 break;
2620 2679
2621 2680 case ixgbe_mac_82599EB:
2681 + case ixgbe_mac_X540:
2622 2682 /*
2623 2683 * Enable RSS & Setup RSS Hash functions
2624 2684 */
2625 2685 mrqc = IXGBE_MRQC_RSS_FIELD_IPV4 |
2626 2686 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
2627 2687 IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2628 2688 IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP |
2629 2689 IXGBE_MRQC_RSS_FIELD_IPV6_EX |
2630 2690 IXGBE_MRQC_RSS_FIELD_IPV6 |
2631 2691 IXGBE_MRQC_RSS_FIELD_IPV6_TCP |
2632 2692 IXGBE_MRQC_RSS_FIELD_IPV6_UDP |
2633 2693 IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2634 2694
2635 2695 /*
2636 2696 * Enable VMDq+RSS.
2637 2697 */
2638 2698 if (ixgbe->num_rx_groups > 32) {
2639 2699 mrqc = mrqc | IXGBE_MRQC_VMDQRSS64EN;
2640 2700 } else {
2641 2701 mrqc = mrqc | IXGBE_MRQC_VMDQRSS32EN;
2642 2702 }
2643 2703
2644 2704 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2645 2705
2646 2706 for (i = 0; i < hw->mac.num_rar_entries; i++) {
2647 2707 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(i), 0);
2648 2708 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(i), 0);
2649 2709 }
2650 2710 break;
2651 2711
2652 2712 default:
2653 2713 break;
2654 2714
2655 2715 }
2656 2716
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2657 2717 /*
2658 2718 * Disable Packet Checksum to enable RSS for multiple receive queues.
2659 2719 * It is an adapter hardware limitation that Packet Checksum is
2660 2720 * mutually exclusive with RSS.
2661 2721 */
2662 2722 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2663 2723 rxcsum |= IXGBE_RXCSUM_PCSD;
2664 2724 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
2665 2725 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2666 2726
2667 - if (hw->mac.type == ixgbe_mac_82599EB) {
2727 + if (hw->mac.type >= ixgbe_mac_82599EB) {
2668 2728 /*
2669 2729 * Enable Virtualization and Replication.
2670 2730 */
2671 2731 vtctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2672 2732 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
2673 2733
2674 2734 /*
2675 2735 * Enable receiving packets to all VFs
2676 2736 */
2677 2737 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), IXGBE_VFRE_ENABLE_ALL);
2678 2738 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), IXGBE_VFRE_ENABLE_ALL);
2679 2739 }
2680 2740 }
2681 2741
2682 2742 /*
2683 2743 * ixgbe_init_unicst - Initialize the unicast addresses.
2684 2744 */
2685 2745 static void
2686 2746 ixgbe_init_unicst(ixgbe_t *ixgbe)
2687 2747 {
2688 2748 struct ixgbe_hw *hw = &ixgbe->hw;
2689 2749 uint8_t *mac_addr;
2690 2750 int slot;
2691 2751 /*
2692 2752 * Here we should consider two situations:
2693 2753 *
2694 2754 * 1. Chipset is initialized at the first time,
2695 2755 * Clear all the multiple unicast addresses.
2696 2756 *
2697 2757 * 2. Chipset is reset
2698 2758 * Recover the multiple unicast addresses from the
2699 2759 * software data structure to the RAR registers.
2700 2760 */
2701 2761 if (!ixgbe->unicst_init) {
2702 2762 /*
2703 2763 * Initialize the multiple unicast addresses
2704 2764 */
2705 2765 ixgbe->unicst_total = hw->mac.num_rar_entries;
2706 2766 ixgbe->unicst_avail = ixgbe->unicst_total;
2707 2767 for (slot = 0; slot < ixgbe->unicst_total; slot++) {
2708 2768 mac_addr = ixgbe->unicst_addr[slot].mac.addr;
2709 2769 bzero(mac_addr, ETHERADDRL);
2710 2770 (void) ixgbe_set_rar(hw, slot, mac_addr, NULL, NULL);
2711 2771 ixgbe->unicst_addr[slot].mac.set = 0;
2712 2772 }
2713 2773 ixgbe->unicst_init = B_TRUE;
2714 2774 } else {
2715 2775 /* Re-configure the RAR registers */
2716 2776 for (slot = 0; slot < ixgbe->unicst_total; slot++) {
2717 2777 mac_addr = ixgbe->unicst_addr[slot].mac.addr;
2718 2778 if (ixgbe->unicst_addr[slot].mac.set == 1) {
2719 2779 (void) ixgbe_set_rar(hw, slot, mac_addr,
2720 2780 ixgbe->unicst_addr[slot].mac.group_index,
2721 2781 IXGBE_RAH_AV);
2722 2782 } else {
2723 2783 bzero(mac_addr, ETHERADDRL);
2724 2784 (void) ixgbe_set_rar(hw, slot, mac_addr,
2725 2785 NULL, NULL);
2726 2786 }
2727 2787 }
2728 2788 }
2729 2789 }
2730 2790
2731 2791 /*
2732 2792 * ixgbe_unicst_find - Find the slot for the specified unicast address
2733 2793 */
2734 2794 int
2735 2795 ixgbe_unicst_find(ixgbe_t *ixgbe, const uint8_t *mac_addr)
2736 2796 {
2737 2797 int slot;
2738 2798
2739 2799 ASSERT(mutex_owned(&ixgbe->gen_lock));
2740 2800
2741 2801 for (slot = 0; slot < ixgbe->unicst_total; slot++) {
2742 2802 if (bcmp(ixgbe->unicst_addr[slot].mac.addr,
2743 2803 mac_addr, ETHERADDRL) == 0)
2744 2804 return (slot);
2745 2805 }
2746 2806
2747 2807 return (-1);
2748 2808 }
2749 2809
2750 2810 /*
2751 2811 * ixgbe_multicst_add - Add a multicst address.
2752 2812 */
2753 2813 int
2754 2814 ixgbe_multicst_add(ixgbe_t *ixgbe, const uint8_t *multiaddr)
2755 2815 {
2756 2816 ASSERT(mutex_owned(&ixgbe->gen_lock));
2757 2817
2758 2818 if ((multiaddr[0] & 01) == 0) {
2759 2819 return (EINVAL);
2760 2820 }
2761 2821
2762 2822 if (ixgbe->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) {
2763 2823 return (ENOENT);
2764 2824 }
2765 2825
2766 2826 bcopy(multiaddr,
2767 2827 &ixgbe->mcast_table[ixgbe->mcast_count], ETHERADDRL);
2768 2828 ixgbe->mcast_count++;
2769 2829
2770 2830 /*
2771 2831 * Update the multicast table in the hardware
2772 2832 */
2773 2833 ixgbe_setup_multicst(ixgbe);
2774 2834
2775 2835 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
2776 2836 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
2777 2837 return (EIO);
2778 2838 }
2779 2839
2780 2840 return (0);
2781 2841 }
2782 2842
2783 2843 /*
2784 2844 * ixgbe_multicst_remove - Remove a multicst address.
2785 2845 */
2786 2846 int
2787 2847 ixgbe_multicst_remove(ixgbe_t *ixgbe, const uint8_t *multiaddr)
2788 2848 {
2789 2849 int i;
2790 2850
2791 2851 ASSERT(mutex_owned(&ixgbe->gen_lock));
2792 2852
2793 2853 for (i = 0; i < ixgbe->mcast_count; i++) {
2794 2854 if (bcmp(multiaddr, &ixgbe->mcast_table[i],
2795 2855 ETHERADDRL) == 0) {
2796 2856 for (i++; i < ixgbe->mcast_count; i++) {
2797 2857 ixgbe->mcast_table[i - 1] =
2798 2858 ixgbe->mcast_table[i];
2799 2859 }
2800 2860 ixgbe->mcast_count--;
2801 2861 break;
2802 2862 }
2803 2863 }
2804 2864
2805 2865 /*
2806 2866 * Update the multicast table in the hardware
2807 2867 */
2808 2868 ixgbe_setup_multicst(ixgbe);
2809 2869
2810 2870 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
2811 2871 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
2812 2872 return (EIO);
2813 2873 }
2814 2874
2815 2875 return (0);
2816 2876 }
2817 2877
2818 2878 /*
2819 2879 * ixgbe_setup_multicast - Setup multicast data structures.
2820 2880 *
2821 2881 * This routine initializes all of the multicast related structures
2822 2882 * and save them in the hardware registers.
2823 2883 */
2824 2884 static void
2825 2885 ixgbe_setup_multicst(ixgbe_t *ixgbe)
2826 2886 {
2827 2887 uint8_t *mc_addr_list;
2828 2888 uint32_t mc_addr_count;
2829 2889 struct ixgbe_hw *hw = &ixgbe->hw;
2830 2890
2831 2891 ASSERT(mutex_owned(&ixgbe->gen_lock));
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2832 2892
2833 2893 ASSERT(ixgbe->mcast_count <= MAX_NUM_MULTICAST_ADDRESSES);
2834 2894
2835 2895 mc_addr_list = (uint8_t *)ixgbe->mcast_table;
2836 2896 mc_addr_count = ixgbe->mcast_count;
2837 2897
2838 2898 /*
2839 2899 * Update the multicast addresses to the MTA registers
2840 2900 */
2841 2901 (void) ixgbe_update_mc_addr_list(hw, mc_addr_list, mc_addr_count,
2842 - ixgbe_mc_table_itr);
2902 + ixgbe_mc_table_itr, TRUE);
2843 2903 }
2844 2904
2845 2905 /*
2846 2906 * ixgbe_setup_vmdq_rss_conf - Configure vmdq and rss (number and mode).
2847 2907 *
2848 2908 * Configure the rx classification mode (vmdq & rss) and vmdq & rss numbers.
2849 2909 * Different chipsets may have different allowed configuration of vmdq and rss.
2850 2910 */
2851 2911 static void
2852 2912 ixgbe_setup_vmdq_rss_conf(ixgbe_t *ixgbe)
2853 2913 {
2854 2914 struct ixgbe_hw *hw = &ixgbe->hw;
2855 2915 uint32_t ring_per_group;
2856 2916
2857 2917 switch (hw->mac.type) {
2858 2918 case ixgbe_mac_82598EB:
2859 2919 /*
2860 2920 * 82598 supports the following combination:
2861 2921 * vmdq no. x rss no.
2862 2922 * [5..16] x 1
2863 2923 * [1..4] x [1..16]
2864 2924 * However 8 rss queue per pool (vmdq) is sufficient for
2865 2925 * most cases.
2866 2926 */
2867 2927 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
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2868 2928 if (ixgbe->num_rx_groups > 4) {
2869 2929 ixgbe->num_rx_rings = ixgbe->num_rx_groups;
2870 2930 } else {
2871 2931 ixgbe->num_rx_rings = ixgbe->num_rx_groups *
2872 2932 min(8, ring_per_group);
2873 2933 }
2874 2934
2875 2935 break;
2876 2936
2877 2937 case ixgbe_mac_82599EB:
2938 + case ixgbe_mac_X540:
2878 2939 /*
2879 2940 * 82599 supports the following combination:
2880 2941 * vmdq no. x rss no.
2881 2942 * [33..64] x [1..2]
2882 2943 * [2..32] x [1..4]
2883 2944 * 1 x [1..16]
2884 2945 * However 8 rss queue per pool (vmdq) is sufficient for
2885 2946 * most cases.
2947 + *
2948 + * For now, treat X540 like the 82599.
2886 2949 */
2887 2950 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
2888 2951 if (ixgbe->num_rx_groups == 1) {
2889 2952 ixgbe->num_rx_rings = min(8, ring_per_group);
2890 2953 } else if (ixgbe->num_rx_groups <= 32) {
2891 2954 ixgbe->num_rx_rings = ixgbe->num_rx_groups *
2892 2955 min(4, ring_per_group);
2893 2956 } else if (ixgbe->num_rx_groups <= 64) {
2894 2957 ixgbe->num_rx_rings = ixgbe->num_rx_groups *
2895 2958 min(2, ring_per_group);
2896 2959 }
2897 2960 break;
2898 2961
2899 2962 default:
2900 2963 break;
2901 2964 }
2902 2965
2903 2966 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
2904 2967
2905 2968 if (ixgbe->num_rx_groups == 1 && ring_per_group == 1) {
2906 2969 ixgbe->classify_mode = IXGBE_CLASSIFY_NONE;
2907 2970 } else if (ixgbe->num_rx_groups != 1 && ring_per_group == 1) {
2908 2971 ixgbe->classify_mode = IXGBE_CLASSIFY_VMDQ;
2909 2972 } else if (ixgbe->num_rx_groups != 1 && ring_per_group != 1) {
2910 2973 ixgbe->classify_mode = IXGBE_CLASSIFY_VMDQ_RSS;
2911 2974 } else {
2912 2975 ixgbe->classify_mode = IXGBE_CLASSIFY_RSS;
2913 2976 }
2914 2977
2915 2978 IXGBE_DEBUGLOG_2(ixgbe, "rx group number:%d, rx ring number:%d",
2916 2979 ixgbe->num_rx_groups, ixgbe->num_rx_rings);
2917 2980 }
2918 2981
2919 2982 /*
2920 2983 * ixgbe_get_conf - Get driver configurations set in driver.conf.
2921 2984 *
2922 2985 * This routine gets user-configured values out of the configuration
2923 2986 * file ixgbe.conf.
2924 2987 *
2925 2988 * For each configurable value, there is a minimum, a maximum, and a
2926 2989 * default.
2927 2990 * If user does not configure a value, use the default.
2928 2991 * If user configures below the minimum, use the minumum.
2929 2992 * If user configures above the maximum, use the maxumum.
2930 2993 */
2931 2994 static void
2932 2995 ixgbe_get_conf(ixgbe_t *ixgbe)
2933 2996 {
2934 2997 struct ixgbe_hw *hw = &ixgbe->hw;
2935 2998 uint32_t flow_control;
2936 2999
2937 3000 /*
2938 3001 * ixgbe driver supports the following user configurations:
2939 3002 *
2940 3003 * Jumbo frame configuration:
2941 3004 * default_mtu
2942 3005 *
2943 3006 * Ethernet flow control configuration:
2944 3007 * flow_control
2945 3008 *
2946 3009 * Multiple rings configurations:
2947 3010 * tx_queue_number
2948 3011 * tx_ring_size
2949 3012 * rx_queue_number
2950 3013 * rx_ring_size
2951 3014 *
2952 3015 * Call ixgbe_get_prop() to get the value for a specific
2953 3016 * configuration parameter.
2954 3017 */
2955 3018
2956 3019 /*
2957 3020 * Jumbo frame configuration - max_frame_size controls host buffer
2958 3021 * allocation, so includes MTU, ethernet header, vlan tag and
2959 3022 * frame check sequence.
2960 3023 */
2961 3024 ixgbe->default_mtu = ixgbe_get_prop(ixgbe, PROP_DEFAULT_MTU,
2962 3025 MIN_MTU, ixgbe->capab->max_mtu, DEFAULT_MTU);
2963 3026
2964 3027 ixgbe->max_frame_size = ixgbe->default_mtu +
2965 3028 sizeof (struct ether_vlan_header) + ETHERFCSL;
2966 3029
2967 3030 /*
2968 3031 * Ethernet flow control configuration
2969 3032 */
2970 3033 flow_control = ixgbe_get_prop(ixgbe, PROP_FLOW_CONTROL,
2971 3034 ixgbe_fc_none, 3, ixgbe_fc_none);
2972 3035 if (flow_control == 3)
2973 3036 flow_control = ixgbe_fc_default;
2974 3037
2975 3038 /*
2976 3039 * fc.requested mode is what the user requests. After autoneg,
2977 3040 * fc.current_mode will be the flow_control mode that was negotiated.
2978 3041 */
2979 3042 hw->fc.requested_mode = flow_control;
2980 3043
2981 3044 /*
2982 3045 * Multiple rings configurations
2983 3046 */
2984 3047 ixgbe->num_tx_rings = ixgbe_get_prop(ixgbe, PROP_TX_QUEUE_NUM,
2985 3048 ixgbe->capab->min_tx_que_num,
2986 3049 ixgbe->capab->max_tx_que_num,
2987 3050 ixgbe->capab->def_tx_que_num);
2988 3051 ixgbe->tx_ring_size = ixgbe_get_prop(ixgbe, PROP_TX_RING_SIZE,
2989 3052 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE);
2990 3053
2991 3054 ixgbe->num_rx_rings = ixgbe_get_prop(ixgbe, PROP_RX_QUEUE_NUM,
2992 3055 ixgbe->capab->min_rx_que_num,
2993 3056 ixgbe->capab->max_rx_que_num,
2994 3057 ixgbe->capab->def_rx_que_num);
2995 3058 ixgbe->rx_ring_size = ixgbe_get_prop(ixgbe, PROP_RX_RING_SIZE,
2996 3059 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE);
2997 3060
2998 3061 /*
2999 3062 * Multiple groups configuration
3000 3063 */
3001 3064 ixgbe->num_rx_groups = ixgbe_get_prop(ixgbe, PROP_RX_GROUP_NUM,
3002 3065 ixgbe->capab->min_rx_grp_num, ixgbe->capab->max_rx_grp_num,
3003 3066 ixgbe->capab->def_rx_grp_num);
3004 3067
3005 3068 ixgbe->mr_enable = ixgbe_get_prop(ixgbe, PROP_MR_ENABLE,
3006 3069 0, 1, DEFAULT_MR_ENABLE);
3007 3070
3008 3071 if (ixgbe->mr_enable == B_FALSE) {
3009 3072 ixgbe->num_tx_rings = 1;
3010 3073 ixgbe->num_rx_rings = 1;
3011 3074 ixgbe->num_rx_groups = 1;
3012 3075 ixgbe->classify_mode = IXGBE_CLASSIFY_NONE;
3013 3076 } else {
3014 3077 ixgbe->num_rx_rings = ixgbe->num_rx_groups *
3015 3078 max(ixgbe->num_rx_rings / ixgbe->num_rx_groups, 1);
3016 3079 /*
3017 3080 * The combination of num_rx_rings and num_rx_groups
3018 3081 * may be not supported by h/w. We need to adjust
3019 3082 * them to appropriate values.
3020 3083 */
3021 3084 ixgbe_setup_vmdq_rss_conf(ixgbe);
3022 3085 }
3023 3086
3024 3087 /*
3025 3088 * Tunable used to force an interrupt type. The only use is
3026 3089 * for testing of the lesser interrupt types.
3027 3090 * 0 = don't force interrupt type
3028 3091 * 1 = force interrupt type MSI-X
3029 3092 * 2 = force interrupt type MSI
3030 3093 * 3 = force interrupt type Legacy
3031 3094 */
3032 3095 ixgbe->intr_force = ixgbe_get_prop(ixgbe, PROP_INTR_FORCE,
3033 3096 IXGBE_INTR_NONE, IXGBE_INTR_LEGACY, IXGBE_INTR_NONE);
3034 3097
3035 3098 ixgbe->tx_hcksum_enable = ixgbe_get_prop(ixgbe, PROP_TX_HCKSUM_ENABLE,
3036 3099 0, 1, DEFAULT_TX_HCKSUM_ENABLE);
3037 3100 ixgbe->rx_hcksum_enable = ixgbe_get_prop(ixgbe, PROP_RX_HCKSUM_ENABLE,
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3038 3101 0, 1, DEFAULT_RX_HCKSUM_ENABLE);
3039 3102 ixgbe->lso_enable = ixgbe_get_prop(ixgbe, PROP_LSO_ENABLE,
3040 3103 0, 1, DEFAULT_LSO_ENABLE);
3041 3104 ixgbe->lro_enable = ixgbe_get_prop(ixgbe, PROP_LRO_ENABLE,
3042 3105 0, 1, DEFAULT_LRO_ENABLE);
3043 3106 ixgbe->tx_head_wb_enable = ixgbe_get_prop(ixgbe, PROP_TX_HEAD_WB_ENABLE,
3044 3107 0, 1, DEFAULT_TX_HEAD_WB_ENABLE);
3045 3108 ixgbe->relax_order_enable = ixgbe_get_prop(ixgbe,
3046 3109 PROP_RELAX_ORDER_ENABLE, 0, 1, DEFAULT_RELAX_ORDER_ENABLE);
3047 3110
3048 - /* Head Write Back not recommended for 82599 */
3111 + /* Head Write Back not recommended for 82599 and X540 */
3049 3112 if (hw->mac.type >= ixgbe_mac_82599EB) {
3050 3113 ixgbe->tx_head_wb_enable = B_FALSE;
3051 3114 }
3052 3115
3053 3116 /*
3054 3117 * ixgbe LSO needs the tx h/w checksum support.
3055 3118 * LSO will be disabled if tx h/w checksum is not
3056 3119 * enabled.
3057 3120 */
3058 3121 if (ixgbe->tx_hcksum_enable == B_FALSE) {
3059 3122 ixgbe->lso_enable = B_FALSE;
3060 3123 }
3061 3124
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3062 3125 /*
3063 3126 * ixgbe LRO needs the rx h/w checksum support.
3064 3127 * LRO will be disabled if rx h/w checksum is not
3065 3128 * enabled.
3066 3129 */
3067 3130 if (ixgbe->rx_hcksum_enable == B_FALSE) {
3068 3131 ixgbe->lro_enable = B_FALSE;
3069 3132 }
3070 3133
3071 3134 /*
3072 - * ixgbe LRO only been supported by 82599 now
3135 + * ixgbe LRO only been supported by 82599 and X540 now
3073 3136 */
3074 - if (hw->mac.type != ixgbe_mac_82599EB) {
3137 + if (hw->mac.type < ixgbe_mac_82599EB) {
3075 3138 ixgbe->lro_enable = B_FALSE;
3076 3139 }
3077 3140 ixgbe->tx_copy_thresh = ixgbe_get_prop(ixgbe, PROP_TX_COPY_THRESHOLD,
3078 3141 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD,
3079 3142 DEFAULT_TX_COPY_THRESHOLD);
3080 3143 ixgbe->tx_recycle_thresh = ixgbe_get_prop(ixgbe,
3081 3144 PROP_TX_RECYCLE_THRESHOLD, MIN_TX_RECYCLE_THRESHOLD,
3082 3145 MAX_TX_RECYCLE_THRESHOLD, DEFAULT_TX_RECYCLE_THRESHOLD);
3083 3146 ixgbe->tx_overload_thresh = ixgbe_get_prop(ixgbe,
3084 3147 PROP_TX_OVERLOAD_THRESHOLD, MIN_TX_OVERLOAD_THRESHOLD,
3085 3148 MAX_TX_OVERLOAD_THRESHOLD, DEFAULT_TX_OVERLOAD_THRESHOLD);
3086 3149 ixgbe->tx_resched_thresh = ixgbe_get_prop(ixgbe,
3087 3150 PROP_TX_RESCHED_THRESHOLD, MIN_TX_RESCHED_THRESHOLD,
3088 3151 MAX_TX_RESCHED_THRESHOLD, DEFAULT_TX_RESCHED_THRESHOLD);
3089 3152
3090 3153 ixgbe->rx_copy_thresh = ixgbe_get_prop(ixgbe, PROP_RX_COPY_THRESHOLD,
3091 3154 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD,
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3092 3155 DEFAULT_RX_COPY_THRESHOLD);
3093 3156 ixgbe->rx_limit_per_intr = ixgbe_get_prop(ixgbe, PROP_RX_LIMIT_PER_INTR,
3094 3157 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR,
3095 3158 DEFAULT_RX_LIMIT_PER_INTR);
3096 3159
3097 3160 ixgbe->intr_throttling[0] = ixgbe_get_prop(ixgbe, PROP_INTR_THROTTLING,
3098 3161 ixgbe->capab->min_intr_throttle,
3099 3162 ixgbe->capab->max_intr_throttle,
3100 3163 ixgbe->capab->def_intr_throttle);
3101 3164 /*
3102 - * 82599 requires the interupt throttling rate is
3165 + * 82599 and X540 require the interupt throttling rate is
3103 3166 * a multiple of 8. This is enforced by the register
3104 3167 * definiton.
3105 3168 */
3106 - if (hw->mac.type == ixgbe_mac_82599EB)
3169 + if (hw->mac.type >= ixgbe_mac_82599EB)
3107 3170 ixgbe->intr_throttling[0] = ixgbe->intr_throttling[0] & 0xFF8;
3108 3171 }
3109 3172
3110 3173 static void
3111 3174 ixgbe_init_params(ixgbe_t *ixgbe)
3112 3175 {
3113 3176 ixgbe->param_en_10000fdx_cap = 1;
3114 3177 ixgbe->param_en_1000fdx_cap = 1;
3115 3178 ixgbe->param_en_100fdx_cap = 1;
3116 3179 ixgbe->param_adv_10000fdx_cap = 1;
3117 3180 ixgbe->param_adv_1000fdx_cap = 1;
3118 3181 ixgbe->param_adv_100fdx_cap = 1;
3119 3182
3120 3183 ixgbe->param_pause_cap = 1;
3121 3184 ixgbe->param_asym_pause_cap = 1;
3122 3185 ixgbe->param_rem_fault = 0;
3123 3186
3124 3187 ixgbe->param_adv_autoneg_cap = 1;
3125 3188 ixgbe->param_adv_pause_cap = 1;
3126 3189 ixgbe->param_adv_asym_pause_cap = 1;
3127 3190 ixgbe->param_adv_rem_fault = 0;
3128 3191
3129 3192 ixgbe->param_lp_10000fdx_cap = 0;
3130 3193 ixgbe->param_lp_1000fdx_cap = 0;
3131 3194 ixgbe->param_lp_100fdx_cap = 0;
3132 3195 ixgbe->param_lp_autoneg_cap = 0;
3133 3196 ixgbe->param_lp_pause_cap = 0;
3134 3197 ixgbe->param_lp_asym_pause_cap = 0;
3135 3198 ixgbe->param_lp_rem_fault = 0;
3136 3199 }
3137 3200
3138 3201 /*
3139 3202 * ixgbe_get_prop - Get a property value out of the configuration file
3140 3203 * ixgbe.conf.
3141 3204 *
3142 3205 * Caller provides the name of the property, a default value, a minimum
3143 3206 * value, and a maximum value.
3144 3207 *
3145 3208 * Return configured value of the property, with default, minimum and
3146 3209 * maximum properly applied.
3147 3210 */
3148 3211 static int
3149 3212 ixgbe_get_prop(ixgbe_t *ixgbe,
3150 3213 char *propname, /* name of the property */
3151 3214 int minval, /* minimum acceptable value */
3152 3215 int maxval, /* maximim acceptable value */
3153 3216 int defval) /* default value */
3154 3217 {
3155 3218 int value;
3156 3219
3157 3220 /*
3158 3221 * Call ddi_prop_get_int() to read the conf settings
3159 3222 */
3160 3223 value = ddi_prop_get_int(DDI_DEV_T_ANY, ixgbe->dip,
3161 3224 DDI_PROP_DONTPASS, propname, defval);
3162 3225 if (value > maxval)
3163 3226 value = maxval;
3164 3227
3165 3228 if (value < minval)
3166 3229 value = minval;
3167 3230
3168 3231 return (value);
3169 3232 }
3170 3233
3171 3234 /*
3172 3235 * ixgbe_driver_setup_link - Using the link properties to setup the link.
3173 3236 */
3174 3237 int
3175 3238 ixgbe_driver_setup_link(ixgbe_t *ixgbe, boolean_t setup_hw)
3176 3239 {
3177 3240 u32 autoneg_advertised = 0;
3178 3241
3179 3242 /*
3180 3243 * No half duplex support with 10Gb parts
3181 3244 */
3182 3245 if (ixgbe->param_adv_10000fdx_cap == 1)
3183 3246 autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
3184 3247
3185 3248 if (ixgbe->param_adv_1000fdx_cap == 1)
3186 3249 autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
3187 3250
3188 3251 if (ixgbe->param_adv_100fdx_cap == 1)
3189 3252 autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
3190 3253
3191 3254 if (ixgbe->param_adv_autoneg_cap == 1 && autoneg_advertised == 0) {
3192 3255 ixgbe_notice(ixgbe, "Invalid link settings. Setup link "
3193 3256 "to autonegotiation with full link capabilities.");
3194 3257
3195 3258 autoneg_advertised = IXGBE_LINK_SPEED_10GB_FULL |
3196 3259 IXGBE_LINK_SPEED_1GB_FULL |
3197 3260 IXGBE_LINK_SPEED_100_FULL;
3198 3261 }
3199 3262
3200 3263 if (setup_hw) {
3201 3264 if (ixgbe_setup_link(&ixgbe->hw, autoneg_advertised,
3202 3265 ixgbe->param_adv_autoneg_cap, B_TRUE) != IXGBE_SUCCESS) {
3203 3266 ixgbe_notice(ixgbe, "Setup link failed on this "
3204 3267 "device.");
3205 3268 return (IXGBE_FAILURE);
3206 3269 }
3207 3270 }
3208 3271
3209 3272 return (IXGBE_SUCCESS);
3210 3273 }
3211 3274
3212 3275 /*
3213 3276 * ixgbe_driver_link_check - Link status processing.
3214 3277 *
3215 3278 * This function can be called in both kernel context and interrupt context
3216 3279 */
3217 3280 static void
3218 3281 ixgbe_driver_link_check(ixgbe_t *ixgbe)
3219 3282 {
3220 3283 struct ixgbe_hw *hw = &ixgbe->hw;
3221 3284 ixgbe_link_speed speed = IXGBE_LINK_SPEED_UNKNOWN;
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3222 3285 boolean_t link_up = B_FALSE;
3223 3286 boolean_t link_changed = B_FALSE;
3224 3287
3225 3288 ASSERT(mutex_owned(&ixgbe->gen_lock));
3226 3289
3227 3290 (void) ixgbe_check_link(hw, &speed, &link_up, false);
3228 3291 if (link_up) {
3229 3292 ixgbe->link_check_complete = B_TRUE;
3230 3293
3231 3294 /* Link is up, enable flow control settings */
3232 - (void) ixgbe_fc_enable(hw, 0);
3295 + (void) ixgbe_fc_enable(hw);
3233 3296
3234 3297 /*
3235 3298 * The Link is up, check whether it was marked as down earlier
3236 3299 */
3237 3300 if (ixgbe->link_state != LINK_STATE_UP) {
3238 3301 switch (speed) {
3239 3302 case IXGBE_LINK_SPEED_10GB_FULL:
3240 3303 ixgbe->link_speed = SPEED_10GB;
3241 3304 break;
3242 3305 case IXGBE_LINK_SPEED_1GB_FULL:
3243 3306 ixgbe->link_speed = SPEED_1GB;
3244 3307 break;
3245 3308 case IXGBE_LINK_SPEED_100_FULL:
3246 3309 ixgbe->link_speed = SPEED_100;
3247 3310 }
3248 3311 ixgbe->link_duplex = LINK_DUPLEX_FULL;
3249 3312 ixgbe->link_state = LINK_STATE_UP;
3250 3313 link_changed = B_TRUE;
3251 3314 }
3252 3315 } else {
3253 3316 if (ixgbe->link_check_complete == B_TRUE ||
3254 3317 (ixgbe->link_check_complete == B_FALSE &&
3255 3318 gethrtime() >= ixgbe->link_check_hrtime)) {
3256 3319 /*
3257 3320 * The link is really down
3258 3321 */
3259 3322 ixgbe->link_check_complete = B_TRUE;
3260 3323
3261 3324 if (ixgbe->link_state != LINK_STATE_DOWN) {
3262 3325 ixgbe->link_speed = 0;
3263 3326 ixgbe->link_duplex = LINK_DUPLEX_UNKNOWN;
3264 3327 ixgbe->link_state = LINK_STATE_DOWN;
3265 3328 link_changed = B_TRUE;
3266 3329 }
3267 3330 }
3268 3331 }
3269 3332
3270 3333 /*
3271 3334 * If we are in an interrupt context, need to re-enable the
3272 3335 * interrupt, which was automasked
3273 3336 */
3274 3337 if (servicing_interrupt() != 0) {
3275 3338 ixgbe->eims |= IXGBE_EICR_LSC;
3276 3339 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
3277 3340 }
3278 3341
3279 3342 if (link_changed) {
3280 3343 mac_link_update(ixgbe->mac_hdl, ixgbe->link_state);
3281 3344 }
3282 3345 }
3283 3346
3284 3347 /*
3285 3348 * ixgbe_sfp_check - sfp module processing done in taskq only for 82599.
3286 3349 */
3287 3350 static void
3288 3351 ixgbe_sfp_check(void *arg)
3289 3352 {
3290 3353 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3291 3354 uint32_t eicr = ixgbe->eicr;
3292 3355 struct ixgbe_hw *hw = &ixgbe->hw;
3293 3356
3294 3357 mutex_enter(&ixgbe->gen_lock);
3295 3358 if (eicr & IXGBE_EICR_GPI_SDP1) {
3296 3359 /* clear the interrupt */
3297 3360 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
3298 3361
3299 3362 /* if link up, do multispeed fiber setup */
3300 3363 (void) ixgbe_setup_link(hw, IXGBE_LINK_SPEED_82599_AUTONEG,
3301 3364 B_TRUE, B_TRUE);
3302 3365 ixgbe_driver_link_check(ixgbe);
3303 3366 ixgbe_get_hw_state(ixgbe);
3304 3367 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
3305 3368 /* clear the interrupt */
3306 3369 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
3307 3370
3308 3371 /* if link up, do sfp module setup */
3309 3372 (void) hw->mac.ops.setup_sfp(hw);
3310 3373
3311 3374 /* do multispeed fiber setup */
3312 3375 (void) ixgbe_setup_link(hw, IXGBE_LINK_SPEED_82599_AUTONEG,
3313 3376 B_TRUE, B_TRUE);
3314 3377 ixgbe_driver_link_check(ixgbe);
3315 3378 ixgbe_get_hw_state(ixgbe);
3316 3379 }
3317 3380 mutex_exit(&ixgbe->gen_lock);
3318 3381
3319 3382 /*
3320 3383 * We need to fully re-check the link later.
3321 3384 */
3322 3385 ixgbe->link_check_complete = B_FALSE;
3323 3386 ixgbe->link_check_hrtime = gethrtime() +
3324 3387 (IXGBE_LINK_UP_TIME * 100000000ULL);
3325 3388 }
3326 3389
3327 3390 /*
3328 3391 * ixgbe_overtemp_check - overtemp module processing done in taskq
3329 3392 *
3330 3393 * This routine will only be called on adapters with temperature sensor.
3331 3394 * The indication of over-temperature can be either SDP0 interrupt or the link
3332 3395 * status change interrupt.
3333 3396 */
3334 3397 static void
3335 3398 ixgbe_overtemp_check(void *arg)
3336 3399 {
3337 3400 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3338 3401 struct ixgbe_hw *hw = &ixgbe->hw;
3339 3402 uint32_t eicr = ixgbe->eicr;
3340 3403 ixgbe_link_speed speed;
3341 3404 boolean_t link_up;
3342 3405
3343 3406 mutex_enter(&ixgbe->gen_lock);
3344 3407
3345 3408 /* make sure we know current state of link */
3346 3409 (void) ixgbe_check_link(hw, &speed, &link_up, false);
3347 3410
3348 3411 /* check over-temp condition */
3349 3412 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
3350 3413 (eicr & IXGBE_EICR_LSC)) {
3351 3414 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP) {
3352 3415 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_OVERTEMP);
3353 3416
3354 3417 /*
3355 3418 * Disable the adapter interrupts
3356 3419 */
3357 3420 ixgbe_disable_adapter_interrupts(ixgbe);
3358 3421
3359 3422 /*
3360 3423 * Disable Rx/Tx units
3361 3424 */
3362 3425 (void) ixgbe_stop_adapter(hw);
3363 3426
3364 3427 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
3365 3428 ixgbe_error(ixgbe,
3366 3429 "Problem: Network adapter has been stopped "
3367 3430 "because it has overheated");
3368 3431 ixgbe_error(ixgbe,
3369 3432 "Action: Restart the computer. "
3370 3433 "If the problem persists, power off the system "
3371 3434 "and replace the adapter");
3372 3435 }
3373 3436 }
3374 3437
3375 3438 /* write to clear the interrupt */
3376 3439 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
3377 3440
3378 3441 mutex_exit(&ixgbe->gen_lock);
3379 3442 }
3380 3443
3381 3444 /*
3382 3445 * ixgbe_link_timer - timer for link status detection
3383 3446 */
3384 3447 static void
3385 3448 ixgbe_link_timer(void *arg)
3386 3449 {
3387 3450 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3388 3451
3389 3452 mutex_enter(&ixgbe->gen_lock);
3390 3453 ixgbe_driver_link_check(ixgbe);
3391 3454 mutex_exit(&ixgbe->gen_lock);
3392 3455 }
3393 3456
3394 3457 /*
3395 3458 * ixgbe_local_timer - Driver watchdog function.
3396 3459 *
3397 3460 * This function will handle the transmit stall check and other routines.
3398 3461 */
3399 3462 static void
3400 3463 ixgbe_local_timer(void *arg)
3401 3464 {
3402 3465 ixgbe_t *ixgbe = (ixgbe_t *)arg;
3403 3466
3404 3467 if (ixgbe->ixgbe_state & IXGBE_OVERTEMP)
3405 3468 goto out;
3406 3469
3407 3470 if (ixgbe->ixgbe_state & IXGBE_ERROR) {
3408 3471 ixgbe->reset_count++;
3409 3472 if (ixgbe_reset(ixgbe) == IXGBE_SUCCESS)
3410 3473 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_RESTORED);
3411 3474 goto out;
3412 3475 }
3413 3476
3414 3477 if (ixgbe_stall_check(ixgbe)) {
3415 3478 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_STALL);
3416 3479 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
3417 3480
3418 3481 ixgbe->reset_count++;
3419 3482 if (ixgbe_reset(ixgbe) == IXGBE_SUCCESS)
3420 3483 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_RESTORED);
3421 3484 }
3422 3485
3423 3486 out:
3424 3487 ixgbe_restart_watchdog_timer(ixgbe);
3425 3488 }
3426 3489
3427 3490 /*
3428 3491 * ixgbe_stall_check - Check for transmit stall.
3429 3492 *
3430 3493 * This function checks if the adapter is stalled (in transmit).
3431 3494 *
3432 3495 * It is called each time the watchdog timeout is invoked.
3433 3496 * If the transmit descriptor reclaim continuously fails,
3434 3497 * the watchdog value will increment by 1. If the watchdog
3435 3498 * value exceeds the threshold, the ixgbe is assumed to
3436 3499 * have stalled and need to be reset.
3437 3500 */
3438 3501 static boolean_t
3439 3502 ixgbe_stall_check(ixgbe_t *ixgbe)
3440 3503 {
3441 3504 ixgbe_tx_ring_t *tx_ring;
3442 3505 boolean_t result;
3443 3506 int i;
3444 3507
3445 3508 if (ixgbe->link_state != LINK_STATE_UP)
3446 3509 return (B_FALSE);
3447 3510
3448 3511 /*
3449 3512 * If any tx ring is stalled, we'll reset the chipset
3450 3513 */
3451 3514 result = B_FALSE;
3452 3515 for (i = 0; i < ixgbe->num_tx_rings; i++) {
3453 3516 tx_ring = &ixgbe->tx_rings[i];
3454 3517 if (tx_ring->tbd_free <= ixgbe->tx_recycle_thresh) {
3455 3518 tx_ring->tx_recycle(tx_ring);
3456 3519 }
3457 3520
3458 3521 if (tx_ring->recycle_fail > 0)
3459 3522 tx_ring->stall_watchdog++;
3460 3523 else
3461 3524 tx_ring->stall_watchdog = 0;
3462 3525
3463 3526 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) {
3464 3527 result = B_TRUE;
3465 3528 break;
3466 3529 }
3467 3530 }
3468 3531
3469 3532 if (result) {
3470 3533 tx_ring->stall_watchdog = 0;
3471 3534 tx_ring->recycle_fail = 0;
3472 3535 }
3473 3536
3474 3537 return (result);
3475 3538 }
3476 3539
3477 3540
3478 3541 /*
3479 3542 * is_valid_mac_addr - Check if the mac address is valid.
3480 3543 */
3481 3544 static boolean_t
3482 3545 is_valid_mac_addr(uint8_t *mac_addr)
3483 3546 {
3484 3547 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 };
3485 3548 const uint8_t addr_test2[6] =
3486 3549 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3487 3550
3488 3551 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) ||
3489 3552 !(bcmp(addr_test2, mac_addr, ETHERADDRL)))
3490 3553 return (B_FALSE);
3491 3554
3492 3555 return (B_TRUE);
3493 3556 }
3494 3557
3495 3558 static boolean_t
3496 3559 ixgbe_find_mac_address(ixgbe_t *ixgbe)
3497 3560 {
3498 3561 #ifdef __sparc
3499 3562 struct ixgbe_hw *hw = &ixgbe->hw;
3500 3563 uchar_t *bytes;
3501 3564 struct ether_addr sysaddr;
3502 3565 uint_t nelts;
3503 3566 int err;
3504 3567 boolean_t found = B_FALSE;
3505 3568
3506 3569 /*
3507 3570 * The "vendor's factory-set address" may already have
3508 3571 * been extracted from the chip, but if the property
3509 3572 * "local-mac-address" is set we use that instead.
3510 3573 *
3511 3574 * We check whether it looks like an array of 6
3512 3575 * bytes (which it should, if OBP set it). If we can't
3513 3576 * make sense of it this way, we'll ignore it.
3514 3577 */
3515 3578 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, ixgbe->dip,
3516 3579 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts);
3517 3580 if (err == DDI_PROP_SUCCESS) {
3518 3581 if (nelts == ETHERADDRL) {
3519 3582 while (nelts--)
3520 3583 hw->mac.addr[nelts] = bytes[nelts];
3521 3584 found = B_TRUE;
3522 3585 }
3523 3586 ddi_prop_free(bytes);
3524 3587 }
3525 3588
3526 3589 /*
3527 3590 * Look up the OBP property "local-mac-address?". If the user has set
3528 3591 * 'local-mac-address? = false', use "the system address" instead.
3529 3592 */
3530 3593 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, ixgbe->dip, 0,
3531 3594 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) {
3532 3595 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) {
3533 3596 if (localetheraddr(NULL, &sysaddr) != 0) {
3534 3597 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL);
3535 3598 found = B_TRUE;
3536 3599 }
3537 3600 }
3538 3601 ddi_prop_free(bytes);
3539 3602 }
3540 3603
3541 3604 /*
3542 3605 * Finally(!), if there's a valid "mac-address" property (created
3543 3606 * if we netbooted from this interface), we must use this instead
3544 3607 * of any of the above to ensure that the NFS/install server doesn't
3545 3608 * get confused by the address changing as Solaris takes over!
3546 3609 */
3547 3610 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, ixgbe->dip,
3548 3611 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts);
3549 3612 if (err == DDI_PROP_SUCCESS) {
3550 3613 if (nelts == ETHERADDRL) {
3551 3614 while (nelts--)
3552 3615 hw->mac.addr[nelts] = bytes[nelts];
3553 3616 found = B_TRUE;
3554 3617 }
3555 3618 ddi_prop_free(bytes);
3556 3619 }
3557 3620
3558 3621 if (found) {
3559 3622 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL);
3560 3623 return (B_TRUE);
3561 3624 }
3562 3625 #else
3563 3626 _NOTE(ARGUNUSED(ixgbe));
3564 3627 #endif
3565 3628
3566 3629 return (B_TRUE);
3567 3630 }
3568 3631
3569 3632 #pragma inline(ixgbe_arm_watchdog_timer)
3570 3633 static void
3571 3634 ixgbe_arm_watchdog_timer(ixgbe_t *ixgbe)
3572 3635 {
3573 3636 /*
3574 3637 * Fire a watchdog timer
3575 3638 */
3576 3639 ixgbe->watchdog_tid =
3577 3640 timeout(ixgbe_local_timer,
3578 3641 (void *)ixgbe, 1 * drv_usectohz(1000000));
3579 3642
3580 3643 }
3581 3644
3582 3645 /*
3583 3646 * ixgbe_enable_watchdog_timer - Enable and start the driver watchdog timer.
3584 3647 */
3585 3648 void
3586 3649 ixgbe_enable_watchdog_timer(ixgbe_t *ixgbe)
3587 3650 {
3588 3651 mutex_enter(&ixgbe->watchdog_lock);
3589 3652
3590 3653 if (!ixgbe->watchdog_enable) {
3591 3654 ixgbe->watchdog_enable = B_TRUE;
3592 3655 ixgbe->watchdog_start = B_TRUE;
3593 3656 ixgbe_arm_watchdog_timer(ixgbe);
3594 3657 }
3595 3658
3596 3659 mutex_exit(&ixgbe->watchdog_lock);
3597 3660 }
3598 3661
3599 3662 /*
3600 3663 * ixgbe_disable_watchdog_timer - Disable and stop the driver watchdog timer.
3601 3664 */
3602 3665 void
3603 3666 ixgbe_disable_watchdog_timer(ixgbe_t *ixgbe)
3604 3667 {
3605 3668 timeout_id_t tid;
3606 3669
3607 3670 mutex_enter(&ixgbe->watchdog_lock);
3608 3671
3609 3672 ixgbe->watchdog_enable = B_FALSE;
3610 3673 ixgbe->watchdog_start = B_FALSE;
3611 3674 tid = ixgbe->watchdog_tid;
3612 3675 ixgbe->watchdog_tid = 0;
3613 3676
3614 3677 mutex_exit(&ixgbe->watchdog_lock);
3615 3678
3616 3679 if (tid != 0)
3617 3680 (void) untimeout(tid);
3618 3681 }
3619 3682
3620 3683 /*
3621 3684 * ixgbe_start_watchdog_timer - Start the driver watchdog timer.
3622 3685 */
3623 3686 void
3624 3687 ixgbe_start_watchdog_timer(ixgbe_t *ixgbe)
3625 3688 {
3626 3689 mutex_enter(&ixgbe->watchdog_lock);
3627 3690
3628 3691 if (ixgbe->watchdog_enable) {
3629 3692 if (!ixgbe->watchdog_start) {
3630 3693 ixgbe->watchdog_start = B_TRUE;
3631 3694 ixgbe_arm_watchdog_timer(ixgbe);
3632 3695 }
3633 3696 }
3634 3697
3635 3698 mutex_exit(&ixgbe->watchdog_lock);
3636 3699 }
3637 3700
3638 3701 /*
3639 3702 * ixgbe_restart_watchdog_timer - Restart the driver watchdog timer.
3640 3703 */
3641 3704 static void
3642 3705 ixgbe_restart_watchdog_timer(ixgbe_t *ixgbe)
3643 3706 {
3644 3707 mutex_enter(&ixgbe->watchdog_lock);
3645 3708
3646 3709 if (ixgbe->watchdog_start)
3647 3710 ixgbe_arm_watchdog_timer(ixgbe);
3648 3711
3649 3712 mutex_exit(&ixgbe->watchdog_lock);
3650 3713 }
3651 3714
3652 3715 /*
3653 3716 * ixgbe_stop_watchdog_timer - Stop the driver watchdog timer.
3654 3717 */
3655 3718 void
3656 3719 ixgbe_stop_watchdog_timer(ixgbe_t *ixgbe)
3657 3720 {
3658 3721 timeout_id_t tid;
3659 3722
3660 3723 mutex_enter(&ixgbe->watchdog_lock);
3661 3724
3662 3725 ixgbe->watchdog_start = B_FALSE;
3663 3726 tid = ixgbe->watchdog_tid;
3664 3727 ixgbe->watchdog_tid = 0;
3665 3728
3666 3729 mutex_exit(&ixgbe->watchdog_lock);
3667 3730
3668 3731 if (tid != 0)
3669 3732 (void) untimeout(tid);
3670 3733 }
3671 3734
3672 3735 /*
3673 3736 * ixgbe_disable_adapter_interrupts - Disable all adapter interrupts.
3674 3737 */
3675 3738 static void
3676 3739 ixgbe_disable_adapter_interrupts(ixgbe_t *ixgbe)
3677 3740 {
3678 3741 struct ixgbe_hw *hw = &ixgbe->hw;
3679 3742
3680 3743 /*
3681 3744 * mask all interrupts off
3682 3745 */
3683 3746 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xffffffff);
3684 3747
3685 3748 /*
3686 3749 * for MSI-X, also disable autoclear
3687 3750 */
3688 3751 if (ixgbe->intr_type == DDI_INTR_TYPE_MSIX) {
3689 3752 IXGBE_WRITE_REG(hw, IXGBE_EIAC, 0x0);
3690 3753 }
3691 3754
3692 3755 IXGBE_WRITE_FLUSH(hw);
3693 3756 }
3694 3757
3695 3758 /*
3696 3759 * ixgbe_enable_adapter_interrupts - Enable all hardware interrupts.
3697 3760 */
3698 3761 static void
3699 3762 ixgbe_enable_adapter_interrupts(ixgbe_t *ixgbe)
3700 3763 {
3701 3764 struct ixgbe_hw *hw = &ixgbe->hw;
3702 3765 uint32_t eiac, eiam;
3703 3766 uint32_t gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
3704 3767
3705 3768 /* interrupt types to enable */
3706 3769 ixgbe->eims = IXGBE_EIMS_ENABLE_MASK; /* shared code default */
3707 3770 ixgbe->eims &= ~IXGBE_EIMS_TCP_TIMER; /* minus tcp timer */
3708 3771 ixgbe->eims |= ixgbe->capab->other_intr; /* "other" interrupt types */
3709 3772
3710 3773 /* enable automask on "other" causes that this adapter can generate */
3711 3774 eiam = ixgbe->capab->other_intr;
3712 3775
3713 3776 /*
3714 3777 * msi-x mode
3715 3778 */
3716 3779 if (ixgbe->intr_type == DDI_INTR_TYPE_MSIX) {
3717 3780 /* enable autoclear but not on bits 29:20 */
3718 3781 eiac = (ixgbe->eims & ~IXGBE_OTHER_INTR);
3719 3782
3720 3783 /* general purpose interrupt enable */
3721 3784 gpie |= (IXGBE_GPIE_MSIX_MODE
3722 3785 | IXGBE_GPIE_PBA_SUPPORT
3723 3786 | IXGBE_GPIE_OCD
3724 3787 | IXGBE_GPIE_EIAME);
3725 3788 /*
3726 3789 * non-msi-x mode
3727 3790 */
3728 3791 } else {
3729 3792
3730 3793 /* disable autoclear, leave gpie at default */
3731 3794 eiac = 0;
3732 3795
3733 3796 /*
3734 3797 * General purpose interrupt enable.
3735 3798 * For 82599, extended interrupt automask enable
3736 3799 * only in MSI or MSI-X mode
3737 3800 */
3738 3801 if ((hw->mac.type < ixgbe_mac_82599EB) ||
3739 3802 (ixgbe->intr_type == DDI_INTR_TYPE_MSI)) {
3740 3803 gpie |= IXGBE_GPIE_EIAME;
|
↓ open down ↓ |
498 lines elided |
↑ open up ↑ |
3741 3804 }
3742 3805 }
3743 3806
3744 3807 /* Enable specific "other" interrupt types */
3745 3808 switch (hw->mac.type) {
3746 3809 case ixgbe_mac_82598EB:
3747 3810 gpie |= ixgbe->capab->other_gpie;
3748 3811 break;
3749 3812
3750 3813 case ixgbe_mac_82599EB:
3814 + case ixgbe_mac_X540:
3751 3815 gpie |= ixgbe->capab->other_gpie;
3752 3816
3753 3817 /* Enable RSC Delay 8us when LRO enabled */
3754 3818 if (ixgbe->lro_enable) {
3755 3819 gpie |= (1 << IXGBE_GPIE_RSC_DELAY_SHIFT);
3756 3820 }
3757 3821 break;
3758 3822
3759 3823 default:
3760 3824 break;
3761 3825 }
3762 3826
3763 3827 /* write to interrupt control registers */
3764 3828 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
3765 3829 IXGBE_WRITE_REG(hw, IXGBE_EIAC, eiac);
3766 3830 IXGBE_WRITE_REG(hw, IXGBE_EIAM, eiam);
3767 3831 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3768 3832 IXGBE_WRITE_FLUSH(hw);
3769 3833 }
3770 3834
3771 3835 /*
3772 3836 * ixgbe_loopback_ioctl - Loopback support.
3773 3837 */
3774 3838 enum ioc_reply
3775 3839 ixgbe_loopback_ioctl(ixgbe_t *ixgbe, struct iocblk *iocp, mblk_t *mp)
3776 3840 {
3777 3841 lb_info_sz_t *lbsp;
3778 3842 lb_property_t *lbpp;
3779 3843 uint32_t *lbmp;
3780 3844 uint32_t size;
3781 3845 uint32_t value;
3782 3846
3783 3847 if (mp->b_cont == NULL)
3784 3848 return (IOC_INVAL);
3785 3849
3786 3850 switch (iocp->ioc_cmd) {
3787 3851 default:
3788 3852 return (IOC_INVAL);
3789 3853
3790 3854 case LB_GET_INFO_SIZE:
3791 3855 size = sizeof (lb_info_sz_t);
3792 3856 if (iocp->ioc_count != size)
3793 3857 return (IOC_INVAL);
3794 3858
3795 3859 value = sizeof (lb_normal);
3796 3860 value += sizeof (lb_mac);
3797 3861 value += sizeof (lb_external);
3798 3862
3799 3863 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr;
3800 3864 *lbsp = value;
3801 3865 break;
3802 3866
3803 3867 case LB_GET_INFO:
3804 3868 value = sizeof (lb_normal);
3805 3869 value += sizeof (lb_mac);
3806 3870 value += sizeof (lb_external);
3807 3871
3808 3872 size = value;
3809 3873 if (iocp->ioc_count != size)
3810 3874 return (IOC_INVAL);
3811 3875
3812 3876 value = 0;
3813 3877 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr;
3814 3878
3815 3879 lbpp[value++] = lb_normal;
3816 3880 lbpp[value++] = lb_mac;
3817 3881 lbpp[value++] = lb_external;
3818 3882 break;
3819 3883
3820 3884 case LB_GET_MODE:
3821 3885 size = sizeof (uint32_t);
3822 3886 if (iocp->ioc_count != size)
3823 3887 return (IOC_INVAL);
3824 3888
3825 3889 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
3826 3890 *lbmp = ixgbe->loopback_mode;
3827 3891 break;
3828 3892
3829 3893 case LB_SET_MODE:
3830 3894 size = 0;
3831 3895 if (iocp->ioc_count != sizeof (uint32_t))
3832 3896 return (IOC_INVAL);
3833 3897
3834 3898 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr;
3835 3899 if (!ixgbe_set_loopback_mode(ixgbe, *lbmp))
3836 3900 return (IOC_INVAL);
3837 3901 break;
3838 3902 }
3839 3903
3840 3904 iocp->ioc_count = size;
3841 3905 iocp->ioc_error = 0;
3842 3906
3843 3907 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
3844 3908 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
3845 3909 return (IOC_INVAL);
3846 3910 }
3847 3911
3848 3912 return (IOC_REPLY);
3849 3913 }
3850 3914
3851 3915 /*
3852 3916 * ixgbe_set_loopback_mode - Setup loopback based on the loopback mode.
3853 3917 */
3854 3918 static boolean_t
3855 3919 ixgbe_set_loopback_mode(ixgbe_t *ixgbe, uint32_t mode)
3856 3920 {
3857 3921 if (mode == ixgbe->loopback_mode)
3858 3922 return (B_TRUE);
3859 3923
3860 3924 ixgbe->loopback_mode = mode;
3861 3925
3862 3926 if (mode == IXGBE_LB_NONE) {
3863 3927 /*
3864 3928 * Reset the chip
3865 3929 */
3866 3930 (void) ixgbe_reset(ixgbe);
3867 3931 return (B_TRUE);
3868 3932 }
3869 3933
3870 3934 mutex_enter(&ixgbe->gen_lock);
3871 3935
3872 3936 switch (mode) {
3873 3937 default:
3874 3938 mutex_exit(&ixgbe->gen_lock);
3875 3939 return (B_FALSE);
3876 3940
3877 3941 case IXGBE_LB_EXTERNAL:
3878 3942 break;
3879 3943
3880 3944 case IXGBE_LB_INTERNAL_MAC:
3881 3945 ixgbe_set_internal_mac_loopback(ixgbe);
3882 3946 break;
3883 3947 }
3884 3948
3885 3949 mutex_exit(&ixgbe->gen_lock);
3886 3950
3887 3951 return (B_TRUE);
3888 3952 }
3889 3953
3890 3954 /*
3891 3955 * ixgbe_set_internal_mac_loopback - Set the internal MAC loopback mode.
3892 3956 */
3893 3957 static void
3894 3958 ixgbe_set_internal_mac_loopback(ixgbe_t *ixgbe)
3895 3959 {
3896 3960 struct ixgbe_hw *hw;
3897 3961 uint32_t reg;
3898 3962 uint8_t atlas;
3899 3963
3900 3964 hw = &ixgbe->hw;
3901 3965
3902 3966 /*
3903 3967 * Setup MAC loopback
3904 3968 */
3905 3969 reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_HLREG0);
3906 3970 reg |= IXGBE_HLREG0_LPBK;
3907 3971 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_HLREG0, reg);
3908 3972
3909 3973 reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_AUTOC);
3910 3974 reg &= ~IXGBE_AUTOC_LMS_MASK;
3911 3975 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_AUTOC, reg);
3912 3976
3913 3977 /*
3914 3978 * Disable Atlas Tx lanes to keep packets in loopback and not on wire
3915 3979 */
3916 3980 switch (hw->mac.type) {
3917 3981 case ixgbe_mac_82598EB:
3918 3982 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_LPBK,
3919 3983 &atlas);
3920 3984 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
3921 3985 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_LPBK,
3922 3986 atlas);
3923 3987
3924 3988 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_10G,
3925 3989 &atlas);
3926 3990 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
3927 3991 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_10G,
3928 3992 atlas);
3929 3993
3930 3994 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_1G,
3931 3995 &atlas);
3932 3996 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
3933 3997 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_1G,
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3934 3998 atlas);
3935 3999
3936 4000 (void) ixgbe_read_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_AN,
3937 4001 &atlas);
3938 4002 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
3939 4003 (void) ixgbe_write_analog_reg8(&ixgbe->hw, IXGBE_ATLAS_PDN_AN,
3940 4004 atlas);
3941 4005 break;
3942 4006
3943 4007 case ixgbe_mac_82599EB:
4008 + case ixgbe_mac_X540:
3944 4009 reg = IXGBE_READ_REG(&ixgbe->hw, IXGBE_AUTOC);
3945 4010 reg |= (IXGBE_AUTOC_FLU |
3946 4011 IXGBE_AUTOC_10G_KX4);
3947 4012 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_AUTOC, reg);
3948 4013
3949 4014 (void) ixgbe_setup_link(&ixgbe->hw, IXGBE_LINK_SPEED_10GB_FULL,
3950 4015 B_FALSE, B_TRUE);
3951 4016 break;
3952 4017
3953 4018 default:
3954 4019 break;
3955 4020 }
3956 4021 }
3957 4022
3958 4023 #pragma inline(ixgbe_intr_rx_work)
3959 4024 /*
3960 4025 * ixgbe_intr_rx_work - RX processing of ISR.
3961 4026 */
3962 4027 static void
3963 4028 ixgbe_intr_rx_work(ixgbe_rx_ring_t *rx_ring)
3964 4029 {
3965 4030 mblk_t *mp;
3966 4031
3967 4032 mutex_enter(&rx_ring->rx_lock);
3968 4033
3969 4034 mp = ixgbe_ring_rx(rx_ring, IXGBE_POLL_NULL);
3970 4035 mutex_exit(&rx_ring->rx_lock);
3971 4036
3972 4037 if (mp != NULL)
3973 4038 mac_rx_ring(rx_ring->ixgbe->mac_hdl, rx_ring->ring_handle, mp,
3974 4039 rx_ring->ring_gen_num);
3975 4040 }
3976 4041
3977 4042 #pragma inline(ixgbe_intr_tx_work)
3978 4043 /*
3979 4044 * ixgbe_intr_tx_work - TX processing of ISR.
3980 4045 */
3981 4046 static void
3982 4047 ixgbe_intr_tx_work(ixgbe_tx_ring_t *tx_ring)
3983 4048 {
3984 4049 ixgbe_t *ixgbe = tx_ring->ixgbe;
3985 4050
3986 4051 /*
3987 4052 * Recycle the tx descriptors
3988 4053 */
3989 4054 tx_ring->tx_recycle(tx_ring);
3990 4055
3991 4056 /*
3992 4057 * Schedule the re-transmit
3993 4058 */
3994 4059 if (tx_ring->reschedule &&
3995 4060 (tx_ring->tbd_free >= ixgbe->tx_resched_thresh)) {
3996 4061 tx_ring->reschedule = B_FALSE;
3997 4062 mac_tx_ring_update(tx_ring->ixgbe->mac_hdl,
3998 4063 tx_ring->ring_handle);
3999 4064 IXGBE_DEBUG_STAT(tx_ring->stat_reschedule);
4000 4065 }
4001 4066 }
4002 4067
4003 4068 #pragma inline(ixgbe_intr_other_work)
4004 4069 /*
4005 4070 * ixgbe_intr_other_work - Process interrupt types other than tx/rx
4006 4071 */
4007 4072 static void
4008 4073 ixgbe_intr_other_work(ixgbe_t *ixgbe, uint32_t eicr)
4009 4074 {
4010 4075 ASSERT(mutex_owned(&ixgbe->gen_lock));
4011 4076
4012 4077 /*
4013 4078 * handle link status change
4014 4079 */
4015 4080 if (eicr & IXGBE_EICR_LSC) {
4016 4081 ixgbe_driver_link_check(ixgbe);
4017 4082 ixgbe_get_hw_state(ixgbe);
4018 4083 }
4019 4084
4020 4085 /*
4021 4086 * check for fan failure on adapters with fans
4022 4087 */
4023 4088 if ((ixgbe->capab->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
4024 4089 (eicr & IXGBE_EICR_GPI_SDP1)) {
4025 4090 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_OVERTEMP);
4026 4091
4027 4092 /*
4028 4093 * Disable the adapter interrupts
4029 4094 */
4030 4095 ixgbe_disable_adapter_interrupts(ixgbe);
4031 4096
4032 4097 /*
4033 4098 * Disable Rx/Tx units
4034 4099 */
4035 4100 (void) ixgbe_stop_adapter(&ixgbe->hw);
4036 4101
4037 4102 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_LOST);
4038 4103 ixgbe_error(ixgbe,
4039 4104 "Problem: Network adapter has been stopped "
4040 4105 "because the fan has stopped.\n");
4041 4106 ixgbe_error(ixgbe,
4042 4107 "Action: Replace the adapter.\n");
4043 4108
4044 4109 /* re-enable the interrupt, which was automasked */
4045 4110 ixgbe->eims |= IXGBE_EICR_GPI_SDP1;
4046 4111 }
4047 4112
4048 4113 /*
4049 4114 * Do SFP check for adapters with hot-plug capability
4050 4115 */
4051 4116 if ((ixgbe->capab->flags & IXGBE_FLAG_SFP_PLUG_CAPABLE) &&
4052 4117 ((eicr & IXGBE_EICR_GPI_SDP1) || (eicr & IXGBE_EICR_GPI_SDP2))) {
4053 4118 ixgbe->eicr = eicr;
4054 4119 if ((ddi_taskq_dispatch(ixgbe->sfp_taskq,
4055 4120 ixgbe_sfp_check, (void *)ixgbe,
4056 4121 DDI_NOSLEEP)) != DDI_SUCCESS) {
4057 4122 ixgbe_log(ixgbe, "No memory available to dispatch "
4058 4123 "taskq for SFP check");
4059 4124 }
4060 4125 }
4061 4126
4062 4127 /*
4063 4128 * Do over-temperature check for adapters with temp sensor
4064 4129 */
4065 4130 if ((ixgbe->capab->flags & IXGBE_FLAG_TEMP_SENSOR_CAPABLE) &&
4066 4131 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
4067 4132 ixgbe->eicr = eicr;
4068 4133 if ((ddi_taskq_dispatch(ixgbe->overtemp_taskq,
4069 4134 ixgbe_overtemp_check, (void *)ixgbe,
4070 4135 DDI_NOSLEEP)) != DDI_SUCCESS) {
4071 4136 ixgbe_log(ixgbe, "No memory available to dispatch "
4072 4137 "taskq for overtemp check");
4073 4138 }
4074 4139 }
4075 4140 }
4076 4141
4077 4142 /*
4078 4143 * ixgbe_intr_legacy - Interrupt handler for legacy interrupts.
4079 4144 */
4080 4145 static uint_t
4081 4146 ixgbe_intr_legacy(void *arg1, void *arg2)
4082 4147 {
4083 4148 ixgbe_t *ixgbe = (ixgbe_t *)arg1;
4084 4149 struct ixgbe_hw *hw = &ixgbe->hw;
4085 4150 ixgbe_tx_ring_t *tx_ring;
4086 4151 ixgbe_rx_ring_t *rx_ring;
4087 4152 uint32_t eicr;
4088 4153 mblk_t *mp;
4089 4154 boolean_t tx_reschedule;
4090 4155 uint_t result;
4091 4156
4092 4157 _NOTE(ARGUNUSED(arg2));
4093 4158
4094 4159 mutex_enter(&ixgbe->gen_lock);
4095 4160 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
4096 4161 mutex_exit(&ixgbe->gen_lock);
4097 4162 return (DDI_INTR_UNCLAIMED);
4098 4163 }
4099 4164
4100 4165 mp = NULL;
4101 4166 tx_reschedule = B_FALSE;
4102 4167
4103 4168 /*
4104 4169 * Any bit set in eicr: claim this interrupt
4105 4170 */
4106 4171 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4107 4172
4108 4173 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
4109 4174 mutex_exit(&ixgbe->gen_lock);
4110 4175 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
4111 4176 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_ERROR);
4112 4177 return (DDI_INTR_CLAIMED);
4113 4178 }
4114 4179
4115 4180 if (eicr) {
4116 4181 /*
4117 4182 * For legacy interrupt, we have only one interrupt,
4118 4183 * so we have only one rx ring and one tx ring enabled.
4119 4184 */
4120 4185 ASSERT(ixgbe->num_rx_rings == 1);
4121 4186 ASSERT(ixgbe->num_tx_rings == 1);
4122 4187
4123 4188 /*
4124 4189 * For legacy interrupt, rx rings[0] will use RTxQ[0].
4125 4190 */
4126 4191 if (eicr & 0x1) {
4127 4192 ixgbe->eimc |= IXGBE_EICR_RTX_QUEUE;
4128 4193 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ixgbe->eimc);
4129 4194 ixgbe->eims |= IXGBE_EICR_RTX_QUEUE;
4130 4195 /*
4131 4196 * Clean the rx descriptors
4132 4197 */
4133 4198 rx_ring = &ixgbe->rx_rings[0];
4134 4199 mp = ixgbe_ring_rx(rx_ring, IXGBE_POLL_NULL);
4135 4200 }
4136 4201
4137 4202 /*
4138 4203 * For legacy interrupt, tx rings[0] will use RTxQ[1].
4139 4204 */
4140 4205 if (eicr & 0x2) {
4141 4206 /*
4142 4207 * Recycle the tx descriptors
4143 4208 */
4144 4209 tx_ring = &ixgbe->tx_rings[0];
4145 4210 tx_ring->tx_recycle(tx_ring);
4146 4211
4147 4212 /*
4148 4213 * Schedule the re-transmit
4149 4214 */
4150 4215 tx_reschedule = (tx_ring->reschedule &&
4151 4216 (tx_ring->tbd_free >= ixgbe->tx_resched_thresh));
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4152 4217 }
4153 4218
4154 4219 /* any interrupt type other than tx/rx */
4155 4220 if (eicr & ixgbe->capab->other_intr) {
4156 4221 switch (hw->mac.type) {
4157 4222 case ixgbe_mac_82598EB:
4158 4223 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4159 4224 break;
4160 4225
4161 4226 case ixgbe_mac_82599EB:
4227 + case ixgbe_mac_X540:
4162 4228 ixgbe->eimc = IXGBE_82599_OTHER_INTR;
4163 4229 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ixgbe->eimc);
4164 4230 break;
4165 4231
4166 4232 default:
4167 4233 break;
4168 4234 }
4169 4235 ixgbe_intr_other_work(ixgbe, eicr);
4170 4236 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4171 4237 }
4172 4238
4173 4239 mutex_exit(&ixgbe->gen_lock);
4174 4240
4175 4241 result = DDI_INTR_CLAIMED;
4176 4242 } else {
4177 4243 mutex_exit(&ixgbe->gen_lock);
4178 4244
4179 4245 /*
4180 4246 * No interrupt cause bits set: don't claim this interrupt.
4181 4247 */
4182 4248 result = DDI_INTR_UNCLAIMED;
4183 4249 }
4184 4250
4185 4251 /* re-enable the interrupts which were automasked */
4186 4252 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
4187 4253
4188 4254 /*
4189 4255 * Do the following work outside of the gen_lock
4190 4256 */
4191 4257 if (mp != NULL) {
4192 4258 mac_rx_ring(rx_ring->ixgbe->mac_hdl, rx_ring->ring_handle, mp,
4193 4259 rx_ring->ring_gen_num);
4194 4260 }
4195 4261
4196 4262 if (tx_reschedule) {
4197 4263 tx_ring->reschedule = B_FALSE;
4198 4264 mac_tx_ring_update(ixgbe->mac_hdl, tx_ring->ring_handle);
4199 4265 IXGBE_DEBUG_STAT(tx_ring->stat_reschedule);
4200 4266 }
4201 4267
4202 4268 return (result);
4203 4269 }
4204 4270
4205 4271 /*
4206 4272 * ixgbe_intr_msi - Interrupt handler for MSI.
4207 4273 */
4208 4274 static uint_t
4209 4275 ixgbe_intr_msi(void *arg1, void *arg2)
4210 4276 {
4211 4277 ixgbe_t *ixgbe = (ixgbe_t *)arg1;
4212 4278 struct ixgbe_hw *hw = &ixgbe->hw;
4213 4279 uint32_t eicr;
4214 4280
4215 4281 _NOTE(ARGUNUSED(arg2));
4216 4282
4217 4283 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4218 4284
4219 4285 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) != DDI_FM_OK) {
4220 4286 ddi_fm_service_impact(ixgbe->dip, DDI_SERVICE_DEGRADED);
4221 4287 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_ERROR);
4222 4288 return (DDI_INTR_CLAIMED);
4223 4289 }
4224 4290
4225 4291 /*
4226 4292 * For MSI interrupt, we have only one vector,
4227 4293 * so we have only one rx ring and one tx ring enabled.
4228 4294 */
4229 4295 ASSERT(ixgbe->num_rx_rings == 1);
4230 4296 ASSERT(ixgbe->num_tx_rings == 1);
4231 4297
4232 4298 /*
4233 4299 * For MSI interrupt, rx rings[0] will use RTxQ[0].
4234 4300 */
4235 4301 if (eicr & 0x1) {
4236 4302 ixgbe_intr_rx_work(&ixgbe->rx_rings[0]);
4237 4303 }
4238 4304
4239 4305 /*
4240 4306 * For MSI interrupt, tx rings[0] will use RTxQ[1].
4241 4307 */
4242 4308 if (eicr & 0x2) {
4243 4309 ixgbe_intr_tx_work(&ixgbe->tx_rings[0]);
4244 4310 }
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4245 4311
4246 4312 /* any interrupt type other than tx/rx */
4247 4313 if (eicr & ixgbe->capab->other_intr) {
4248 4314 mutex_enter(&ixgbe->gen_lock);
4249 4315 switch (hw->mac.type) {
4250 4316 case ixgbe_mac_82598EB:
4251 4317 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4252 4318 break;
4253 4319
4254 4320 case ixgbe_mac_82599EB:
4321 + case ixgbe_mac_X540:
4255 4322 ixgbe->eimc = IXGBE_82599_OTHER_INTR;
4256 4323 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ixgbe->eimc);
4257 4324 break;
4258 4325
4259 4326 default:
4260 4327 break;
4261 4328 }
4262 4329 ixgbe_intr_other_work(ixgbe, eicr);
4263 4330 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4264 4331 mutex_exit(&ixgbe->gen_lock);
4265 4332 }
4266 4333
4267 4334 /* re-enable the interrupts which were automasked */
4268 4335 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
4269 4336
4270 4337 return (DDI_INTR_CLAIMED);
4271 4338 }
4272 4339
4273 4340 /*
4274 4341 * ixgbe_intr_msix - Interrupt handler for MSI-X.
4275 4342 */
4276 4343 static uint_t
4277 4344 ixgbe_intr_msix(void *arg1, void *arg2)
4278 4345 {
4279 4346 ixgbe_intr_vector_t *vect = (ixgbe_intr_vector_t *)arg1;
4280 4347 ixgbe_t *ixgbe = vect->ixgbe;
4281 4348 struct ixgbe_hw *hw = &ixgbe->hw;
4282 4349 uint32_t eicr;
4283 4350 int r_idx = 0;
4284 4351
4285 4352 _NOTE(ARGUNUSED(arg2));
4286 4353
4287 4354 /*
4288 4355 * Clean each rx ring that has its bit set in the map
4289 4356 */
4290 4357 r_idx = bt_getlowbit(vect->rx_map, 0, (ixgbe->num_rx_rings - 1));
4291 4358 while (r_idx >= 0) {
4292 4359 ixgbe_intr_rx_work(&ixgbe->rx_rings[r_idx]);
4293 4360 r_idx = bt_getlowbit(vect->rx_map, (r_idx + 1),
4294 4361 (ixgbe->num_rx_rings - 1));
4295 4362 }
4296 4363
4297 4364 /*
4298 4365 * Clean each tx ring that has its bit set in the map
4299 4366 */
4300 4367 r_idx = bt_getlowbit(vect->tx_map, 0, (ixgbe->num_tx_rings - 1));
4301 4368 while (r_idx >= 0) {
4302 4369 ixgbe_intr_tx_work(&ixgbe->tx_rings[r_idx]);
4303 4370 r_idx = bt_getlowbit(vect->tx_map, (r_idx + 1),
4304 4371 (ixgbe->num_tx_rings - 1));
4305 4372 }
4306 4373
4307 4374
4308 4375 /*
4309 4376 * Clean other interrupt (link change) that has its bit set in the map
4310 4377 */
4311 4378 if (BT_TEST(vect->other_map, 0) == 1) {
4312 4379 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4313 4380
4314 4381 if (ixgbe_check_acc_handle(ixgbe->osdep.reg_handle) !=
4315 4382 DDI_FM_OK) {
4316 4383 ddi_fm_service_impact(ixgbe->dip,
4317 4384 DDI_SERVICE_DEGRADED);
4318 4385 atomic_or_32(&ixgbe->ixgbe_state, IXGBE_ERROR);
4319 4386 return (DDI_INTR_CLAIMED);
4320 4387 }
4321 4388
4322 4389 /*
4323 4390 * Check "other" cause bits: any interrupt type other than tx/rx
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↑ open up ↑ |
4324 4391 */
4325 4392 if (eicr & ixgbe->capab->other_intr) {
4326 4393 mutex_enter(&ixgbe->gen_lock);
4327 4394 switch (hw->mac.type) {
4328 4395 case ixgbe_mac_82598EB:
4329 4396 ixgbe->eims &= ~(eicr & IXGBE_OTHER_INTR);
4330 4397 ixgbe_intr_other_work(ixgbe, eicr);
4331 4398 break;
4332 4399
4333 4400 case ixgbe_mac_82599EB:
4401 + case ixgbe_mac_X540:
4334 4402 ixgbe->eims |= IXGBE_EICR_RTX_QUEUE;
4335 4403 ixgbe_intr_other_work(ixgbe, eicr);
4336 4404 break;
4337 4405
4338 4406 default:
4339 4407 break;
4340 4408 }
4341 4409 mutex_exit(&ixgbe->gen_lock);
4342 4410 }
4343 4411
4344 4412 /* re-enable the interrupts which were automasked */
4345 4413 IXGBE_WRITE_REG(hw, IXGBE_EIMS, ixgbe->eims);
4346 4414 }
4347 4415
4348 4416 return (DDI_INTR_CLAIMED);
4349 4417 }
4350 4418
4351 4419 /*
4352 4420 * ixgbe_alloc_intrs - Allocate interrupts for the driver.
4353 4421 *
4354 4422 * Normal sequence is to try MSI-X; if not sucessful, try MSI;
4355 4423 * if not successful, try Legacy.
4356 4424 * ixgbe->intr_force can be used to force sequence to start with
4357 4425 * any of the 3 types.
4358 4426 * If MSI-X is not used, number of tx/rx rings is forced to 1.
4359 4427 */
4360 4428 static int
4361 4429 ixgbe_alloc_intrs(ixgbe_t *ixgbe)
4362 4430 {
4363 4431 dev_info_t *devinfo;
4364 4432 int intr_types;
4365 4433 int rc;
4366 4434
4367 4435 devinfo = ixgbe->dip;
4368 4436
4369 4437 /*
4370 4438 * Get supported interrupt types
4371 4439 */
4372 4440 rc = ddi_intr_get_supported_types(devinfo, &intr_types);
4373 4441
4374 4442 if (rc != DDI_SUCCESS) {
4375 4443 ixgbe_log(ixgbe,
4376 4444 "Get supported interrupt types failed: %d", rc);
4377 4445 return (IXGBE_FAILURE);
4378 4446 }
4379 4447 IXGBE_DEBUGLOG_1(ixgbe, "Supported interrupt types: %x", intr_types);
4380 4448
4381 4449 ixgbe->intr_type = 0;
4382 4450
4383 4451 /*
4384 4452 * Install MSI-X interrupts
4385 4453 */
4386 4454 if ((intr_types & DDI_INTR_TYPE_MSIX) &&
4387 4455 (ixgbe->intr_force <= IXGBE_INTR_MSIX)) {
4388 4456 rc = ixgbe_alloc_intr_handles(ixgbe, DDI_INTR_TYPE_MSIX);
4389 4457 if (rc == IXGBE_SUCCESS)
4390 4458 return (IXGBE_SUCCESS);
4391 4459
4392 4460 ixgbe_log(ixgbe,
4393 4461 "Allocate MSI-X failed, trying MSI interrupts...");
4394 4462 }
4395 4463
4396 4464 /*
4397 4465 * MSI-X not used, force rings and groups to 1
4398 4466 */
4399 4467 ixgbe->num_rx_rings = 1;
4400 4468 ixgbe->num_rx_groups = 1;
4401 4469 ixgbe->num_tx_rings = 1;
4402 4470 ixgbe->classify_mode = IXGBE_CLASSIFY_NONE;
4403 4471 ixgbe_log(ixgbe,
4404 4472 "MSI-X not used, force rings and groups number to 1");
4405 4473
4406 4474 /*
4407 4475 * Install MSI interrupts
4408 4476 */
4409 4477 if ((intr_types & DDI_INTR_TYPE_MSI) &&
4410 4478 (ixgbe->intr_force <= IXGBE_INTR_MSI)) {
4411 4479 rc = ixgbe_alloc_intr_handles(ixgbe, DDI_INTR_TYPE_MSI);
4412 4480 if (rc == IXGBE_SUCCESS)
4413 4481 return (IXGBE_SUCCESS);
4414 4482
4415 4483 ixgbe_log(ixgbe,
4416 4484 "Allocate MSI failed, trying Legacy interrupts...");
4417 4485 }
4418 4486
4419 4487 /*
4420 4488 * Install legacy interrupts
4421 4489 */
4422 4490 if (intr_types & DDI_INTR_TYPE_FIXED) {
4423 4491 rc = ixgbe_alloc_intr_handles(ixgbe, DDI_INTR_TYPE_FIXED);
4424 4492 if (rc == IXGBE_SUCCESS)
4425 4493 return (IXGBE_SUCCESS);
4426 4494
4427 4495 ixgbe_log(ixgbe,
4428 4496 "Allocate Legacy interrupts failed");
4429 4497 }
4430 4498
4431 4499 /*
4432 4500 * If none of the 3 types succeeded, return failure
4433 4501 */
4434 4502 return (IXGBE_FAILURE);
4435 4503 }
4436 4504
4437 4505 /*
4438 4506 * ixgbe_alloc_intr_handles - Allocate interrupt handles.
4439 4507 *
4440 4508 * For legacy and MSI, only 1 handle is needed. For MSI-X,
4441 4509 * if fewer than 2 handles are available, return failure.
4442 4510 * Upon success, this maps the vectors to rx and tx rings for
4443 4511 * interrupts.
4444 4512 */
4445 4513 static int
4446 4514 ixgbe_alloc_intr_handles(ixgbe_t *ixgbe, int intr_type)
4447 4515 {
4448 4516 dev_info_t *devinfo;
4449 4517 int request, count, actual;
4450 4518 int minimum;
4451 4519 int rc;
4452 4520 uint32_t ring_per_group;
4453 4521
4454 4522 devinfo = ixgbe->dip;
4455 4523
4456 4524 switch (intr_type) {
4457 4525 case DDI_INTR_TYPE_FIXED:
4458 4526 request = 1; /* Request 1 legacy interrupt handle */
4459 4527 minimum = 1;
4460 4528 IXGBE_DEBUGLOG_0(ixgbe, "interrupt type: legacy");
4461 4529 break;
4462 4530
4463 4531 case DDI_INTR_TYPE_MSI:
4464 4532 request = 1; /* Request 1 MSI interrupt handle */
4465 4533 minimum = 1;
4466 4534 IXGBE_DEBUGLOG_0(ixgbe, "interrupt type: MSI");
4467 4535 break;
4468 4536
4469 4537 case DDI_INTR_TYPE_MSIX:
4470 4538 /*
4471 4539 * Best number of vectors for the adapter is
4472 4540 * (# rx rings + # tx rings), however we will
4473 4541 * limit the request number.
4474 4542 */
4475 4543 request = min(16, ixgbe->num_rx_rings + ixgbe->num_tx_rings);
4476 4544 if (request > ixgbe->capab->max_ring_vect)
4477 4545 request = ixgbe->capab->max_ring_vect;
4478 4546 minimum = 1;
4479 4547 IXGBE_DEBUGLOG_0(ixgbe, "interrupt type: MSI-X");
4480 4548 break;
4481 4549
4482 4550 default:
4483 4551 ixgbe_log(ixgbe,
4484 4552 "invalid call to ixgbe_alloc_intr_handles(): %d\n",
4485 4553 intr_type);
4486 4554 return (IXGBE_FAILURE);
4487 4555 }
4488 4556 IXGBE_DEBUGLOG_2(ixgbe, "interrupt handles requested: %d minimum: %d",
4489 4557 request, minimum);
4490 4558
4491 4559 /*
4492 4560 * Get number of supported interrupts
4493 4561 */
4494 4562 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count);
4495 4563 if ((rc != DDI_SUCCESS) || (count < minimum)) {
4496 4564 ixgbe_log(ixgbe,
4497 4565 "Get interrupt number failed. Return: %d, count: %d",
4498 4566 rc, count);
4499 4567 return (IXGBE_FAILURE);
4500 4568 }
4501 4569 IXGBE_DEBUGLOG_1(ixgbe, "interrupts supported: %d", count);
4502 4570
4503 4571 actual = 0;
4504 4572 ixgbe->intr_cnt = 0;
4505 4573 ixgbe->intr_cnt_max = 0;
4506 4574 ixgbe->intr_cnt_min = 0;
4507 4575
4508 4576 /*
4509 4577 * Allocate an array of interrupt handles
4510 4578 */
4511 4579 ixgbe->intr_size = request * sizeof (ddi_intr_handle_t);
4512 4580 ixgbe->htable = kmem_alloc(ixgbe->intr_size, KM_SLEEP);
4513 4581
4514 4582 rc = ddi_intr_alloc(devinfo, ixgbe->htable, intr_type, 0,
4515 4583 request, &actual, DDI_INTR_ALLOC_NORMAL);
4516 4584 if (rc != DDI_SUCCESS) {
4517 4585 ixgbe_log(ixgbe, "Allocate interrupts failed. "
4518 4586 "return: %d, request: %d, actual: %d",
4519 4587 rc, request, actual);
4520 4588 goto alloc_handle_fail;
4521 4589 }
4522 4590 IXGBE_DEBUGLOG_1(ixgbe, "interrupts actually allocated: %d", actual);
4523 4591
4524 4592 /*
4525 4593 * upper/lower limit of interrupts
4526 4594 */
4527 4595 ixgbe->intr_cnt = actual;
4528 4596 ixgbe->intr_cnt_max = request;
4529 4597 ixgbe->intr_cnt_min = minimum;
4530 4598
4531 4599 /*
4532 4600 * rss number per group should not exceed the rx interrupt number,
4533 4601 * else need to adjust rx ring number.
4534 4602 */
4535 4603 ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
4536 4604 ASSERT((ixgbe->num_rx_rings % ixgbe->num_rx_groups) == 0);
4537 4605 if (actual < ring_per_group) {
4538 4606 ixgbe->num_rx_rings = ixgbe->num_rx_groups * actual;
4539 4607 ixgbe_setup_vmdq_rss_conf(ixgbe);
4540 4608 }
4541 4609
4542 4610 /*
4543 4611 * Now we know the actual number of vectors. Here we map the vector
4544 4612 * to other, rx rings and tx ring.
4545 4613 */
4546 4614 if (actual < minimum) {
4547 4615 ixgbe_log(ixgbe, "Insufficient interrupt handles available: %d",
4548 4616 actual);
4549 4617 goto alloc_handle_fail;
4550 4618 }
4551 4619
4552 4620 /*
4553 4621 * Get priority for first vector, assume remaining are all the same
4554 4622 */
4555 4623 rc = ddi_intr_get_pri(ixgbe->htable[0], &ixgbe->intr_pri);
4556 4624 if (rc != DDI_SUCCESS) {
4557 4625 ixgbe_log(ixgbe,
4558 4626 "Get interrupt priority failed: %d", rc);
4559 4627 goto alloc_handle_fail;
4560 4628 }
4561 4629
4562 4630 rc = ddi_intr_get_cap(ixgbe->htable[0], &ixgbe->intr_cap);
4563 4631 if (rc != DDI_SUCCESS) {
4564 4632 ixgbe_log(ixgbe,
4565 4633 "Get interrupt cap failed: %d", rc);
4566 4634 goto alloc_handle_fail;
4567 4635 }
4568 4636
4569 4637 ixgbe->intr_type = intr_type;
4570 4638
4571 4639 return (IXGBE_SUCCESS);
4572 4640
4573 4641 alloc_handle_fail:
4574 4642 ixgbe_rem_intrs(ixgbe);
4575 4643
4576 4644 return (IXGBE_FAILURE);
4577 4645 }
4578 4646
4579 4647 /*
4580 4648 * ixgbe_add_intr_handlers - Add interrupt handlers based on the interrupt type.
4581 4649 *
4582 4650 * Before adding the interrupt handlers, the interrupt vectors have
4583 4651 * been allocated, and the rx/tx rings have also been allocated.
4584 4652 */
4585 4653 static int
4586 4654 ixgbe_add_intr_handlers(ixgbe_t *ixgbe)
4587 4655 {
4588 4656 int vector = 0;
4589 4657 int rc;
4590 4658
4591 4659 switch (ixgbe->intr_type) {
4592 4660 case DDI_INTR_TYPE_MSIX:
4593 4661 /*
4594 4662 * Add interrupt handler for all vectors
4595 4663 */
4596 4664 for (vector = 0; vector < ixgbe->intr_cnt; vector++) {
4597 4665 /*
4598 4666 * install pointer to vect_map[vector]
4599 4667 */
4600 4668 rc = ddi_intr_add_handler(ixgbe->htable[vector],
4601 4669 (ddi_intr_handler_t *)ixgbe_intr_msix,
4602 4670 (void *)&ixgbe->vect_map[vector], NULL);
4603 4671
4604 4672 if (rc != DDI_SUCCESS) {
4605 4673 ixgbe_log(ixgbe,
4606 4674 "Add interrupt handler failed. "
4607 4675 "return: %d, vector: %d", rc, vector);
4608 4676 for (vector--; vector >= 0; vector--) {
4609 4677 (void) ddi_intr_remove_handler(
4610 4678 ixgbe->htable[vector]);
4611 4679 }
4612 4680 return (IXGBE_FAILURE);
4613 4681 }
4614 4682 }
4615 4683
4616 4684 break;
4617 4685
4618 4686 case DDI_INTR_TYPE_MSI:
4619 4687 /*
4620 4688 * Add interrupt handlers for the only vector
4621 4689 */
4622 4690 rc = ddi_intr_add_handler(ixgbe->htable[vector],
4623 4691 (ddi_intr_handler_t *)ixgbe_intr_msi,
4624 4692 (void *)ixgbe, NULL);
4625 4693
4626 4694 if (rc != DDI_SUCCESS) {
4627 4695 ixgbe_log(ixgbe,
4628 4696 "Add MSI interrupt handler failed: %d", rc);
4629 4697 return (IXGBE_FAILURE);
4630 4698 }
4631 4699
4632 4700 break;
4633 4701
4634 4702 case DDI_INTR_TYPE_FIXED:
4635 4703 /*
4636 4704 * Add interrupt handlers for the only vector
4637 4705 */
4638 4706 rc = ddi_intr_add_handler(ixgbe->htable[vector],
4639 4707 (ddi_intr_handler_t *)ixgbe_intr_legacy,
4640 4708 (void *)ixgbe, NULL);
4641 4709
4642 4710 if (rc != DDI_SUCCESS) {
4643 4711 ixgbe_log(ixgbe,
4644 4712 "Add legacy interrupt handler failed: %d", rc);
4645 4713 return (IXGBE_FAILURE);
4646 4714 }
4647 4715
4648 4716 break;
4649 4717
4650 4718 default:
4651 4719 return (IXGBE_FAILURE);
4652 4720 }
4653 4721
4654 4722 return (IXGBE_SUCCESS);
4655 4723 }
4656 4724
4657 4725 #pragma inline(ixgbe_map_rxring_to_vector)
4658 4726 /*
4659 4727 * ixgbe_map_rxring_to_vector - Map given rx ring to given interrupt vector.
4660 4728 */
4661 4729 static void
4662 4730 ixgbe_map_rxring_to_vector(ixgbe_t *ixgbe, int r_idx, int v_idx)
4663 4731 {
4664 4732 /*
4665 4733 * Set bit in map
4666 4734 */
4667 4735 BT_SET(ixgbe->vect_map[v_idx].rx_map, r_idx);
4668 4736
4669 4737 /*
4670 4738 * Count bits set
4671 4739 */
4672 4740 ixgbe->vect_map[v_idx].rxr_cnt++;
4673 4741
4674 4742 /*
4675 4743 * Remember bit position
4676 4744 */
4677 4745 ixgbe->rx_rings[r_idx].intr_vector = v_idx;
4678 4746 ixgbe->rx_rings[r_idx].vect_bit = 1 << v_idx;
4679 4747 }
4680 4748
4681 4749 #pragma inline(ixgbe_map_txring_to_vector)
4682 4750 /*
4683 4751 * ixgbe_map_txring_to_vector - Map given tx ring to given interrupt vector.
4684 4752 */
4685 4753 static void
4686 4754 ixgbe_map_txring_to_vector(ixgbe_t *ixgbe, int t_idx, int v_idx)
4687 4755 {
4688 4756 /*
4689 4757 * Set bit in map
4690 4758 */
4691 4759 BT_SET(ixgbe->vect_map[v_idx].tx_map, t_idx);
4692 4760
4693 4761 /*
4694 4762 * Count bits set
4695 4763 */
4696 4764 ixgbe->vect_map[v_idx].txr_cnt++;
4697 4765
4698 4766 /*
4699 4767 * Remember bit position
4700 4768 */
4701 4769 ixgbe->tx_rings[t_idx].intr_vector = v_idx;
4702 4770 ixgbe->tx_rings[t_idx].vect_bit = 1 << v_idx;
4703 4771 }
4704 4772
4705 4773 /*
4706 4774 * ixgbe_setup_ivar - Set the given entry in the given interrupt vector
4707 4775 * allocation register (IVAR).
4708 4776 * cause:
4709 4777 * -1 : other cause
4710 4778 * 0 : rx
4711 4779 * 1 : tx
4712 4780 */
4713 4781 static void
4714 4782 ixgbe_setup_ivar(ixgbe_t *ixgbe, uint16_t intr_alloc_entry, uint8_t msix_vector,
4715 4783 int8_t cause)
4716 4784 {
4717 4785 struct ixgbe_hw *hw = &ixgbe->hw;
4718 4786 u32 ivar, index;
4719 4787
4720 4788 switch (hw->mac.type) {
4721 4789 case ixgbe_mac_82598EB:
4722 4790 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4723 4791 if (cause == -1) {
|
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380 lines elided |
↑ open up ↑ |
4724 4792 cause = 0;
4725 4793 }
4726 4794 index = (((cause * 64) + intr_alloc_entry) >> 2) & 0x1F;
4727 4795 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4728 4796 ivar &= ~(0xFF << (8 * (intr_alloc_entry & 0x3)));
4729 4797 ivar |= (msix_vector << (8 * (intr_alloc_entry & 0x3)));
4730 4798 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
4731 4799 break;
4732 4800
4733 4801 case ixgbe_mac_82599EB:
4802 + case ixgbe_mac_X540:
4734 4803 if (cause == -1) {
4735 4804 /* other causes */
4736 4805 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4737 4806 index = (intr_alloc_entry & 1) * 8;
4738 4807 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4739 4808 ivar &= ~(0xFF << index);
4740 4809 ivar |= (msix_vector << index);
4741 4810 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4742 4811 } else {
4743 4812 /* tx or rx causes */
4744 4813 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4745 4814 index = ((16 * (intr_alloc_entry & 1)) + (8 * cause));
4746 4815 ivar = IXGBE_READ_REG(hw,
4747 4816 IXGBE_IVAR(intr_alloc_entry >> 1));
4748 4817 ivar &= ~(0xFF << index);
4749 4818 ivar |= (msix_vector << index);
4750 4819 IXGBE_WRITE_REG(hw, IXGBE_IVAR(intr_alloc_entry >> 1),
4751 4820 ivar);
4752 4821 }
4753 4822 break;
4754 4823
4755 4824 default:
4756 4825 break;
4757 4826 }
4758 4827 }
4759 4828
4760 4829 /*
4761 4830 * ixgbe_enable_ivar - Enable the given entry by setting the VAL bit of
4762 4831 * given interrupt vector allocation register (IVAR).
4763 4832 * cause:
4764 4833 * -1 : other cause
4765 4834 * 0 : rx
4766 4835 * 1 : tx
4767 4836 */
4768 4837 static void
4769 4838 ixgbe_enable_ivar(ixgbe_t *ixgbe, uint16_t intr_alloc_entry, int8_t cause)
4770 4839 {
4771 4840 struct ixgbe_hw *hw = &ixgbe->hw;
4772 4841 u32 ivar, index;
4773 4842
4774 4843 switch (hw->mac.type) {
4775 4844 case ixgbe_mac_82598EB:
4776 4845 if (cause == -1) {
|
↓ open down ↓ |
33 lines elided |
↑ open up ↑ |
4777 4846 cause = 0;
4778 4847 }
4779 4848 index = (((cause * 64) + intr_alloc_entry) >> 2) & 0x1F;
4780 4849 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4781 4850 ivar |= (IXGBE_IVAR_ALLOC_VAL << (8 *
4782 4851 (intr_alloc_entry & 0x3)));
4783 4852 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
4784 4853 break;
4785 4854
4786 4855 case ixgbe_mac_82599EB:
4856 + case ixgbe_mac_X540:
4787 4857 if (cause == -1) {
4788 4858 /* other causes */
4789 4859 index = (intr_alloc_entry & 1) * 8;
4790 4860 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4791 4861 ivar |= (IXGBE_IVAR_ALLOC_VAL << index);
4792 4862 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4793 4863 } else {
4794 4864 /* tx or rx causes */
4795 4865 index = ((16 * (intr_alloc_entry & 1)) + (8 * cause));
4796 4866 ivar = IXGBE_READ_REG(hw,
4797 4867 IXGBE_IVAR(intr_alloc_entry >> 1));
4798 4868 ivar |= (IXGBE_IVAR_ALLOC_VAL << index);
4799 4869 IXGBE_WRITE_REG(hw, IXGBE_IVAR(intr_alloc_entry >> 1),
4800 4870 ivar);
4801 4871 }
4802 4872 break;
4803 4873
4804 4874 default:
4805 4875 break;
4806 4876 }
4807 4877 }
4808 4878
4809 4879 /*
4810 4880 * ixgbe_disable_ivar - Disble the given entry by clearing the VAL bit of
4811 4881 * given interrupt vector allocation register (IVAR).
4812 4882 * cause:
4813 4883 * -1 : other cause
4814 4884 * 0 : rx
4815 4885 * 1 : tx
4816 4886 */
4817 4887 static void
4818 4888 ixgbe_disable_ivar(ixgbe_t *ixgbe, uint16_t intr_alloc_entry, int8_t cause)
4819 4889 {
4820 4890 struct ixgbe_hw *hw = &ixgbe->hw;
4821 4891 u32 ivar, index;
4822 4892
4823 4893 switch (hw->mac.type) {
4824 4894 case ixgbe_mac_82598EB:
4825 4895 if (cause == -1) {
|
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29 lines elided |
↑ open up ↑ |
4826 4896 cause = 0;
4827 4897 }
4828 4898 index = (((cause * 64) + intr_alloc_entry) >> 2) & 0x1F;
4829 4899 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
4830 4900 ivar &= ~(IXGBE_IVAR_ALLOC_VAL<< (8 *
4831 4901 (intr_alloc_entry & 0x3)));
4832 4902 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
4833 4903 break;
4834 4904
4835 4905 case ixgbe_mac_82599EB:
4906 + case ixgbe_mac_X540:
4836 4907 if (cause == -1) {
4837 4908 /* other causes */
4838 4909 index = (intr_alloc_entry & 1) * 8;
4839 4910 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4840 4911 ivar &= ~(IXGBE_IVAR_ALLOC_VAL << index);
4841 4912 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
4842 4913 } else {
4843 4914 /* tx or rx causes */
4844 4915 index = ((16 * (intr_alloc_entry & 1)) + (8 * cause));
4845 4916 ivar = IXGBE_READ_REG(hw,
4846 4917 IXGBE_IVAR(intr_alloc_entry >> 1));
4847 4918 ivar &= ~(IXGBE_IVAR_ALLOC_VAL << index);
4848 4919 IXGBE_WRITE_REG(hw, IXGBE_IVAR(intr_alloc_entry >> 1),
4849 4920 ivar);
4850 4921 }
4851 4922 break;
4852 4923
4853 4924 default:
4854 4925 break;
4855 4926 }
4856 4927 }
4857 4928
4858 4929 /*
4859 4930 * Convert the rx ring index driver maintained to the rx ring index
4860 4931 * in h/w.
4861 4932 */
4862 4933 static uint32_t
4863 4934 ixgbe_get_hw_rx_index(ixgbe_t *ixgbe, uint32_t sw_rx_index)
4864 4935 {
4865 4936
4866 4937 struct ixgbe_hw *hw = &ixgbe->hw;
4867 4938 uint32_t rx_ring_per_group, hw_rx_index;
|
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22 lines elided |
↑ open up ↑ |
4868 4939
4869 4940 if (ixgbe->classify_mode == IXGBE_CLASSIFY_RSS ||
4870 4941 ixgbe->classify_mode == IXGBE_CLASSIFY_NONE) {
4871 4942 return (sw_rx_index);
4872 4943 } else if (ixgbe->classify_mode == IXGBE_CLASSIFY_VMDQ) {
4873 4944 switch (hw->mac.type) {
4874 4945 case ixgbe_mac_82598EB:
4875 4946 return (sw_rx_index);
4876 4947
4877 4948 case ixgbe_mac_82599EB:
4949 + case ixgbe_mac_X540:
4878 4950 return (sw_rx_index * 2);
4879 4951
4880 4952 default:
4881 4953 break;
4882 4954 }
4883 4955 } else if (ixgbe->classify_mode == IXGBE_CLASSIFY_VMDQ_RSS) {
4884 4956 rx_ring_per_group = ixgbe->num_rx_rings / ixgbe->num_rx_groups;
4885 4957
4886 4958 switch (hw->mac.type) {
4887 4959 case ixgbe_mac_82598EB:
4888 4960 hw_rx_index = (sw_rx_index / rx_ring_per_group) *
4889 4961 16 + (sw_rx_index % rx_ring_per_group);
4890 4962 return (hw_rx_index);
4891 4963
4892 4964 case ixgbe_mac_82599EB:
4965 + case ixgbe_mac_X540:
4893 4966 if (ixgbe->num_rx_groups > 32) {
4894 4967 hw_rx_index = (sw_rx_index /
4895 4968 rx_ring_per_group) * 2 +
4896 4969 (sw_rx_index % rx_ring_per_group);
4897 4970 } else {
4898 4971 hw_rx_index = (sw_rx_index /
4899 4972 rx_ring_per_group) * 4 +
4900 4973 (sw_rx_index % rx_ring_per_group);
4901 4974 }
4902 4975 return (hw_rx_index);
4903 4976
4904 4977 default:
4905 4978 break;
4906 4979 }
4907 4980 }
4908 4981
4909 4982 /*
4910 4983 * Should never reach. Just to make compiler happy.
4911 4984 */
4912 4985 return (sw_rx_index);
4913 4986 }
4914 4987
4915 4988 /*
4916 4989 * ixgbe_map_intrs_to_vectors - Map different interrupts to MSI-X vectors.
4917 4990 *
4918 4991 * For MSI-X, here will map rx interrupt, tx interrupt and other interrupt
4919 4992 * to vector[0 - (intr_cnt -1)].
4920 4993 */
4921 4994 static int
4922 4995 ixgbe_map_intrs_to_vectors(ixgbe_t *ixgbe)
4923 4996 {
4924 4997 int i, vector = 0;
4925 4998
4926 4999 /* initialize vector map */
4927 5000 bzero(&ixgbe->vect_map, sizeof (ixgbe->vect_map));
4928 5001 for (i = 0; i < ixgbe->intr_cnt; i++) {
4929 5002 ixgbe->vect_map[i].ixgbe = ixgbe;
4930 5003 }
4931 5004
4932 5005 /*
4933 5006 * non-MSI-X case is very simple: rx rings[0] on RTxQ[0],
4934 5007 * tx rings[0] on RTxQ[1].
4935 5008 */
4936 5009 if (ixgbe->intr_type != DDI_INTR_TYPE_MSIX) {
4937 5010 ixgbe_map_rxring_to_vector(ixgbe, 0, 0);
4938 5011 ixgbe_map_txring_to_vector(ixgbe, 0, 1);
4939 5012 return (IXGBE_SUCCESS);
4940 5013 }
4941 5014
4942 5015 /*
4943 5016 * Interrupts/vectors mapping for MSI-X
4944 5017 */
4945 5018
4946 5019 /*
4947 5020 * Map other interrupt to vector 0,
4948 5021 * Set bit in map and count the bits set.
4949 5022 */
4950 5023 BT_SET(ixgbe->vect_map[vector].other_map, 0);
4951 5024 ixgbe->vect_map[vector].other_cnt++;
4952 5025
4953 5026 /*
4954 5027 * Map rx ring interrupts to vectors
4955 5028 */
4956 5029 for (i = 0; i < ixgbe->num_rx_rings; i++) {
4957 5030 ixgbe_map_rxring_to_vector(ixgbe, i, vector);
4958 5031 vector = (vector +1) % ixgbe->intr_cnt;
4959 5032 }
4960 5033
4961 5034 /*
4962 5035 * Map tx ring interrupts to vectors
4963 5036 */
4964 5037 for (i = 0; i < ixgbe->num_tx_rings; i++) {
4965 5038 ixgbe_map_txring_to_vector(ixgbe, i, vector);
4966 5039 vector = (vector +1) % ixgbe->intr_cnt;
4967 5040 }
4968 5041
4969 5042 return (IXGBE_SUCCESS);
4970 5043 }
4971 5044
4972 5045 /*
4973 5046 * ixgbe_setup_adapter_vector - Setup the adapter interrupt vector(s).
4974 5047 *
4975 5048 * This relies on ring/vector mapping already set up in the
4976 5049 * vect_map[] structures
4977 5050 */
4978 5051 static void
4979 5052 ixgbe_setup_adapter_vector(ixgbe_t *ixgbe)
4980 5053 {
4981 5054 struct ixgbe_hw *hw = &ixgbe->hw;
4982 5055 ixgbe_intr_vector_t *vect; /* vector bitmap */
4983 5056 int r_idx; /* ring index */
4984 5057 int v_idx; /* vector index */
4985 5058 uint32_t hw_index;
4986 5059
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4987 5060 /*
4988 5061 * Clear any previous entries
4989 5062 */
4990 5063 switch (hw->mac.type) {
4991 5064 case ixgbe_mac_82598EB:
4992 5065 for (v_idx = 0; v_idx < 25; v_idx++)
4993 5066 IXGBE_WRITE_REG(hw, IXGBE_IVAR(v_idx), 0);
4994 5067 break;
4995 5068
4996 5069 case ixgbe_mac_82599EB:
5070 + case ixgbe_mac_X540:
4997 5071 for (v_idx = 0; v_idx < 64; v_idx++)
4998 5072 IXGBE_WRITE_REG(hw, IXGBE_IVAR(v_idx), 0);
4999 5073 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, 0);
5000 5074 break;
5001 5075
5002 5076 default:
5003 5077 break;
5004 5078 }
5005 5079
5006 5080 /*
5007 5081 * For non MSI-X interrupt, rx rings[0] will use RTxQ[0], and
5008 5082 * tx rings[0] will use RTxQ[1].
5009 5083 */
5010 5084 if (ixgbe->intr_type != DDI_INTR_TYPE_MSIX) {
5011 5085 ixgbe_setup_ivar(ixgbe, 0, 0, 0);
5012 5086 ixgbe_setup_ivar(ixgbe, 0, 1, 1);
5013 5087 return;
5014 5088 }
5015 5089
5016 5090 /*
5017 5091 * For MSI-X interrupt, "Other" is always on vector[0].
5018 5092 */
5019 5093 ixgbe_setup_ivar(ixgbe, IXGBE_IVAR_OTHER_CAUSES_INDEX, 0, -1);
5020 5094
5021 5095 /*
5022 5096 * For each interrupt vector, populate the IVAR table
5023 5097 */
5024 5098 for (v_idx = 0; v_idx < ixgbe->intr_cnt; v_idx++) {
5025 5099 vect = &ixgbe->vect_map[v_idx];
5026 5100
5027 5101 /*
5028 5102 * For each rx ring bit set
5029 5103 */
5030 5104 r_idx = bt_getlowbit(vect->rx_map, 0,
5031 5105 (ixgbe->num_rx_rings - 1));
5032 5106
5033 5107 while (r_idx >= 0) {
5034 5108 hw_index = ixgbe->rx_rings[r_idx].hw_index;
5035 5109 ixgbe_setup_ivar(ixgbe, hw_index, v_idx, 0);
5036 5110 r_idx = bt_getlowbit(vect->rx_map, (r_idx + 1),
5037 5111 (ixgbe->num_rx_rings - 1));
5038 5112 }
5039 5113
5040 5114 /*
5041 5115 * For each tx ring bit set
5042 5116 */
5043 5117 r_idx = bt_getlowbit(vect->tx_map, 0,
5044 5118 (ixgbe->num_tx_rings - 1));
5045 5119
5046 5120 while (r_idx >= 0) {
5047 5121 ixgbe_setup_ivar(ixgbe, r_idx, v_idx, 1);
5048 5122 r_idx = bt_getlowbit(vect->tx_map, (r_idx + 1),
5049 5123 (ixgbe->num_tx_rings - 1));
5050 5124 }
5051 5125 }
5052 5126 }
5053 5127
5054 5128 /*
5055 5129 * ixgbe_rem_intr_handlers - Remove the interrupt handlers.
5056 5130 */
5057 5131 static void
5058 5132 ixgbe_rem_intr_handlers(ixgbe_t *ixgbe)
5059 5133 {
5060 5134 int i;
5061 5135 int rc;
5062 5136
5063 5137 for (i = 0; i < ixgbe->intr_cnt; i++) {
5064 5138 rc = ddi_intr_remove_handler(ixgbe->htable[i]);
5065 5139 if (rc != DDI_SUCCESS) {
5066 5140 IXGBE_DEBUGLOG_1(ixgbe,
5067 5141 "Remove intr handler failed: %d", rc);
5068 5142 }
5069 5143 }
5070 5144 }
5071 5145
5072 5146 /*
5073 5147 * ixgbe_rem_intrs - Remove the allocated interrupts.
5074 5148 */
5075 5149 static void
5076 5150 ixgbe_rem_intrs(ixgbe_t *ixgbe)
5077 5151 {
5078 5152 int i;
5079 5153 int rc;
5080 5154
5081 5155 for (i = 0; i < ixgbe->intr_cnt; i++) {
5082 5156 rc = ddi_intr_free(ixgbe->htable[i]);
5083 5157 if (rc != DDI_SUCCESS) {
5084 5158 IXGBE_DEBUGLOG_1(ixgbe,
5085 5159 "Free intr failed: %d", rc);
5086 5160 }
5087 5161 }
5088 5162
5089 5163 kmem_free(ixgbe->htable, ixgbe->intr_size);
5090 5164 ixgbe->htable = NULL;
5091 5165 }
5092 5166
5093 5167 /*
5094 5168 * ixgbe_enable_intrs - Enable all the ddi interrupts.
5095 5169 */
5096 5170 static int
5097 5171 ixgbe_enable_intrs(ixgbe_t *ixgbe)
5098 5172 {
5099 5173 int i;
5100 5174 int rc;
5101 5175
5102 5176 /*
5103 5177 * Enable interrupts
5104 5178 */
5105 5179 if (ixgbe->intr_cap & DDI_INTR_FLAG_BLOCK) {
5106 5180 /*
5107 5181 * Call ddi_intr_block_enable() for MSI
5108 5182 */
5109 5183 rc = ddi_intr_block_enable(ixgbe->htable, ixgbe->intr_cnt);
5110 5184 if (rc != DDI_SUCCESS) {
5111 5185 ixgbe_log(ixgbe,
5112 5186 "Enable block intr failed: %d", rc);
5113 5187 return (IXGBE_FAILURE);
5114 5188 }
5115 5189 } else {
5116 5190 /*
5117 5191 * Call ddi_intr_enable() for Legacy/MSI non block enable
5118 5192 */
5119 5193 for (i = 0; i < ixgbe->intr_cnt; i++) {
5120 5194 rc = ddi_intr_enable(ixgbe->htable[i]);
5121 5195 if (rc != DDI_SUCCESS) {
5122 5196 ixgbe_log(ixgbe,
5123 5197 "Enable intr failed: %d", rc);
5124 5198 return (IXGBE_FAILURE);
5125 5199 }
5126 5200 }
5127 5201 }
5128 5202
5129 5203 return (IXGBE_SUCCESS);
5130 5204 }
5131 5205
5132 5206 /*
5133 5207 * ixgbe_disable_intrs - Disable all the interrupts.
5134 5208 */
5135 5209 static int
5136 5210 ixgbe_disable_intrs(ixgbe_t *ixgbe)
5137 5211 {
5138 5212 int i;
5139 5213 int rc;
5140 5214
5141 5215 /*
5142 5216 * Disable all interrupts
5143 5217 */
5144 5218 if (ixgbe->intr_cap & DDI_INTR_FLAG_BLOCK) {
5145 5219 rc = ddi_intr_block_disable(ixgbe->htable, ixgbe->intr_cnt);
5146 5220 if (rc != DDI_SUCCESS) {
5147 5221 ixgbe_log(ixgbe,
5148 5222 "Disable block intr failed: %d", rc);
5149 5223 return (IXGBE_FAILURE);
5150 5224 }
5151 5225 } else {
5152 5226 for (i = 0; i < ixgbe->intr_cnt; i++) {
5153 5227 rc = ddi_intr_disable(ixgbe->htable[i]);
5154 5228 if (rc != DDI_SUCCESS) {
5155 5229 ixgbe_log(ixgbe,
5156 5230 "Disable intr failed: %d", rc);
5157 5231 return (IXGBE_FAILURE);
5158 5232 }
5159 5233 }
5160 5234 }
5161 5235
5162 5236 return (IXGBE_SUCCESS);
5163 5237 }
5164 5238
5165 5239 /*
5166 5240 * ixgbe_get_hw_state - Get and save parameters related to adapter hardware.
5167 5241 */
5168 5242 static void
5169 5243 ixgbe_get_hw_state(ixgbe_t *ixgbe)
5170 5244 {
5171 5245 struct ixgbe_hw *hw = &ixgbe->hw;
5172 5246 ixgbe_link_speed speed = IXGBE_LINK_SPEED_UNKNOWN;
5173 5247 boolean_t link_up = B_FALSE;
5174 5248 uint32_t pcs1g_anlp = 0;
5175 5249 uint32_t pcs1g_ana = 0;
5176 5250 boolean_t autoneg = B_FALSE;
5177 5251
5178 5252 ASSERT(mutex_owned(&ixgbe->gen_lock));
5179 5253 ixgbe->param_lp_1000fdx_cap = 0;
5180 5254 ixgbe->param_lp_100fdx_cap = 0;
5181 5255
5182 5256 /* check for link, don't wait */
5183 5257 (void) ixgbe_check_link(hw, &speed, &link_up, false);
5184 5258 pcs1g_ana = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
5185 5259
5186 5260 if (link_up) {
5187 5261 pcs1g_anlp = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
5188 5262
5189 5263 ixgbe->param_lp_1000fdx_cap =
5190 5264 (pcs1g_anlp & IXGBE_PCS1GANLP_LPFD) ? 1 : 0;
5191 5265 ixgbe->param_lp_100fdx_cap =
5192 5266 (pcs1g_anlp & IXGBE_PCS1GANLP_LPFD) ? 1 : 0;
5193 5267 }
5194 5268
5195 5269 (void) ixgbe_get_link_capabilities(hw, &speed, &autoneg);
5196 5270
5197 5271 ixgbe->param_adv_1000fdx_cap = ((pcs1g_ana & IXGBE_PCS1GANA_FDC) &&
5198 5272 (speed & IXGBE_LINK_SPEED_1GB_FULL)) ? 1 : 0;
5199 5273 ixgbe->param_adv_100fdx_cap = ((pcs1g_ana & IXGBE_PCS1GANA_FDC) &&
5200 5274 (speed & IXGBE_LINK_SPEED_100_FULL)) ? 1 : 0;
5201 5275 }
5202 5276
5203 5277 /*
5204 5278 * ixgbe_get_driver_control - Notify that driver is in control of device.
5205 5279 */
5206 5280 static void
5207 5281 ixgbe_get_driver_control(struct ixgbe_hw *hw)
5208 5282 {
5209 5283 uint32_t ctrl_ext;
5210 5284
5211 5285 /*
5212 5286 * Notify firmware that driver is in control of device
5213 5287 */
5214 5288 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5215 5289 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
5216 5290 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5217 5291 }
5218 5292
5219 5293 /*
5220 5294 * ixgbe_release_driver_control - Notify that driver is no longer in control
5221 5295 * of device.
5222 5296 */
5223 5297 static void
5224 5298 ixgbe_release_driver_control(struct ixgbe_hw *hw)
5225 5299 {
5226 5300 uint32_t ctrl_ext;
5227 5301
5228 5302 /*
5229 5303 * Notify firmware that driver is no longer in control of device
5230 5304 */
5231 5305 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5232 5306 ctrl_ext &= ~IXGBE_CTRL_EXT_DRV_LOAD;
5233 5307 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5234 5308 }
5235 5309
5236 5310 /*
5237 5311 * ixgbe_atomic_reserve - Atomic decrease operation.
5238 5312 */
5239 5313 int
5240 5314 ixgbe_atomic_reserve(uint32_t *count_p, uint32_t n)
5241 5315 {
5242 5316 uint32_t oldval;
5243 5317 uint32_t newval;
5244 5318
5245 5319 /*
5246 5320 * ATOMICALLY
5247 5321 */
5248 5322 do {
5249 5323 oldval = *count_p;
5250 5324 if (oldval < n)
5251 5325 return (-1);
5252 5326 newval = oldval - n;
5253 5327 } while (atomic_cas_32(count_p, oldval, newval) != oldval);
5254 5328
5255 5329 return (newval);
5256 5330 }
5257 5331
5258 5332 /*
5259 5333 * ixgbe_mc_table_itr - Traverse the entries in the multicast table.
5260 5334 */
5261 5335 static uint8_t *
5262 5336 ixgbe_mc_table_itr(struct ixgbe_hw *hw, uint8_t **upd_ptr, uint32_t *vmdq)
5263 5337 {
5264 5338 uint8_t *addr = *upd_ptr;
5265 5339 uint8_t *new_ptr;
5266 5340
5267 5341 _NOTE(ARGUNUSED(hw));
5268 5342 _NOTE(ARGUNUSED(vmdq));
5269 5343
5270 5344 new_ptr = addr + IXGBE_ETH_LENGTH_OF_ADDRESS;
5271 5345 *upd_ptr = new_ptr;
5272 5346 return (addr);
5273 5347 }
5274 5348
5275 5349 /*
5276 5350 * FMA support
5277 5351 */
5278 5352 int
5279 5353 ixgbe_check_acc_handle(ddi_acc_handle_t handle)
5280 5354 {
5281 5355 ddi_fm_error_t de;
5282 5356
5283 5357 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
5284 5358 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION);
5285 5359 return (de.fme_status);
5286 5360 }
5287 5361
5288 5362 int
5289 5363 ixgbe_check_dma_handle(ddi_dma_handle_t handle)
5290 5364 {
5291 5365 ddi_fm_error_t de;
5292 5366
5293 5367 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
5294 5368 return (de.fme_status);
5295 5369 }
5296 5370
5297 5371 /*
5298 5372 * ixgbe_fm_error_cb - The IO fault service error handling callback function.
5299 5373 */
5300 5374 static int
5301 5375 ixgbe_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
5302 5376 {
5303 5377 _NOTE(ARGUNUSED(impl_data));
5304 5378 /*
5305 5379 * as the driver can always deal with an error in any dma or
5306 5380 * access handle, we can just return the fme_status value.
5307 5381 */
5308 5382 pci_ereport_post(dip, err, NULL);
5309 5383 return (err->fme_status);
5310 5384 }
5311 5385
5312 5386 static void
5313 5387 ixgbe_fm_init(ixgbe_t *ixgbe)
5314 5388 {
5315 5389 ddi_iblock_cookie_t iblk;
5316 5390 int fma_dma_flag;
5317 5391
5318 5392 /*
5319 5393 * Only register with IO Fault Services if we have some capability
5320 5394 */
5321 5395 if (ixgbe->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) {
5322 5396 ixgbe_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
5323 5397 } else {
5324 5398 ixgbe_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
5325 5399 }
5326 5400
5327 5401 if (ixgbe->fm_capabilities & DDI_FM_DMACHK_CAPABLE) {
5328 5402 fma_dma_flag = 1;
5329 5403 } else {
5330 5404 fma_dma_flag = 0;
5331 5405 }
5332 5406
5333 5407 ixgbe_set_fma_flags(fma_dma_flag);
5334 5408
5335 5409 if (ixgbe->fm_capabilities) {
5336 5410
5337 5411 /*
5338 5412 * Register capabilities with IO Fault Services
5339 5413 */
5340 5414 ddi_fm_init(ixgbe->dip, &ixgbe->fm_capabilities, &iblk);
5341 5415
5342 5416 /*
5343 5417 * Initialize pci ereport capabilities if ereport capable
5344 5418 */
5345 5419 if (DDI_FM_EREPORT_CAP(ixgbe->fm_capabilities) ||
5346 5420 DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities))
5347 5421 pci_ereport_setup(ixgbe->dip);
5348 5422
5349 5423 /*
5350 5424 * Register error callback if error callback capable
5351 5425 */
5352 5426 if (DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities))
5353 5427 ddi_fm_handler_register(ixgbe->dip,
5354 5428 ixgbe_fm_error_cb, (void*) ixgbe);
5355 5429 }
5356 5430 }
5357 5431
5358 5432 static void
5359 5433 ixgbe_fm_fini(ixgbe_t *ixgbe)
5360 5434 {
5361 5435 /*
5362 5436 * Only unregister FMA capabilities if they are registered
5363 5437 */
5364 5438 if (ixgbe->fm_capabilities) {
5365 5439
5366 5440 /*
5367 5441 * Release any resources allocated by pci_ereport_setup()
5368 5442 */
5369 5443 if (DDI_FM_EREPORT_CAP(ixgbe->fm_capabilities) ||
5370 5444 DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities))
5371 5445 pci_ereport_teardown(ixgbe->dip);
5372 5446
5373 5447 /*
5374 5448 * Un-register error callback if error callback capable
5375 5449 */
5376 5450 if (DDI_FM_ERRCB_CAP(ixgbe->fm_capabilities))
5377 5451 ddi_fm_handler_unregister(ixgbe->dip);
5378 5452
5379 5453 /*
5380 5454 * Unregister from IO Fault Service
5381 5455 */
5382 5456 ddi_fm_fini(ixgbe->dip);
5383 5457 }
5384 5458 }
5385 5459
5386 5460 void
5387 5461 ixgbe_fm_ereport(ixgbe_t *ixgbe, char *detail)
5388 5462 {
5389 5463 uint64_t ena;
5390 5464 char buf[FM_MAX_CLASS];
5391 5465
5392 5466 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
5393 5467 ena = fm_ena_generate(0, FM_ENA_FMT1);
5394 5468 if (DDI_FM_EREPORT_CAP(ixgbe->fm_capabilities)) {
5395 5469 ddi_fm_ereport_post(ixgbe->dip, buf, ena, DDI_NOSLEEP,
5396 5470 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
5397 5471 }
5398 5472 }
5399 5473
5400 5474 static int
5401 5475 ixgbe_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num)
5402 5476 {
5403 5477 ixgbe_rx_ring_t *rx_ring = (ixgbe_rx_ring_t *)rh;
5404 5478
5405 5479 mutex_enter(&rx_ring->rx_lock);
5406 5480 rx_ring->ring_gen_num = mr_gen_num;
5407 5481 mutex_exit(&rx_ring->rx_lock);
5408 5482 return (0);
5409 5483 }
5410 5484
5411 5485 /*
5412 5486 * Get the global ring index by a ring index within a group.
5413 5487 */
5414 5488 static int
5415 5489 ixgbe_get_rx_ring_index(ixgbe_t *ixgbe, int gindex, int rindex)
5416 5490 {
5417 5491 ixgbe_rx_ring_t *rx_ring;
5418 5492 int i;
5419 5493
5420 5494 for (i = 0; i < ixgbe->num_rx_rings; i++) {
5421 5495 rx_ring = &ixgbe->rx_rings[i];
5422 5496 if (rx_ring->group_index == gindex)
5423 5497 rindex--;
5424 5498 if (rindex < 0)
5425 5499 return (i);
5426 5500 }
5427 5501
5428 5502 return (-1);
5429 5503 }
5430 5504
5431 5505 /*
5432 5506 * Callback funtion for MAC layer to register all rings.
5433 5507 */
5434 5508 /* ARGSUSED */
5435 5509 void
5436 5510 ixgbe_fill_ring(void *arg, mac_ring_type_t rtype, const int group_index,
5437 5511 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh)
5438 5512 {
5439 5513 ixgbe_t *ixgbe = (ixgbe_t *)arg;
5440 5514 mac_intr_t *mintr = &infop->mri_intr;
5441 5515
5442 5516 switch (rtype) {
5443 5517 case MAC_RING_TYPE_RX: {
5444 5518 /*
5445 5519 * 'index' is the ring index within the group.
5446 5520 * Need to get the global ring index by searching in groups.
5447 5521 */
5448 5522 int global_ring_index = ixgbe_get_rx_ring_index(
5449 5523 ixgbe, group_index, ring_index);
5450 5524
5451 5525 ASSERT(global_ring_index >= 0);
5452 5526
5453 5527 ixgbe_rx_ring_t *rx_ring = &ixgbe->rx_rings[global_ring_index];
5454 5528 rx_ring->ring_handle = rh;
5455 5529
5456 5530 infop->mri_driver = (mac_ring_driver_t)rx_ring;
5457 5531 infop->mri_start = ixgbe_ring_start;
5458 5532 infop->mri_stop = NULL;
5459 5533 infop->mri_poll = ixgbe_ring_rx_poll;
5460 5534 infop->mri_stat = ixgbe_rx_ring_stat;
5461 5535
5462 5536 mintr->mi_handle = (mac_intr_handle_t)rx_ring;
5463 5537 mintr->mi_enable = ixgbe_rx_ring_intr_enable;
5464 5538 mintr->mi_disable = ixgbe_rx_ring_intr_disable;
5465 5539 if (ixgbe->intr_type &
5466 5540 (DDI_INTR_TYPE_MSIX | DDI_INTR_TYPE_MSI)) {
5467 5541 mintr->mi_ddi_handle =
5468 5542 ixgbe->htable[rx_ring->intr_vector];
5469 5543 }
5470 5544
5471 5545 break;
5472 5546 }
5473 5547 case MAC_RING_TYPE_TX: {
5474 5548 ASSERT(group_index == -1);
5475 5549 ASSERT(ring_index < ixgbe->num_tx_rings);
5476 5550
5477 5551 ixgbe_tx_ring_t *tx_ring = &ixgbe->tx_rings[ring_index];
5478 5552 tx_ring->ring_handle = rh;
5479 5553
5480 5554 infop->mri_driver = (mac_ring_driver_t)tx_ring;
5481 5555 infop->mri_start = NULL;
5482 5556 infop->mri_stop = NULL;
5483 5557 infop->mri_tx = ixgbe_ring_tx;
5484 5558 infop->mri_stat = ixgbe_tx_ring_stat;
5485 5559 if (ixgbe->intr_type &
5486 5560 (DDI_INTR_TYPE_MSIX | DDI_INTR_TYPE_MSI)) {
5487 5561 mintr->mi_ddi_handle =
5488 5562 ixgbe->htable[tx_ring->intr_vector];
5489 5563 }
5490 5564 break;
5491 5565 }
5492 5566 default:
5493 5567 break;
5494 5568 }
5495 5569 }
5496 5570
5497 5571 /*
5498 5572 * Callback funtion for MAC layer to register all groups.
5499 5573 */
5500 5574 void
5501 5575 ixgbe_fill_group(void *arg, mac_ring_type_t rtype, const int index,
5502 5576 mac_group_info_t *infop, mac_group_handle_t gh)
5503 5577 {
5504 5578 ixgbe_t *ixgbe = (ixgbe_t *)arg;
5505 5579
5506 5580 switch (rtype) {
5507 5581 case MAC_RING_TYPE_RX: {
5508 5582 ixgbe_rx_group_t *rx_group;
5509 5583
5510 5584 rx_group = &ixgbe->rx_groups[index];
5511 5585 rx_group->group_handle = gh;
5512 5586
5513 5587 infop->mgi_driver = (mac_group_driver_t)rx_group;
5514 5588 infop->mgi_start = NULL;
5515 5589 infop->mgi_stop = NULL;
5516 5590 infop->mgi_addmac = ixgbe_addmac;
5517 5591 infop->mgi_remmac = ixgbe_remmac;
5518 5592 infop->mgi_count = (ixgbe->num_rx_rings / ixgbe->num_rx_groups);
5519 5593
5520 5594 break;
5521 5595 }
5522 5596 case MAC_RING_TYPE_TX:
5523 5597 break;
5524 5598 default:
5525 5599 break;
5526 5600 }
5527 5601 }
5528 5602
5529 5603 /*
5530 5604 * Enable interrupt on the specificed rx ring.
5531 5605 */
5532 5606 int
5533 5607 ixgbe_rx_ring_intr_enable(mac_intr_handle_t intrh)
5534 5608 {
5535 5609 ixgbe_rx_ring_t *rx_ring = (ixgbe_rx_ring_t *)intrh;
5536 5610 ixgbe_t *ixgbe = rx_ring->ixgbe;
5537 5611 int r_idx = rx_ring->index;
5538 5612 int hw_r_idx = rx_ring->hw_index;
5539 5613 int v_idx = rx_ring->intr_vector;
5540 5614
5541 5615 mutex_enter(&ixgbe->gen_lock);
5542 5616 if (ixgbe->ixgbe_state & IXGBE_INTR_ADJUST) {
5543 5617 mutex_exit(&ixgbe->gen_lock);
5544 5618 /*
5545 5619 * Simply return 0.
5546 5620 * Interrupts are being adjusted. ixgbe_intr_adjust()
5547 5621 * will eventually re-enable the interrupt when it's
5548 5622 * done with the adjustment.
5549 5623 */
5550 5624 return (0);
5551 5625 }
5552 5626
5553 5627 /*
5554 5628 * To enable interrupt by setting the VAL bit of given interrupt
5555 5629 * vector allocation register (IVAR).
5556 5630 */
5557 5631 ixgbe_enable_ivar(ixgbe, hw_r_idx, 0);
5558 5632
5559 5633 BT_SET(ixgbe->vect_map[v_idx].rx_map, r_idx);
5560 5634
5561 5635 /*
5562 5636 * Trigger a Rx interrupt on this ring
5563 5637 */
5564 5638 IXGBE_WRITE_REG(&ixgbe->hw, IXGBE_EICS, (1 << v_idx));
5565 5639 IXGBE_WRITE_FLUSH(&ixgbe->hw);
5566 5640
5567 5641 mutex_exit(&ixgbe->gen_lock);
5568 5642
5569 5643 return (0);
5570 5644 }
5571 5645
5572 5646 /*
5573 5647 * Disable interrupt on the specificed rx ring.
5574 5648 */
5575 5649 int
5576 5650 ixgbe_rx_ring_intr_disable(mac_intr_handle_t intrh)
5577 5651 {
5578 5652 ixgbe_rx_ring_t *rx_ring = (ixgbe_rx_ring_t *)intrh;
5579 5653 ixgbe_t *ixgbe = rx_ring->ixgbe;
5580 5654 int r_idx = rx_ring->index;
5581 5655 int hw_r_idx = rx_ring->hw_index;
5582 5656 int v_idx = rx_ring->intr_vector;
5583 5657
5584 5658 mutex_enter(&ixgbe->gen_lock);
5585 5659 if (ixgbe->ixgbe_state & IXGBE_INTR_ADJUST) {
5586 5660 mutex_exit(&ixgbe->gen_lock);
5587 5661 /*
5588 5662 * Simply return 0.
5589 5663 * In the rare case where an interrupt is being
5590 5664 * disabled while interrupts are being adjusted,
5591 5665 * we don't fail the operation. No interrupts will
5592 5666 * be generated while they are adjusted, and
5593 5667 * ixgbe_intr_adjust() will cause the interrupts
5594 5668 * to be re-enabled once it completes. Note that
5595 5669 * in this case, packets may be delivered to the
5596 5670 * stack via interrupts before xgbe_rx_ring_intr_enable()
5597 5671 * is called again. This is acceptable since interrupt
5598 5672 * adjustment is infrequent, and the stack will be
5599 5673 * able to handle these packets.
5600 5674 */
5601 5675 return (0);
5602 5676 }
5603 5677
5604 5678 /*
5605 5679 * To disable interrupt by clearing the VAL bit of given interrupt
5606 5680 * vector allocation register (IVAR).
5607 5681 */
5608 5682 ixgbe_disable_ivar(ixgbe, hw_r_idx, 0);
5609 5683
5610 5684 BT_CLEAR(ixgbe->vect_map[v_idx].rx_map, r_idx);
5611 5685
5612 5686 mutex_exit(&ixgbe->gen_lock);
5613 5687
5614 5688 return (0);
5615 5689 }
5616 5690
5617 5691 /*
5618 5692 * Add a mac address.
5619 5693 */
5620 5694 static int
5621 5695 ixgbe_addmac(void *arg, const uint8_t *mac_addr)
5622 5696 {
5623 5697 ixgbe_rx_group_t *rx_group = (ixgbe_rx_group_t *)arg;
5624 5698 ixgbe_t *ixgbe = rx_group->ixgbe;
5625 5699 struct ixgbe_hw *hw = &ixgbe->hw;
5626 5700 int slot, i;
5627 5701
5628 5702 mutex_enter(&ixgbe->gen_lock);
5629 5703
5630 5704 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
5631 5705 mutex_exit(&ixgbe->gen_lock);
5632 5706 return (ECANCELED);
5633 5707 }
5634 5708
5635 5709 if (ixgbe->unicst_avail == 0) {
5636 5710 /* no slots available */
5637 5711 mutex_exit(&ixgbe->gen_lock);
5638 5712 return (ENOSPC);
5639 5713 }
5640 5714
5641 5715 /*
5642 5716 * The first ixgbe->num_rx_groups slots are reserved for each respective
5643 5717 * group. The rest slots are shared by all groups. While adding a
5644 5718 * MAC address, reserved slots are firstly checked then the shared
5645 5719 * slots are searched.
5646 5720 */
5647 5721 slot = -1;
5648 5722 if (ixgbe->unicst_addr[rx_group->index].mac.set == 1) {
5649 5723 for (i = ixgbe->num_rx_groups; i < ixgbe->unicst_total; i++) {
5650 5724 if (ixgbe->unicst_addr[i].mac.set == 0) {
5651 5725 slot = i;
5652 5726 break;
5653 5727 }
5654 5728 }
5655 5729 } else {
5656 5730 slot = rx_group->index;
5657 5731 }
5658 5732
5659 5733 if (slot == -1) {
5660 5734 /* no slots available */
5661 5735 mutex_exit(&ixgbe->gen_lock);
5662 5736 return (ENOSPC);
5663 5737 }
5664 5738
5665 5739 bcopy(mac_addr, ixgbe->unicst_addr[slot].mac.addr, ETHERADDRL);
5666 5740 (void) ixgbe_set_rar(hw, slot, ixgbe->unicst_addr[slot].mac.addr,
5667 5741 rx_group->index, IXGBE_RAH_AV);
5668 5742 ixgbe->unicst_addr[slot].mac.set = 1;
5669 5743 ixgbe->unicst_addr[slot].mac.group_index = rx_group->index;
5670 5744 ixgbe->unicst_avail--;
5671 5745
5672 5746 mutex_exit(&ixgbe->gen_lock);
5673 5747
5674 5748 return (0);
5675 5749 }
5676 5750
5677 5751 /*
5678 5752 * Remove a mac address.
5679 5753 */
5680 5754 static int
5681 5755 ixgbe_remmac(void *arg, const uint8_t *mac_addr)
5682 5756 {
5683 5757 ixgbe_rx_group_t *rx_group = (ixgbe_rx_group_t *)arg;
5684 5758 ixgbe_t *ixgbe = rx_group->ixgbe;
5685 5759 struct ixgbe_hw *hw = &ixgbe->hw;
5686 5760 int slot;
5687 5761
5688 5762 mutex_enter(&ixgbe->gen_lock);
5689 5763
5690 5764 if (ixgbe->ixgbe_state & IXGBE_SUSPENDED) {
5691 5765 mutex_exit(&ixgbe->gen_lock);
5692 5766 return (ECANCELED);
5693 5767 }
5694 5768
5695 5769 slot = ixgbe_unicst_find(ixgbe, mac_addr);
5696 5770 if (slot == -1) {
5697 5771 mutex_exit(&ixgbe->gen_lock);
5698 5772 return (EINVAL);
5699 5773 }
5700 5774
5701 5775 if (ixgbe->unicst_addr[slot].mac.set == 0) {
5702 5776 mutex_exit(&ixgbe->gen_lock);
5703 5777 return (EINVAL);
5704 5778 }
5705 5779
5706 5780 bzero(ixgbe->unicst_addr[slot].mac.addr, ETHERADDRL);
5707 5781 (void) ixgbe_clear_rar(hw, slot);
5708 5782 ixgbe->unicst_addr[slot].mac.set = 0;
5709 5783 ixgbe->unicst_avail++;
5710 5784
5711 5785 mutex_exit(&ixgbe->gen_lock);
5712 5786
5713 5787 return (0);
5714 5788 }
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