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3014 Intel X540 Support (fix lint)
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--- old/usr/src/uts/common/io/ixgbe/ixgbe_x540.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_x540.c
1 1 /******************************************************************************
2 2
3 3 Copyright (c) 2001-2012, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_x540.c,v 1.2 2012/07/05 20:51:44 jfv Exp $*/
34 34
35 35 #include "ixgbe_x540.h"
36 36 #include "ixgbe_type.h"
37 37 #include "ixgbe_api.h"
38 38 #include "ixgbe_common.h"
39 39 #include "ixgbe_phy.h"
40 40
41 41 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
42 42 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
43 43 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
44 44 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
45 45
46 46 /**
47 47 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
48 48 * @hw: pointer to hardware structure
49 49 *
50 50 * Initialize the function pointers and assign the MAC type for X540.
51 51 * Does not touch the hardware.
52 52 **/
53 53 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
54 54 {
55 55 struct ixgbe_mac_info *mac = &hw->mac;
56 56 struct ixgbe_phy_info *phy = &hw->phy;
57 57 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
58 58 s32 ret_val;
59 59
60 60 DEBUGFUNC("ixgbe_init_ops_X540");
61 61
62 62 ret_val = ixgbe_init_phy_ops_generic(hw);
63 63 ret_val = ixgbe_init_ops_generic(hw);
64 64
65 65
66 66 /* EEPROM */
67 67 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
68 68 eeprom->ops.read = &ixgbe_read_eerd_X540;
69 69 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
70 70 eeprom->ops.write = &ixgbe_write_eewr_X540;
71 71 eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
72 72 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
73 73 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
74 74 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
75 75
76 76 /* PHY */
77 77 phy->ops.init = &ixgbe_init_phy_ops_generic;
78 78 phy->ops.reset = NULL;
79 79
80 80 /* MAC */
81 81 mac->ops.reset_hw = &ixgbe_reset_hw_X540;
82 82 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
83 83 mac->ops.get_media_type = &ixgbe_get_media_type_X540;
84 84 mac->ops.get_supported_physical_layer =
85 85 &ixgbe_get_supported_physical_layer_X540;
86 86 mac->ops.read_analog_reg8 = NULL;
87 87 mac->ops.write_analog_reg8 = NULL;
88 88 mac->ops.start_hw = &ixgbe_start_hw_X540;
89 89 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
90 90 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
91 91 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
92 92 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
93 93 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
94 94 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
95 95 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
96 96 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
97 97 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
98 98
99 99 /* RAR, Multicast, VLAN */
100 100 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
101 101 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
102 102 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
103 103 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
104 104 mac->rar_highwater = 1;
105 105 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
106 106 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
107 107 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
108 108 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
109 109 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
110 110 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
111 111
112 112 /* Link */
113 113 mac->ops.get_link_capabilities =
114 114 &ixgbe_get_copper_link_capabilities_generic;
115 115 mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
116 116 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
117 117 mac->ops.check_link = &ixgbe_check_mac_link_generic;
118 118
119 119 mac->mcft_size = 128;
120 120 mac->vft_size = 128;
121 121 mac->num_rar_entries = 128;
122 122 mac->rx_pb_size = 384;
123 123 mac->max_tx_queues = 128;
124 124 mac->max_rx_queues = 128;
125 125 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
126 126
127 127 /*
128 128 * FWSM register
129 129 * ARC supported; valid only if manageability features are
130 130 * enabled.
131 131 */
132 132 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
133 133 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
134 134
135 135 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
136 136
137 137 /* LEDs */
138 138 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
139 139 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
140 140
141 141 /* Manageability interface */
142 142 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
143 143
144 144 return ret_val;
145 145 }
146 146
147 147 /**
148 148 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
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149 149 * @hw: pointer to hardware structure
150 150 * @speed: pointer to link speed
151 151 * @autoneg: TRUE when autoneg or autotry is enabled
152 152 *
153 153 * Determines the link capabilities by reading the AUTOC register.
154 154 **/
155 155 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
156 156 ixgbe_link_speed *speed,
157 157 bool *autoneg)
158 158 {
159 - ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
160 -
161 - return IXGBE_SUCCESS;
159 + return ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
162 160 }
163 161
164 162 /**
165 163 * ixgbe_get_media_type_X540 - Get media type
166 164 * @hw: pointer to hardware structure
167 165 *
168 166 * Returns the media type (fiber, copper, backplane)
169 167 **/
170 168 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
171 169 {
172 170 UNREFERENCED_1PARAMETER(hw);
173 171 return ixgbe_media_type_copper;
174 172 }
175 173
176 174 /**
177 175 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
178 176 * @hw: pointer to hardware structure
179 177 * @speed: new link speed
180 178 * @autoneg: TRUE if autonegotiation enabled
181 179 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
182 180 **/
183 181 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
184 182 ixgbe_link_speed speed, bool autoneg,
185 183 bool autoneg_wait_to_complete)
186 184 {
187 185 DEBUGFUNC("ixgbe_setup_mac_link_X540");
188 186 return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
189 187 autoneg_wait_to_complete);
190 188 }
191 189
192 190 /**
193 191 * ixgbe_reset_hw_X540 - Perform hardware reset
194 192 * @hw: pointer to hardware structure
195 193 *
196 194 * Resets the hardware by resetting the transmit and receive units, masks
197 195 * and clears all interrupts, and perform a reset.
198 196 **/
199 197 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
200 198 {
201 199 s32 status;
202 200 u32 ctrl, i;
203 201
204 202 DEBUGFUNC("ixgbe_reset_hw_X540");
205 203
206 204 /* Call adapter stop to disable tx/rx and clear interrupts */
207 205 status = hw->mac.ops.stop_adapter(hw);
208 206 if (status != IXGBE_SUCCESS)
209 207 goto reset_hw_out;
210 208
211 209 /* flush pending Tx transactions */
212 210 ixgbe_clear_tx_pending(hw);
213 211
214 212 mac_reset_top:
215 213 ctrl = IXGBE_CTRL_RST;
216 214 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
217 215 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
218 216 IXGBE_WRITE_FLUSH(hw);
219 217
220 218 /* Poll for reset bit to self-clear indicating reset is complete */
221 219 for (i = 0; i < 10; i++) {
222 220 usec_delay(1);
223 221 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
224 222 if (!(ctrl & IXGBE_CTRL_RST_MASK))
225 223 break;
226 224 }
227 225
228 226 if (ctrl & IXGBE_CTRL_RST_MASK) {
229 227 status = IXGBE_ERR_RESET_FAILED;
230 228 DEBUGOUT("Reset polling failed to complete.\n");
231 229 }
232 230 msec_delay(100);
233 231
234 232 /*
235 233 * Double resets are required for recovery from certain error
236 234 * conditions. Between resets, it is necessary to stall to allow time
237 235 * for any pending HW events to complete.
238 236 */
239 237 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
240 238 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
241 239 goto mac_reset_top;
242 240 }
243 241
244 242 /* Set the Rx packet buffer size. */
245 243 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
246 244
247 245 /* Store the permanent mac address */
248 246 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
249 247
250 248 /*
251 249 * Store MAC address from RAR0, clear receive address registers, and
252 250 * clear the multicast table. Also reset num_rar_entries to 128,
253 251 * since we modify this value when programming the SAN MAC address.
254 252 */
255 253 hw->mac.num_rar_entries = 128;
256 254 hw->mac.ops.init_rx_addrs(hw);
257 255
258 256 /* Store the permanent SAN mac address */
259 257 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
260 258
261 259 /* Add the SAN MAC address to the RAR only if it's a valid address */
262 260 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
263 261 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
264 262 hw->mac.san_addr, 0, IXGBE_RAH_AV);
265 263
266 264 /* Save the SAN MAC RAR index */
267 265 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
268 266
269 267 /* Reserve the last RAR for the SAN MAC address */
270 268 hw->mac.num_rar_entries--;
271 269 }
272 270
273 271 /* Store the alternative WWNN/WWPN prefix */
274 272 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
275 273 &hw->mac.wwpn_prefix);
276 274
277 275 reset_hw_out:
278 276 return status;
279 277 }
280 278
281 279 /**
282 280 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
283 281 * @hw: pointer to hardware structure
284 282 *
285 283 * Starts the hardware using the generic start_hw function
286 284 * and the generation start_hw function.
287 285 * Then performs revision-specific operations, if any.
288 286 **/
289 287 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
290 288 {
291 289 s32 ret_val = IXGBE_SUCCESS;
292 290
293 291 DEBUGFUNC("ixgbe_start_hw_X540");
294 292
295 293 ret_val = ixgbe_start_hw_generic(hw);
296 294 if (ret_val != IXGBE_SUCCESS)
297 295 goto out;
298 296
299 297 ret_val = ixgbe_start_hw_gen2(hw);
300 298
301 299 out:
302 300 return ret_val;
303 301 }
304 302
305 303 /**
306 304 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
307 305 * @hw: pointer to hardware structure
308 306 *
309 307 * Determines physical layer capabilities of the current configuration.
310 308 **/
311 309 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
312 310 {
313 311 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
314 312 u16 ext_ability = 0;
315 313
316 314 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
317 315
318 316 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
319 317 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
320 318 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
321 319 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
322 320 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
323 321 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
324 322 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
325 323 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
326 324
327 325 return physical_layer;
328 326 }
329 327
330 328 /**
331 329 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
332 330 * @hw: pointer to hardware structure
333 331 *
334 332 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
335 333 * ixgbe_hw struct in order to set up EEPROM access.
336 334 **/
337 335 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
338 336 {
339 337 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
340 338 u32 eec;
341 339 u16 eeprom_size;
342 340
343 341 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
344 342
345 343 if (eeprom->type == ixgbe_eeprom_uninitialized) {
346 344 eeprom->semaphore_delay = 10;
347 345 eeprom->type = ixgbe_flash;
348 346
349 347 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
350 348 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
351 349 IXGBE_EEC_SIZE_SHIFT);
352 350 eeprom->word_size = 1 << (eeprom_size +
353 351 IXGBE_EEPROM_WORD_SIZE_SHIFT);
354 352
355 353 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
356 354 eeprom->type, eeprom->word_size);
357 355 }
358 356
359 357 return IXGBE_SUCCESS;
360 358 }
361 359
362 360 /**
363 361 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
364 362 * @hw: pointer to hardware structure
365 363 * @offset: offset of word in the EEPROM to read
366 364 * @data: word read from the EEPROM
367 365 *
368 366 * Reads a 16 bit word from the EEPROM using the EERD register.
369 367 **/
370 368 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
371 369 {
372 370 s32 status = IXGBE_SUCCESS;
373 371
374 372 DEBUGFUNC("ixgbe_read_eerd_X540");
375 373 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
376 374 IXGBE_SUCCESS)
377 375 status = ixgbe_read_eerd_generic(hw, offset, data);
378 376 else
379 377 status = IXGBE_ERR_SWFW_SYNC;
380 378
381 379 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
382 380 return status;
383 381 }
384 382
385 383 /**
386 384 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
387 385 * @hw: pointer to hardware structure
388 386 * @offset: offset of word in the EEPROM to read
389 387 * @words: number of words
390 388 * @data: word(s) read from the EEPROM
391 389 *
392 390 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
393 391 **/
394 392 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
395 393 u16 offset, u16 words, u16 *data)
396 394 {
397 395 s32 status = IXGBE_SUCCESS;
398 396
399 397 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
400 398 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
401 399 IXGBE_SUCCESS)
402 400 status = ixgbe_read_eerd_buffer_generic(hw, offset,
403 401 words, data);
404 402 else
405 403 status = IXGBE_ERR_SWFW_SYNC;
406 404
407 405 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
408 406 return status;
409 407 }
410 408
411 409 /**
412 410 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
413 411 * @hw: pointer to hardware structure
414 412 * @offset: offset of word in the EEPROM to write
415 413 * @data: word write to the EEPROM
416 414 *
417 415 * Write a 16 bit word to the EEPROM using the EEWR register.
418 416 **/
419 417 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
420 418 {
421 419 s32 status = IXGBE_SUCCESS;
422 420
423 421 DEBUGFUNC("ixgbe_write_eewr_X540");
424 422 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
425 423 IXGBE_SUCCESS)
426 424 status = ixgbe_write_eewr_generic(hw, offset, data);
427 425 else
428 426 status = IXGBE_ERR_SWFW_SYNC;
429 427
430 428 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
431 429 return status;
432 430 }
433 431
434 432 /**
435 433 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
436 434 * @hw: pointer to hardware structure
437 435 * @offset: offset of word in the EEPROM to write
438 436 * @words: number of words
439 437 * @data: word(s) write to the EEPROM
440 438 *
441 439 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
442 440 **/
443 441 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
444 442 u16 offset, u16 words, u16 *data)
445 443 {
446 444 s32 status = IXGBE_SUCCESS;
447 445
448 446 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
449 447 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
450 448 IXGBE_SUCCESS)
451 449 status = ixgbe_write_eewr_buffer_generic(hw, offset,
452 450 words, data);
453 451 else
454 452 status = IXGBE_ERR_SWFW_SYNC;
455 453
456 454 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
457 455 return status;
458 456 }
459 457
460 458 /**
461 459 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
462 460 *
463 461 * This function does not use synchronization for EERD and EEWR. It can
464 462 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
465 463 *
466 464 * @hw: pointer to hardware structure
467 465 **/
468 466 u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
469 467 {
470 468 u16 i;
471 469 u16 j;
472 470 u16 checksum = 0;
473 471 u16 length = 0;
474 472 u16 pointer = 0;
475 473 u16 word = 0;
476 474
477 475 /*
478 476 * Do not use hw->eeprom.ops.read because we do not want to take
479 477 * the synchronization semaphores here. Instead use
480 478 * ixgbe_read_eerd_generic
481 479 */
482 480
483 481 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
484 482
485 483 /* Include 0x0-0x3F in the checksum */
486 484 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
487 485 if (ixgbe_read_eerd_generic(hw, i, &word) != IXGBE_SUCCESS) {
488 486 DEBUGOUT("EEPROM read failed\n");
489 487 break;
490 488 }
491 489 checksum += word;
492 490 }
493 491
494 492 /*
495 493 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
496 494 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
497 495 */
498 496 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
499 497 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
500 498 continue;
501 499
502 500 if (ixgbe_read_eerd_generic(hw, i, &pointer) != IXGBE_SUCCESS) {
503 501 DEBUGOUT("EEPROM read failed\n");
504 502 break;
505 503 }
506 504
507 505 /* Skip pointer section if the pointer is invalid. */
508 506 if (pointer == 0xFFFF || pointer == 0 ||
509 507 pointer >= hw->eeprom.word_size)
510 508 continue;
511 509
512 510 if (ixgbe_read_eerd_generic(hw, pointer, &length) !=
513 511 IXGBE_SUCCESS) {
514 512 DEBUGOUT("EEPROM read failed\n");
515 513 break;
516 514 }
517 515
518 516 /* Skip pointer section if length is invalid. */
519 517 if (length == 0xFFFF || length == 0 ||
520 518 (pointer + length) >= hw->eeprom.word_size)
521 519 continue;
522 520
523 521 for (j = pointer+1; j <= pointer+length; j++) {
524 522 if (ixgbe_read_eerd_generic(hw, j, &word) !=
525 523 IXGBE_SUCCESS) {
526 524 DEBUGOUT("EEPROM read failed\n");
527 525 break;
528 526 }
529 527 checksum += word;
530 528 }
531 529 }
532 530
533 531 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
534 532
535 533 return checksum;
536 534 }
537 535
538 536 /**
539 537 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
540 538 * @hw: pointer to hardware structure
541 539 * @checksum_val: calculated checksum
542 540 *
543 541 * Performs checksum calculation and validates the EEPROM checksum. If the
544 542 * caller does not need checksum_val, the value can be NULL.
545 543 **/
546 544 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
547 545 u16 *checksum_val)
548 546 {
549 547 s32 status;
550 548 u16 checksum;
551 549 u16 read_checksum = 0;
552 550
553 551 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
554 552
555 553 /*
556 554 * Read the first word from the EEPROM. If this times out or fails, do
557 555 * not continue or we could be in for a very long wait while every
558 556 * EEPROM read fails
559 557 */
560 558 status = hw->eeprom.ops.read(hw, 0, &checksum);
561 559
562 560 if (status != IXGBE_SUCCESS) {
563 561 DEBUGOUT("EEPROM read failed\n");
564 562 goto out;
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565 563 }
566 564
567 565 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
568 566 IXGBE_SUCCESS) {
569 567 checksum = hw->eeprom.ops.calc_checksum(hw);
570 568
571 569 /*
572 570 * Do not use hw->eeprom.ops.read because we do not want to take
573 571 * the synchronization semaphores twice here.
574 572 */
575 - ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
573 + status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
576 574 &read_checksum);
577 575
578 - /*
579 - * Verify read checksum from EEPROM is the same as
580 - * calculated checksum
581 - */
582 - if (read_checksum != checksum)
583 - status = IXGBE_ERR_EEPROM_CHECKSUM;
576 + if (status == IXGBE_SUCCESS) {
577 + /*
578 + * Verify read checksum from EEPROM is the same as
579 + * calculated checksum
580 + */
581 + if (read_checksum != checksum)
582 + status = IXGBE_ERR_EEPROM_CHECKSUM;
584 583
585 - /* If the user cares, return the calculated checksum */
586 - if (checksum_val)
587 - *checksum_val = checksum;
584 + /* If the user cares, return the calculated checksum */
585 + if (checksum_val)
586 + *checksum_val = checksum;
587 + }
588 588 } else {
589 589 status = IXGBE_ERR_SWFW_SYNC;
590 590 }
591 591
592 592 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
593 593 out:
594 594 return status;
595 595 }
596 596
597 597 /**
598 598 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
599 599 * @hw: pointer to hardware structure
600 600 *
601 601 * After writing EEPROM to shadow RAM using EEWR register, software calculates
602 602 * checksum and updates the EEPROM and instructs the hardware to update
603 603 * the flash.
604 604 **/
605 605 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
606 606 {
607 607 s32 status;
608 608 u16 checksum;
609 609
610 610 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
611 611
612 612 /*
613 613 * Read the first word from the EEPROM. If this times out or fails, do
614 614 * not continue or we could be in for a very long wait while every
615 615 * EEPROM read fails
616 616 */
617 617 status = hw->eeprom.ops.read(hw, 0, &checksum);
618 618
619 619 if (status != IXGBE_SUCCESS)
620 620 DEBUGOUT("EEPROM read failed\n");
621 621
622 622 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
623 623 IXGBE_SUCCESS) {
624 624 checksum = hw->eeprom.ops.calc_checksum(hw);
625 625
626 626 /*
627 627 * Do not use hw->eeprom.ops.write because we do not want to
628 628 * take the synchronization semaphores twice here.
629 629 */
630 630 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
631 631 checksum);
632 632
633 633 if (status == IXGBE_SUCCESS)
634 634 status = ixgbe_update_flash_X540(hw);
635 635 else
636 636 status = IXGBE_ERR_SWFW_SYNC;
637 637 }
638 638
639 639 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
640 640
641 641 return status;
642 642 }
643 643
644 644 /**
645 645 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
646 646 * @hw: pointer to hardware structure
647 647 *
648 648 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
649 649 * EEPROM from shadow RAM to the flash device.
650 650 **/
651 651 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
652 652 {
653 653 u32 flup;
654 654 s32 status = IXGBE_ERR_EEPROM;
655 655
656 656 DEBUGFUNC("ixgbe_update_flash_X540");
657 657
658 658 status = ixgbe_poll_flash_update_done_X540(hw);
659 659 if (status == IXGBE_ERR_EEPROM) {
660 660 DEBUGOUT("Flash update time out\n");
661 661 goto out;
662 662 }
663 663
664 664 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
665 665 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
666 666
667 667 status = ixgbe_poll_flash_update_done_X540(hw);
668 668 if (status == IXGBE_SUCCESS)
669 669 DEBUGOUT("Flash update complete\n");
670 670 else
671 671 DEBUGOUT("Flash update time out\n");
672 672
673 673 if (hw->revision_id == 0) {
674 674 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
675 675
676 676 if (flup & IXGBE_EEC_SEC1VAL) {
677 677 flup |= IXGBE_EEC_FLUP;
678 678 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
679 679 }
680 680
681 681 status = ixgbe_poll_flash_update_done_X540(hw);
682 682 if (status == IXGBE_SUCCESS)
683 683 DEBUGOUT("Flash update complete\n");
684 684 else
685 685 DEBUGOUT("Flash update time out\n");
686 686 }
687 687 out:
688 688 return status;
689 689 }
690 690
691 691 /**
692 692 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
693 693 * @hw: pointer to hardware structure
694 694 *
695 695 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
696 696 * flash update is done.
697 697 **/
698 698 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
699 699 {
700 700 u32 i;
701 701 u32 reg;
702 702 s32 status = IXGBE_ERR_EEPROM;
703 703
704 704 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
705 705
706 706 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
707 707 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
708 708 if (reg & IXGBE_EEC_FLUDONE) {
709 709 status = IXGBE_SUCCESS;
710 710 break;
711 711 }
712 712 usec_delay(5);
713 713 }
714 714 return status;
715 715 }
716 716
717 717 /**
718 718 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
719 719 * @hw: pointer to hardware structure
720 720 * @mask: Mask to specify which semaphore to acquire
721 721 *
722 722 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
723 723 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
724 724 **/
725 725 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
726 726 {
727 727 u32 swfw_sync;
728 728 u32 swmask = mask;
729 729 u32 fwmask = mask << 5;
730 730 u32 hwmask = 0;
731 731 u32 timeout = 200;
732 732 u32 i;
733 733 s32 ret_val = IXGBE_SUCCESS;
734 734
735 735 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
736 736
737 737 if (swmask == IXGBE_GSSR_EEP_SM)
738 738 hwmask = IXGBE_GSSR_FLASH_SM;
739 739
740 740 /* SW only mask doesn't have FW bit pair */
741 741 if (swmask == IXGBE_GSSR_SW_MNG_SM)
742 742 fwmask = 0;
743 743
744 744 for (i = 0; i < timeout; i++) {
745 745 /*
746 746 * SW NVM semaphore bit is used for access to all
747 747 * SW_FW_SYNC bits (not just NVM)
748 748 */
749 749 if (ixgbe_get_swfw_sync_semaphore(hw)) {
750 750 ret_val = IXGBE_ERR_SWFW_SYNC;
751 751 goto out;
752 752 }
753 753
754 754 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
755 755 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
756 756 swfw_sync |= swmask;
757 757 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
758 758 ixgbe_release_swfw_sync_semaphore(hw);
759 759 msec_delay(5);
760 760 goto out;
761 761 } else {
762 762 /*
763 763 * Firmware currently using resource (fwmask), hardware
764 764 * currently using resource (hwmask), or other software
765 765 * thread currently using resource (swmask)
766 766 */
767 767 ixgbe_release_swfw_sync_semaphore(hw);
768 768 msec_delay(5);
769 769 }
770 770 }
771 771
772 772 /* Failed to get SW only semaphore */
773 773 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
774 774 ret_val = IXGBE_ERR_SWFW_SYNC;
775 775 goto out;
776 776 }
777 777
778 778 /* If the resource is not released by the FW/HW the SW can assume that
779 779 * the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
780 780 * of the requested resource(s) while ignoring the corresponding FW/HW
781 781 * bits in the SW_FW_SYNC register.
782 782 */
783 783 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
784 784 if (swfw_sync & (fwmask | hwmask)) {
785 785 if (ixgbe_get_swfw_sync_semaphore(hw)) {
786 786 ret_val = IXGBE_ERR_SWFW_SYNC;
787 787 goto out;
788 788 }
789 789
790 790 swfw_sync |= swmask;
791 791 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
792 792 ixgbe_release_swfw_sync_semaphore(hw);
793 793 msec_delay(5);
794 794 }
795 795
796 796 out:
797 797 return ret_val;
798 798 }
799 799
800 800 /**
801 801 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
802 802 * @hw: pointer to hardware structure
803 803 * @mask: Mask to specify which semaphore to release
804 804 *
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805 805 * Releases the SWFW semaphore through the SW_FW_SYNC register
806 806 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
807 807 **/
808 808 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
809 809 {
810 810 u32 swfw_sync;
811 811 u32 swmask = mask;
812 812
813 813 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
814 814
815 - ixgbe_get_swfw_sync_semaphore(hw);
815 + (void) ixgbe_get_swfw_sync_semaphore(hw);
816 816
817 817 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
818 818 swfw_sync &= ~swmask;
819 819 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
820 820
821 821 ixgbe_release_swfw_sync_semaphore(hw);
822 822 msec_delay(5);
823 823 }
824 824
825 825 /**
826 826 * ixgbe_get_nvm_semaphore - Get hardware semaphore
827 827 * @hw: pointer to hardware structure
828 828 *
829 829 * Sets the hardware semaphores so SW/FW can gain control of shared resources
830 830 **/
831 831 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
832 832 {
833 833 s32 status = IXGBE_ERR_EEPROM;
834 834 u32 timeout = 2000;
835 835 u32 i;
836 836 u32 swsm;
837 837
838 838 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
839 839
840 840 /* Get SMBI software semaphore between device drivers first */
841 841 for (i = 0; i < timeout; i++) {
842 842 /*
843 843 * If the SMBI bit is 0 when we read it, then the bit will be
844 844 * set and we have the semaphore
845 845 */
846 846 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
847 847 if (!(swsm & IXGBE_SWSM_SMBI)) {
848 848 status = IXGBE_SUCCESS;
849 849 break;
850 850 }
851 851 usec_delay(50);
852 852 }
853 853
854 854 /* Now get the semaphore between SW/FW through the REGSMP bit */
855 855 if (status == IXGBE_SUCCESS) {
856 856 for (i = 0; i < timeout; i++) {
857 857 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
858 858 if (!(swsm & IXGBE_SWFW_REGSMP))
859 859 break;
860 860
861 861 usec_delay(50);
862 862 }
863 863
864 864 /*
865 865 * Release semaphores and return error if SW NVM semaphore
866 866 * was not granted because we don't have access to the EEPROM
867 867 */
868 868 if (i >= timeout) {
869 869 DEBUGOUT("REGSMP Software NVM semaphore not "
870 870 "granted.\n");
871 871 ixgbe_release_swfw_sync_semaphore(hw);
872 872 status = IXGBE_ERR_EEPROM;
873 873 }
874 874 } else {
875 875 DEBUGOUT("Software semaphore SMBI between device drivers "
876 876 "not granted.\n");
877 877 }
878 878
879 879 return status;
880 880 }
881 881
882 882 /**
883 883 * ixgbe_release_nvm_semaphore - Release hardware semaphore
884 884 * @hw: pointer to hardware structure
885 885 *
886 886 * This function clears hardware semaphore bits.
887 887 **/
888 888 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
889 889 {
890 890 u32 swsm;
891 891
892 892 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
893 893
894 894 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
895 895
896 896 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
897 897 swsm &= ~IXGBE_SWSM_SMBI;
898 898 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
899 899
900 900 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
901 901 swsm &= ~IXGBE_SWFW_REGSMP;
902 902 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
903 903
904 904 IXGBE_WRITE_FLUSH(hw);
905 905 }
906 906
907 907 /**
908 908 * ixgbe_blink_led_start_X540 - Blink LED based on index.
909 909 * @hw: pointer to hardware structure
910 910 * @index: led number to blink
911 911 *
912 912 * Devices that implement the version 2 interface:
913 913 * X540
914 914 **/
915 915 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
916 916 {
917 917 u32 macc_reg;
918 918 u32 ledctl_reg;
919 919 ixgbe_link_speed speed;
920 920 bool link_up;
921 921
922 922 DEBUGFUNC("ixgbe_blink_led_start_X540");
923 923
924 924 /*
925 925 * Link should be up in order for the blink bit in the LED control
926 926 * register to work. Force link and speed in the MAC if link is down.
927 927 * This will be reversed when we stop the blinking.
928 928 */
929 929 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
930 930 if (link_up == FALSE) {
931 931 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
932 932 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
933 933 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
934 934 }
935 935 /* Set the LED to LINK_UP + BLINK. */
936 936 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
937 937 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
938 938 ledctl_reg |= IXGBE_LED_BLINK(index);
939 939 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
940 940 IXGBE_WRITE_FLUSH(hw);
941 941
942 942 return IXGBE_SUCCESS;
943 943 }
944 944
945 945 /**
946 946 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
947 947 * @hw: pointer to hardware structure
948 948 * @index: led number to stop blinking
949 949 *
950 950 * Devices that implement the version 2 interface:
951 951 * X540
952 952 **/
953 953 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
954 954 {
955 955 u32 macc_reg;
956 956 u32 ledctl_reg;
957 957
958 958 DEBUGFUNC("ixgbe_blink_led_stop_X540");
959 959
960 960 /* Restore the LED to its default value. */
961 961 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
962 962 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
963 963 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
964 964 ledctl_reg &= ~IXGBE_LED_BLINK(index);
965 965 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
966 966
967 967 /* Unforce link and speed in the MAC. */
968 968 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
969 969 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
970 970 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
971 971 IXGBE_WRITE_FLUSH(hw);
972 972
973 973 return IXGBE_SUCCESS;
974 974 }
975 975
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