139 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
140
141 /* Manageability interface */
142 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
143
144 return ret_val;
145 }
146
147 /**
148 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
149 * @hw: pointer to hardware structure
150 * @speed: pointer to link speed
151 * @autoneg: TRUE when autoneg or autotry is enabled
152 *
153 * Determines the link capabilities by reading the AUTOC register.
154 **/
155 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
156 ixgbe_link_speed *speed,
157 bool *autoneg)
158 {
159 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
160
161 return IXGBE_SUCCESS;
162 }
163
164 /**
165 * ixgbe_get_media_type_X540 - Get media type
166 * @hw: pointer to hardware structure
167 *
168 * Returns the media type (fiber, copper, backplane)
169 **/
170 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
171 {
172 UNREFERENCED_1PARAMETER(hw);
173 return ixgbe_media_type_copper;
174 }
175
176 /**
177 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
178 * @hw: pointer to hardware structure
179 * @speed: new link speed
180 * @autoneg: TRUE if autonegotiation enabled
181 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
555 /*
556 * Read the first word from the EEPROM. If this times out or fails, do
557 * not continue or we could be in for a very long wait while every
558 * EEPROM read fails
559 */
560 status = hw->eeprom.ops.read(hw, 0, &checksum);
561
562 if (status != IXGBE_SUCCESS) {
563 DEBUGOUT("EEPROM read failed\n");
564 goto out;
565 }
566
567 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
568 IXGBE_SUCCESS) {
569 checksum = hw->eeprom.ops.calc_checksum(hw);
570
571 /*
572 * Do not use hw->eeprom.ops.read because we do not want to take
573 * the synchronization semaphores twice here.
574 */
575 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
576 &read_checksum);
577
578 /*
579 * Verify read checksum from EEPROM is the same as
580 * calculated checksum
581 */
582 if (read_checksum != checksum)
583 status = IXGBE_ERR_EEPROM_CHECKSUM;
584
585 /* If the user cares, return the calculated checksum */
586 if (checksum_val)
587 *checksum_val = checksum;
588 } else {
589 status = IXGBE_ERR_SWFW_SYNC;
590 }
591
592 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
593 out:
594 return status;
595 }
596
597 /**
598 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
599 * @hw: pointer to hardware structure
600 *
601 * After writing EEPROM to shadow RAM using EEWR register, software calculates
602 * checksum and updates the EEPROM and instructs the hardware to update
603 * the flash.
604 **/
605 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
606 {
607 s32 status;
795
796 out:
797 return ret_val;
798 }
799
800 /**
801 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
802 * @hw: pointer to hardware structure
803 * @mask: Mask to specify which semaphore to release
804 *
805 * Releases the SWFW semaphore through the SW_FW_SYNC register
806 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
807 **/
808 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
809 {
810 u32 swfw_sync;
811 u32 swmask = mask;
812
813 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
814
815 ixgbe_get_swfw_sync_semaphore(hw);
816
817 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
818 swfw_sync &= ~swmask;
819 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
820
821 ixgbe_release_swfw_sync_semaphore(hw);
822 msec_delay(5);
823 }
824
825 /**
826 * ixgbe_get_nvm_semaphore - Get hardware semaphore
827 * @hw: pointer to hardware structure
828 *
829 * Sets the hardware semaphores so SW/FW can gain control of shared resources
830 **/
831 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
832 {
833 s32 status = IXGBE_ERR_EEPROM;
834 u32 timeout = 2000;
835 u32 i;
|
139 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
140
141 /* Manageability interface */
142 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
143
144 return ret_val;
145 }
146
147 /**
148 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
149 * @hw: pointer to hardware structure
150 * @speed: pointer to link speed
151 * @autoneg: TRUE when autoneg or autotry is enabled
152 *
153 * Determines the link capabilities by reading the AUTOC register.
154 **/
155 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
156 ixgbe_link_speed *speed,
157 bool *autoneg)
158 {
159 return ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
160 }
161
162 /**
163 * ixgbe_get_media_type_X540 - Get media type
164 * @hw: pointer to hardware structure
165 *
166 * Returns the media type (fiber, copper, backplane)
167 **/
168 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
169 {
170 UNREFERENCED_1PARAMETER(hw);
171 return ixgbe_media_type_copper;
172 }
173
174 /**
175 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
176 * @hw: pointer to hardware structure
177 * @speed: new link speed
178 * @autoneg: TRUE if autonegotiation enabled
179 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
553 /*
554 * Read the first word from the EEPROM. If this times out or fails, do
555 * not continue or we could be in for a very long wait while every
556 * EEPROM read fails
557 */
558 status = hw->eeprom.ops.read(hw, 0, &checksum);
559
560 if (status != IXGBE_SUCCESS) {
561 DEBUGOUT("EEPROM read failed\n");
562 goto out;
563 }
564
565 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
566 IXGBE_SUCCESS) {
567 checksum = hw->eeprom.ops.calc_checksum(hw);
568
569 /*
570 * Do not use hw->eeprom.ops.read because we do not want to take
571 * the synchronization semaphores twice here.
572 */
573 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
574 &read_checksum);
575
576 if (status == IXGBE_SUCCESS) {
577 /*
578 * Verify read checksum from EEPROM is the same as
579 * calculated checksum
580 */
581 if (read_checksum != checksum)
582 status = IXGBE_ERR_EEPROM_CHECKSUM;
583
584 /* If the user cares, return the calculated checksum */
585 if (checksum_val)
586 *checksum_val = checksum;
587 }
588 } else {
589 status = IXGBE_ERR_SWFW_SYNC;
590 }
591
592 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
593 out:
594 return status;
595 }
596
597 /**
598 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
599 * @hw: pointer to hardware structure
600 *
601 * After writing EEPROM to shadow RAM using EEWR register, software calculates
602 * checksum and updates the EEPROM and instructs the hardware to update
603 * the flash.
604 **/
605 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
606 {
607 s32 status;
795
796 out:
797 return ret_val;
798 }
799
800 /**
801 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
802 * @hw: pointer to hardware structure
803 * @mask: Mask to specify which semaphore to release
804 *
805 * Releases the SWFW semaphore through the SW_FW_SYNC register
806 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
807 **/
808 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
809 {
810 u32 swfw_sync;
811 u32 swmask = mask;
812
813 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
814
815 (void) ixgbe_get_swfw_sync_semaphore(hw);
816
817 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
818 swfw_sync &= ~swmask;
819 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
820
821 ixgbe_release_swfw_sync_semaphore(hw);
822 msec_delay(5);
823 }
824
825 /**
826 * ixgbe_get_nvm_semaphore - Get hardware semaphore
827 * @hw: pointer to hardware structure
828 *
829 * Sets the hardware semaphores so SW/FW can gain control of shared resources
830 **/
831 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
832 {
833 s32 status = IXGBE_ERR_EEPROM;
834 u32 timeout = 2000;
835 u32 i;
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