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3014 Intel X540 Support (fix lint)
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--- old/usr/src/uts/common/io/ixgbe/ixgbe_phy.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_phy.c
1 1 /******************************************************************************
2 2
3 3 Copyright (c) 2001-2012, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34 34
35 35 #include "ixgbe_api.h"
36 36 #include "ixgbe_common.h"
37 37 #include "ixgbe_phy.h"
38 38
39 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
50 50
51 51 /**
52 52 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
53 53 * @hw: pointer to the hardware structure
54 54 *
55 55 * Initialize the function pointers.
56 56 **/
57 57 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
58 58 {
59 59 struct ixgbe_phy_info *phy = &hw->phy;
60 60
61 61 DEBUGFUNC("ixgbe_init_phy_ops_generic");
62 62
63 63 /* PHY */
64 64 phy->ops.identify = &ixgbe_identify_phy_generic;
65 65 phy->ops.reset = &ixgbe_reset_phy_generic;
66 66 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
67 67 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
68 68 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
69 69 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
70 70 phy->ops.check_link = NULL;
71 71 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
72 72 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
73 73 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
74 74 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
75 75 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
76 76 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
77 77 phy->ops.identify_sfp = &ixgbe_identify_module_generic;
78 78 phy->sfp_type = ixgbe_sfp_type_unknown;
79 79 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
80 80 return IXGBE_SUCCESS;
81 81 }
82 82
83 83 /**
84 84 * ixgbe_identify_phy_generic - Get physical layer module
85 85 * @hw: pointer to hardware structure
86 86 *
87 87 * Determines the physical layer module found on the current adapter.
88 88 **/
89 89 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
90 90 {
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91 91 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
92 92 u32 phy_addr;
93 93 u16 ext_ability = 0;
94 94
95 95 DEBUGFUNC("ixgbe_identify_phy_generic");
96 96
97 97 if (hw->phy.type == ixgbe_phy_unknown) {
98 98 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
99 99 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
100 100 hw->phy.addr = phy_addr;
101 - ixgbe_get_phy_id(hw);
101 + (void) ixgbe_get_phy_id(hw);
102 102 hw->phy.type =
103 103 ixgbe_get_phy_type_from_id(hw->phy.id);
104 104
105 105 if (hw->phy.type == ixgbe_phy_unknown) {
106 106 hw->phy.ops.read_reg(hw,
107 107 IXGBE_MDIO_PHY_EXT_ABILITY,
108 108 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
109 109 &ext_ability);
110 110 if (ext_ability &
111 111 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
112 112 IXGBE_MDIO_PHY_1000BASET_ABILITY))
113 113 hw->phy.type =
114 114 ixgbe_phy_cu_unknown;
115 115 else
116 116 hw->phy.type =
117 117 ixgbe_phy_generic;
118 118 }
119 119
120 120 status = IXGBE_SUCCESS;
121 121 break;
122 122 }
123 123 }
124 124 /* clear value if nothing found */
125 125 if (status != IXGBE_SUCCESS)
126 126 hw->phy.addr = 0;
127 127 } else {
128 128 status = IXGBE_SUCCESS;
129 129 }
130 130
131 131 return status;
132 132 }
133 133
134 134 /**
135 135 * ixgbe_validate_phy_addr - Determines phy address is valid
136 136 * @hw: pointer to hardware structure
137 137 *
138 138 **/
139 139 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
140 140 {
141 141 u16 phy_id = 0;
142 142 bool valid = FALSE;
143 143
144 144 DEBUGFUNC("ixgbe_validate_phy_addr");
145 145
146 146 hw->phy.addr = phy_addr;
147 147 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
148 148 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
149 149
150 150 if (phy_id != 0xFFFF && phy_id != 0x0)
151 151 valid = TRUE;
152 152
153 153 return valid;
154 154 }
155 155
156 156 /**
157 157 * ixgbe_get_phy_id - Get the phy type
158 158 * @hw: pointer to hardware structure
159 159 *
160 160 **/
161 161 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
162 162 {
163 163 u32 status;
164 164 u16 phy_id_high = 0;
165 165 u16 phy_id_low = 0;
166 166
167 167 DEBUGFUNC("ixgbe_get_phy_id");
168 168
169 169 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
170 170 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
171 171 &phy_id_high);
172 172
173 173 if (status == IXGBE_SUCCESS) {
174 174 hw->phy.id = (u32)(phy_id_high << 16);
175 175 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
176 176 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
177 177 &phy_id_low);
178 178 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
179 179 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
180 180 }
181 181 return status;
182 182 }
183 183
184 184 /**
185 185 * ixgbe_get_phy_type_from_id - Get the phy type
186 186 * @hw: pointer to hardware structure
187 187 *
188 188 **/
189 189 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
190 190 {
191 191 enum ixgbe_phy_type phy_type;
192 192
193 193 DEBUGFUNC("ixgbe_get_phy_type_from_id");
194 194
195 195 switch (phy_id) {
196 196 case TN1010_PHY_ID:
197 197 phy_type = ixgbe_phy_tn;
198 198 break;
199 199 case X540_PHY_ID:
200 200 phy_type = ixgbe_phy_aq;
201 201 break;
202 202 case QT2022_PHY_ID:
203 203 phy_type = ixgbe_phy_qt;
204 204 break;
205 205 case ATH_PHY_ID:
206 206 phy_type = ixgbe_phy_nl;
207 207 break;
208 208 default:
209 209 phy_type = ixgbe_phy_unknown;
210 210 break;
211 211 }
212 212
213 213 DEBUGOUT1("phy type found is %d\n", phy_type);
214 214 return phy_type;
215 215 }
216 216
217 217 /**
218 218 * ixgbe_reset_phy_generic - Performs a PHY reset
219 219 * @hw: pointer to hardware structure
220 220 **/
221 221 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
222 222 {
223 223 u32 i;
224 224 u16 ctrl = 0;
225 225 s32 status = IXGBE_SUCCESS;
226 226
227 227 DEBUGFUNC("ixgbe_reset_phy_generic");
228 228
229 229 if (hw->phy.type == ixgbe_phy_unknown)
230 230 status = ixgbe_identify_phy_generic(hw);
231 231
232 232 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
233 233 goto out;
234 234
235 235 /* Don't reset PHY if it's shut down due to overtemp. */
236 236 if (!hw->phy.reset_if_overtemp &&
237 237 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
238 238 goto out;
239 239
240 240 /*
241 241 * Perform soft PHY reset to the PHY_XS.
242 242 * This will cause a soft reset to the PHY
243 243 */
244 244 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
245 245 IXGBE_MDIO_PHY_XS_DEV_TYPE,
246 246 IXGBE_MDIO_PHY_XS_RESET);
247 247
248 248 /*
249 249 * Poll for reset bit to self-clear indicating reset is complete.
250 250 * Some PHYs could take up to 3 seconds to complete and need about
251 251 * 1.7 usec delay after the reset is complete.
252 252 */
253 253 for (i = 0; i < 30; i++) {
254 254 msec_delay(100);
255 255 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
256 256 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
257 257 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
258 258 usec_delay(2);
259 259 break;
260 260 }
261 261 }
262 262
263 263 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
264 264 status = IXGBE_ERR_RESET_FAILED;
265 265 DEBUGOUT("PHY reset polling failed to complete.\n");
266 266 }
267 267
268 268 out:
269 269 return status;
270 270 }
271 271
272 272 /**
273 273 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
274 274 * @hw: pointer to hardware structure
275 275 * @reg_addr: 32 bit address of PHY register to read
276 276 * @phy_data: Pointer to read data from PHY register
277 277 **/
278 278 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
279 279 u32 device_type, u16 *phy_data)
280 280 {
281 281 u32 command;
282 282 u32 i;
283 283 u32 data;
284 284 s32 status = IXGBE_SUCCESS;
285 285 u16 gssr;
286 286
287 287 DEBUGFUNC("ixgbe_read_phy_reg_generic");
288 288
289 289 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
290 290 gssr = IXGBE_GSSR_PHY1_SM;
291 291 else
292 292 gssr = IXGBE_GSSR_PHY0_SM;
293 293
294 294 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
295 295 status = IXGBE_ERR_SWFW_SYNC;
296 296
297 297 if (status == IXGBE_SUCCESS) {
298 298 /* Setup and write the address cycle command */
299 299 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
300 300 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
301 301 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
302 302 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
303 303
304 304 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
305 305
306 306 /*
307 307 * Check every 10 usec to see if the address cycle completed.
308 308 * The MDI Command bit will clear when the operation is
309 309 * complete
310 310 */
311 311 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
312 312 usec_delay(10);
313 313
314 314 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
315 315
316 316 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
317 317 break;
318 318 }
319 319
320 320 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
321 321 DEBUGOUT("PHY address command did not complete.\n");
322 322 status = IXGBE_ERR_PHY;
323 323 }
324 324
325 325 if (status == IXGBE_SUCCESS) {
326 326 /*
327 327 * Address cycle complete, setup and write the read
328 328 * command
329 329 */
330 330 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
331 331 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
332 332 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
333 333 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
334 334
335 335 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
336 336
337 337 /*
338 338 * Check every 10 usec to see if the address cycle
339 339 * completed. The MDI Command bit will clear when the
340 340 * operation is complete
341 341 */
342 342 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
343 343 usec_delay(10);
344 344
345 345 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
346 346
347 347 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
348 348 break;
349 349 }
350 350
351 351 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
352 352 DEBUGOUT("PHY read command didn't complete\n");
353 353 status = IXGBE_ERR_PHY;
354 354 } else {
355 355 /*
356 356 * Read operation is complete. Get the data
357 357 * from MSRWD
358 358 */
359 359 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
360 360 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
361 361 *phy_data = (u16)(data);
362 362 }
363 363 }
364 364
365 365 hw->mac.ops.release_swfw_sync(hw, gssr);
366 366 }
367 367
368 368 return status;
369 369 }
370 370
371 371 /**
372 372 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
373 373 * @hw: pointer to hardware structure
374 374 * @reg_addr: 32 bit PHY register to write
375 375 * @device_type: 5 bit device type
376 376 * @phy_data: Data to write to the PHY register
377 377 **/
378 378 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
379 379 u32 device_type, u16 phy_data)
380 380 {
381 381 u32 command;
382 382 u32 i;
383 383 s32 status = IXGBE_SUCCESS;
384 384 u16 gssr;
385 385
386 386 DEBUGFUNC("ixgbe_write_phy_reg_generic");
387 387
388 388 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
389 389 gssr = IXGBE_GSSR_PHY1_SM;
390 390 else
391 391 gssr = IXGBE_GSSR_PHY0_SM;
392 392
393 393 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
394 394 status = IXGBE_ERR_SWFW_SYNC;
395 395
396 396 if (status == IXGBE_SUCCESS) {
397 397 /* Put the data in the MDI single read and write data register*/
398 398 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
399 399
400 400 /* Setup and write the address cycle command */
401 401 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
402 402 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
403 403 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
404 404 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
405 405
406 406 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
407 407
408 408 /*
409 409 * Check every 10 usec to see if the address cycle completed.
410 410 * The MDI Command bit will clear when the operation is
411 411 * complete
412 412 */
413 413 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
414 414 usec_delay(10);
415 415
416 416 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
417 417
418 418 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
419 419 break;
420 420 }
421 421
422 422 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
423 423 DEBUGOUT("PHY address cmd didn't complete\n");
424 424 status = IXGBE_ERR_PHY;
425 425 }
426 426
427 427 if (status == IXGBE_SUCCESS) {
428 428 /*
429 429 * Address cycle complete, setup and write the write
430 430 * command
431 431 */
432 432 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
433 433 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
434 434 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
435 435 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
436 436
437 437 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
438 438
439 439 /*
440 440 * Check every 10 usec to see if the address cycle
441 441 * completed. The MDI Command bit will clear when the
442 442 * operation is complete
443 443 */
444 444 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
445 445 usec_delay(10);
446 446
447 447 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
448 448
449 449 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
450 450 break;
451 451 }
452 452
453 453 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
454 454 DEBUGOUT("PHY address cmd didn't complete\n");
455 455 status = IXGBE_ERR_PHY;
456 456 }
457 457 }
458 458
459 459 hw->mac.ops.release_swfw_sync(hw, gssr);
460 460 }
461 461
462 462 return status;
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463 463 }
464 464
465 465 /**
466 466 * ixgbe_setup_phy_link_generic - Set and restart autoneg
467 467 * @hw: pointer to hardware structure
468 468 *
469 469 * Restart autonegotiation and PHY and waits for completion.
470 470 **/
471 471 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
472 472 {
473 - s32 status = IXGBE_SUCCESS;
473 + s32 status;
474 474 u32 time_out;
475 475 u32 max_time_out = 10;
476 476 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
477 477 bool autoneg = FALSE;
478 478 ixgbe_link_speed speed;
479 479
480 480 DEBUGFUNC("ixgbe_setup_phy_link_generic");
481 481
482 - ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
482 + status =
483 + ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
484 + if (status != IXGBE_SUCCESS)
485 + return status;
483 486
484 487 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
485 488 /* Set or unset auto-negotiation 10G advertisement */
486 489 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
487 490 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
488 491 &autoneg_reg);
489 492
490 493 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
491 494 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
492 495 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
493 496
494 497 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
495 498 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
496 499 autoneg_reg);
497 500 }
498 501
499 502 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
500 503 /* Set or unset auto-negotiation 1G advertisement */
501 504 hw->phy.ops.read_reg(hw,
502 505 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
503 506 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
504 507 &autoneg_reg);
505 508
506 509 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
507 510 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
508 511 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
509 512
510 513 hw->phy.ops.write_reg(hw,
511 514 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
512 515 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
513 516 autoneg_reg);
514 517 }
515 518
516 519 if (speed & IXGBE_LINK_SPEED_100_FULL) {
517 520 /* Set or unset auto-negotiation 100M advertisement */
518 521 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
519 522 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
520 523 &autoneg_reg);
521 524
522 525 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
523 526 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
524 527 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
525 528 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
526 529
527 530 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
528 531 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
529 532 autoneg_reg);
530 533 }
531 534
532 535 /* Restart PHY autonegotiation and wait for completion */
533 536 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
534 537 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
535 538
536 539 autoneg_reg |= IXGBE_MII_RESTART;
537 540
538 541 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
539 542 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
540 543
541 544 /* Wait for autonegotiation to finish */
542 545 for (time_out = 0; time_out < max_time_out; time_out++) {
543 546 usec_delay(10);
544 547 /* Restart PHY autonegotiation and wait for completion */
545 548 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
546 549 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
547 550 &autoneg_reg);
548 551
549 552 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
550 553 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
551 554 break;
552 555 }
553 556
554 557 if (time_out == max_time_out) {
555 558 status = IXGBE_ERR_LINK_SETUP;
556 559 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
557 560 }
558 561
559 562 return status;
560 563 }
561 564
562 565 /**
563 566 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
564 567 * @hw: pointer to hardware structure
565 568 * @speed: new link speed
566 569 * @autoneg: TRUE if autonegotiation enabled
567 570 **/
568 571 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
569 572 ixgbe_link_speed speed,
570 573 bool autoneg,
571 574 bool autoneg_wait_to_complete)
572 575 {
573 576 UNREFERENCED_2PARAMETER(autoneg, autoneg_wait_to_complete);
574 577
575 578 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
576 579
577 580 /*
578 581 * Clear autoneg_advertised and set new values based on input link
579 582 * speed.
580 583 */
581 584 hw->phy.autoneg_advertised = 0;
582 585
583 586 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
584 587 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
585 588
586 589 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
587 590 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
588 591
589 592 if (speed & IXGBE_LINK_SPEED_100_FULL)
590 593 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
591 594
592 595 /* Setup link based on the new speed settings */
593 596 hw->phy.ops.setup_link(hw);
594 597
595 598 return IXGBE_SUCCESS;
596 599 }
597 600
598 601 /**
599 602 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
600 603 * @hw: pointer to hardware structure
601 604 * @speed: pointer to link speed
602 605 * @autoneg: boolean auto-negotiation value
603 606 *
604 607 * Determines the link capabilities by reading the AUTOC register.
605 608 **/
606 609 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
607 610 ixgbe_link_speed *speed,
608 611 bool *autoneg)
609 612 {
610 613 s32 status = IXGBE_ERR_LINK_SETUP;
611 614 u16 speed_ability;
612 615
613 616 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
614 617
615 618 *speed = 0;
616 619 *autoneg = TRUE;
617 620
618 621 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
619 622 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
620 623 &speed_ability);
621 624
622 625 if (status == IXGBE_SUCCESS) {
623 626 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
624 627 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
625 628 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
626 629 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
627 630 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
628 631 *speed |= IXGBE_LINK_SPEED_100_FULL;
629 632 }
630 633
631 634 return status;
632 635 }
633 636
634 637 /**
635 638 * ixgbe_check_phy_link_tnx - Determine link and speed status
636 639 * @hw: pointer to hardware structure
637 640 *
638 641 * Reads the VS1 register to determine if link is up and the current speed for
639 642 * the PHY.
640 643 **/
641 644 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
642 645 bool *link_up)
643 646 {
644 647 s32 status = IXGBE_SUCCESS;
645 648 u32 time_out;
646 649 u32 max_time_out = 10;
647 650 u16 phy_link = 0;
648 651 u16 phy_speed = 0;
649 652 u16 phy_data = 0;
650 653
651 654 DEBUGFUNC("ixgbe_check_phy_link_tnx");
652 655
653 656 /* Initialize speed and link to default case */
654 657 *link_up = FALSE;
655 658 *speed = IXGBE_LINK_SPEED_10GB_FULL;
656 659
657 660 /*
658 661 * Check current speed and link status of the PHY register.
659 662 * This is a vendor specific register and may have to
660 663 * be changed for other copper PHYs.
661 664 */
662 665 for (time_out = 0; time_out < max_time_out; time_out++) {
663 666 usec_delay(10);
664 667 status = hw->phy.ops.read_reg(hw,
665 668 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
666 669 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
667 670 &phy_data);
668 671 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
669 672 phy_speed = phy_data &
670 673 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
671 674 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
672 675 *link_up = TRUE;
673 676 if (phy_speed ==
674 677 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
675 678 *speed = IXGBE_LINK_SPEED_1GB_FULL;
676 679 break;
677 680 }
678 681 }
679 682
680 683 return status;
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681 684 }
682 685
683 686 /**
684 687 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
685 688 * @hw: pointer to hardware structure
686 689 *
687 690 * Restart autonegotiation and PHY and waits for completion.
688 691 **/
689 692 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
690 693 {
691 - s32 status = IXGBE_SUCCESS;
694 + s32 status;
692 695 u32 time_out;
693 696 u32 max_time_out = 10;
694 697 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
695 698 bool autoneg = FALSE;
696 699 ixgbe_link_speed speed;
697 700
698 701 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
699 702
700 - ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
703 + status =
704 + ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
705 + if (status != IXGBE_SUCCESS)
706 + return status;
701 707
702 708 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
703 709 /* Set or unset auto-negotiation 10G advertisement */
704 710 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
705 711 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
706 712 &autoneg_reg);
707 713
708 714 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
709 715 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
710 716 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
711 717
712 718 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
713 719 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
714 720 autoneg_reg);
715 721 }
716 722
717 723 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
718 724 /* Set or unset auto-negotiation 1G advertisement */
719 725 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
720 726 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
721 727 &autoneg_reg);
722 728
723 729 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
724 730 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
725 731 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
726 732
727 733 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
728 734 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
729 735 autoneg_reg);
730 736 }
731 737
732 738 if (speed & IXGBE_LINK_SPEED_100_FULL) {
733 739 /* Set or unset auto-negotiation 100M advertisement */
734 740 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
735 741 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
736 742 &autoneg_reg);
737 743
738 744 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
739 745 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
740 746 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
741 747
742 748 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
743 749 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
744 750 autoneg_reg);
745 751 }
746 752
747 753 /* Restart PHY autonegotiation and wait for completion */
748 754 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
749 755 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
750 756
751 757 autoneg_reg |= IXGBE_MII_RESTART;
752 758
753 759 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
754 760 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
755 761
756 762 /* Wait for autonegotiation to finish */
757 763 for (time_out = 0; time_out < max_time_out; time_out++) {
758 764 usec_delay(10);
759 765 /* Restart PHY autonegotiation and wait for completion */
760 766 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
761 767 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
762 768 &autoneg_reg);
763 769
764 770 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
765 771 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
766 772 break;
767 773 }
768 774
769 775 if (time_out == max_time_out) {
770 776 status = IXGBE_ERR_LINK_SETUP;
771 777 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
772 778 }
773 779
774 780 return status;
775 781 }
776 782
777 783 /**
778 784 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
779 785 * @hw: pointer to hardware structure
780 786 * @firmware_version: pointer to the PHY Firmware Version
781 787 **/
782 788 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
783 789 u16 *firmware_version)
784 790 {
785 791 s32 status = IXGBE_SUCCESS;
786 792
787 793 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
788 794
789 795 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
790 796 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
791 797 firmware_version);
792 798
793 799 return status;
794 800 }
795 801
796 802 /**
797 803 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
798 804 * @hw: pointer to hardware structure
799 805 * @firmware_version: pointer to the PHY Firmware Version
800 806 **/
801 807 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
802 808 u16 *firmware_version)
803 809 {
804 810 s32 status = IXGBE_SUCCESS;
805 811
806 812 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
807 813
808 814 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
809 815 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
810 816 firmware_version);
811 817
812 818 return status;
813 819 }
814 820
815 821 /**
816 822 * ixgbe_reset_phy_nl - Performs a PHY reset
817 823 * @hw: pointer to hardware structure
818 824 **/
819 825 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
820 826 {
821 827 u16 phy_offset, control, eword, edata, block_crc;
822 828 bool end_data = FALSE;
823 829 u16 list_offset, data_offset;
824 830 u16 phy_data = 0;
825 831 s32 ret_val = IXGBE_SUCCESS;
826 832 u32 i;
827 833
828 834 DEBUGFUNC("ixgbe_reset_phy_nl");
829 835
830 836 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
831 837 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
832 838
833 839 /* reset the PHY and poll for completion */
834 840 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
835 841 IXGBE_MDIO_PHY_XS_DEV_TYPE,
836 842 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
837 843
838 844 for (i = 0; i < 100; i++) {
839 845 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
840 846 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
841 847 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
842 848 break;
843 849 msec_delay(10);
844 850 }
845 851
846 852 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
847 853 DEBUGOUT("PHY reset did not complete.\n");
848 854 ret_val = IXGBE_ERR_PHY;
849 855 goto out;
850 856 }
851 857
852 858 /* Get init offsets */
853 859 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
854 860 &data_offset);
855 861 if (ret_val != IXGBE_SUCCESS)
856 862 goto out;
857 863
858 864 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
859 865 data_offset++;
860 866 while (!end_data) {
861 867 /*
862 868 * Read control word from PHY init contents offset
863 869 */
864 870 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
865 871 control = (eword & IXGBE_CONTROL_MASK_NL) >>
866 872 IXGBE_CONTROL_SHIFT_NL;
867 873 edata = eword & IXGBE_DATA_MASK_NL;
868 874 switch (control) {
869 875 case IXGBE_DELAY_NL:
870 876 data_offset++;
871 877 DEBUGOUT1("DELAY: %d MS\n", edata);
872 878 msec_delay(edata);
873 879 break;
874 880 case IXGBE_DATA_NL:
875 881 DEBUGOUT("DATA:\n");
876 882 data_offset++;
877 883 hw->eeprom.ops.read(hw, data_offset++,
878 884 &phy_offset);
879 885 for (i = 0; i < edata; i++) {
880 886 hw->eeprom.ops.read(hw, data_offset, &eword);
881 887 hw->phy.ops.write_reg(hw, phy_offset,
882 888 IXGBE_TWINAX_DEV, eword);
883 889 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
884 890 phy_offset);
885 891 data_offset++;
886 892 phy_offset++;
887 893 }
888 894 break;
889 895 case IXGBE_CONTROL_NL:
890 896 data_offset++;
891 897 DEBUGOUT("CONTROL:\n");
892 898 if (edata == IXGBE_CONTROL_EOL_NL) {
893 899 DEBUGOUT("EOL\n");
894 900 end_data = TRUE;
895 901 } else if (edata == IXGBE_CONTROL_SOL_NL) {
896 902 DEBUGOUT("SOL\n");
897 903 } else {
898 904 DEBUGOUT("Bad control value\n");
899 905 ret_val = IXGBE_ERR_PHY;
900 906 goto out;
901 907 }
902 908 break;
903 909 default:
904 910 DEBUGOUT("Bad control type\n");
905 911 ret_val = IXGBE_ERR_PHY;
906 912 goto out;
907 913 }
908 914 }
909 915
910 916 out:
911 917 return ret_val;
912 918 }
913 919
914 920 /**
915 921 * ixgbe_identify_module_generic - Identifies module type
916 922 * @hw: pointer to hardware structure
917 923 *
918 924 * Determines HW type and calls appropriate function.
919 925 **/
920 926 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
921 927 {
922 928 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
923 929
924 930 DEBUGFUNC("ixgbe_identify_module_generic");
925 931
926 932 switch (hw->mac.ops.get_media_type(hw)) {
927 933 case ixgbe_media_type_fiber:
928 934 status = ixgbe_identify_sfp_module_generic(hw);
929 935 break;
930 936
931 937
932 938 default:
933 939 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
934 940 status = IXGBE_ERR_SFP_NOT_PRESENT;
935 941 break;
936 942 }
937 943
938 944 return status;
939 945 }
940 946
941 947 /**
942 948 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
943 949 * @hw: pointer to hardware structure
944 950 *
945 951 * Searches for and identifies the SFP module and assigns appropriate PHY type.
946 952 **/
947 953 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
948 954 {
949 955 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
950 956 u32 vendor_oui = 0;
951 957 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
952 958 u8 identifier = 0;
953 959 u8 comp_codes_1g = 0;
954 960 u8 comp_codes_10g = 0;
955 961 u8 oui_bytes[3] = {0, 0, 0};
956 962 u8 cable_tech = 0;
957 963 u8 cable_spec = 0;
958 964 u16 enforce_sfp = 0;
959 965
960 966 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
961 967
962 968 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
963 969 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
964 970 status = IXGBE_ERR_SFP_NOT_PRESENT;
965 971 goto out;
966 972 }
967 973
968 974 status = hw->phy.ops.read_i2c_eeprom(hw,
969 975 IXGBE_SFF_IDENTIFIER,
970 976 &identifier);
971 977
972 978 if (status == IXGBE_ERR_SWFW_SYNC ||
973 979 status == IXGBE_ERR_I2C ||
974 980 status == IXGBE_ERR_SFP_NOT_PRESENT)
975 981 goto err_read_i2c_eeprom;
976 982
977 983 /* LAN ID is needed for sfp_type determination */
978 984 hw->mac.ops.set_lan_id(hw);
979 985
980 986 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
981 987 hw->phy.type = ixgbe_phy_sfp_unsupported;
982 988 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
983 989 } else {
984 990 status = hw->phy.ops.read_i2c_eeprom(hw,
985 991 IXGBE_SFF_1GBE_COMP_CODES,
986 992 &comp_codes_1g);
987 993
988 994 if (status == IXGBE_ERR_SWFW_SYNC ||
989 995 status == IXGBE_ERR_I2C ||
990 996 status == IXGBE_ERR_SFP_NOT_PRESENT)
991 997 goto err_read_i2c_eeprom;
992 998
993 999 status = hw->phy.ops.read_i2c_eeprom(hw,
994 1000 IXGBE_SFF_10GBE_COMP_CODES,
995 1001 &comp_codes_10g);
996 1002
997 1003 if (status == IXGBE_ERR_SWFW_SYNC ||
998 1004 status == IXGBE_ERR_I2C ||
999 1005 status == IXGBE_ERR_SFP_NOT_PRESENT)
1000 1006 goto err_read_i2c_eeprom;
1001 1007 status = hw->phy.ops.read_i2c_eeprom(hw,
1002 1008 IXGBE_SFF_CABLE_TECHNOLOGY,
1003 1009 &cable_tech);
1004 1010
1005 1011 if (status == IXGBE_ERR_SWFW_SYNC ||
1006 1012 status == IXGBE_ERR_I2C ||
1007 1013 status == IXGBE_ERR_SFP_NOT_PRESENT)
1008 1014 goto err_read_i2c_eeprom;
1009 1015
1010 1016 /* ID Module
1011 1017 * =========
1012 1018 * 0 SFP_DA_CU
1013 1019 * 1 SFP_SR
1014 1020 * 2 SFP_LR
1015 1021 * 3 SFP_DA_CORE0 - 82599-specific
1016 1022 * 4 SFP_DA_CORE1 - 82599-specific
1017 1023 * 5 SFP_SR/LR_CORE0 - 82599-specific
1018 1024 * 6 SFP_SR/LR_CORE1 - 82599-specific
1019 1025 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1020 1026 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1021 1027 * 9 SFP_1g_cu_CORE0 - 82599-specific
1022 1028 * 10 SFP_1g_cu_CORE1 - 82599-specific
1023 1029 * 11 SFP_1g_sx_CORE0 - 82599-specific
1024 1030 * 12 SFP_1g_sx_CORE1 - 82599-specific
1025 1031 */
1026 1032 if (hw->mac.type == ixgbe_mac_82598EB) {
1027 1033 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1028 1034 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1029 1035 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1030 1036 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1031 1037 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1032 1038 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1033 1039 else
1034 1040 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1035 1041 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1036 1042 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1037 1043 if (hw->bus.lan_id == 0)
1038 1044 hw->phy.sfp_type =
1039 1045 ixgbe_sfp_type_da_cu_core0;
1040 1046 else
1041 1047 hw->phy.sfp_type =
1042 1048 ixgbe_sfp_type_da_cu_core1;
1043 1049 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1044 1050 hw->phy.ops.read_i2c_eeprom(
1045 1051 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1046 1052 &cable_spec);
1047 1053 if (cable_spec &
1048 1054 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1049 1055 if (hw->bus.lan_id == 0)
1050 1056 hw->phy.sfp_type =
1051 1057 ixgbe_sfp_type_da_act_lmt_core0;
1052 1058 else
1053 1059 hw->phy.sfp_type =
1054 1060 ixgbe_sfp_type_da_act_lmt_core1;
1055 1061 } else {
1056 1062 hw->phy.sfp_type =
1057 1063 ixgbe_sfp_type_unknown;
1058 1064 }
1059 1065 } else if (comp_codes_10g &
1060 1066 (IXGBE_SFF_10GBASESR_CAPABLE |
1061 1067 IXGBE_SFF_10GBASELR_CAPABLE)) {
1062 1068 if (hw->bus.lan_id == 0)
1063 1069 hw->phy.sfp_type =
1064 1070 ixgbe_sfp_type_srlr_core0;
1065 1071 else
1066 1072 hw->phy.sfp_type =
1067 1073 ixgbe_sfp_type_srlr_core1;
1068 1074 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1069 1075 if (hw->bus.lan_id == 0)
1070 1076 hw->phy.sfp_type =
1071 1077 ixgbe_sfp_type_1g_cu_core0;
1072 1078 else
1073 1079 hw->phy.sfp_type =
1074 1080 ixgbe_sfp_type_1g_cu_core1;
1075 1081 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1076 1082 if (hw->bus.lan_id == 0)
1077 1083 hw->phy.sfp_type =
1078 1084 ixgbe_sfp_type_1g_sx_core0;
1079 1085 else
1080 1086 hw->phy.sfp_type =
1081 1087 ixgbe_sfp_type_1g_sx_core1;
1082 1088 } else {
1083 1089 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1084 1090 }
1085 1091 }
1086 1092
1087 1093 if (hw->phy.sfp_type != stored_sfp_type)
1088 1094 hw->phy.sfp_setup_needed = TRUE;
1089 1095
1090 1096 /* Determine if the SFP+ PHY is dual speed or not. */
1091 1097 hw->phy.multispeed_fiber = FALSE;
1092 1098 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1093 1099 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1094 1100 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1095 1101 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1096 1102 hw->phy.multispeed_fiber = TRUE;
1097 1103
1098 1104 /* Determine PHY vendor */
1099 1105 if (hw->phy.type != ixgbe_phy_nl) {
1100 1106 hw->phy.id = identifier;
1101 1107 status = hw->phy.ops.read_i2c_eeprom(hw,
1102 1108 IXGBE_SFF_VENDOR_OUI_BYTE0,
1103 1109 &oui_bytes[0]);
1104 1110
1105 1111 if (status == IXGBE_ERR_SWFW_SYNC ||
1106 1112 status == IXGBE_ERR_I2C ||
1107 1113 status == IXGBE_ERR_SFP_NOT_PRESENT)
1108 1114 goto err_read_i2c_eeprom;
1109 1115
1110 1116 status = hw->phy.ops.read_i2c_eeprom(hw,
1111 1117 IXGBE_SFF_VENDOR_OUI_BYTE1,
1112 1118 &oui_bytes[1]);
1113 1119
1114 1120 if (status == IXGBE_ERR_SWFW_SYNC ||
1115 1121 status == IXGBE_ERR_I2C ||
1116 1122 status == IXGBE_ERR_SFP_NOT_PRESENT)
1117 1123 goto err_read_i2c_eeprom;
1118 1124
1119 1125 status = hw->phy.ops.read_i2c_eeprom(hw,
1120 1126 IXGBE_SFF_VENDOR_OUI_BYTE2,
1121 1127 &oui_bytes[2]);
1122 1128
1123 1129 if (status == IXGBE_ERR_SWFW_SYNC ||
1124 1130 status == IXGBE_ERR_I2C ||
1125 1131 status == IXGBE_ERR_SFP_NOT_PRESENT)
1126 1132 goto err_read_i2c_eeprom;
1127 1133
1128 1134 vendor_oui =
1129 1135 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1130 1136 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1131 1137 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1132 1138
1133 1139 switch (vendor_oui) {
1134 1140 case IXGBE_SFF_VENDOR_OUI_TYCO:
1135 1141 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1136 1142 hw->phy.type =
1137 1143 ixgbe_phy_sfp_passive_tyco;
1138 1144 break;
1139 1145 case IXGBE_SFF_VENDOR_OUI_FTL:
1140 1146 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1141 1147 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1142 1148 else
1143 1149 hw->phy.type = ixgbe_phy_sfp_ftl;
1144 1150 break;
1145 1151 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1146 1152 hw->phy.type = ixgbe_phy_sfp_avago;
1147 1153 break;
1148 1154 case IXGBE_SFF_VENDOR_OUI_INTEL:
1149 1155 hw->phy.type = ixgbe_phy_sfp_intel;
1150 1156 break;
1151 1157 default:
1152 1158 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1153 1159 hw->phy.type =
1154 1160 ixgbe_phy_sfp_passive_unknown;
1155 1161 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1156 1162 hw->phy.type =
1157 1163 ixgbe_phy_sfp_active_unknown;
1158 1164 else
1159 1165 hw->phy.type = ixgbe_phy_sfp_unknown;
1160 1166 break;
1161 1167 }
1162 1168 }
1163 1169
1164 1170 /* Allow any DA cable vendor */
1165 1171 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1166 1172 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1167 1173 status = IXGBE_SUCCESS;
1168 1174 goto out;
1169 1175 }
1170 1176
1171 1177 /* Verify supported 1G SFP modules */
1172 1178 if (comp_codes_10g == 0 &&
1173 1179 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1174 1180 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1175 1181 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1176 1182 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1177 1183 hw->phy.type = ixgbe_phy_sfp_unsupported;
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1178 1184 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1179 1185 goto out;
1180 1186 }
1181 1187
1182 1188 /* Anything else 82598-based is supported */
1183 1189 if (hw->mac.type == ixgbe_mac_82598EB) {
1184 1190 status = IXGBE_SUCCESS;
1185 1191 goto out;
1186 1192 }
1187 1193
1188 - ixgbe_get_device_caps(hw, &enforce_sfp);
1194 + (void) ixgbe_get_device_caps(hw, &enforce_sfp);
1189 1195 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1190 1196 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1191 1197 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1192 1198 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
1193 1199 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1194 1200 /* Make sure we're a supported PHY type */
1195 1201 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1196 1202 status = IXGBE_SUCCESS;
1197 1203 } else {
1198 1204 if (hw->allow_unsupported_sfp == TRUE) {
1199 1205 EWARN(hw, "WARNING: Intel (R) Network "
1200 1206 "Connections are quality tested "
1201 1207 "using Intel (R) Ethernet Optics."
1202 1208 " Using untested modules is not "
1203 1209 "supported and may cause unstable"
1204 1210 " operation or damage to the "
1205 1211 "module or the adapter. Intel "
1206 1212 "Corporation is not responsible "
1207 1213 "for any harm caused by using "
1208 1214 "untested modules.\n", status);
1209 1215 status = IXGBE_SUCCESS;
1210 1216 } else {
1211 1217 DEBUGOUT("SFP+ module not supported\n");
1212 1218 hw->phy.type =
1213 1219 ixgbe_phy_sfp_unsupported;
1214 1220 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1215 1221 }
1216 1222 }
1217 1223 } else {
1218 1224 status = IXGBE_SUCCESS;
1219 1225 }
1220 1226 }
1221 1227
1222 1228 out:
1223 1229 return status;
1224 1230
1225 1231 err_read_i2c_eeprom:
1226 1232 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1227 1233 if (hw->phy.type != ixgbe_phy_nl) {
1228 1234 hw->phy.id = 0;
1229 1235 hw->phy.type = ixgbe_phy_unknown;
1230 1236 }
1231 1237 return IXGBE_ERR_SFP_NOT_PRESENT;
1232 1238 }
1233 1239
1234 1240
1235 1241
1236 1242 /**
1237 1243 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1238 1244 * @hw: pointer to hardware structure
1239 1245 * @list_offset: offset to the SFP ID list
1240 1246 * @data_offset: offset to the SFP data block
1241 1247 *
1242 1248 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1243 1249 * so it returns the offsets to the phy init sequence block.
1244 1250 **/
1245 1251 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1246 1252 u16 *list_offset,
1247 1253 u16 *data_offset)
1248 1254 {
1249 1255 u16 sfp_id;
1250 1256 u16 sfp_type = hw->phy.sfp_type;
1251 1257
1252 1258 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1253 1259
1254 1260 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1255 1261 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1256 1262
1257 1263 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1258 1264 return IXGBE_ERR_SFP_NOT_PRESENT;
1259 1265
1260 1266 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1261 1267 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1262 1268 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1263 1269
1264 1270 /*
1265 1271 * Limiting active cables and 1G Phys must be initialized as
1266 1272 * SR modules
1267 1273 */
1268 1274 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1269 1275 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1270 1276 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1271 1277 sfp_type = ixgbe_sfp_type_srlr_core0;
1272 1278 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1273 1279 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1274 1280 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1275 1281 sfp_type = ixgbe_sfp_type_srlr_core1;
1276 1282
1277 1283 /* Read offset to PHY init contents */
1278 1284 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1279 1285
1280 1286 if ((!*list_offset) || (*list_offset == 0xFFFF))
1281 1287 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1282 1288
1283 1289 /* Shift offset to first ID word */
1284 1290 (*list_offset)++;
1285 1291
1286 1292 /*
1287 1293 * Find the matching SFP ID in the EEPROM
1288 1294 * and program the init sequence
1289 1295 */
1290 1296 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1291 1297
1292 1298 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1293 1299 if (sfp_id == sfp_type) {
1294 1300 (*list_offset)++;
1295 1301 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1296 1302 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1297 1303 DEBUGOUT("SFP+ module not supported\n");
1298 1304 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1299 1305 } else {
1300 1306 break;
1301 1307 }
1302 1308 } else {
1303 1309 (*list_offset) += 2;
1304 1310 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1305 1311 return IXGBE_ERR_PHY;
1306 1312 }
1307 1313 }
1308 1314
1309 1315 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1310 1316 DEBUGOUT("No matching SFP+ module found\n");
1311 1317 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1312 1318 }
1313 1319
1314 1320 return IXGBE_SUCCESS;
1315 1321 }
1316 1322
1317 1323 /**
1318 1324 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1319 1325 * @hw: pointer to hardware structure
1320 1326 * @byte_offset: EEPROM byte offset to read
1321 1327 * @eeprom_data: value read
1322 1328 *
1323 1329 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1324 1330 **/
1325 1331 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1326 1332 u8 *eeprom_data)
1327 1333 {
1328 1334 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1329 1335
1330 1336 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1331 1337 IXGBE_I2C_EEPROM_DEV_ADDR,
1332 1338 eeprom_data);
1333 1339 }
1334 1340
1335 1341 /**
1336 1342 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1337 1343 * @hw: pointer to hardware structure
1338 1344 * @byte_offset: EEPROM byte offset to write
1339 1345 * @eeprom_data: value to write
1340 1346 *
1341 1347 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1342 1348 **/
1343 1349 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1344 1350 u8 eeprom_data)
1345 1351 {
1346 1352 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1347 1353
1348 1354 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1349 1355 IXGBE_I2C_EEPROM_DEV_ADDR,
1350 1356 eeprom_data);
1351 1357 }
1352 1358
1353 1359 /**
1354 1360 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1355 1361 * @hw: pointer to hardware structure
1356 1362 * @byte_offset: byte offset to read
1357 1363 * @data: value read
1358 1364 *
1359 1365 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1360 1366 * a specified device address.
1361 1367 **/
1362 1368 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1363 1369 u8 dev_addr, u8 *data)
1364 1370 {
1365 1371 s32 status = IXGBE_SUCCESS;
1366 1372 u32 max_retry = 10;
1367 1373 u32 retry = 0;
1368 1374 u16 swfw_mask = 0;
1369 1375 bool nack = 1;
1370 1376 *data = 0;
1371 1377
1372 1378 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1373 1379
1374 1380 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1375 1381 swfw_mask = IXGBE_GSSR_PHY1_SM;
1376 1382 else
1377 1383 swfw_mask = IXGBE_GSSR_PHY0_SM;
1378 1384
1379 1385 do {
1380 1386 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1381 1387 != IXGBE_SUCCESS) {
1382 1388 status = IXGBE_ERR_SWFW_SYNC;
1383 1389 goto read_byte_out;
1384 1390 }
1385 1391
1386 1392 ixgbe_i2c_start(hw);
1387 1393
1388 1394 /* Device Address and write indication */
1389 1395 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1390 1396 if (status != IXGBE_SUCCESS)
1391 1397 goto fail;
1392 1398
1393 1399 status = ixgbe_get_i2c_ack(hw);
1394 1400 if (status != IXGBE_SUCCESS)
1395 1401 goto fail;
1396 1402
1397 1403 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1398 1404 if (status != IXGBE_SUCCESS)
1399 1405 goto fail;
1400 1406
1401 1407 status = ixgbe_get_i2c_ack(hw);
1402 1408 if (status != IXGBE_SUCCESS)
1403 1409 goto fail;
1404 1410
1405 1411 ixgbe_i2c_start(hw);
1406 1412
1407 1413 /* Device Address and read indication */
1408 1414 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1409 1415 if (status != IXGBE_SUCCESS)
1410 1416 goto fail;
1411 1417
1412 1418 status = ixgbe_get_i2c_ack(hw);
1413 1419 if (status != IXGBE_SUCCESS)
1414 1420 goto fail;
1415 1421
1416 1422 status = ixgbe_clock_in_i2c_byte(hw, data);
1417 1423 if (status != IXGBE_SUCCESS)
1418 1424 goto fail;
1419 1425
1420 1426 status = ixgbe_clock_out_i2c_bit(hw, nack);
1421 1427 if (status != IXGBE_SUCCESS)
1422 1428 goto fail;
1423 1429
1424 1430 ixgbe_i2c_stop(hw);
1425 1431 break;
1426 1432
1427 1433 fail:
1428 1434 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1429 1435 msec_delay(100);
1430 1436 ixgbe_i2c_bus_clear(hw);
1431 1437 retry++;
1432 1438 if (retry < max_retry)
1433 1439 DEBUGOUT("I2C byte read error - Retrying.\n");
1434 1440 else
1435 1441 DEBUGOUT("I2C byte read error.\n");
1436 1442
1437 1443 } while (retry < max_retry);
1438 1444
1439 1445 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1440 1446
1441 1447 read_byte_out:
1442 1448 return status;
1443 1449 }
1444 1450
1445 1451 /**
1446 1452 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1447 1453 * @hw: pointer to hardware structure
1448 1454 * @byte_offset: byte offset to write
1449 1455 * @data: value to write
1450 1456 *
1451 1457 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1452 1458 * a specified device address.
1453 1459 **/
1454 1460 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1455 1461 u8 dev_addr, u8 data)
1456 1462 {
1457 1463 s32 status = IXGBE_SUCCESS;
1458 1464 u32 max_retry = 1;
1459 1465 u32 retry = 0;
1460 1466 u16 swfw_mask = 0;
1461 1467
1462 1468 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1463 1469
1464 1470 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1465 1471 swfw_mask = IXGBE_GSSR_PHY1_SM;
1466 1472 else
1467 1473 swfw_mask = IXGBE_GSSR_PHY0_SM;
1468 1474
1469 1475 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1470 1476 status = IXGBE_ERR_SWFW_SYNC;
1471 1477 goto write_byte_out;
1472 1478 }
1473 1479
1474 1480 do {
1475 1481 ixgbe_i2c_start(hw);
1476 1482
1477 1483 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1478 1484 if (status != IXGBE_SUCCESS)
1479 1485 goto fail;
1480 1486
1481 1487 status = ixgbe_get_i2c_ack(hw);
1482 1488 if (status != IXGBE_SUCCESS)
1483 1489 goto fail;
1484 1490
1485 1491 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1486 1492 if (status != IXGBE_SUCCESS)
1487 1493 goto fail;
1488 1494
1489 1495 status = ixgbe_get_i2c_ack(hw);
1490 1496 if (status != IXGBE_SUCCESS)
1491 1497 goto fail;
1492 1498
1493 1499 status = ixgbe_clock_out_i2c_byte(hw, data);
1494 1500 if (status != IXGBE_SUCCESS)
1495 1501 goto fail;
1496 1502
1497 1503 status = ixgbe_get_i2c_ack(hw);
1498 1504 if (status != IXGBE_SUCCESS)
1499 1505 goto fail;
1500 1506
1501 1507 ixgbe_i2c_stop(hw);
1502 1508 break;
1503 1509
1504 1510 fail:
1505 1511 ixgbe_i2c_bus_clear(hw);
1506 1512 retry++;
1507 1513 if (retry < max_retry)
1508 1514 DEBUGOUT("I2C byte write error - Retrying.\n");
1509 1515 else
1510 1516 DEBUGOUT("I2C byte write error.\n");
1511 1517 } while (retry < max_retry);
1512 1518
1513 1519 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1514 1520
1515 1521 write_byte_out:
1516 1522 return status;
1517 1523 }
1518 1524
1519 1525 /**
1520 1526 * ixgbe_i2c_start - Sets I2C start condition
1521 1527 * @hw: pointer to hardware structure
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1522 1528 *
1523 1529 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1524 1530 **/
1525 1531 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1526 1532 {
1527 1533 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1528 1534
1529 1535 DEBUGFUNC("ixgbe_i2c_start");
1530 1536
1531 1537 /* Start condition must begin with data and clock high */
1532 - ixgbe_set_i2c_data(hw, &i2cctl, 1);
1538 + (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1533 1539 ixgbe_raise_i2c_clk(hw, &i2cctl);
1534 1540
1535 1541 /* Setup time for start condition (4.7us) */
1536 1542 usec_delay(IXGBE_I2C_T_SU_STA);
1537 1543
1538 - ixgbe_set_i2c_data(hw, &i2cctl, 0);
1544 + (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1539 1545
1540 1546 /* Hold time for start condition (4us) */
1541 1547 usec_delay(IXGBE_I2C_T_HD_STA);
1542 1548
1543 1549 ixgbe_lower_i2c_clk(hw, &i2cctl);
1544 1550
1545 1551 /* Minimum low period of clock is 4.7 us */
1546 1552 usec_delay(IXGBE_I2C_T_LOW);
1547 1553
1548 1554 }
1549 1555
1550 1556 /**
1551 1557 * ixgbe_i2c_stop - Sets I2C stop condition
1552 1558 * @hw: pointer to hardware structure
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1553 1559 *
1554 1560 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1555 1561 **/
1556 1562 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1557 1563 {
1558 1564 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1559 1565
1560 1566 DEBUGFUNC("ixgbe_i2c_stop");
1561 1567
1562 1568 /* Stop condition must begin with data low and clock high */
1563 - ixgbe_set_i2c_data(hw, &i2cctl, 0);
1569 + (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1564 1570 ixgbe_raise_i2c_clk(hw, &i2cctl);
1565 1571
1566 1572 /* Setup time for stop condition (4us) */
1567 1573 usec_delay(IXGBE_I2C_T_SU_STO);
1568 1574
1569 - ixgbe_set_i2c_data(hw, &i2cctl, 1);
1575 + (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1570 1576
1571 1577 /* bus free time between stop and start (4.7us)*/
1572 1578 usec_delay(IXGBE_I2C_T_BUF);
1573 1579 }
1574 1580
1575 1581 /**
1576 1582 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1577 1583 * @hw: pointer to hardware structure
1578 1584 * @data: data byte to clock in
1579 1585 *
1580 1586 * Clocks in one byte data via I2C data/clock
1581 1587 **/
1582 1588 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1583 1589 {
1584 - s32 i;
1590 + s32 i, status = IXGBE_SUCCESS;
1585 1591 bool bit = 0;
1586 1592
1587 1593 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1588 1594
1589 1595 for (i = 7; i >= 0; i--) {
1590 - ixgbe_clock_in_i2c_bit(hw, &bit);
1596 + status = ixgbe_clock_in_i2c_bit(hw, &bit);
1597 + if (status != IXGBE_SUCCESS)
1598 + break;
1591 1599 *data |= bit << i;
1592 1600 }
1593 1601
1594 - return IXGBE_SUCCESS;
1602 + return status;
1595 1603 }
1596 1604
1597 1605 /**
1598 1606 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1599 1607 * @hw: pointer to hardware structure
1600 1608 * @data: data byte clocked out
1601 1609 *
1602 1610 * Clocks out one byte data via I2C data/clock
1603 1611 **/
1604 1612 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1605 1613 {
1606 1614 s32 status = IXGBE_SUCCESS;
1607 1615 s32 i;
1608 1616 u32 i2cctl;
1609 1617 bool bit = 0;
1610 1618
1611 1619 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1612 1620
1613 1621 for (i = 7; i >= 0; i--) {
1614 1622 bit = (data >> i) & 0x1;
1615 1623 status = ixgbe_clock_out_i2c_bit(hw, bit);
1616 1624
1617 1625 if (status != IXGBE_SUCCESS)
1618 1626 break;
1619 1627 }
1620 1628
1621 1629 /* Release SDA line (set high) */
1622 1630 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1623 1631 i2cctl |= IXGBE_I2C_DATA_OUT;
1624 1632 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1625 1633 IXGBE_WRITE_FLUSH(hw);
1626 1634
1627 1635 return status;
1628 1636 }
1629 1637
1630 1638 /**
1631 1639 * ixgbe_get_i2c_ack - Polls for I2C ACK
1632 1640 * @hw: pointer to hardware structure
1633 1641 *
1634 1642 * Clocks in/out one bit via I2C data/clock
1635 1643 **/
1636 1644 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1637 1645 {
1638 1646 s32 status = IXGBE_SUCCESS;
1639 1647 u32 i = 0;
1640 1648 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1641 1649 u32 timeout = 10;
1642 1650 bool ack = 1;
1643 1651
1644 1652 DEBUGFUNC("ixgbe_get_i2c_ack");
1645 1653
1646 1654 ixgbe_raise_i2c_clk(hw, &i2cctl);
1647 1655
1648 1656
1649 1657 /* Minimum high period of clock is 4us */
1650 1658 usec_delay(IXGBE_I2C_T_HIGH);
1651 1659
1652 1660 /* Poll for ACK. Note that ACK in I2C spec is
1653 1661 * transition from 1 to 0 */
1654 1662 for (i = 0; i < timeout; i++) {
1655 1663 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1656 1664 ack = ixgbe_get_i2c_data(&i2cctl);
1657 1665
1658 1666 usec_delay(1);
1659 1667 if (ack == 0)
1660 1668 break;
1661 1669 }
1662 1670
1663 1671 if (ack == 1) {
1664 1672 DEBUGOUT("I2C ack was not received.\n");
1665 1673 status = IXGBE_ERR_I2C;
1666 1674 }
1667 1675
1668 1676 ixgbe_lower_i2c_clk(hw, &i2cctl);
1669 1677
1670 1678 /* Minimum low period of clock is 4.7 us */
1671 1679 usec_delay(IXGBE_I2C_T_LOW);
1672 1680
1673 1681 return status;
1674 1682 }
1675 1683
1676 1684 /**
1677 1685 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1678 1686 * @hw: pointer to hardware structure
1679 1687 * @data: read data value
1680 1688 *
1681 1689 * Clocks in one bit via I2C data/clock
1682 1690 **/
1683 1691 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1684 1692 {
1685 1693 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1686 1694
1687 1695 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1688 1696
1689 1697 ixgbe_raise_i2c_clk(hw, &i2cctl);
1690 1698
1691 1699 /* Minimum high period of clock is 4us */
1692 1700 usec_delay(IXGBE_I2C_T_HIGH);
1693 1701
1694 1702 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1695 1703 *data = ixgbe_get_i2c_data(&i2cctl);
1696 1704
1697 1705 ixgbe_lower_i2c_clk(hw, &i2cctl);
1698 1706
1699 1707 /* Minimum low period of clock is 4.7 us */
1700 1708 usec_delay(IXGBE_I2C_T_LOW);
1701 1709
1702 1710 return IXGBE_SUCCESS;
1703 1711 }
1704 1712
1705 1713 /**
1706 1714 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1707 1715 * @hw: pointer to hardware structure
1708 1716 * @data: data value to write
1709 1717 *
1710 1718 * Clocks out one bit via I2C data/clock
1711 1719 **/
1712 1720 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1713 1721 {
1714 1722 s32 status;
1715 1723 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1716 1724
1717 1725 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1718 1726
1719 1727 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1720 1728 if (status == IXGBE_SUCCESS) {
1721 1729 ixgbe_raise_i2c_clk(hw, &i2cctl);
1722 1730
1723 1731 /* Minimum high period of clock is 4us */
1724 1732 usec_delay(IXGBE_I2C_T_HIGH);
1725 1733
1726 1734 ixgbe_lower_i2c_clk(hw, &i2cctl);
1727 1735
1728 1736 /* Minimum low period of clock is 4.7 us.
1729 1737 * This also takes care of the data hold time.
1730 1738 */
1731 1739 usec_delay(IXGBE_I2C_T_LOW);
1732 1740 } else {
1733 1741 status = IXGBE_ERR_I2C;
1734 1742 DEBUGOUT1("I2C data was not set to %X\n", data);
1735 1743 }
1736 1744
1737 1745 return status;
1738 1746 }
1739 1747 /**
1740 1748 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1741 1749 * @hw: pointer to hardware structure
1742 1750 * @i2cctl: Current value of I2CCTL register
1743 1751 *
1744 1752 * Raises the I2C clock line '0'->'1'
1745 1753 **/
1746 1754 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1747 1755 {
1748 1756 u32 i = 0;
1749 1757 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1750 1758 u32 i2cctl_r = 0;
1751 1759
1752 1760 DEBUGFUNC("ixgbe_raise_i2c_clk");
1753 1761
1754 1762 for (i = 0; i < timeout; i++) {
1755 1763 *i2cctl |= IXGBE_I2C_CLK_OUT;
1756 1764
1757 1765 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1758 1766 IXGBE_WRITE_FLUSH(hw);
1759 1767 /* SCL rise time (1000ns) */
1760 1768 usec_delay(IXGBE_I2C_T_RISE);
1761 1769
1762 1770 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1763 1771 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1764 1772 break;
1765 1773 }
1766 1774 }
1767 1775
1768 1776 /**
1769 1777 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1770 1778 * @hw: pointer to hardware structure
1771 1779 * @i2cctl: Current value of I2CCTL register
1772 1780 *
1773 1781 * Lowers the I2C clock line '1'->'0'
1774 1782 **/
1775 1783 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1776 1784 {
1777 1785
1778 1786 DEBUGFUNC("ixgbe_lower_i2c_clk");
1779 1787
1780 1788 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1781 1789
1782 1790 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1783 1791 IXGBE_WRITE_FLUSH(hw);
1784 1792
1785 1793 /* SCL fall time (300ns) */
1786 1794 usec_delay(IXGBE_I2C_T_FALL);
1787 1795 }
1788 1796
1789 1797 /**
1790 1798 * ixgbe_set_i2c_data - Sets the I2C data bit
1791 1799 * @hw: pointer to hardware structure
1792 1800 * @i2cctl: Current value of I2CCTL register
1793 1801 * @data: I2C data value (0 or 1) to set
1794 1802 *
1795 1803 * Sets the I2C data bit
1796 1804 **/
1797 1805 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1798 1806 {
1799 1807 s32 status = IXGBE_SUCCESS;
1800 1808
1801 1809 DEBUGFUNC("ixgbe_set_i2c_data");
1802 1810
1803 1811 if (data)
1804 1812 *i2cctl |= IXGBE_I2C_DATA_OUT;
1805 1813 else
1806 1814 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1807 1815
1808 1816 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1809 1817 IXGBE_WRITE_FLUSH(hw);
1810 1818
1811 1819 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1812 1820 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1813 1821
1814 1822 /* Verify data was set correctly */
1815 1823 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1816 1824 if (data != ixgbe_get_i2c_data(i2cctl)) {
1817 1825 status = IXGBE_ERR_I2C;
1818 1826 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1819 1827 }
1820 1828
1821 1829 return status;
1822 1830 }
1823 1831
1824 1832 /**
1825 1833 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1826 1834 * @hw: pointer to hardware structure
1827 1835 * @i2cctl: Current value of I2CCTL register
1828 1836 *
1829 1837 * Returns the I2C data bit value
1830 1838 **/
1831 1839 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1832 1840 {
1833 1841 bool data;
1834 1842
1835 1843 DEBUGFUNC("ixgbe_get_i2c_data");
1836 1844
1837 1845 if (*i2cctl & IXGBE_I2C_DATA_IN)
1838 1846 data = 1;
1839 1847 else
1840 1848 data = 0;
1841 1849
1842 1850 return data;
1843 1851 }
1844 1852
1845 1853 /**
1846 1854 * ixgbe_i2c_bus_clear - Clears the I2C bus
1847 1855 * @hw: pointer to hardware structure
1848 1856 *
1849 1857 * Clears the I2C bus by sending nine clock pulses.
1850 1858 * Used when data line is stuck low.
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1851 1859 **/
1852 1860 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1853 1861 {
1854 1862 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1855 1863 u32 i;
1856 1864
1857 1865 DEBUGFUNC("ixgbe_i2c_bus_clear");
1858 1866
1859 1867 ixgbe_i2c_start(hw);
1860 1868
1861 - ixgbe_set_i2c_data(hw, &i2cctl, 1);
1869 + (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1862 1870
1863 1871 for (i = 0; i < 9; i++) {
1864 1872 ixgbe_raise_i2c_clk(hw, &i2cctl);
1865 1873
1866 1874 /* Min high period of clock is 4us */
1867 1875 usec_delay(IXGBE_I2C_T_HIGH);
1868 1876
1869 1877 ixgbe_lower_i2c_clk(hw, &i2cctl);
1870 1878
1871 1879 /* Min low period of clock is 4.7us*/
1872 1880 usec_delay(IXGBE_I2C_T_LOW);
1873 1881 }
1874 1882
1875 1883 ixgbe_i2c_start(hw);
1876 1884
1877 1885 /* Put the i2c bus back to default state */
1878 1886 ixgbe_i2c_stop(hw);
1879 1887 }
1880 1888
1881 1889 /**
1882 1890 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1883 1891 * @hw: pointer to hardware structure
1884 1892 *
1885 1893 * Checks if the LASI temp alarm status was triggered due to overtemp
1886 1894 **/
1887 1895 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1888 1896 {
1889 1897 s32 status = IXGBE_SUCCESS;
1890 1898 u16 phy_data = 0;
1891 1899
1892 1900 DEBUGFUNC("ixgbe_tn_check_overtemp");
1893 1901
1894 1902 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1895 1903 goto out;
1896 1904
1897 1905 /* Check that the LASI temp alarm status was triggered */
1898 1906 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1899 1907 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1900 1908
1901 1909 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1902 1910 goto out;
1903 1911
1904 1912 status = IXGBE_ERR_OVERTEMP;
1905 1913 out:
1906 1914 return status;
1907 1915 }
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