81 }
82
83 /**
84 * ixgbe_identify_phy_generic - Get physical layer module
85 * @hw: pointer to hardware structure
86 *
87 * Determines the physical layer module found on the current adapter.
88 **/
89 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
90 {
91 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
92 u32 phy_addr;
93 u16 ext_ability = 0;
94
95 DEBUGFUNC("ixgbe_identify_phy_generic");
96
97 if (hw->phy.type == ixgbe_phy_unknown) {
98 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
99 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
100 hw->phy.addr = phy_addr;
101 ixgbe_get_phy_id(hw);
102 hw->phy.type =
103 ixgbe_get_phy_type_from_id(hw->phy.id);
104
105 if (hw->phy.type == ixgbe_phy_unknown) {
106 hw->phy.ops.read_reg(hw,
107 IXGBE_MDIO_PHY_EXT_ABILITY,
108 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
109 &ext_ability);
110 if (ext_ability &
111 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
112 IXGBE_MDIO_PHY_1000BASET_ABILITY))
113 hw->phy.type =
114 ixgbe_phy_cu_unknown;
115 else
116 hw->phy.type =
117 ixgbe_phy_generic;
118 }
119
120 status = IXGBE_SUCCESS;
121 break;
453 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
454 DEBUGOUT("PHY address cmd didn't complete\n");
455 status = IXGBE_ERR_PHY;
456 }
457 }
458
459 hw->mac.ops.release_swfw_sync(hw, gssr);
460 }
461
462 return status;
463 }
464
465 /**
466 * ixgbe_setup_phy_link_generic - Set and restart autoneg
467 * @hw: pointer to hardware structure
468 *
469 * Restart autonegotiation and PHY and waits for completion.
470 **/
471 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
472 {
473 s32 status = IXGBE_SUCCESS;
474 u32 time_out;
475 u32 max_time_out = 10;
476 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
477 bool autoneg = FALSE;
478 ixgbe_link_speed speed;
479
480 DEBUGFUNC("ixgbe_setup_phy_link_generic");
481
482 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
483
484 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
485 /* Set or unset auto-negotiation 10G advertisement */
486 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
487 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
488 &autoneg_reg);
489
490 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
491 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
492 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
493
494 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
495 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
496 autoneg_reg);
497 }
498
499 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
500 /* Set or unset auto-negotiation 1G advertisement */
501 hw->phy.ops.read_reg(hw,
502 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
671 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
672 *link_up = TRUE;
673 if (phy_speed ==
674 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
675 *speed = IXGBE_LINK_SPEED_1GB_FULL;
676 break;
677 }
678 }
679
680 return status;
681 }
682
683 /**
684 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
685 * @hw: pointer to hardware structure
686 *
687 * Restart autonegotiation and PHY and waits for completion.
688 **/
689 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
690 {
691 s32 status = IXGBE_SUCCESS;
692 u32 time_out;
693 u32 max_time_out = 10;
694 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
695 bool autoneg = FALSE;
696 ixgbe_link_speed speed;
697
698 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
699
700 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
701
702 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
703 /* Set or unset auto-negotiation 10G advertisement */
704 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
705 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
706 &autoneg_reg);
707
708 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
709 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
710 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
711
712 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
713 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
714 autoneg_reg);
715 }
716
717 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
718 /* Set or unset auto-negotiation 1G advertisement */
719 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
720 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1168 goto out;
1169 }
1170
1171 /* Verify supported 1G SFP modules */
1172 if (comp_codes_10g == 0 &&
1173 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1174 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1175 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1176 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1177 hw->phy.type = ixgbe_phy_sfp_unsupported;
1178 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1179 goto out;
1180 }
1181
1182 /* Anything else 82598-based is supported */
1183 if (hw->mac.type == ixgbe_mac_82598EB) {
1184 status = IXGBE_SUCCESS;
1185 goto out;
1186 }
1187
1188 ixgbe_get_device_caps(hw, &enforce_sfp);
1189 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1190 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1191 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1192 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
1193 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1194 /* Make sure we're a supported PHY type */
1195 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1196 status = IXGBE_SUCCESS;
1197 } else {
1198 if (hw->allow_unsupported_sfp == TRUE) {
1199 EWARN(hw, "WARNING: Intel (R) Network "
1200 "Connections are quality tested "
1201 "using Intel (R) Ethernet Optics."
1202 " Using untested modules is not "
1203 "supported and may cause unstable"
1204 " operation or damage to the "
1205 "module or the adapter. Intel "
1206 "Corporation is not responsible "
1207 "for any harm caused by using "
1208 "untested modules.\n", status);
1512
1513 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1514
1515 write_byte_out:
1516 return status;
1517 }
1518
1519 /**
1520 * ixgbe_i2c_start - Sets I2C start condition
1521 * @hw: pointer to hardware structure
1522 *
1523 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1524 **/
1525 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1526 {
1527 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1528
1529 DEBUGFUNC("ixgbe_i2c_start");
1530
1531 /* Start condition must begin with data and clock high */
1532 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1533 ixgbe_raise_i2c_clk(hw, &i2cctl);
1534
1535 /* Setup time for start condition (4.7us) */
1536 usec_delay(IXGBE_I2C_T_SU_STA);
1537
1538 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1539
1540 /* Hold time for start condition (4us) */
1541 usec_delay(IXGBE_I2C_T_HD_STA);
1542
1543 ixgbe_lower_i2c_clk(hw, &i2cctl);
1544
1545 /* Minimum low period of clock is 4.7 us */
1546 usec_delay(IXGBE_I2C_T_LOW);
1547
1548 }
1549
1550 /**
1551 * ixgbe_i2c_stop - Sets I2C stop condition
1552 * @hw: pointer to hardware structure
1553 *
1554 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1555 **/
1556 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1557 {
1558 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1559
1560 DEBUGFUNC("ixgbe_i2c_stop");
1561
1562 /* Stop condition must begin with data low and clock high */
1563 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1564 ixgbe_raise_i2c_clk(hw, &i2cctl);
1565
1566 /* Setup time for stop condition (4us) */
1567 usec_delay(IXGBE_I2C_T_SU_STO);
1568
1569 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1570
1571 /* bus free time between stop and start (4.7us)*/
1572 usec_delay(IXGBE_I2C_T_BUF);
1573 }
1574
1575 /**
1576 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1577 * @hw: pointer to hardware structure
1578 * @data: data byte to clock in
1579 *
1580 * Clocks in one byte data via I2C data/clock
1581 **/
1582 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1583 {
1584 s32 i;
1585 bool bit = 0;
1586
1587 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1588
1589 for (i = 7; i >= 0; i--) {
1590 ixgbe_clock_in_i2c_bit(hw, &bit);
1591 *data |= bit << i;
1592 }
1593
1594 return IXGBE_SUCCESS;
1595 }
1596
1597 /**
1598 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1599 * @hw: pointer to hardware structure
1600 * @data: data byte clocked out
1601 *
1602 * Clocks out one byte data via I2C data/clock
1603 **/
1604 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1605 {
1606 s32 status = IXGBE_SUCCESS;
1607 s32 i;
1608 u32 i2cctl;
1609 bool bit = 0;
1610
1611 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1612
1613 for (i = 7; i >= 0; i--) {
1614 bit = (data >> i) & 0x1;
1841
1842 return data;
1843 }
1844
1845 /**
1846 * ixgbe_i2c_bus_clear - Clears the I2C bus
1847 * @hw: pointer to hardware structure
1848 *
1849 * Clears the I2C bus by sending nine clock pulses.
1850 * Used when data line is stuck low.
1851 **/
1852 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1853 {
1854 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1855 u32 i;
1856
1857 DEBUGFUNC("ixgbe_i2c_bus_clear");
1858
1859 ixgbe_i2c_start(hw);
1860
1861 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1862
1863 for (i = 0; i < 9; i++) {
1864 ixgbe_raise_i2c_clk(hw, &i2cctl);
1865
1866 /* Min high period of clock is 4us */
1867 usec_delay(IXGBE_I2C_T_HIGH);
1868
1869 ixgbe_lower_i2c_clk(hw, &i2cctl);
1870
1871 /* Min low period of clock is 4.7us*/
1872 usec_delay(IXGBE_I2C_T_LOW);
1873 }
1874
1875 ixgbe_i2c_start(hw);
1876
1877 /* Put the i2c bus back to default state */
1878 ixgbe_i2c_stop(hw);
1879 }
1880
1881 /**
|
81 }
82
83 /**
84 * ixgbe_identify_phy_generic - Get physical layer module
85 * @hw: pointer to hardware structure
86 *
87 * Determines the physical layer module found on the current adapter.
88 **/
89 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
90 {
91 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
92 u32 phy_addr;
93 u16 ext_ability = 0;
94
95 DEBUGFUNC("ixgbe_identify_phy_generic");
96
97 if (hw->phy.type == ixgbe_phy_unknown) {
98 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
99 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
100 hw->phy.addr = phy_addr;
101 (void) ixgbe_get_phy_id(hw);
102 hw->phy.type =
103 ixgbe_get_phy_type_from_id(hw->phy.id);
104
105 if (hw->phy.type == ixgbe_phy_unknown) {
106 hw->phy.ops.read_reg(hw,
107 IXGBE_MDIO_PHY_EXT_ABILITY,
108 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
109 &ext_ability);
110 if (ext_ability &
111 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
112 IXGBE_MDIO_PHY_1000BASET_ABILITY))
113 hw->phy.type =
114 ixgbe_phy_cu_unknown;
115 else
116 hw->phy.type =
117 ixgbe_phy_generic;
118 }
119
120 status = IXGBE_SUCCESS;
121 break;
453 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
454 DEBUGOUT("PHY address cmd didn't complete\n");
455 status = IXGBE_ERR_PHY;
456 }
457 }
458
459 hw->mac.ops.release_swfw_sync(hw, gssr);
460 }
461
462 return status;
463 }
464
465 /**
466 * ixgbe_setup_phy_link_generic - Set and restart autoneg
467 * @hw: pointer to hardware structure
468 *
469 * Restart autonegotiation and PHY and waits for completion.
470 **/
471 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
472 {
473 s32 status;
474 u32 time_out;
475 u32 max_time_out = 10;
476 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
477 bool autoneg = FALSE;
478 ixgbe_link_speed speed;
479
480 DEBUGFUNC("ixgbe_setup_phy_link_generic");
481
482 status =
483 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
484 if (status != IXGBE_SUCCESS)
485 return status;
486
487 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
488 /* Set or unset auto-negotiation 10G advertisement */
489 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
490 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
491 &autoneg_reg);
492
493 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
494 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
495 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
496
497 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
498 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
499 autoneg_reg);
500 }
501
502 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
503 /* Set or unset auto-negotiation 1G advertisement */
504 hw->phy.ops.read_reg(hw,
505 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
674 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
675 *link_up = TRUE;
676 if (phy_speed ==
677 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
678 *speed = IXGBE_LINK_SPEED_1GB_FULL;
679 break;
680 }
681 }
682
683 return status;
684 }
685
686 /**
687 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
688 * @hw: pointer to hardware structure
689 *
690 * Restart autonegotiation and PHY and waits for completion.
691 **/
692 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
693 {
694 s32 status;
695 u32 time_out;
696 u32 max_time_out = 10;
697 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
698 bool autoneg = FALSE;
699 ixgbe_link_speed speed;
700
701 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
702
703 status =
704 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
705 if (status != IXGBE_SUCCESS)
706 return status;
707
708 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
709 /* Set or unset auto-negotiation 10G advertisement */
710 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
711 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
712 &autoneg_reg);
713
714 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
715 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
716 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
717
718 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
719 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
720 autoneg_reg);
721 }
722
723 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
724 /* Set or unset auto-negotiation 1G advertisement */
725 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
726 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1174 goto out;
1175 }
1176
1177 /* Verify supported 1G SFP modules */
1178 if (comp_codes_10g == 0 &&
1179 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1180 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1181 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1182 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1183 hw->phy.type = ixgbe_phy_sfp_unsupported;
1184 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1185 goto out;
1186 }
1187
1188 /* Anything else 82598-based is supported */
1189 if (hw->mac.type == ixgbe_mac_82598EB) {
1190 status = IXGBE_SUCCESS;
1191 goto out;
1192 }
1193
1194 (void) ixgbe_get_device_caps(hw, &enforce_sfp);
1195 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1196 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1197 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1198 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
1199 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1200 /* Make sure we're a supported PHY type */
1201 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1202 status = IXGBE_SUCCESS;
1203 } else {
1204 if (hw->allow_unsupported_sfp == TRUE) {
1205 EWARN(hw, "WARNING: Intel (R) Network "
1206 "Connections are quality tested "
1207 "using Intel (R) Ethernet Optics."
1208 " Using untested modules is not "
1209 "supported and may cause unstable"
1210 " operation or damage to the "
1211 "module or the adapter. Intel "
1212 "Corporation is not responsible "
1213 "for any harm caused by using "
1214 "untested modules.\n", status);
1518
1519 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1520
1521 write_byte_out:
1522 return status;
1523 }
1524
1525 /**
1526 * ixgbe_i2c_start - Sets I2C start condition
1527 * @hw: pointer to hardware structure
1528 *
1529 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1530 **/
1531 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1532 {
1533 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1534
1535 DEBUGFUNC("ixgbe_i2c_start");
1536
1537 /* Start condition must begin with data and clock high */
1538 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1539 ixgbe_raise_i2c_clk(hw, &i2cctl);
1540
1541 /* Setup time for start condition (4.7us) */
1542 usec_delay(IXGBE_I2C_T_SU_STA);
1543
1544 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1545
1546 /* Hold time for start condition (4us) */
1547 usec_delay(IXGBE_I2C_T_HD_STA);
1548
1549 ixgbe_lower_i2c_clk(hw, &i2cctl);
1550
1551 /* Minimum low period of clock is 4.7 us */
1552 usec_delay(IXGBE_I2C_T_LOW);
1553
1554 }
1555
1556 /**
1557 * ixgbe_i2c_stop - Sets I2C stop condition
1558 * @hw: pointer to hardware structure
1559 *
1560 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1561 **/
1562 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1563 {
1564 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1565
1566 DEBUGFUNC("ixgbe_i2c_stop");
1567
1568 /* Stop condition must begin with data low and clock high */
1569 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1570 ixgbe_raise_i2c_clk(hw, &i2cctl);
1571
1572 /* Setup time for stop condition (4us) */
1573 usec_delay(IXGBE_I2C_T_SU_STO);
1574
1575 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1576
1577 /* bus free time between stop and start (4.7us)*/
1578 usec_delay(IXGBE_I2C_T_BUF);
1579 }
1580
1581 /**
1582 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1583 * @hw: pointer to hardware structure
1584 * @data: data byte to clock in
1585 *
1586 * Clocks in one byte data via I2C data/clock
1587 **/
1588 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1589 {
1590 s32 i, status = IXGBE_SUCCESS;
1591 bool bit = 0;
1592
1593 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1594
1595 for (i = 7; i >= 0; i--) {
1596 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1597 if (status != IXGBE_SUCCESS)
1598 break;
1599 *data |= bit << i;
1600 }
1601
1602 return status;
1603 }
1604
1605 /**
1606 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1607 * @hw: pointer to hardware structure
1608 * @data: data byte clocked out
1609 *
1610 * Clocks out one byte data via I2C data/clock
1611 **/
1612 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1613 {
1614 s32 status = IXGBE_SUCCESS;
1615 s32 i;
1616 u32 i2cctl;
1617 bool bit = 0;
1618
1619 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1620
1621 for (i = 7; i >= 0; i--) {
1622 bit = (data >> i) & 0x1;
1849
1850 return data;
1851 }
1852
1853 /**
1854 * ixgbe_i2c_bus_clear - Clears the I2C bus
1855 * @hw: pointer to hardware structure
1856 *
1857 * Clears the I2C bus by sending nine clock pulses.
1858 * Used when data line is stuck low.
1859 **/
1860 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1861 {
1862 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1863 u32 i;
1864
1865 DEBUGFUNC("ixgbe_i2c_bus_clear");
1866
1867 ixgbe_i2c_start(hw);
1868
1869 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1870
1871 for (i = 0; i < 9; i++) {
1872 ixgbe_raise_i2c_clk(hw, &i2cctl);
1873
1874 /* Min high period of clock is 4us */
1875 usec_delay(IXGBE_I2C_T_HIGH);
1876
1877 ixgbe_lower_i2c_clk(hw, &i2cctl);
1878
1879 /* Min low period of clock is 4.7us*/
1880 usec_delay(IXGBE_I2C_T_LOW);
1881 }
1882
1883 ixgbe_i2c_start(hw);
1884
1885 /* Put the i2c bus back to default state */
1886 ixgbe_i2c_stop(hw);
1887 }
1888
1889 /**
|