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3014 Intel X540 Support (fix lint)
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--- old/usr/src/uts/common/io/ixgbe/ixgbe_api.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_api.c
1 1 /******************************************************************************
2 2
3 3 Copyright (c) 2001-2012, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34 34
35 35 #include "ixgbe_api.h"
36 36 #include "ixgbe_common.h"
37 37
38 38 /**
39 39 * ixgbe_init_shared_code - Initialize the shared code
40 40 * @hw: pointer to hardware structure
41 41 *
42 42 * This will assign function pointers and assign the MAC type and PHY code.
43 43 * Does not touch the hardware. This function must be called prior to any
44 44 * other function in the shared code. The ixgbe_hw structure should be
45 45 * memset to 0 prior to calling this function. The following fields in
46 46 * hw structure should be filled in prior to calling this function:
47 47 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
48 48 * subsystem_vendor_id, and revision_id
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49 49 **/
50 50 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
51 51 {
52 52 s32 status;
53 53
54 54 DEBUGFUNC("ixgbe_init_shared_code");
55 55
56 56 /*
57 57 * Set the mac type
58 58 */
59 - ixgbe_set_mac_type(hw);
59 + status = ixgbe_set_mac_type(hw);
60 + if (status != IXGBE_SUCCESS)
61 + return (status);
60 62
61 63 switch (hw->mac.type) {
62 64 case ixgbe_mac_82598EB:
63 65 status = ixgbe_init_ops_82598(hw);
64 66 break;
65 67 case ixgbe_mac_82599EB:
66 68 status = ixgbe_init_ops_82599(hw);
67 69 break;
68 70 case ixgbe_mac_X540:
69 71 status = ixgbe_init_ops_X540(hw);
70 72 break;
71 73 default:
72 74 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
73 75 break;
74 76 }
75 77
76 78 return status;
77 79 }
78 80
79 81 /**
80 82 * ixgbe_set_mac_type - Sets MAC type
81 83 * @hw: pointer to the HW structure
82 84 *
83 85 * This function sets the mac type of the adapter based on the
84 86 * vendor ID and device ID stored in the hw structure.
85 87 **/
86 88 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
87 89 {
88 90 s32 ret_val = IXGBE_SUCCESS;
89 91
90 92 DEBUGFUNC("ixgbe_set_mac_type\n");
91 93
92 94 if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
93 95 switch (hw->device_id) {
94 96 case IXGBE_DEV_ID_82598:
95 97 case IXGBE_DEV_ID_82598_BX:
96 98 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
97 99 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
98 100 case IXGBE_DEV_ID_82598AT:
99 101 case IXGBE_DEV_ID_82598AT2:
100 102 case IXGBE_DEV_ID_82598EB_CX4:
101 103 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
102 104 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
103 105 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
104 106 case IXGBE_DEV_ID_82598EB_XF_LR:
105 107 case IXGBE_DEV_ID_82598EB_SFP_LOM:
106 108 hw->mac.type = ixgbe_mac_82598EB;
107 109 break;
108 110 case IXGBE_DEV_ID_82599_KX4:
109 111 case IXGBE_DEV_ID_82599_KX4_MEZZ:
110 112 case IXGBE_DEV_ID_82599_XAUI_LOM:
111 113 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
112 114 case IXGBE_DEV_ID_82599_KR:
113 115 case IXGBE_DEV_ID_82599_SFP:
114 116 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
115 117 case IXGBE_DEV_ID_82599_SFP_FCOE:
116 118 case IXGBE_DEV_ID_82599_SFP_EM:
117 119 case IXGBE_DEV_ID_82599_SFP_SF2:
118 120 case IXGBE_DEV_ID_82599EN_SFP:
119 121 case IXGBE_DEV_ID_82599_CX4:
120 122 case IXGBE_DEV_ID_82599_T3_LOM:
121 123 hw->mac.type = ixgbe_mac_82599EB;
122 124 break;
123 125 case IXGBE_DEV_ID_82599_VF:
124 126 hw->mac.type = ixgbe_mac_82599_vf;
125 127 break;
126 128 case IXGBE_DEV_ID_X540_VF:
127 129 hw->mac.type = ixgbe_mac_X540_vf;
128 130 break;
129 131 case IXGBE_DEV_ID_X540T:
130 132 case IXGBE_DEV_ID_X540T1:
131 133 hw->mac.type = ixgbe_mac_X540;
132 134 break;
133 135 default:
134 136 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
135 137 break;
136 138 }
137 139 } else {
138 140 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
139 141 }
140 142
141 143 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
142 144 hw->mac.type, ret_val);
143 145 return ret_val;
144 146 }
145 147
146 148 /**
147 149 * ixgbe_init_hw - Initialize the hardware
148 150 * @hw: pointer to hardware structure
149 151 *
150 152 * Initialize the hardware by resetting and then starting the hardware
151 153 **/
152 154 s32 ixgbe_init_hw(struct ixgbe_hw *hw)
153 155 {
154 156 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
155 157 IXGBE_NOT_IMPLEMENTED);
156 158 }
157 159
158 160 /**
159 161 * ixgbe_reset_hw - Performs a hardware reset
160 162 * @hw: pointer to hardware structure
161 163 *
162 164 * Resets the hardware by resetting the transmit and receive units, masks and
163 165 * clears all interrupts, performs a PHY reset, and performs a MAC reset
164 166 **/
165 167 s32 ixgbe_reset_hw(struct ixgbe_hw *hw)
166 168 {
167 169 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),
168 170 IXGBE_NOT_IMPLEMENTED);
169 171 }
170 172
171 173 /**
172 174 * ixgbe_start_hw - Prepares hardware for Rx/Tx
173 175 * @hw: pointer to hardware structure
174 176 *
175 177 * Starts the hardware by filling the bus info structure and media type,
176 178 * clears all on chip counters, initializes receive address registers,
177 179 * multicast table, VLAN filter table, calls routine to setup link and
178 180 * flow control settings, and leaves transmit and receive units disabled
179 181 * and uninitialized.
180 182 **/
181 183 s32 ixgbe_start_hw(struct ixgbe_hw *hw)
182 184 {
183 185 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),
184 186 IXGBE_NOT_IMPLEMENTED);
185 187 }
186 188
187 189 /**
188 190 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,
189 191 * which is disabled by default in ixgbe_start_hw();
190 192 *
191 193 * @hw: pointer to hardware structure
192 194 *
193 195 * Enable relaxed ordering;
194 196 **/
195 197 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw)
196 198 {
197 199 if (hw->mac.ops.enable_relaxed_ordering)
198 200 hw->mac.ops.enable_relaxed_ordering(hw);
199 201 }
200 202
201 203 /**
202 204 * ixgbe_clear_hw_cntrs - Clear hardware counters
203 205 * @hw: pointer to hardware structure
204 206 *
205 207 * Clears all hardware statistics counters by reading them from the hardware
206 208 * Statistics counters are clear on read.
207 209 **/
208 210 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
209 211 {
210 212 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),
211 213 IXGBE_NOT_IMPLEMENTED);
212 214 }
213 215
214 216 /**
215 217 * ixgbe_get_media_type - Get media type
216 218 * @hw: pointer to hardware structure
217 219 *
218 220 * Returns the media type (fiber, copper, backplane)
219 221 **/
220 222 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)
221 223 {
222 224 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),
223 225 ixgbe_media_type_unknown);
224 226 }
225 227
226 228 /**
227 229 * ixgbe_get_mac_addr - Get MAC address
228 230 * @hw: pointer to hardware structure
229 231 * @mac_addr: Adapter MAC address
230 232 *
231 233 * Reads the adapter's MAC address from the first Receive Address Register
232 234 * (RAR0) A reset of the adapter must have been performed prior to calling
233 235 * this function in order for the MAC address to have been loaded from the
234 236 * EEPROM into RAR0
235 237 **/
236 238 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
237 239 {
238 240 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,
239 241 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
240 242 }
241 243
242 244 /**
243 245 * ixgbe_get_san_mac_addr - Get SAN MAC address
244 246 * @hw: pointer to hardware structure
245 247 * @san_mac_addr: SAN MAC address
246 248 *
247 249 * Reads the SAN MAC address from the EEPROM, if it's available. This is
248 250 * per-port, so set_lan_id() must be called before reading the addresses.
249 251 **/
250 252 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
251 253 {
252 254 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr,
253 255 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
254 256 }
255 257
256 258 /**
257 259 * ixgbe_set_san_mac_addr - Write a SAN MAC address
258 260 * @hw: pointer to hardware structure
259 261 * @san_mac_addr: SAN MAC address
260 262 *
261 263 * Writes A SAN MAC address to the EEPROM.
262 264 **/
263 265 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
264 266 {
265 267 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr,
266 268 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
267 269 }
268 270
269 271 /**
270 272 * ixgbe_get_device_caps - Get additional device capabilities
271 273 * @hw: pointer to hardware structure
272 274 * @device_caps: the EEPROM word for device capabilities
273 275 *
274 276 * Reads the extra device capabilities from the EEPROM
275 277 **/
276 278 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
277 279 {
278 280 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps,
279 281 (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
280 282 }
281 283
282 284 /**
283 285 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM
284 286 * @hw: pointer to hardware structure
285 287 * @wwnn_prefix: the alternative WWNN prefix
286 288 * @wwpn_prefix: the alternative WWPN prefix
287 289 *
288 290 * This function will read the EEPROM from the alternative SAN MAC address
289 291 * block to check the support for the alternative WWNN/WWPN prefix support.
290 292 **/
291 293 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
292 294 u16 *wwpn_prefix)
293 295 {
294 296 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,
295 297 (hw, wwnn_prefix, wwpn_prefix),
296 298 IXGBE_NOT_IMPLEMENTED);
297 299 }
298 300
299 301 /**
300 302 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM
301 303 * @hw: pointer to hardware structure
302 304 * @bs: the fcoe boot status
303 305 *
304 306 * This function will read the FCOE boot status from the iSCSI FCOE block
305 307 **/
306 308 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)
307 309 {
308 310 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status,
309 311 (hw, bs),
310 312 IXGBE_NOT_IMPLEMENTED);
311 313 }
312 314
313 315 /**
314 316 * ixgbe_get_bus_info - Set PCI bus info
315 317 * @hw: pointer to hardware structure
316 318 *
317 319 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
318 320 **/
319 321 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)
320 322 {
321 323 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),
322 324 IXGBE_NOT_IMPLEMENTED);
323 325 }
324 326
325 327 /**
326 328 * ixgbe_get_num_of_tx_queues - Get Tx queues
327 329 * @hw: pointer to hardware structure
328 330 *
329 331 * Returns the number of transmit queues for the given adapter.
330 332 **/
331 333 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
332 334 {
333 335 return hw->mac.max_tx_queues;
334 336 }
335 337
336 338 /**
337 339 * ixgbe_get_num_of_rx_queues - Get Rx queues
338 340 * @hw: pointer to hardware structure
339 341 *
340 342 * Returns the number of receive queues for the given adapter.
341 343 **/
342 344 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
343 345 {
344 346 return hw->mac.max_rx_queues;
345 347 }
346 348
347 349 /**
348 350 * ixgbe_stop_adapter - Disable Rx/Tx units
349 351 * @hw: pointer to hardware structure
350 352 *
351 353 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
352 354 * disables transmit and receive units. The adapter_stopped flag is used by
353 355 * the shared code and drivers to determine if the adapter is in a stopped
354 356 * state and should not touch the hardware.
355 357 **/
356 358 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
357 359 {
358 360 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),
359 361 IXGBE_NOT_IMPLEMENTED);
360 362 }
361 363
362 364 /**
363 365 * ixgbe_read_pba_string - Reads part number string from EEPROM
364 366 * @hw: pointer to hardware structure
365 367 * @pba_num: stores the part number string from the EEPROM
366 368 * @pba_num_size: part number string buffer length
367 369 *
368 370 * Reads the part number string from the EEPROM.
369 371 **/
370 372 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)
371 373 {
372 374 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);
373 375 }
374 376
375 377 /**
376 378 * ixgbe_read_pba_num - Reads part number from EEPROM
377 379 * @hw: pointer to hardware structure
378 380 * @pba_num: stores the part number from the EEPROM
379 381 *
380 382 * Reads the part number from the EEPROM.
381 383 **/
382 384 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)
383 385 {
384 386 return ixgbe_read_pba_num_generic(hw, pba_num);
385 387 }
386 388
387 389 /**
388 390 * ixgbe_identify_phy - Get PHY type
389 391 * @hw: pointer to hardware structure
390 392 *
391 393 * Determines the physical layer module found on the current adapter.
392 394 **/
393 395 s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
394 396 {
395 397 s32 status = IXGBE_SUCCESS;
396 398
397 399 if (hw->phy.type == ixgbe_phy_unknown) {
398 400 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),
399 401 IXGBE_NOT_IMPLEMENTED);
400 402 }
401 403
402 404 return status;
403 405 }
404 406
405 407 /**
406 408 * ixgbe_reset_phy - Perform a PHY reset
407 409 * @hw: pointer to hardware structure
408 410 **/
409 411 s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
410 412 {
411 413 s32 status = IXGBE_SUCCESS;
412 414
413 415 if (hw->phy.type == ixgbe_phy_unknown) {
414 416 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS)
415 417 status = IXGBE_ERR_PHY;
416 418 }
417 419
418 420 if (status == IXGBE_SUCCESS) {
419 421 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),
420 422 IXGBE_NOT_IMPLEMENTED);
421 423 }
422 424 return status;
423 425 }
424 426
425 427 /**
426 428 * ixgbe_get_phy_firmware_version -
427 429 * @hw: pointer to hardware structure
428 430 * @firmware_version: pointer to firmware version
429 431 **/
430 432 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)
431 433 {
432 434 s32 status = IXGBE_SUCCESS;
433 435
434 436 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
435 437 (hw, firmware_version),
436 438 IXGBE_NOT_IMPLEMENTED);
437 439 return status;
438 440 }
439 441
440 442 /**
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441 443 * ixgbe_read_phy_reg - Read PHY register
442 444 * @hw: pointer to hardware structure
443 445 * @reg_addr: 32 bit address of PHY register to read
444 446 * @phy_data: Pointer to read data from PHY register
445 447 *
446 448 * Reads a value from a specified PHY register
447 449 **/
448 450 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
449 451 u16 *phy_data)
450 452 {
453 + s32 status;
454 +
451 455 if (hw->phy.id == 0)
452 - ixgbe_identify_phy(hw);
456 + status = ixgbe_identify_phy(hw);
457 + else
458 + status = IXGBE_SUCCESS;
453 459
454 - return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
455 - device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
460 + if (status == IXGBE_SUCCESS) {
461 + status = ixgbe_call_func(hw, hw->phy.ops.read_reg,
462 + (hw, reg_addr, device_type, phy_data),
463 + IXGBE_NOT_IMPLEMENTED);
464 + }
465 + return (status);
456 466 }
457 467
458 468 /**
459 469 * ixgbe_write_phy_reg - Write PHY register
460 470 * @hw: pointer to hardware structure
461 471 * @reg_addr: 32 bit PHY register to write
462 472 * @phy_data: Data to write to the PHY register
463 473 *
464 474 * Writes a value to specified PHY register
465 475 **/
466 476 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
467 477 u16 phy_data)
468 478 {
479 + s32 status;
480 +
469 481 if (hw->phy.id == 0)
470 - ixgbe_identify_phy(hw);
482 + status = ixgbe_identify_phy(hw);
483 + else
484 + status = IXGBE_SUCCESS;
471 485
472 - return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
473 - device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
486 + if (status == IXGBE_SUCCESS) {
487 + status = ixgbe_call_func(hw, hw->phy.ops.write_reg,
488 + (hw, reg_addr, device_type, phy_data),
489 + IXGBE_NOT_IMPLEMENTED);
490 + }
491 +
492 + return status;
474 493 }
475 494
476 495 /**
477 496 * ixgbe_setup_phy_link - Restart PHY autoneg
478 497 * @hw: pointer to hardware structure
479 498 *
480 499 * Restart autonegotiation and PHY and waits for completion.
481 500 **/
482 501 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
483 502 {
484 503 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
485 504 IXGBE_NOT_IMPLEMENTED);
486 505 }
487 506
488 507 /**
489 508 * ixgbe_check_phy_link - Determine link and speed status
490 509 * @hw: pointer to hardware structure
491 510 *
492 511 * Reads a PHY register to determine if link is up and the current speed for
493 512 * the PHY.
494 513 **/
495 514 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
496 515 bool *link_up)
497 516 {
498 517 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
499 518 link_up), IXGBE_NOT_IMPLEMENTED);
500 519 }
501 520
502 521 /**
503 522 * ixgbe_setup_phy_link_speed - Set auto advertise
504 523 * @hw: pointer to hardware structure
505 524 * @speed: new link speed
506 525 * @autoneg: TRUE if autonegotiation enabled
507 526 *
508 527 * Sets the auto advertised capabilities
509 528 **/
510 529 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
511 530 bool autoneg,
512 531 bool autoneg_wait_to_complete)
513 532 {
514 533 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
515 534 autoneg, autoneg_wait_to_complete),
516 535 IXGBE_NOT_IMPLEMENTED);
517 536 }
518 537
519 538 /**
520 539 * ixgbe_check_link - Get link and speed status
521 540 * @hw: pointer to hardware structure
522 541 *
523 542 * Reads the links register to determine if link is up and the current speed
524 543 **/
525 544 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
526 545 bool *link_up, bool link_up_wait_to_complete)
527 546 {
528 547 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
529 548 link_up, link_up_wait_to_complete),
530 549 IXGBE_NOT_IMPLEMENTED);
531 550 }
532 551
533 552 /**
534 553 * ixgbe_disable_tx_laser - Disable Tx laser
535 554 * @hw: pointer to hardware structure
536 555 *
537 556 * If the driver needs to disable the laser on SFI optics.
538 557 **/
539 558 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)
540 559 {
541 560 if (hw->mac.ops.disable_tx_laser)
542 561 hw->mac.ops.disable_tx_laser(hw);
543 562 }
544 563
545 564 /**
546 565 * ixgbe_enable_tx_laser - Enable Tx laser
547 566 * @hw: pointer to hardware structure
548 567 *
549 568 * If the driver needs to enable the laser on SFI optics.
550 569 **/
551 570 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw)
552 571 {
553 572 if (hw->mac.ops.enable_tx_laser)
554 573 hw->mac.ops.enable_tx_laser(hw);
555 574 }
556 575
557 576 /**
558 577 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process
559 578 * @hw: pointer to hardware structure
560 579 *
561 580 * When the driver changes the link speeds that it can support then
562 581 * flap the tx laser to alert the link partner to start autotry
563 582 * process on its end.
564 583 **/
565 584 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
566 585 {
567 586 if (hw->mac.ops.flap_tx_laser)
568 587 hw->mac.ops.flap_tx_laser(hw);
569 588 }
570 589
571 590 /**
572 591 * ixgbe_setup_link - Set link speed
573 592 * @hw: pointer to hardware structure
574 593 * @speed: new link speed
575 594 * @autoneg: TRUE if autonegotiation enabled
576 595 *
577 596 * Configures link settings. Restarts the link.
578 597 * Performs autonegotiation if needed.
579 598 **/
580 599 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
581 600 bool autoneg,
582 601 bool autoneg_wait_to_complete)
583 602 {
584 603 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
585 604 autoneg, autoneg_wait_to_complete),
586 605 IXGBE_NOT_IMPLEMENTED);
587 606 }
588 607
589 608 /**
590 609 * ixgbe_get_link_capabilities - Returns link capabilities
591 610 * @hw: pointer to hardware structure
592 611 *
593 612 * Determines the link capabilities of the current configuration.
594 613 **/
595 614 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
596 615 bool *autoneg)
597 616 {
598 617 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
599 618 speed, autoneg), IXGBE_NOT_IMPLEMENTED);
600 619 }
601 620
602 621 /**
603 622 * ixgbe_led_on - Turn on LEDs
604 623 * @hw: pointer to hardware structure
605 624 * @index: led number to turn on
606 625 *
607 626 * Turns on the software controllable LEDs.
608 627 **/
609 628 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
610 629 {
611 630 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),
612 631 IXGBE_NOT_IMPLEMENTED);
613 632 }
614 633
615 634 /**
616 635 * ixgbe_led_off - Turn off LEDs
617 636 * @hw: pointer to hardware structure
618 637 * @index: led number to turn off
619 638 *
620 639 * Turns off the software controllable LEDs.
621 640 **/
622 641 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
623 642 {
624 643 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),
625 644 IXGBE_NOT_IMPLEMENTED);
626 645 }
627 646
628 647 /**
629 648 * ixgbe_blink_led_start - Blink LEDs
630 649 * @hw: pointer to hardware structure
631 650 * @index: led number to blink
632 651 *
633 652 * Blink LED based on index.
634 653 **/
635 654 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
636 655 {
637 656 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),
638 657 IXGBE_NOT_IMPLEMENTED);
639 658 }
640 659
641 660 /**
642 661 * ixgbe_blink_led_stop - Stop blinking LEDs
643 662 * @hw: pointer to hardware structure
644 663 *
645 664 * Stop blinking LED based on index.
646 665 **/
647 666 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
648 667 {
649 668 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),
650 669 IXGBE_NOT_IMPLEMENTED);
651 670 }
652 671
653 672 /**
654 673 * ixgbe_init_eeprom_params - Initialize EEPROM parameters
655 674 * @hw: pointer to hardware structure
656 675 *
657 676 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
658 677 * ixgbe_hw struct in order to set up EEPROM access.
659 678 **/
660 679 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
661 680 {
662 681 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),
663 682 IXGBE_NOT_IMPLEMENTED);
664 683 }
665 684
666 685
667 686 /**
668 687 * ixgbe_write_eeprom - Write word to EEPROM
669 688 * @hw: pointer to hardware structure
670 689 * @offset: offset within the EEPROM to be written to
671 690 * @data: 16 bit word to be written to the EEPROM
672 691 *
673 692 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
674 693 * called after this function, the EEPROM will most likely contain an
675 694 * invalid checksum.
676 695 **/
677 696 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
678 697 {
679 698 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),
680 699 IXGBE_NOT_IMPLEMENTED);
681 700 }
682 701
683 702 /**
684 703 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM
685 704 * @hw: pointer to hardware structure
686 705 * @offset: offset within the EEPROM to be written to
687 706 * @data: 16 bit word(s) to be written to the EEPROM
688 707 * @words: number of words
689 708 *
690 709 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not
691 710 * called after this function, the EEPROM will most likely contain an
692 711 * invalid checksum.
693 712 **/
694 713 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,
695 714 u16 *data)
696 715 {
697 716 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer,
698 717 (hw, offset, words, data),
699 718 IXGBE_NOT_IMPLEMENTED);
700 719 }
701 720
702 721 /**
703 722 * ixgbe_read_eeprom - Read word from EEPROM
704 723 * @hw: pointer to hardware structure
705 724 * @offset: offset within the EEPROM to be read
706 725 * @data: read 16 bit value from EEPROM
707 726 *
708 727 * Reads 16 bit value from EEPROM
709 728 **/
710 729 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
711 730 {
712 731 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),
713 732 IXGBE_NOT_IMPLEMENTED);
714 733 }
715 734
716 735 /**
717 736 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM
718 737 * @hw: pointer to hardware structure
719 738 * @offset: offset within the EEPROM to be read
720 739 * @data: read 16 bit word(s) from EEPROM
721 740 * @words: number of words
722 741 *
723 742 * Reads 16 bit word(s) from EEPROM
724 743 **/
725 744 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
726 745 u16 words, u16 *data)
727 746 {
728 747 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer,
729 748 (hw, offset, words, data),
730 749 IXGBE_NOT_IMPLEMENTED);
731 750 }
732 751
733 752 /**
734 753 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
735 754 * @hw: pointer to hardware structure
736 755 * @checksum_val: calculated checksum
737 756 *
738 757 * Performs checksum calculation and validates the EEPROM checksum
739 758 **/
740 759 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
741 760 {
742 761 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,
743 762 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
744 763 }
745 764
746 765 /**
747 766 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
748 767 * @hw: pointer to hardware structure
749 768 **/
750 769 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
751 770 {
752 771 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),
753 772 IXGBE_NOT_IMPLEMENTED);
754 773 }
755 774
756 775 /**
757 776 * ixgbe_insert_mac_addr - Find a RAR for this mac address
758 777 * @hw: pointer to hardware structure
759 778 * @addr: Address to put into receive address register
760 779 * @vmdq: VMDq pool to assign
761 780 *
762 781 * Puts an ethernet address into a receive address register, or
763 782 * finds the rar that it is aleady in; adds to the pool list
764 783 **/
765 784 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
766 785 {
767 786 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr,
768 787 (hw, addr, vmdq),
769 788 IXGBE_NOT_IMPLEMENTED);
770 789 }
771 790
772 791 /**
773 792 * ixgbe_set_rar - Set Rx address register
774 793 * @hw: pointer to hardware structure
775 794 * @index: Receive address register to write
776 795 * @addr: Address to put into receive address register
777 796 * @vmdq: VMDq "set"
778 797 * @enable_addr: set flag that address is active
779 798 *
780 799 * Puts an ethernet address into a receive address register.
781 800 **/
782 801 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
783 802 u32 enable_addr)
784 803 {
785 804 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,
786 805 enable_addr), IXGBE_NOT_IMPLEMENTED);
787 806 }
788 807
789 808 /**
790 809 * ixgbe_clear_rar - Clear Rx address register
791 810 * @hw: pointer to hardware structure
792 811 * @index: Receive address register to write
793 812 *
794 813 * Puts an ethernet address into a receive address register.
795 814 **/
796 815 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
797 816 {
798 817 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),
799 818 IXGBE_NOT_IMPLEMENTED);
800 819 }
801 820
802 821 /**
803 822 * ixgbe_set_vmdq - Associate a VMDq index with a receive address
804 823 * @hw: pointer to hardware structure
805 824 * @rar: receive address register index to associate with VMDq index
806 825 * @vmdq: VMDq set or pool index
807 826 **/
808 827 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
809 828 {
810 829 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
811 830 IXGBE_NOT_IMPLEMENTED);
812 831
813 832 }
814 833
815 834 /**
816 835 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
817 836 * @hw: pointer to hardware structure
818 837 * @vmdq: VMDq default pool index
819 838 **/
820 839 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)
821 840 {
822 841 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,
823 842 (hw, vmdq), IXGBE_NOT_IMPLEMENTED);
824 843 }
825 844
826 845 /**
827 846 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
828 847 * @hw: pointer to hardware structure
829 848 * @rar: receive address register index to disassociate with VMDq index
830 849 * @vmdq: VMDq set or pool index
831 850 **/
832 851 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
833 852 {
834 853 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),
835 854 IXGBE_NOT_IMPLEMENTED);
836 855 }
837 856
838 857 /**
839 858 * ixgbe_init_rx_addrs - Initializes receive address filters.
840 859 * @hw: pointer to hardware structure
841 860 *
842 861 * Places the MAC address in receive address register 0 and clears the rest
843 862 * of the receive address registers. Clears the multicast table. Assumes
844 863 * the receiver is in reset when the routine is called.
845 864 **/
846 865 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
847 866 {
848 867 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),
849 868 IXGBE_NOT_IMPLEMENTED);
850 869 }
851 870
852 871 /**
853 872 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
854 873 * @hw: pointer to hardware structure
855 874 **/
856 875 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)
857 876 {
858 877 return hw->mac.num_rar_entries;
859 878 }
860 879
861 880 /**
862 881 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses
863 882 * @hw: pointer to hardware structure
864 883 * @addr_list: the list of new multicast addresses
865 884 * @addr_count: number of addresses
866 885 * @func: iterator function to walk the multicast address list
867 886 *
868 887 * The given list replaces any existing list. Clears the secondary addrs from
869 888 * receive address registers. Uses unused receive address registers for the
870 889 * first secondary addresses, and falls back to promiscuous mode as needed.
871 890 **/
872 891 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
873 892 u32 addr_count, ixgbe_mc_addr_itr func)
874 893 {
875 894 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,
876 895 addr_list, addr_count, func),
877 896 IXGBE_NOT_IMPLEMENTED);
878 897 }
879 898
880 899 /**
881 900 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
882 901 * @hw: pointer to hardware structure
883 902 * @mc_addr_list: the list of new multicast addresses
884 903 * @mc_addr_count: number of addresses
885 904 * @func: iterator function to walk the multicast address list
886 905 *
887 906 * The given list replaces any existing list. Clears the MC addrs from receive
888 907 * address registers and the multicast table. Uses unused receive address
889 908 * registers for the first multicast addresses, and hashes the rest into the
890 909 * multicast table.
891 910 **/
892 911 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
893 912 u32 mc_addr_count, ixgbe_mc_addr_itr func,
894 913 bool clear)
895 914 {
896 915 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
897 916 mc_addr_list, mc_addr_count, func, clear),
898 917 IXGBE_NOT_IMPLEMENTED);
899 918 }
900 919
901 920 /**
902 921 * ixgbe_enable_mc - Enable multicast address in RAR
903 922 * @hw: pointer to hardware structure
904 923 *
905 924 * Enables multicast address in RAR and the use of the multicast hash table.
906 925 **/
907 926 s32 ixgbe_enable_mc(struct ixgbe_hw *hw)
908 927 {
909 928 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),
910 929 IXGBE_NOT_IMPLEMENTED);
911 930 }
912 931
913 932 /**
914 933 * ixgbe_disable_mc - Disable multicast address in RAR
915 934 * @hw: pointer to hardware structure
916 935 *
917 936 * Disables multicast address in RAR and the use of the multicast hash table.
918 937 **/
919 938 s32 ixgbe_disable_mc(struct ixgbe_hw *hw)
920 939 {
921 940 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),
922 941 IXGBE_NOT_IMPLEMENTED);
923 942 }
924 943
925 944 /**
926 945 * ixgbe_clear_vfta - Clear VLAN filter table
927 946 * @hw: pointer to hardware structure
928 947 *
929 948 * Clears the VLAN filer table, and the VMDq index associated with the filter
930 949 **/
931 950 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
932 951 {
933 952 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
934 953 IXGBE_NOT_IMPLEMENTED);
935 954 }
936 955
937 956 /**
938 957 * ixgbe_set_vfta - Set VLAN filter table
939 958 * @hw: pointer to hardware structure
940 959 * @vlan: VLAN id to write to VLAN filter
941 960 * @vind: VMDq output index that maps queue to VLAN id in VFTA
942 961 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
943 962 *
944 963 * Turn on/off specified VLAN in the VLAN filter table.
945 964 **/
946 965 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
947 966 {
948 967 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
949 968 vlan_on), IXGBE_NOT_IMPLEMENTED);
950 969 }
951 970
952 971 /**
953 972 * ixgbe_set_vlvf - Set VLAN Pool Filter
954 973 * @hw: pointer to hardware structure
955 974 * @vlan: VLAN id to write to VLAN filter
956 975 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
957 976 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
958 977 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
959 978 * should be changed
960 979 *
961 980 * Turn on/off specified bit in VLVF table.
962 981 **/
963 982 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
964 983 bool *vfta_changed)
965 984 {
966 985 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
967 986 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);
968 987 }
969 988
970 989 /**
971 990 * ixgbe_fc_enable - Enable flow control
972 991 * @hw: pointer to hardware structure
973 992 *
974 993 * Configures the flow control settings based on SW configuration.
975 994 **/
976 995 s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
977 996 {
978 997 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
979 998 IXGBE_NOT_IMPLEMENTED);
980 999 }
981 1000
982 1001 /**
983 1002 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
984 1003 * @hw: pointer to hardware structure
985 1004 * @maj: driver major number to be sent to firmware
986 1005 * @min: driver minor number to be sent to firmware
987 1006 * @build: driver build number to be sent to firmware
988 1007 * @ver: driver version number to be sent to firmware
989 1008 **/
990 1009 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
991 1010 u8 ver)
992 1011 {
993 1012 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
994 1013 build, ver), IXGBE_NOT_IMPLEMENTED);
995 1014 }
996 1015
997 1016
998 1017 /**
999 1018 * ixgbe_read_analog_reg8 - Reads 8 bit analog register
1000 1019 * @hw: pointer to hardware structure
1001 1020 * @reg: analog register to read
1002 1021 * @val: read value
1003 1022 *
1004 1023 * Performs write operation to analog register specified.
1005 1024 **/
1006 1025 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
1007 1026 {
1008 1027 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
1009 1028 val), IXGBE_NOT_IMPLEMENTED);
1010 1029 }
1011 1030
1012 1031 /**
1013 1032 * ixgbe_write_analog_reg8 - Writes 8 bit analog register
1014 1033 * @hw: pointer to hardware structure
1015 1034 * @reg: analog register to write
1016 1035 * @val: value to write
1017 1036 *
1018 1037 * Performs write operation to Atlas analog register specified.
1019 1038 **/
1020 1039 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
1021 1040 {
1022 1041 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,
1023 1042 val), IXGBE_NOT_IMPLEMENTED);
1024 1043 }
1025 1044
1026 1045 /**
1027 1046 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
1028 1047 * @hw: pointer to hardware structure
1029 1048 *
1030 1049 * Initializes the Unicast Table Arrays to zero on device load. This
1031 1050 * is part of the Rx init addr execution path.
1032 1051 **/
1033 1052 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
1034 1053 {
1035 1054 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
1036 1055 IXGBE_NOT_IMPLEMENTED);
1037 1056 }
1038 1057
1039 1058 /**
1040 1059 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
1041 1060 * @hw: pointer to hardware structure
1042 1061 * @byte_offset: byte offset to read
1043 1062 * @data: value read
1044 1063 *
1045 1064 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1046 1065 **/
1047 1066 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1048 1067 u8 *data)
1049 1068 {
1050 1069 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,
1051 1070 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1052 1071 }
1053 1072
1054 1073 /**
1055 1074 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
1056 1075 * @hw: pointer to hardware structure
1057 1076 * @byte_offset: byte offset to write
1058 1077 * @data: value to write
1059 1078 *
1060 1079 * Performs byte write operation to SFP module's EEPROM over I2C interface
1061 1080 * at a specified device address.
1062 1081 **/
1063 1082 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1064 1083 u8 data)
1065 1084 {
1066 1085 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,
1067 1086 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1068 1087 }
1069 1088
1070 1089 /**
1071 1090 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1072 1091 * @hw: pointer to hardware structure
1073 1092 * @byte_offset: EEPROM byte offset to write
1074 1093 * @eeprom_data: value to write
1075 1094 *
1076 1095 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1077 1096 **/
1078 1097 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,
1079 1098 u8 byte_offset, u8 eeprom_data)
1080 1099 {
1081 1100 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,
1082 1101 (hw, byte_offset, eeprom_data),
1083 1102 IXGBE_NOT_IMPLEMENTED);
1084 1103 }
1085 1104
1086 1105 /**
1087 1106 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1088 1107 * @hw: pointer to hardware structure
1089 1108 * @byte_offset: EEPROM byte offset to read
1090 1109 * @eeprom_data: value read
1091 1110 *
1092 1111 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1093 1112 **/
1094 1113 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
1095 1114 {
1096 1115 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,
1097 1116 (hw, byte_offset, eeprom_data),
1098 1117 IXGBE_NOT_IMPLEMENTED);
1099 1118 }
1100 1119
1101 1120 /**
1102 1121 * ixgbe_get_supported_physical_layer - Returns physical layer type
1103 1122 * @hw: pointer to hardware structure
1104 1123 *
1105 1124 * Determines physical layer capabilities of the current configuration.
1106 1125 **/
1107 1126 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
1108 1127 {
1109 1128 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
1110 1129 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
1111 1130 }
1112 1131
1113 1132 /**
1114 1133 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
1115 1134 * @hw: pointer to hardware structure
1116 1135 * @regval: bitfield to write to the Rx DMA register
1117 1136 *
1118 1137 * Enables the Rx DMA unit of the device.
1119 1138 **/
1120 1139 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)
1121 1140 {
1122 1141 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
1123 1142 (hw, regval), IXGBE_NOT_IMPLEMENTED);
1124 1143 }
1125 1144
1126 1145 /**
1127 1146 * ixgbe_disable_sec_rx_path - Stops the receive data path
1128 1147 * @hw: pointer to hardware structure
1129 1148 *
1130 1149 * Stops the receive data path.
1131 1150 **/
1132 1151 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)
1133 1152 {
1134 1153 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path,
1135 1154 (hw), IXGBE_NOT_IMPLEMENTED);
1136 1155 }
1137 1156
1138 1157 /**
1139 1158 * ixgbe_enable_sec_rx_path - Enables the receive data path
1140 1159 * @hw: pointer to hardware structure
1141 1160 *
1142 1161 * Enables the receive data path.
1143 1162 **/
1144 1163 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)
1145 1164 {
1146 1165 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,
1147 1166 (hw), IXGBE_NOT_IMPLEMENTED);
1148 1167 }
1149 1168
1150 1169 /**
1151 1170 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
1152 1171 * @hw: pointer to hardware structure
1153 1172 * @mask: Mask to specify which semaphore to acquire
1154 1173 *
1155 1174 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
1156 1175 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1157 1176 **/
1158 1177 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
1159 1178 {
1160 1179 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
1161 1180 (hw, mask), IXGBE_NOT_IMPLEMENTED);
1162 1181 }
1163 1182
1164 1183 /**
1165 1184 * ixgbe_release_swfw_semaphore - Release SWFW semaphore
1166 1185 * @hw: pointer to hardware structure
1167 1186 * @mask: Mask to specify which semaphore to release
1168 1187 *
1169 1188 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified
1170 1189 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1171 1190 **/
1172 1191 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
1173 1192 {
1174 1193 if (hw->mac.ops.release_swfw_sync)
1175 1194 hw->mac.ops.release_swfw_sync(hw, mask);
1176 1195 }
1177 1196
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