39 * ixgbe_init_shared_code - Initialize the shared code
40 * @hw: pointer to hardware structure
41 *
42 * This will assign function pointers and assign the MAC type and PHY code.
43 * Does not touch the hardware. This function must be called prior to any
44 * other function in the shared code. The ixgbe_hw structure should be
45 * memset to 0 prior to calling this function. The following fields in
46 * hw structure should be filled in prior to calling this function:
47 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
48 * subsystem_vendor_id, and revision_id
49 **/
50 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
51 {
52 s32 status;
53
54 DEBUGFUNC("ixgbe_init_shared_code");
55
56 /*
57 * Set the mac type
58 */
59 ixgbe_set_mac_type(hw);
60
61 switch (hw->mac.type) {
62 case ixgbe_mac_82598EB:
63 status = ixgbe_init_ops_82598(hw);
64 break;
65 case ixgbe_mac_82599EB:
66 status = ixgbe_init_ops_82599(hw);
67 break;
68 case ixgbe_mac_X540:
69 status = ixgbe_init_ops_X540(hw);
70 break;
71 default:
72 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
73 break;
74 }
75
76 return status;
77 }
78
79 /**
431 {
432 s32 status = IXGBE_SUCCESS;
433
434 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
435 (hw, firmware_version),
436 IXGBE_NOT_IMPLEMENTED);
437 return status;
438 }
439
440 /**
441 * ixgbe_read_phy_reg - Read PHY register
442 * @hw: pointer to hardware structure
443 * @reg_addr: 32 bit address of PHY register to read
444 * @phy_data: Pointer to read data from PHY register
445 *
446 * Reads a value from a specified PHY register
447 **/
448 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
449 u16 *phy_data)
450 {
451 if (hw->phy.id == 0)
452 ixgbe_identify_phy(hw);
453
454 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr,
455 device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
456 }
457
458 /**
459 * ixgbe_write_phy_reg - Write PHY register
460 * @hw: pointer to hardware structure
461 * @reg_addr: 32 bit PHY register to write
462 * @phy_data: Data to write to the PHY register
463 *
464 * Writes a value to specified PHY register
465 **/
466 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
467 u16 phy_data)
468 {
469 if (hw->phy.id == 0)
470 ixgbe_identify_phy(hw);
471
472 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr,
473 device_type, phy_data), IXGBE_NOT_IMPLEMENTED);
474 }
475
476 /**
477 * ixgbe_setup_phy_link - Restart PHY autoneg
478 * @hw: pointer to hardware structure
479 *
480 * Restart autonegotiation and PHY and waits for completion.
481 **/
482 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
483 {
484 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
485 IXGBE_NOT_IMPLEMENTED);
486 }
487
488 /**
489 * ixgbe_check_phy_link - Determine link and speed status
490 * @hw: pointer to hardware structure
491 *
492 * Reads a PHY register to determine if link is up and the current speed for
493 * the PHY.
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39 * ixgbe_init_shared_code - Initialize the shared code
40 * @hw: pointer to hardware structure
41 *
42 * This will assign function pointers and assign the MAC type and PHY code.
43 * Does not touch the hardware. This function must be called prior to any
44 * other function in the shared code. The ixgbe_hw structure should be
45 * memset to 0 prior to calling this function. The following fields in
46 * hw structure should be filled in prior to calling this function:
47 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
48 * subsystem_vendor_id, and revision_id
49 **/
50 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
51 {
52 s32 status;
53
54 DEBUGFUNC("ixgbe_init_shared_code");
55
56 /*
57 * Set the mac type
58 */
59 status = ixgbe_set_mac_type(hw);
60 if (status != IXGBE_SUCCESS)
61 return (status);
62
63 switch (hw->mac.type) {
64 case ixgbe_mac_82598EB:
65 status = ixgbe_init_ops_82598(hw);
66 break;
67 case ixgbe_mac_82599EB:
68 status = ixgbe_init_ops_82599(hw);
69 break;
70 case ixgbe_mac_X540:
71 status = ixgbe_init_ops_X540(hw);
72 break;
73 default:
74 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
75 break;
76 }
77
78 return status;
79 }
80
81 /**
433 {
434 s32 status = IXGBE_SUCCESS;
435
436 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
437 (hw, firmware_version),
438 IXGBE_NOT_IMPLEMENTED);
439 return status;
440 }
441
442 /**
443 * ixgbe_read_phy_reg - Read PHY register
444 * @hw: pointer to hardware structure
445 * @reg_addr: 32 bit address of PHY register to read
446 * @phy_data: Pointer to read data from PHY register
447 *
448 * Reads a value from a specified PHY register
449 **/
450 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
451 u16 *phy_data)
452 {
453 s32 status;
454
455 if (hw->phy.id == 0)
456 status = ixgbe_identify_phy(hw);
457 else
458 status = IXGBE_SUCCESS;
459
460 if (status == IXGBE_SUCCESS) {
461 status = ixgbe_call_func(hw, hw->phy.ops.read_reg,
462 (hw, reg_addr, device_type, phy_data),
463 IXGBE_NOT_IMPLEMENTED);
464 }
465 return (status);
466 }
467
468 /**
469 * ixgbe_write_phy_reg - Write PHY register
470 * @hw: pointer to hardware structure
471 * @reg_addr: 32 bit PHY register to write
472 * @phy_data: Data to write to the PHY register
473 *
474 * Writes a value to specified PHY register
475 **/
476 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
477 u16 phy_data)
478 {
479 s32 status;
480
481 if (hw->phy.id == 0)
482 status = ixgbe_identify_phy(hw);
483 else
484 status = IXGBE_SUCCESS;
485
486 if (status == IXGBE_SUCCESS) {
487 status = ixgbe_call_func(hw, hw->phy.ops.write_reg,
488 (hw, reg_addr, device_type, phy_data),
489 IXGBE_NOT_IMPLEMENTED);
490 }
491
492 return status;
493 }
494
495 /**
496 * ixgbe_setup_phy_link - Restart PHY autoneg
497 * @hw: pointer to hardware structure
498 *
499 * Restart autonegotiation and PHY and waits for completion.
500 **/
501 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
502 {
503 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
504 IXGBE_NOT_IMPLEMENTED);
505 }
506
507 /**
508 * ixgbe_check_phy_link - Determine link and speed status
509 * @hw: pointer to hardware structure
510 *
511 * Reads a PHY register to determine if link is up and the current speed for
512 * the PHY.
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