3014 Intel X540 Support (fix lint)

@@ -950,12 +950,15 @@
         DEBUGFUNC("ixgbe_setup_copper_link_82599");
 
         /* Setup the PHY according to input speed */
         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
                                               autoneg_wait_to_complete);
+        if (status == IXGBE_SUCCESS) {
         /* Set up MAC */
+                status =
         ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
+        }
 
         return status;
 }
 
 /**

@@ -1172,15 +1175,15 @@
                 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
                 return IXGBE_ERR_FDIR_REINIT_FAILED;
         }
 
         /* Clear FDIR statistics registers (read to clear) */
-        IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
-        IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
-        IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
-        IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
-        IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
+        (void) IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
+        (void) IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
+        (void) IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
+        (void) IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
+        (void) IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
 
         return IXGBE_SUCCESS;
 }
 
 /**

@@ -1287,10 +1290,13 @@
  * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
  * for values 0 through 15
  */
 #define IXGBE_ATR_COMMON_HASH_KEY \
                 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
+#if lint
+#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n)
+#else
 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
 do { \
         u32 n = (_n); \
         if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
                 common_hash ^= lo_hash_dword >> n; \

@@ -1303,10 +1309,11 @@
         else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
                 bucket_hash ^= hi_hash_dword >> n; \
         else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
                 sig_hash ^= hi_hash_dword << (16 - n); \
 } while (0);
+#endif
 
 /**
  *  ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
  *  @stream: input bitstream to compute the hash on
  *

@@ -1423,19 +1430,22 @@
         DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
 
         return IXGBE_SUCCESS;
 }
 
+#if lint
+#define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n)
+#else
 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
 do { \
         u32 n = (_n); \
         if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
                 bucket_hash ^= lo_hash_dword >> n; \
         if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
                 bucket_hash ^= hi_hash_dword >> n; \
 } while (0);
-
+#endif
 /**
  *  ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
  *  @atr_input: input bitstream to compute the hash on
  *  @input_mask: mask for the input bitstream
  *

@@ -1582,10 +1592,11 @@
 
         /* Program FDIRM and verify partial masks */
         switch (input_mask->formatted.vm_pool & 0x7F) {
         case 0x0:
                 fdirm |= IXGBE_FDIRM_POOL;
+                /* FALLTHRU */
         case 0x7F:
                 break;
         default:
                 DEBUGOUT(" Error on vm pool mask\n");
                 return IXGBE_ERR_CONFIG;

@@ -1597,10 +1608,11 @@
                 if (input_mask->formatted.dst_port ||
                     input_mask->formatted.src_port) {
                         DEBUGOUT(" Error on src/dst port mask\n");
                         return IXGBE_ERR_CONFIG;
                 }
+                /* FALLTHRU */
         case IXGBE_ATR_L4TYPE_MASK:
                 break;
         default:
                 DEBUGOUT(" Error on flow type mask\n");
                 return IXGBE_ERR_CONFIG;

@@ -1608,17 +1620,19 @@
 
         switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
         case 0x0000:
                 /* mask VLAN ID, fall through to mask VLAN priority */
                 fdirm |= IXGBE_FDIRM_VLANID;
+                /* FALLTHRU */
         case 0x0FFF:
                 /* mask VLAN priority */
                 fdirm |= IXGBE_FDIRM_VLANP;
                 break;
         case 0xE000:
                 /* mask VLAN ID only, fall through */
                 fdirm |= IXGBE_FDIRM_VLANID;
+                /* FALLTHRU */
         case 0xEFFF:
                 /* no VLAN fields masked */
                 break;
         default:
                 DEBUGOUT(" Error on VLAN mask\n");

@@ -1627,10 +1641,11 @@
 
         switch (input_mask->formatted.flex_bytes & 0xFFFF) {
         case 0x0000:
                 /* Mask Flex Bytes, fall through */
                 fdirm |= IXGBE_FDIRM_FLEX;
+                /* FALLTHRU */
         case 0xFFFF:
                 break;
         default:
                 DEBUGOUT(" Error on flexible byte mask\n");
                 return IXGBE_ERR_CONFIG;

@@ -1792,10 +1807,11 @@
         case IXGBE_ATR_FLOW_TYPE_SCTPV4:
                 if (input->formatted.dst_port || input->formatted.src_port) {
                         DEBUGOUT(" Error on src/dst port\n");
                         return IXGBE_ERR_CONFIG;
                 }
+                /* FALLTHRU */
         case IXGBE_ATR_FLOW_TYPE_TCPV4:
         case IXGBE_ATR_FLOW_TYPE_UDPV4:
                 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
                                                   IXGBE_ATR_L4TYPE_MASK;
                 break;