1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c,v 1.8 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_type.h"
36 #include "ixgbe_82599.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
40
41 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
43 bool autoneg,
44 bool autoneg_wait_to_complete);
45 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
46 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
47 u16 offset, u16 *data);
48 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
49 u16 words, u16 *data);
50
51 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
52 {
53 struct ixgbe_mac_info *mac = &hw->mac;
54
55 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
56
57 /* enable the laser control functions for SFP+ fiber */
58 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
59 mac->ops.disable_tx_laser =
60 &ixgbe_disable_tx_laser_multispeed_fiber;
61 mac->ops.enable_tx_laser =
62 &ixgbe_enable_tx_laser_multispeed_fiber;
63 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
64
65 } else {
66 mac->ops.disable_tx_laser = NULL;
67 mac->ops.enable_tx_laser = NULL;
68 mac->ops.flap_tx_laser = NULL;
69 }
70
71 if (hw->phy.multispeed_fiber) {
72 /* Set up dual speed SFP+ support */
73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
74 } else {
75 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
76 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
77 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
78 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
79 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
80 } else {
81 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
82 }
83 }
84 }
85
86 /**
87 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
88 * @hw: pointer to hardware structure
89 *
90 * Initialize any function pointers that were not able to be
91 * set during init_shared_code because the PHY/SFP type was
92 * not known. Perform the SFP init if necessary.
93 *
94 **/
95 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
96 {
97 struct ixgbe_mac_info *mac = &hw->mac;
98 struct ixgbe_phy_info *phy = &hw->phy;
99 s32 ret_val = IXGBE_SUCCESS;
100
101 DEBUGFUNC("ixgbe_init_phy_ops_82599");
102
103 /* Identify the PHY or SFP module */
104 ret_val = phy->ops.identify(hw);
105 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
106 goto init_phy_ops_out;
107
108 /* Setup function pointers based on detected SFP module and speeds */
109 ixgbe_init_mac_link_ops_82599(hw);
110 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
111 hw->phy.ops.reset = NULL;
112
113 /* If copper media, overwrite with copper function pointers */
114 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
115 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
116 mac->ops.get_link_capabilities =
117 &ixgbe_get_copper_link_capabilities_generic;
118 }
119
120 /* Set necessary function pointers based on phy type */
121 switch (hw->phy.type) {
122 case ixgbe_phy_tn:
123 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
124 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
125 phy->ops.get_firmware_version =
126 &ixgbe_get_phy_firmware_version_tnx;
127 break;
128 default:
129 break;
130 }
131 init_phy_ops_out:
132 return ret_val;
133 }
134
135 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
136 {
137 s32 ret_val = IXGBE_SUCCESS;
138 u32 reg_anlp1 = 0;
139 u32 i = 0;
140 u16 list_offset, data_offset, data_value;
141
142 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
143
144 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
145 ixgbe_init_mac_link_ops_82599(hw);
146
147 hw->phy.ops.reset = NULL;
148
149 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
150 &data_offset);
151 if (ret_val != IXGBE_SUCCESS)
152 goto setup_sfp_out;
153
154 /* PHY config will finish before releasing the semaphore */
155 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
156 IXGBE_GSSR_MAC_CSR_SM);
157 if (ret_val != IXGBE_SUCCESS) {
158 ret_val = IXGBE_ERR_SWFW_SYNC;
159 goto setup_sfp_out;
160 }
161
162 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
163 while (data_value != 0xffff) {
164 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
165 IXGBE_WRITE_FLUSH(hw);
166 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
167 }
168
169 /* Release the semaphore */
170 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
171 /* Delay obtaining semaphore again to allow FW access */
172 msec_delay(hw->eeprom.semaphore_delay);
173
174 /* Now restart DSP by setting Restart_AN and clearing LMS */
175 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
176 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
177 IXGBE_AUTOC_AN_RESTART));
178
179 /* Wait for AN to leave state 0 */
180 for (i = 0; i < 10; i++) {
181 msec_delay(4);
182 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
183 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
184 break;
185 }
186 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
187 DEBUGOUT("sfp module setup not complete\n");
188 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
189 goto setup_sfp_out;
190 }
191
192 /* Restart DSP by setting Restart_AN and return to SFI mode */
193 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
194 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
195 IXGBE_AUTOC_AN_RESTART));
196 }
197
198 setup_sfp_out:
199 return ret_val;
200 }
201
202 /**
203 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
204 * @hw: pointer to hardware structure
205 *
206 * Initialize the function pointers and assign the MAC type for 82599.
207 * Does not touch the hardware.
208 **/
209
210 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
211 {
212 struct ixgbe_mac_info *mac = &hw->mac;
213 struct ixgbe_phy_info *phy = &hw->phy;
214 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
215 s32 ret_val;
216
217 DEBUGFUNC("ixgbe_init_ops_82599");
218
219 ret_val = ixgbe_init_phy_ops_generic(hw);
220 ret_val = ixgbe_init_ops_generic(hw);
221
222 /* PHY */
223 phy->ops.identify = &ixgbe_identify_phy_82599;
224 phy->ops.init = &ixgbe_init_phy_ops_82599;
225
226 /* MAC */
227 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
228 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
229 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
230 mac->ops.get_supported_physical_layer =
231 &ixgbe_get_supported_physical_layer_82599;
232 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
233 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
234 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
235 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
236 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
237 mac->ops.start_hw = &ixgbe_start_hw_82599;
238 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
239 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
240 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
241 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
242 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
243
244 /* RAR, Multicast, VLAN */
245 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
246 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
247 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
248 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
249 mac->rar_highwater = 1;
250 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
251 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
252 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
253 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
254 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
255 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
256 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
257
258 /* Link */
259 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
260 mac->ops.check_link = &ixgbe_check_mac_link_generic;
261 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
262 ixgbe_init_mac_link_ops_82599(hw);
263
264 mac->mcft_size = 128;
265 mac->vft_size = 128;
266 mac->num_rar_entries = 128;
267 mac->rx_pb_size = 512;
268 mac->max_tx_queues = 128;
269 mac->max_rx_queues = 128;
270 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
271
272 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
273 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
274
275 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
276
277 /* EEPROM */
278 eeprom->ops.read = &ixgbe_read_eeprom_82599;
279 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
280
281 /* Manageability interface */
282 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
283
284
285 return ret_val;
286 }
287
288 /**
289 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
290 * @hw: pointer to hardware structure
291 * @speed: pointer to link speed
292 * @negotiation: TRUE when autoneg or autotry is enabled
293 *
294 * Determines the link capabilities by reading the AUTOC register.
295 **/
296 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
297 ixgbe_link_speed *speed,
298 bool *negotiation)
299 {
300 s32 status = IXGBE_SUCCESS;
301 u32 autoc = 0;
302
303 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
304
305
306 /* Check if 1G SFP module. */
307 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
308 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
309 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
310 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
311 *speed = IXGBE_LINK_SPEED_1GB_FULL;
312 *negotiation = TRUE;
313 goto out;
314 }
315
316 /*
317 * Determine link capabilities based on the stored value of AUTOC,
318 * which represents EEPROM defaults. If AUTOC value has not
319 * been stored, use the current register values.
320 */
321 if (hw->mac.orig_link_settings_stored)
322 autoc = hw->mac.orig_autoc;
323 else
324 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
325
326 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
327 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
328 *speed = IXGBE_LINK_SPEED_1GB_FULL;
329 *negotiation = FALSE;
330 break;
331
332 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
333 *speed = IXGBE_LINK_SPEED_10GB_FULL;
334 *negotiation = FALSE;
335 break;
336
337 case IXGBE_AUTOC_LMS_1G_AN:
338 *speed = IXGBE_LINK_SPEED_1GB_FULL;
339 *negotiation = TRUE;
340 break;
341
342 case IXGBE_AUTOC_LMS_10G_SERIAL:
343 *speed = IXGBE_LINK_SPEED_10GB_FULL;
344 *negotiation = FALSE;
345 break;
346
347 case IXGBE_AUTOC_LMS_KX4_KX_KR:
348 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
349 *speed = IXGBE_LINK_SPEED_UNKNOWN;
350 if (autoc & IXGBE_AUTOC_KR_SUPP)
351 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
352 if (autoc & IXGBE_AUTOC_KX4_SUPP)
353 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
354 if (autoc & IXGBE_AUTOC_KX_SUPP)
355 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
356 *negotiation = TRUE;
357 break;
358
359 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
360 *speed = IXGBE_LINK_SPEED_100_FULL;
361 if (autoc & IXGBE_AUTOC_KR_SUPP)
362 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
363 if (autoc & IXGBE_AUTOC_KX4_SUPP)
364 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
365 if (autoc & IXGBE_AUTOC_KX_SUPP)
366 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
367 *negotiation = TRUE;
368 break;
369
370 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
371 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
372 *negotiation = FALSE;
373 break;
374
375 default:
376 status = IXGBE_ERR_LINK_SETUP;
377 goto out;
378 }
379
380 if (hw->phy.multispeed_fiber) {
381 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
382 IXGBE_LINK_SPEED_1GB_FULL;
383 *negotiation = TRUE;
384 }
385
386 out:
387 return status;
388 }
389
390 /**
391 * ixgbe_get_media_type_82599 - Get media type
392 * @hw: pointer to hardware structure
393 *
394 * Returns the media type (fiber, copper, backplane)
395 **/
396 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
397 {
398 enum ixgbe_media_type media_type;
399
400 DEBUGFUNC("ixgbe_get_media_type_82599");
401
402 /* Detect if there is a copper PHY attached. */
403 switch (hw->phy.type) {
404 case ixgbe_phy_cu_unknown:
405 case ixgbe_phy_tn:
406 media_type = ixgbe_media_type_copper;
407 goto out;
408 default:
409 break;
410 }
411
412 switch (hw->device_id) {
413 case IXGBE_DEV_ID_82599_KX4:
414 case IXGBE_DEV_ID_82599_KX4_MEZZ:
415 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
416 case IXGBE_DEV_ID_82599_KR:
417 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
418 case IXGBE_DEV_ID_82599_XAUI_LOM:
419 /* Default device ID is mezzanine card KX/KX4 */
420 media_type = ixgbe_media_type_backplane;
421 break;
422 case IXGBE_DEV_ID_82599_SFP:
423 case IXGBE_DEV_ID_82599_SFP_FCOE:
424 case IXGBE_DEV_ID_82599_SFP_EM:
425 case IXGBE_DEV_ID_82599_SFP_SF2:
426 case IXGBE_DEV_ID_82599EN_SFP:
427 media_type = ixgbe_media_type_fiber;
428 break;
429 case IXGBE_DEV_ID_82599_CX4:
430 media_type = ixgbe_media_type_cx4;
431 break;
432 case IXGBE_DEV_ID_82599_T3_LOM:
433 media_type = ixgbe_media_type_copper;
434 break;
435 default:
436 media_type = ixgbe_media_type_unknown;
437 break;
438 }
439 out:
440 return media_type;
441 }
442
443 /**
444 * ixgbe_start_mac_link_82599 - Setup MAC link settings
445 * @hw: pointer to hardware structure
446 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
447 *
448 * Configures link settings based on values in the ixgbe_hw struct.
449 * Restarts the link. Performs autonegotiation if needed.
450 **/
451 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
452 bool autoneg_wait_to_complete)
453 {
454 u32 autoc_reg;
455 u32 links_reg;
456 u32 i;
457 s32 status = IXGBE_SUCCESS;
458
459 DEBUGFUNC("ixgbe_start_mac_link_82599");
460
461
462 /* Restart link */
463 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
464 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
465 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
466
467 /* Only poll for autoneg to complete if specified to do so */
468 if (autoneg_wait_to_complete) {
469 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
470 IXGBE_AUTOC_LMS_KX4_KX_KR ||
471 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
472 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
473 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
474 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
475 links_reg = 0; /* Just in case Autoneg time = 0 */
476 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
477 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
478 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
479 break;
480 msec_delay(100);
481 }
482 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
483 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
484 DEBUGOUT("Autoneg did not complete.\n");
485 }
486 }
487 }
488
489 /* Add delay to filter out noises during initial link setup */
490 msec_delay(50);
491
492 return status;
493 }
494
495 /**
496 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
497 * @hw: pointer to hardware structure
498 *
499 * The base drivers may require better control over SFP+ module
500 * PHY states. This includes selectively shutting down the Tx
501 * laser on the PHY, effectively halting physical link.
502 **/
503 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
504 {
505 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
506
507 /* Disable tx laser; allow 100us to go dark per spec */
508 esdp_reg |= IXGBE_ESDP_SDP3;
509 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
510 IXGBE_WRITE_FLUSH(hw);
511 usec_delay(100);
512 }
513
514 /**
515 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
516 * @hw: pointer to hardware structure
517 *
518 * The base drivers may require better control over SFP+ module
519 * PHY states. This includes selectively turning on the Tx
520 * laser on the PHY, effectively starting physical link.
521 **/
522 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
523 {
524 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
525
526 /* Enable tx laser; allow 100ms to light up */
527 esdp_reg &= ~IXGBE_ESDP_SDP3;
528 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
529 IXGBE_WRITE_FLUSH(hw);
530 msec_delay(100);
531 }
532
533 /**
534 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
535 * @hw: pointer to hardware structure
536 *
537 * When the driver changes the link speeds that it can support,
538 * it sets autotry_restart to TRUE to indicate that we need to
539 * initiate a new autotry session with the link partner. To do
540 * so, we set the speed then disable and re-enable the tx laser, to
541 * alert the link partner that it also needs to restart autotry on its
542 * end. This is consistent with TRUE clause 37 autoneg, which also
543 * involves a loss of signal.
544 **/
545 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
546 {
547 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
548
549 if (hw->mac.autotry_restart) {
550 ixgbe_disable_tx_laser_multispeed_fiber(hw);
551 ixgbe_enable_tx_laser_multispeed_fiber(hw);
552 hw->mac.autotry_restart = FALSE;
553 }
554 }
555
556 /**
557 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
558 * @hw: pointer to hardware structure
559 * @speed: new link speed
560 * @autoneg: TRUE if autonegotiation enabled
561 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
562 *
563 * Set the link speed in the AUTOC register and restarts link.
564 **/
565 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
566 ixgbe_link_speed speed, bool autoneg,
567 bool autoneg_wait_to_complete)
568 {
569 s32 status = IXGBE_SUCCESS;
570 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
571 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
572 u32 speedcnt = 0;
573 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
574 u32 i = 0;
575 bool link_up = FALSE;
576 bool negotiation;
577
578 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
579
580 /* Mask off requested but non-supported speeds */
581 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
582 if (status != IXGBE_SUCCESS)
583 return status;
584
585 speed &= link_speed;
586
587 /*
588 * Try each speed one by one, highest priority first. We do this in
589 * software because 10gb fiber doesn't support speed autonegotiation.
590 */
591 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
592 speedcnt++;
593 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
594
595 /* If we already have link at this speed, just jump out */
596 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
597 if (status != IXGBE_SUCCESS)
598 return status;
599
600 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
601 goto out;
602
603 /* Set the module link speed */
604 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
605 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
606 IXGBE_WRITE_FLUSH(hw);
607
608 /* Allow module to change analog characteristics (1G->10G) */
609 msec_delay(40);
610
611 status = ixgbe_setup_mac_link_82599(hw,
612 IXGBE_LINK_SPEED_10GB_FULL,
613 autoneg,
614 autoneg_wait_to_complete);
615 if (status != IXGBE_SUCCESS)
616 return status;
617
618 /* Flap the tx laser if it has not already been done */
619 ixgbe_flap_tx_laser(hw);
620
621 /*
622 * Wait for the controller to acquire link. Per IEEE 802.3ap,
623 * Section 73.10.2, we may have to wait up to 500ms if KR is
624 * attempted. 82599 uses the same timing for 10g SFI.
625 */
626 for (i = 0; i < 5; i++) {
627 /* Wait for the link partner to also set speed */
628 msec_delay(100);
629
630 /* If we have link, just jump out */
631 status = ixgbe_check_link(hw, &link_speed,
632 &link_up, FALSE);
633 if (status != IXGBE_SUCCESS)
634 return status;
635
636 if (link_up)
637 goto out;
638 }
639 }
640
641 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
642 speedcnt++;
643 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
644 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
645
646 /* If we already have link at this speed, just jump out */
647 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
648 if (status != IXGBE_SUCCESS)
649 return status;
650
651 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
652 goto out;
653
654 /* Set the module link speed */
655 esdp_reg &= ~IXGBE_ESDP_SDP5;
656 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
657 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
658 IXGBE_WRITE_FLUSH(hw);
659
660 /* Allow module to change analog characteristics (10G->1G) */
661 msec_delay(40);
662
663 status = ixgbe_setup_mac_link_82599(hw,
664 IXGBE_LINK_SPEED_1GB_FULL,
665 autoneg,
666 autoneg_wait_to_complete);
667 if (status != IXGBE_SUCCESS)
668 return status;
669
670 /* Flap the tx laser if it has not already been done */
671 ixgbe_flap_tx_laser(hw);
672
673 /* Wait for the link partner to also set speed */
674 msec_delay(100);
675
676 /* If we have link, just jump out */
677 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
678 if (status != IXGBE_SUCCESS)
679 return status;
680
681 if (link_up)
682 goto out;
683 }
684
685 /*
686 * We didn't get link. Configure back to the highest speed we tried,
687 * (if there was more than one). We call ourselves back with just the
688 * single highest speed that the user requested.
689 */
690 if (speedcnt > 1)
691 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
692 highest_link_speed, autoneg, autoneg_wait_to_complete);
693
694 out:
695 /* Set autoneg_advertised value based on input link speed */
696 hw->phy.autoneg_advertised = 0;
697
698 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
699 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
700
701 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
702 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
703
704 return status;
705 }
706
707 /**
708 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
709 * @hw: pointer to hardware structure
710 * @speed: new link speed
711 * @autoneg: TRUE if autonegotiation enabled
712 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
713 *
714 * Implements the Intel SmartSpeed algorithm.
715 **/
716 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
717 ixgbe_link_speed speed, bool autoneg,
718 bool autoneg_wait_to_complete)
719 {
720 s32 status = IXGBE_SUCCESS;
721 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
722 s32 i, j;
723 bool link_up = FALSE;
724 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
725
726 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
727
728 /* Set autoneg_advertised value based on input link speed */
729 hw->phy.autoneg_advertised = 0;
730
731 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
732 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
733
734 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
735 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
736
737 if (speed & IXGBE_LINK_SPEED_100_FULL)
738 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
739
740 /*
741 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
742 * autoneg advertisement if link is unable to be established at the
743 * highest negotiated rate. This can sometimes happen due to integrity
744 * issues with the physical media connection.
745 */
746
747 /* First, try to get link with full advertisement */
748 hw->phy.smart_speed_active = FALSE;
749 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
750 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
751 autoneg_wait_to_complete);
752 if (status != IXGBE_SUCCESS)
753 goto out;
754
755 /*
756 * Wait for the controller to acquire link. Per IEEE 802.3ap,
757 * Section 73.10.2, we may have to wait up to 500ms if KR is
758 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
759 * Table 9 in the AN MAS.
760 */
761 for (i = 0; i < 5; i++) {
762 msec_delay(100);
763
764 /* If we have link, just jump out */
765 status = ixgbe_check_link(hw, &link_speed, &link_up,
766 FALSE);
767 if (status != IXGBE_SUCCESS)
768 goto out;
769
770 if (link_up)
771 goto out;
772 }
773 }
774
775 /*
776 * We didn't get link. If we advertised KR plus one of KX4/KX
777 * (or BX4/BX), then disable KR and try again.
778 */
779 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
780 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
781 goto out;
782
783 /* Turn SmartSpeed on to disable KR support */
784 hw->phy.smart_speed_active = TRUE;
785 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
786 autoneg_wait_to_complete);
787 if (status != IXGBE_SUCCESS)
788 goto out;
789
790 /*
791 * Wait for the controller to acquire link. 600ms will allow for
792 * the AN link_fail_inhibit_timer as well for multiple cycles of
793 * parallel detect, both 10g and 1g. This allows for the maximum
794 * connect attempts as defined in the AN MAS table 73-7.
795 */
796 for (i = 0; i < 6; i++) {
797 msec_delay(100);
798
799 /* If we have link, just jump out */
800 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
801 if (status != IXGBE_SUCCESS)
802 goto out;
803
804 if (link_up)
805 goto out;
806 }
807
808 /* We didn't get link. Turn SmartSpeed back off. */
809 hw->phy.smart_speed_active = FALSE;
810 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
811 autoneg_wait_to_complete);
812
813 out:
814 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
815 DEBUGOUT("Smartspeed has downgraded the link speed "
816 "from the maximum advertised\n");
817 return status;
818 }
819
820 /**
821 * ixgbe_setup_mac_link_82599 - Set MAC link speed
822 * @hw: pointer to hardware structure
823 * @speed: new link speed
824 * @autoneg: TRUE if autonegotiation enabled
825 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
826 *
827 * Set the link speed in the AUTOC register and restarts link.
828 **/
829 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
830 ixgbe_link_speed speed, bool autoneg,
831 bool autoneg_wait_to_complete)
832 {
833 s32 status = IXGBE_SUCCESS;
834 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
835 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
836 u32 start_autoc = autoc;
837 u32 orig_autoc = 0;
838 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
839 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
840 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
841 u32 links_reg;
842 u32 i;
843 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
844
845 DEBUGFUNC("ixgbe_setup_mac_link_82599");
846
847 /* Check to see if speed passed in is supported. */
848 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
849 if (status != IXGBE_SUCCESS)
850 goto out;
851
852 speed &= link_capabilities;
853
854 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
855 status = IXGBE_ERR_LINK_SETUP;
856 goto out;
857 }
858
859 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
860 if (hw->mac.orig_link_settings_stored)
861 orig_autoc = hw->mac.orig_autoc;
862 else
863 orig_autoc = autoc;
864
865 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
866 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
867 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
868 /* Set KX4/KX/KR support according to speed requested */
869 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
870 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
871 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
872 autoc |= IXGBE_AUTOC_KX4_SUPP;
873 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
874 (hw->phy.smart_speed_active == FALSE))
875 autoc |= IXGBE_AUTOC_KR_SUPP;
876 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
877 autoc |= IXGBE_AUTOC_KX_SUPP;
878 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
879 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
880 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
881 /* Switch from 1G SFI to 10G SFI if requested */
882 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
883 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
884 autoc &= ~IXGBE_AUTOC_LMS_MASK;
885 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
886 }
887 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
888 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
889 /* Switch from 10G SFI to 1G SFI if requested */
890 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
891 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
892 autoc &= ~IXGBE_AUTOC_LMS_MASK;
893 if (autoneg)
894 autoc |= IXGBE_AUTOC_LMS_1G_AN;
895 else
896 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
897 }
898 }
899
900 if (autoc != start_autoc) {
901 /* Restart link */
902 autoc |= IXGBE_AUTOC_AN_RESTART;
903 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
904
905 /* Only poll for autoneg to complete if specified to do so */
906 if (autoneg_wait_to_complete) {
907 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
908 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
909 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
910 links_reg = 0; /*Just in case Autoneg time=0*/
911 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
912 links_reg =
913 IXGBE_READ_REG(hw, IXGBE_LINKS);
914 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
915 break;
916 msec_delay(100);
917 }
918 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
919 status =
920 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
921 DEBUGOUT("Autoneg did not complete.\n");
922 }
923 }
924 }
925
926 /* Add delay to filter out noises during initial link setup */
927 msec_delay(50);
928 }
929
930 out:
931 return status;
932 }
933
934 /**
935 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
936 * @hw: pointer to hardware structure
937 * @speed: new link speed
938 * @autoneg: TRUE if autonegotiation enabled
939 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
940 *
941 * Restarts link on PHY and MAC based on settings passed in.
942 **/
943 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
944 ixgbe_link_speed speed,
945 bool autoneg,
946 bool autoneg_wait_to_complete)
947 {
948 s32 status;
949
950 DEBUGFUNC("ixgbe_setup_copper_link_82599");
951
952 /* Setup the PHY according to input speed */
953 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
954 autoneg_wait_to_complete);
955 /* Set up MAC */
956 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
957
958 return status;
959 }
960
961 /**
962 * ixgbe_reset_hw_82599 - Perform hardware reset
963 * @hw: pointer to hardware structure
964 *
965 * Resets the hardware by resetting the transmit and receive units, masks
966 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
967 * reset.
968 **/
969 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
970 {
971 ixgbe_link_speed link_speed;
972 s32 status;
973 u32 ctrl, i, autoc, autoc2;
974 bool link_up = FALSE;
975
976 DEBUGFUNC("ixgbe_reset_hw_82599");
977
978 /* Call adapter stop to disable tx/rx and clear interrupts */
979 status = hw->mac.ops.stop_adapter(hw);
980 if (status != IXGBE_SUCCESS)
981 goto reset_hw_out;
982
983 /* flush pending Tx transactions */
984 ixgbe_clear_tx_pending(hw);
985
986 /* PHY ops must be identified and initialized prior to reset */
987
988 /* Identify PHY and related function pointers */
989 status = hw->phy.ops.init(hw);
990
991 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
992 goto reset_hw_out;
993
994 /* Setup SFP module if there is one present. */
995 if (hw->phy.sfp_setup_needed) {
996 status = hw->mac.ops.setup_sfp(hw);
997 hw->phy.sfp_setup_needed = FALSE;
998 }
999
1000 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1001 goto reset_hw_out;
1002
1003 /* Reset PHY */
1004 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
1005 hw->phy.ops.reset(hw);
1006
1007 mac_reset_top:
1008 /*
1009 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1010 * If link reset is used when link is up, it might reset the PHY when
1011 * mng is using it. If link is down or the flag to force full link
1012 * reset is set, then perform link reset.
1013 */
1014 ctrl = IXGBE_CTRL_LNK_RST;
1015 if (!hw->force_full_reset) {
1016 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
1017 if (link_up)
1018 ctrl = IXGBE_CTRL_RST;
1019 }
1020
1021 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1022 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1023 IXGBE_WRITE_FLUSH(hw);
1024
1025 /* Poll for reset bit to self-clear indicating reset is complete */
1026 for (i = 0; i < 10; i++) {
1027 usec_delay(1);
1028 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1029 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1030 break;
1031 }
1032
1033 if (ctrl & IXGBE_CTRL_RST_MASK) {
1034 status = IXGBE_ERR_RESET_FAILED;
1035 DEBUGOUT("Reset polling failed to complete.\n");
1036 }
1037
1038 msec_delay(50);
1039
1040 /*
1041 * Double resets are required for recovery from certain error
1042 * conditions. Between resets, it is necessary to stall to allow time
1043 * for any pending HW events to complete.
1044 */
1045 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1046 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1047 goto mac_reset_top;
1048 }
1049
1050 /*
1051 * Store the original AUTOC/AUTOC2 values if they have not been
1052 * stored off yet. Otherwise restore the stored original
1053 * values since the reset operation sets back to defaults.
1054 */
1055 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1056 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1057 if (hw->mac.orig_link_settings_stored == FALSE) {
1058 hw->mac.orig_autoc = autoc;
1059 hw->mac.orig_autoc2 = autoc2;
1060 hw->mac.orig_link_settings_stored = TRUE;
1061 } else {
1062 if (autoc != hw->mac.orig_autoc)
1063 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
1064 IXGBE_AUTOC_AN_RESTART));
1065
1066 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1067 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1068 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1069 autoc2 |= (hw->mac.orig_autoc2 &
1070 IXGBE_AUTOC2_UPPER_MASK);
1071 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1072 }
1073 }
1074
1075 /* Store the permanent mac address */
1076 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1077
1078 /*
1079 * Store MAC address from RAR0, clear receive address registers, and
1080 * clear the multicast table. Also reset num_rar_entries to 128,
1081 * since we modify this value when programming the SAN MAC address.
1082 */
1083 hw->mac.num_rar_entries = 128;
1084 hw->mac.ops.init_rx_addrs(hw);
1085
1086 /* Store the permanent SAN mac address */
1087 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1088
1089 /* Add the SAN MAC address to the RAR only if it's a valid address */
1090 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1091 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1092 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1093
1094 /* Save the SAN MAC RAR index */
1095 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1096
1097 /* Reserve the last RAR for the SAN MAC address */
1098 hw->mac.num_rar_entries--;
1099 }
1100
1101 /* Store the alternative WWNN/WWPN prefix */
1102 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1103 &hw->mac.wwpn_prefix);
1104
1105 reset_hw_out:
1106 return status;
1107 }
1108
1109 /**
1110 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1111 * @hw: pointer to hardware structure
1112 **/
1113 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1114 {
1115 int i;
1116 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1117 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1118
1119 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1120
1121 /*
1122 * Before starting reinitialization process,
1123 * FDIRCMD.CMD must be zero.
1124 */
1125 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1126 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1127 IXGBE_FDIRCMD_CMD_MASK))
1128 break;
1129 usec_delay(10);
1130 }
1131 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1132 DEBUGOUT("Flow Director previous command isn't complete, "
1133 "aborting table re-initialization.\n");
1134 return IXGBE_ERR_FDIR_REINIT_FAILED;
1135 }
1136
1137 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1138 IXGBE_WRITE_FLUSH(hw);
1139 /*
1140 * 82599 adapters flow director init flow cannot be restarted,
1141 * Workaround 82599 silicon errata by performing the following steps
1142 * before re-writing the FDIRCTRL control register with the same value.
1143 * - write 1 to bit 8 of FDIRCMD register &
1144 * - write 0 to bit 8 of FDIRCMD register
1145 */
1146 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1147 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1148 IXGBE_FDIRCMD_CLEARHT));
1149 IXGBE_WRITE_FLUSH(hw);
1150 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1151 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1152 ~IXGBE_FDIRCMD_CLEARHT));
1153 IXGBE_WRITE_FLUSH(hw);
1154 /*
1155 * Clear FDIR Hash register to clear any leftover hashes
1156 * waiting to be programmed.
1157 */
1158 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1159 IXGBE_WRITE_FLUSH(hw);
1160
1161 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1162 IXGBE_WRITE_FLUSH(hw);
1163
1164 /* Poll init-done after we write FDIRCTRL register */
1165 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1166 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1167 IXGBE_FDIRCTRL_INIT_DONE)
1168 break;
1169 usec_delay(10);
1170 }
1171 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1172 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1173 return IXGBE_ERR_FDIR_REINIT_FAILED;
1174 }
1175
1176 /* Clear FDIR statistics registers (read to clear) */
1177 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1178 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1179 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1180 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1181 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1182
1183 return IXGBE_SUCCESS;
1184 }
1185
1186 /**
1187 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1188 * @hw: pointer to hardware structure
1189 * @fdirctrl: value to write to flow director control register
1190 **/
1191 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1192 {
1193 int i;
1194
1195 DEBUGFUNC("ixgbe_fdir_enable_82599");
1196
1197 /* Prime the keys for hashing */
1198 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1199 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1200
1201 /*
1202 * Poll init-done after we write the register. Estimated times:
1203 * 10G: PBALLOC = 11b, timing is 60us
1204 * 1G: PBALLOC = 11b, timing is 600us
1205 * 100M: PBALLOC = 11b, timing is 6ms
1206 *
1207 * Multiple these timings by 4 if under full Rx load
1208 *
1209 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1210 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1211 * this might not finish in our poll time, but we can live with that
1212 * for now.
1213 */
1214 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1215 IXGBE_WRITE_FLUSH(hw);
1216 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1217 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1218 IXGBE_FDIRCTRL_INIT_DONE)
1219 break;
1220 msec_delay(1);
1221 }
1222
1223 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1224 DEBUGOUT("Flow Director poll time exceeded!\n");
1225 }
1226
1227 /**
1228 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1229 * @hw: pointer to hardware structure
1230 * @fdirctrl: value to write to flow director control register, initially
1231 * contains just the value of the Rx packet buffer allocation
1232 **/
1233 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1234 {
1235 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1236
1237 /*
1238 * Continue setup of fdirctrl register bits:
1239 * Move the flexible bytes to use the ethertype - shift 6 words
1240 * Set the maximum length per hash bucket to 0xA filters
1241 * Send interrupt when 64 filters are left
1242 */
1243 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1244 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1245 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1246
1247 /* write hashes and fdirctrl register, poll for completion */
1248 ixgbe_fdir_enable_82599(hw, fdirctrl);
1249
1250 return IXGBE_SUCCESS;
1251 }
1252
1253 /**
1254 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1255 * @hw: pointer to hardware structure
1256 * @fdirctrl: value to write to flow director control register, initially
1257 * contains just the value of the Rx packet buffer allocation
1258 **/
1259 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1260 {
1261 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1262
1263 /*
1264 * Continue setup of fdirctrl register bits:
1265 * Turn perfect match filtering on
1266 * Report hash in RSS field of Rx wb descriptor
1267 * Initialize the drop queue
1268 * Move the flexible bytes to use the ethertype - shift 6 words
1269 * Set the maximum length per hash bucket to 0xA filters
1270 * Send interrupt when 64 (0x4 * 16) filters are left
1271 */
1272 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1273 IXGBE_FDIRCTRL_REPORT_STATUS |
1274 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1275 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1276 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1277 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1278
1279 /* write hashes and fdirctrl register, poll for completion */
1280 ixgbe_fdir_enable_82599(hw, fdirctrl);
1281
1282 return IXGBE_SUCCESS;
1283 }
1284
1285 /*
1286 * These defines allow us to quickly generate all of the necessary instructions
1287 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1288 * for values 0 through 15
1289 */
1290 #define IXGBE_ATR_COMMON_HASH_KEY \
1291 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1292 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1293 do { \
1294 u32 n = (_n); \
1295 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1296 common_hash ^= lo_hash_dword >> n; \
1297 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1298 bucket_hash ^= lo_hash_dword >> n; \
1299 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1300 sig_hash ^= lo_hash_dword << (16 - n); \
1301 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1302 common_hash ^= hi_hash_dword >> n; \
1303 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1304 bucket_hash ^= hi_hash_dword >> n; \
1305 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1306 sig_hash ^= hi_hash_dword << (16 - n); \
1307 } while (0);
1308
1309 /**
1310 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1311 * @stream: input bitstream to compute the hash on
1312 *
1313 * This function is almost identical to the function above but contains
1314 * several optomizations such as unwinding all of the loops, letting the
1315 * compiler work out all of the conditional ifs since the keys are static
1316 * defines, and computing two keys at once since the hashed dword stream
1317 * will be the same for both keys.
1318 **/
1319 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1320 union ixgbe_atr_hash_dword common)
1321 {
1322 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1323 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1324
1325 /* record the flow_vm_vlan bits as they are a key part to the hash */
1326 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1327
1328 /* generate common hash dword */
1329 hi_hash_dword = IXGBE_NTOHL(common.dword);
1330
1331 /* low dword is word swapped version of common */
1332 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1333
1334 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1335 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1336
1337 /* Process bits 0 and 16 */
1338 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1339
1340 /*
1341 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1342 * delay this because bit 0 of the stream should not be processed
1343 * so we do not add the vlan until after bit 0 was processed
1344 */
1345 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1346
1347 /* Process remaining 30 bit of the key */
1348 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1349 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1350 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1351 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1352 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1353 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1354 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1355 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1356 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1357 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1358 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1359 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1360 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1361 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1362 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1363
1364 /* combine common_hash result with signature and bucket hashes */
1365 bucket_hash ^= common_hash;
1366 bucket_hash &= IXGBE_ATR_HASH_MASK;
1367
1368 sig_hash ^= common_hash << 16;
1369 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1370
1371 /* return completed signature hash */
1372 return sig_hash ^ bucket_hash;
1373 }
1374
1375 /**
1376 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1377 * @hw: pointer to hardware structure
1378 * @input: unique input dword
1379 * @common: compressed common input dword
1380 * @queue: queue index to direct traffic to
1381 **/
1382 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1383 union ixgbe_atr_hash_dword input,
1384 union ixgbe_atr_hash_dword common,
1385 u8 queue)
1386 {
1387 u64 fdirhashcmd;
1388 u32 fdircmd;
1389
1390 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1391
1392 /*
1393 * Get the flow_type in order to program FDIRCMD properly
1394 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1395 */
1396 switch (input.formatted.flow_type) {
1397 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1398 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1399 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1400 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1401 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1402 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1403 break;
1404 default:
1405 DEBUGOUT(" Error on flow type input\n");
1406 return IXGBE_ERR_CONFIG;
1407 }
1408
1409 /* configure FDIRCMD register */
1410 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1411 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1412 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1413 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1414
1415 /*
1416 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1417 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1418 */
1419 fdirhashcmd = (u64)fdircmd << 32;
1420 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1421 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1422
1423 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1424
1425 return IXGBE_SUCCESS;
1426 }
1427
1428 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1429 do { \
1430 u32 n = (_n); \
1431 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1432 bucket_hash ^= lo_hash_dword >> n; \
1433 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1434 bucket_hash ^= hi_hash_dword >> n; \
1435 } while (0);
1436
1437 /**
1438 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1439 * @atr_input: input bitstream to compute the hash on
1440 * @input_mask: mask for the input bitstream
1441 *
1442 * This function serves two main purposes. First it applys the input_mask
1443 * to the atr_input resulting in a cleaned up atr_input data stream.
1444 * Secondly it computes the hash and stores it in the bkt_hash field at
1445 * the end of the input byte stream. This way it will be available for
1446 * future use without needing to recompute the hash.
1447 **/
1448 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1449 union ixgbe_atr_input *input_mask)
1450 {
1451
1452 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1453 u32 bucket_hash = 0;
1454
1455 /* Apply masks to input data */
1456 input->dword_stream[0] &= input_mask->dword_stream[0];
1457 input->dword_stream[1] &= input_mask->dword_stream[1];
1458 input->dword_stream[2] &= input_mask->dword_stream[2];
1459 input->dword_stream[3] &= input_mask->dword_stream[3];
1460 input->dword_stream[4] &= input_mask->dword_stream[4];
1461 input->dword_stream[5] &= input_mask->dword_stream[5];
1462 input->dword_stream[6] &= input_mask->dword_stream[6];
1463 input->dword_stream[7] &= input_mask->dword_stream[7];
1464 input->dword_stream[8] &= input_mask->dword_stream[8];
1465 input->dword_stream[9] &= input_mask->dword_stream[9];
1466 input->dword_stream[10] &= input_mask->dword_stream[10];
1467
1468 /* record the flow_vm_vlan bits as they are a key part to the hash */
1469 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1470
1471 /* generate common hash dword */
1472 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1473 input->dword_stream[2] ^
1474 input->dword_stream[3] ^
1475 input->dword_stream[4] ^
1476 input->dword_stream[5] ^
1477 input->dword_stream[6] ^
1478 input->dword_stream[7] ^
1479 input->dword_stream[8] ^
1480 input->dword_stream[9] ^
1481 input->dword_stream[10]);
1482
1483 /* low dword is word swapped version of common */
1484 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1485
1486 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1487 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1488
1489 /* Process bits 0 and 16 */
1490 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1491
1492 /*
1493 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1494 * delay this because bit 0 of the stream should not be processed
1495 * so we do not add the vlan until after bit 0 was processed
1496 */
1497 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1498
1499 /* Process remaining 30 bit of the key */
1500 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1501 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1502 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1503 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1504 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1505 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1506 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1507 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1508 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1509 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1510 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1511 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1512 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1513 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1514 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1515
1516 /*
1517 * Limit hash to 13 bits since max bucket count is 8K.
1518 * Store result at the end of the input stream.
1519 */
1520 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1521 }
1522
1523 /**
1524 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1525 * @input_mask: mask to be bit swapped
1526 *
1527 * The source and destination port masks for flow director are bit swapped
1528 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1529 * generate a correctly swapped value we need to bit swap the mask and that
1530 * is what is accomplished by this function.
1531 **/
1532 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1533 {
1534 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1535 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1536 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1537 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1538 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1539 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1540 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1541 }
1542
1543 /*
1544 * These two macros are meant to address the fact that we have registers
1545 * that are either all or in part big-endian. As a result on big-endian
1546 * systems we will end up byte swapping the value to little-endian before
1547 * it is byte swapped again and written to the hardware in the original
1548 * big-endian format.
1549 */
1550 #define IXGBE_STORE_AS_BE32(_value) \
1551 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1552 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1553
1554 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1555 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1556
1557 #define IXGBE_STORE_AS_BE16(_value) \
1558 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1559
1560 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1561 union ixgbe_atr_input *input_mask)
1562 {
1563 /* mask IPv6 since it is currently not supported */
1564 u32 fdirm = IXGBE_FDIRM_DIPv6;
1565 u32 fdirtcpm;
1566
1567 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1568
1569 /*
1570 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1571 * are zero, then assume a full mask for that field. Also assume that
1572 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1573 * cannot be masked out in this implementation.
1574 *
1575 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1576 * point in time.
1577 */
1578
1579 /* verify bucket hash is cleared on hash generation */
1580 if (input_mask->formatted.bkt_hash)
1581 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1582
1583 /* Program FDIRM and verify partial masks */
1584 switch (input_mask->formatted.vm_pool & 0x7F) {
1585 case 0x0:
1586 fdirm |= IXGBE_FDIRM_POOL;
1587 case 0x7F:
1588 break;
1589 default:
1590 DEBUGOUT(" Error on vm pool mask\n");
1591 return IXGBE_ERR_CONFIG;
1592 }
1593
1594 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1595 case 0x0:
1596 fdirm |= IXGBE_FDIRM_L4P;
1597 if (input_mask->formatted.dst_port ||
1598 input_mask->formatted.src_port) {
1599 DEBUGOUT(" Error on src/dst port mask\n");
1600 return IXGBE_ERR_CONFIG;
1601 }
1602 case IXGBE_ATR_L4TYPE_MASK:
1603 break;
1604 default:
1605 DEBUGOUT(" Error on flow type mask\n");
1606 return IXGBE_ERR_CONFIG;
1607 }
1608
1609 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1610 case 0x0000:
1611 /* mask VLAN ID, fall through to mask VLAN priority */
1612 fdirm |= IXGBE_FDIRM_VLANID;
1613 case 0x0FFF:
1614 /* mask VLAN priority */
1615 fdirm |= IXGBE_FDIRM_VLANP;
1616 break;
1617 case 0xE000:
1618 /* mask VLAN ID only, fall through */
1619 fdirm |= IXGBE_FDIRM_VLANID;
1620 case 0xEFFF:
1621 /* no VLAN fields masked */
1622 break;
1623 default:
1624 DEBUGOUT(" Error on VLAN mask\n");
1625 return IXGBE_ERR_CONFIG;
1626 }
1627
1628 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1629 case 0x0000:
1630 /* Mask Flex Bytes, fall through */
1631 fdirm |= IXGBE_FDIRM_FLEX;
1632 case 0xFFFF:
1633 break;
1634 default:
1635 DEBUGOUT(" Error on flexible byte mask\n");
1636 return IXGBE_ERR_CONFIG;
1637 }
1638
1639 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1640 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1641
1642 /* store the TCP/UDP port masks, bit reversed from port layout */
1643 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1644
1645 /* write both the same so that UDP and TCP use the same mask */
1646 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1647 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1648
1649 /* store source and destination IP masks (big-enian) */
1650 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1651 ~input_mask->formatted.src_ip[0]);
1652 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1653 ~input_mask->formatted.dst_ip[0]);
1654
1655 return IXGBE_SUCCESS;
1656 }
1657
1658 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1659 union ixgbe_atr_input *input,
1660 u16 soft_id, u8 queue)
1661 {
1662 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1663
1664 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1665
1666 /* currently IPv6 is not supported, must be programmed with 0 */
1667 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1668 input->formatted.src_ip[0]);
1669 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1670 input->formatted.src_ip[1]);
1671 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1672 input->formatted.src_ip[2]);
1673
1674 /* record the source address (big-endian) */
1675 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1676
1677 /* record the first 32 bits of the destination address (big-endian) */
1678 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1679
1680 /* record source and destination port (little-endian)*/
1681 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1682 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1683 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1684 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1685
1686 /* record vlan (little-endian) and flex_bytes(big-endian) */
1687 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1688 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1689 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1690 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1691
1692 /* configure FDIRHASH register */
1693 fdirhash = input->formatted.bkt_hash;
1694 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1695 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1696
1697 /*
1698 * flush all previous writes to make certain registers are
1699 * programmed prior to issuing the command
1700 */
1701 IXGBE_WRITE_FLUSH(hw);
1702
1703 /* configure FDIRCMD register */
1704 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1705 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1706 if (queue == IXGBE_FDIR_DROP_QUEUE)
1707 fdircmd |= IXGBE_FDIRCMD_DROP;
1708 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1709 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1710 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1711
1712 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1713
1714 return IXGBE_SUCCESS;
1715 }
1716
1717 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1718 union ixgbe_atr_input *input,
1719 u16 soft_id)
1720 {
1721 u32 fdirhash;
1722 u32 fdircmd = 0;
1723 u32 retry_count;
1724 s32 err = IXGBE_SUCCESS;
1725
1726 /* configure FDIRHASH register */
1727 fdirhash = input->formatted.bkt_hash;
1728 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1729 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1730
1731 /* flush hash to HW */
1732 IXGBE_WRITE_FLUSH(hw);
1733
1734 /* Query if filter is present */
1735 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1736
1737 for (retry_count = 10; retry_count; retry_count--) {
1738 /* allow 10us for query to process */
1739 usec_delay(10);
1740 /* verify query completed successfully */
1741 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1742 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1743 break;
1744 }
1745
1746 if (!retry_count)
1747 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1748
1749 /* if filter exists in hardware then remove it */
1750 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1751 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1752 IXGBE_WRITE_FLUSH(hw);
1753 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1754 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1755 }
1756
1757 return err;
1758 }
1759
1760 /**
1761 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1762 * @hw: pointer to hardware structure
1763 * @input: input bitstream
1764 * @input_mask: mask for the input bitstream
1765 * @soft_id: software index for the filters
1766 * @queue: queue index to direct traffic to
1767 *
1768 * Note that the caller to this function must lock before calling, since the
1769 * hardware writes must be protected from one another.
1770 **/
1771 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1772 union ixgbe_atr_input *input,
1773 union ixgbe_atr_input *input_mask,
1774 u16 soft_id, u8 queue)
1775 {
1776 s32 err = IXGBE_ERR_CONFIG;
1777
1778 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1779
1780 /*
1781 * Check flow_type formatting, and bail out before we touch the hardware
1782 * if there's a configuration issue
1783 */
1784 switch (input->formatted.flow_type) {
1785 case IXGBE_ATR_FLOW_TYPE_IPV4:
1786 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1787 if (input->formatted.dst_port || input->formatted.src_port) {
1788 DEBUGOUT(" Error on src/dst port\n");
1789 return IXGBE_ERR_CONFIG;
1790 }
1791 break;
1792 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1793 if (input->formatted.dst_port || input->formatted.src_port) {
1794 DEBUGOUT(" Error on src/dst port\n");
1795 return IXGBE_ERR_CONFIG;
1796 }
1797 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1798 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1799 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1800 IXGBE_ATR_L4TYPE_MASK;
1801 break;
1802 default:
1803 DEBUGOUT(" Error on flow type input\n");
1804 return err;
1805 }
1806
1807 /* program input mask into the HW */
1808 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1809 if (err)
1810 return err;
1811
1812 /* apply mask and compute/store hash */
1813 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1814
1815 /* program filters to filter memory */
1816 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1817 soft_id, queue);
1818 }
1819
1820 /**
1821 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1822 * @hw: pointer to hardware structure
1823 * @reg: analog register to read
1824 * @val: read value
1825 *
1826 * Performs read operation to Omer analog register specified.
1827 **/
1828 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1829 {
1830 u32 core_ctl;
1831
1832 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1833
1834 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1835 (reg << 8));
1836 IXGBE_WRITE_FLUSH(hw);
1837 usec_delay(10);
1838 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1839 *val = (u8)core_ctl;
1840
1841 return IXGBE_SUCCESS;
1842 }
1843
1844 /**
1845 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1846 * @hw: pointer to hardware structure
1847 * @reg: atlas register to write
1848 * @val: value to write
1849 *
1850 * Performs write operation to Omer analog register specified.
1851 **/
1852 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1853 {
1854 u32 core_ctl;
1855
1856 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
1857
1858 core_ctl = (reg << 8) | val;
1859 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1860 IXGBE_WRITE_FLUSH(hw);
1861 usec_delay(10);
1862
1863 return IXGBE_SUCCESS;
1864 }
1865
1866 /**
1867 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1868 * @hw: pointer to hardware structure
1869 *
1870 * Starts the hardware using the generic start_hw function
1871 * and the generation start_hw function.
1872 * Then performs revision-specific operations, if any.
1873 **/
1874 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1875 {
1876 s32 ret_val = IXGBE_SUCCESS;
1877
1878 DEBUGFUNC("ixgbe_start_hw_82599");
1879
1880 ret_val = ixgbe_start_hw_generic(hw);
1881 if (ret_val != IXGBE_SUCCESS)
1882 goto out;
1883
1884 ret_val = ixgbe_start_hw_gen2(hw);
1885 if (ret_val != IXGBE_SUCCESS)
1886 goto out;
1887
1888 /* We need to run link autotry after the driver loads */
1889 hw->mac.autotry_restart = TRUE;
1890
1891 if (ret_val == IXGBE_SUCCESS)
1892 ret_val = ixgbe_verify_fw_version_82599(hw);
1893 out:
1894 return ret_val;
1895 }
1896
1897 /**
1898 * ixgbe_identify_phy_82599 - Get physical layer module
1899 * @hw: pointer to hardware structure
1900 *
1901 * Determines the physical layer module found on the current adapter.
1902 * If PHY already detected, maintains current PHY type in hw struct,
1903 * otherwise executes the PHY detection routine.
1904 **/
1905 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1906 {
1907 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1908
1909 DEBUGFUNC("ixgbe_identify_phy_82599");
1910
1911 /* Detect PHY if not unknown - returns success if already detected. */
1912 status = ixgbe_identify_phy_generic(hw);
1913 if (status != IXGBE_SUCCESS) {
1914 /* 82599 10GBASE-T requires an external PHY */
1915 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1916 goto out;
1917 else
1918 status = ixgbe_identify_module_generic(hw);
1919 }
1920
1921 /* Set PHY type none if no PHY detected */
1922 if (hw->phy.type == ixgbe_phy_unknown) {
1923 hw->phy.type = ixgbe_phy_none;
1924 status = IXGBE_SUCCESS;
1925 }
1926
1927 /* Return error if SFP module has been detected but is not supported */
1928 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1929 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1930
1931 out:
1932 return status;
1933 }
1934
1935 /**
1936 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1937 * @hw: pointer to hardware structure
1938 *
1939 * Determines physical layer capabilities of the current configuration.
1940 **/
1941 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1942 {
1943 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1944 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1945 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1946 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1947 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1948 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1949 u16 ext_ability = 0;
1950 u8 comp_codes_10g = 0;
1951 u8 comp_codes_1g = 0;
1952
1953 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
1954
1955 hw->phy.ops.identify(hw);
1956
1957 switch (hw->phy.type) {
1958 case ixgbe_phy_tn:
1959 case ixgbe_phy_cu_unknown:
1960 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1961 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1962 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1963 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1964 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1965 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1966 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1967 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1968 goto out;
1969 default:
1970 break;
1971 }
1972
1973 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1974 case IXGBE_AUTOC_LMS_1G_AN:
1975 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1976 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1977 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1978 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1979 goto out;
1980 }
1981 /* SFI mode so read SFP module */
1982 goto sfp_check;
1983 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1984 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1985 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1986 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1987 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1988 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1989 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1990 goto out;
1991 case IXGBE_AUTOC_LMS_10G_SERIAL:
1992 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1993 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1994 goto out;
1995 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1996 goto sfp_check;
1997 break;
1998 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1999 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2000 if (autoc & IXGBE_AUTOC_KX_SUPP)
2001 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2002 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2003 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2004 if (autoc & IXGBE_AUTOC_KR_SUPP)
2005 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2006 goto out;
2007 default:
2008 goto out;
2009 }
2010
2011 sfp_check:
2012 /* SFP check must be done last since DA modules are sometimes used to
2013 * test KR mode - we need to id KR mode correctly before SFP module.
2014 * Call identify_sfp because the pluggable module may have changed */
2015 hw->phy.ops.identify_sfp(hw);
2016 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2017 goto out;
2018
2019 switch (hw->phy.type) {
2020 case ixgbe_phy_sfp_passive_tyco:
2021 case ixgbe_phy_sfp_passive_unknown:
2022 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2023 break;
2024 case ixgbe_phy_sfp_ftl_active:
2025 case ixgbe_phy_sfp_active_unknown:
2026 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2027 break;
2028 case ixgbe_phy_sfp_avago:
2029 case ixgbe_phy_sfp_ftl:
2030 case ixgbe_phy_sfp_intel:
2031 case ixgbe_phy_sfp_unknown:
2032 hw->phy.ops.read_i2c_eeprom(hw,
2033 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2034 hw->phy.ops.read_i2c_eeprom(hw,
2035 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2036 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2037 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2038 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2039 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2040 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2041 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2042 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2043 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2044 break;
2045 default:
2046 break;
2047 }
2048
2049 out:
2050 return physical_layer;
2051 }
2052
2053 /**
2054 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2055 * @hw: pointer to hardware structure
2056 * @regval: register value to write to RXCTRL
2057 *
2058 * Enables the Rx DMA unit for 82599
2059 **/
2060 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2061 {
2062
2063 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2064
2065 /*
2066 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2067 * If traffic is incoming before we enable the Rx unit, it could hang
2068 * the Rx DMA unit. Therefore, make sure the security engine is
2069 * completely disabled prior to enabling the Rx unit.
2070 */
2071
2072 hw->mac.ops.disable_sec_rx_path(hw);
2073
2074 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2075
2076 hw->mac.ops.enable_sec_rx_path(hw);
2077
2078 return IXGBE_SUCCESS;
2079 }
2080
2081 /**
2082 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2083 * @hw: pointer to hardware structure
2084 *
2085 * Verifies that installed the firmware version is 0.6 or higher
2086 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2087 *
2088 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2089 * if the FW version is not supported.
2090 **/
2091 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2092 {
2093 s32 status = IXGBE_ERR_EEPROM_VERSION;
2094 u16 fw_offset, fw_ptp_cfg_offset;
2095 u16 fw_version = 0;
2096
2097 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2098
2099 /* firmware check is only necessary for SFI devices */
2100 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2101 status = IXGBE_SUCCESS;
2102 goto fw_version_out;
2103 }
2104
2105 /* get the offset to the Firmware Module block */
2106 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2107
2108 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2109 goto fw_version_out;
2110
2111 /* get the offset to the Pass Through Patch Configuration block */
2112 hw->eeprom.ops.read(hw, (fw_offset +
2113 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2114 &fw_ptp_cfg_offset);
2115
2116 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2117 goto fw_version_out;
2118
2119 /* get the firmware version */
2120 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2121 IXGBE_FW_PATCH_VERSION_4), &fw_version);
2122
2123 if (fw_version > 0x5)
2124 status = IXGBE_SUCCESS;
2125
2126 fw_version_out:
2127 return status;
2128 }
2129
2130 /**
2131 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2132 * @hw: pointer to hardware structure
2133 *
2134 * Returns TRUE if the LESM FW module is present and enabled. Otherwise
2135 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled.
2136 **/
2137 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2138 {
2139 bool lesm_enabled = FALSE;
2140 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2141 s32 status;
2142
2143 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2144
2145 /* get the offset to the Firmware Module block */
2146 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2147
2148 if ((status != IXGBE_SUCCESS) ||
2149 (fw_offset == 0) || (fw_offset == 0xFFFF))
2150 goto out;
2151
2152 /* get the offset to the LESM Parameters block */
2153 status = hw->eeprom.ops.read(hw, (fw_offset +
2154 IXGBE_FW_LESM_PARAMETERS_PTR),
2155 &fw_lesm_param_offset);
2156
2157 if ((status != IXGBE_SUCCESS) ||
2158 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2159 goto out;
2160
2161 /* get the lesm state word */
2162 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2163 IXGBE_FW_LESM_STATE_1),
2164 &fw_lesm_state);
2165
2166 if ((status == IXGBE_SUCCESS) &&
2167 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2168 lesm_enabled = TRUE;
2169
2170 out:
2171 return lesm_enabled;
2172 }
2173
2174 /**
2175 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2176 * fastest available method
2177 *
2178 * @hw: pointer to hardware structure
2179 * @offset: offset of word in EEPROM to read
2180 * @words: number of words
2181 * @data: word(s) read from the EEPROM
2182 *
2183 * Retrieves 16 bit word(s) read from EEPROM
2184 **/
2185 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2186 u16 words, u16 *data)
2187 {
2188 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2189 s32 ret_val = IXGBE_ERR_CONFIG;
2190
2191 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2192
2193 /*
2194 * If EEPROM is detected and can be addressed using 14 bits,
2195 * use EERD otherwise use bit bang
2196 */
2197 if ((eeprom->type == ixgbe_eeprom_spi) &&
2198 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2199 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2200 data);
2201 else
2202 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2203 words,
2204 data);
2205
2206 return ret_val;
2207 }
2208
2209 /**
2210 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2211 * fastest available method
2212 *
2213 * @hw: pointer to hardware structure
2214 * @offset: offset of word in the EEPROM to read
2215 * @data: word read from the EEPROM
2216 *
2217 * Reads a 16 bit word from the EEPROM
2218 **/
2219 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2220 u16 offset, u16 *data)
2221 {
2222 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2223 s32 ret_val = IXGBE_ERR_CONFIG;
2224
2225 DEBUGFUNC("ixgbe_read_eeprom_82599");
2226
2227 /*
2228 * If EEPROM is detected and can be addressed using 14 bits,
2229 * use EERD otherwise use bit bang
2230 */
2231 if ((eeprom->type == ixgbe_eeprom_spi) &&
2232 (offset <= IXGBE_EERD_MAX_ADDR))
2233 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2234 else
2235 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2236
2237 return ret_val;
2238 }
2239
2240