703 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
704 *link_up = FALSE;
705
706 out:
707 return IXGBE_SUCCESS;
708 }
709
710 /**
711 * ixgbe_setup_mac_link_82598 - Set MAC link speed
712 * @hw: pointer to hardware structure
713 * @speed: new link speed
714 * @autoneg: TRUE if autonegotiation enabled
715 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
716 *
717 * Set the link speed in the AUTOC register and restarts link.
718 **/
719 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
720 ixgbe_link_speed speed, bool autoneg,
721 bool autoneg_wait_to_complete)
722 {
723 s32 status = IXGBE_SUCCESS;
724 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
725 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
726 u32 autoc = curr_autoc;
727 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
728
729 DEBUGFUNC("ixgbe_setup_mac_link_82598");
730
731 /* Check to see if speed passed in is supported. */
732 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
733 speed &= link_capabilities;
734
735 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
736 status = IXGBE_ERR_LINK_SETUP;
737
738 /* Set KX4/KX support according to speed requested */
739 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
740 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
741 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
742 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
743 autoc |= IXGBE_AUTOC_KX4_SUPP;
744 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
745 autoc |= IXGBE_AUTOC_KX_SUPP;
746 if (autoc != curr_autoc)
747 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
748 }
749
750 if (status == IXGBE_SUCCESS) {
751 /*
752 * Setup and restart the link based on the new values in
765 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
766 * @hw: pointer to hardware structure
767 * @speed: new link speed
768 * @autoneg: TRUE if autonegotiation enabled
769 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
770 *
771 * Sets the link speed in the AUTOC register in the MAC and restarts link.
772 **/
773 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
774 ixgbe_link_speed speed,
775 bool autoneg,
776 bool autoneg_wait_to_complete)
777 {
778 s32 status;
779
780 DEBUGFUNC("ixgbe_setup_copper_link_82598");
781
782 /* Setup the PHY according to input speed */
783 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
784 autoneg_wait_to_complete);
785 /* Set up MAC */
786 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
787
788 return status;
789 }
790
791 /**
792 * ixgbe_reset_hw_82598 - Performs hardware reset
793 * @hw: pointer to hardware structure
794 *
795 * Resets the hardware by resetting the transmit and receive units, masks and
796 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
797 * reset.
798 **/
799 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
800 {
801 s32 status = IXGBE_SUCCESS;
802 s32 phy_status = IXGBE_SUCCESS;
803 u32 ctrl;
804 u32 gheccr;
805 u32 i;
806 u32 autoc;
1340 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
1341 u32 headroom, int strategy)
1342 {
1343 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1344 u8 i = 0;
1345 UNREFERENCED_1PARAMETER(headroom);
1346
1347 if (!num_pb)
1348 return;
1349
1350 /* Setup Rx packet buffer sizes */
1351 switch (strategy) {
1352 case PBA_STRATEGY_WEIGHTED:
1353 /* Setup the first four at 80KB */
1354 rxpktsize = IXGBE_RXPBSIZE_80KB;
1355 for (; i < 4; i++)
1356 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1357 /* Setup the last four at 48KB...don't re-init i */
1358 rxpktsize = IXGBE_RXPBSIZE_48KB;
1359 /* Fall Through */
1360 case PBA_STRATEGY_EQUAL:
1361 default:
1362 /* Divide the remaining Rx packet buffer evenly among the TCs */
1363 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1364 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1365 break;
1366 }
1367
1368 /* Setup Tx packet buffer sizes */
1369 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1370 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1371
1372 return;
1373 }
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703 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
704 *link_up = FALSE;
705
706 out:
707 return IXGBE_SUCCESS;
708 }
709
710 /**
711 * ixgbe_setup_mac_link_82598 - Set MAC link speed
712 * @hw: pointer to hardware structure
713 * @speed: new link speed
714 * @autoneg: TRUE if autonegotiation enabled
715 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
716 *
717 * Set the link speed in the AUTOC register and restarts link.
718 **/
719 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
720 ixgbe_link_speed speed, bool autoneg,
721 bool autoneg_wait_to_complete)
722 {
723 s32 status;
724 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
725 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
726 u32 autoc = curr_autoc;
727 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
728
729 DEBUGFUNC("ixgbe_setup_mac_link_82598");
730
731 /* Check to see if speed passed in is supported. */
732 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
733 if (status != IXGBE_SUCCESS)
734 return (status);
735 speed &= link_capabilities;
736
737 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
738 status = IXGBE_ERR_LINK_SETUP;
739
740 /* Set KX4/KX support according to speed requested */
741 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
742 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
743 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
744 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
745 autoc |= IXGBE_AUTOC_KX4_SUPP;
746 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
747 autoc |= IXGBE_AUTOC_KX_SUPP;
748 if (autoc != curr_autoc)
749 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
750 }
751
752 if (status == IXGBE_SUCCESS) {
753 /*
754 * Setup and restart the link based on the new values in
767 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
768 * @hw: pointer to hardware structure
769 * @speed: new link speed
770 * @autoneg: TRUE if autonegotiation enabled
771 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
772 *
773 * Sets the link speed in the AUTOC register in the MAC and restarts link.
774 **/
775 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
776 ixgbe_link_speed speed,
777 bool autoneg,
778 bool autoneg_wait_to_complete)
779 {
780 s32 status;
781
782 DEBUGFUNC("ixgbe_setup_copper_link_82598");
783
784 /* Setup the PHY according to input speed */
785 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
786 autoneg_wait_to_complete);
787 if (status == IXGBE_SUCCESS) {
788 /* Set up MAC */
789 status =
790 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
791 }
792
793 return status;
794 }
795
796 /**
797 * ixgbe_reset_hw_82598 - Performs hardware reset
798 * @hw: pointer to hardware structure
799 *
800 * Resets the hardware by resetting the transmit and receive units, masks and
801 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
802 * reset.
803 **/
804 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
805 {
806 s32 status = IXGBE_SUCCESS;
807 s32 phy_status = IXGBE_SUCCESS;
808 u32 ctrl;
809 u32 gheccr;
810 u32 i;
811 u32 autoc;
1345 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
1346 u32 headroom, int strategy)
1347 {
1348 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1349 u8 i = 0;
1350 UNREFERENCED_1PARAMETER(headroom);
1351
1352 if (!num_pb)
1353 return;
1354
1355 /* Setup Rx packet buffer sizes */
1356 switch (strategy) {
1357 case PBA_STRATEGY_WEIGHTED:
1358 /* Setup the first four at 80KB */
1359 rxpktsize = IXGBE_RXPBSIZE_80KB;
1360 for (; i < 4; i++)
1361 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1362 /* Setup the last four at 48KB...don't re-init i */
1363 rxpktsize = IXGBE_RXPBSIZE_48KB;
1364 /* Fall Through */
1365 /* FALLTHRU */
1366 case PBA_STRATEGY_EQUAL:
1367 default:
1368 /* Divide the remaining Rx packet buffer evenly among the TCs */
1369 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1370 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1371 break;
1372 }
1373
1374 /* Setup Tx packet buffer sizes */
1375 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1376 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1377 }
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