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--- old/./mr_sas.h
+++ new/./mr_sas.h
1 1 /*
2 2 * mr_sas.h: header for mr_sas
3 3 *
4 4 * Solaris MegaRAID driver for SAS2.0 controllers
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5 5 * Copyright (c) 2008-2012, LSI Logic Corporation.
6 6 * All rights reserved.
7 7 *
8 8 * Version:
9 9 * Author:
10 10 * Swaminathan K S
11 11 * Arun Chandrashekhar
12 12 * Manju R
13 13 * Rasheed
14 14 * Shakeel Bukhari
15 + *
16 + * Redistribution and use in source and binary forms, with or without
17 + * modification, are permitted provided that the following conditions are met:
18 + *
19 + * 1. Redistributions of source code must retain the above copyright notice,
20 + * this list of conditions and the following disclaimer.
21 + *
22 + * 2. Redistributions in binary form must reproduce the above copyright notice,
23 + * this list of conditions and the following disclaimer in the documentation
24 + * and/or other materials provided with the distribution.
25 + *
26 + * 3. Neither the name of the author nor the names of its contributors may be
27 + * used to endorse or promote products derived from this software without
28 + * specific prior written permission.
29 + *
30 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
34 + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
36 + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
37 + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
38 + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
40 + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41 + * DAMAGE.
15 42 */
16 43
44 +/*
45 + * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
46 + */
47 +
17 48 #ifndef _MR_SAS_H_
18 49 #define _MR_SAS_H_
19 50
20 51 #ifdef __cplusplus
21 52 extern "C" {
22 53 #endif
23 54
24 55 #include <sys/scsi/scsi.h>
25 56 #include "mr_sas_list.h"
26 57 #include "ld_pd_map.h"
27 58
28 59 /*
29 60 * MegaRAID SAS2.0 Driver meta data
30 61 */
31 -#define MRSAS_VERSION "6.503.00.00JOYENT"
62 +#define MRSAS_VERSION "6.503.00.00ILLUMOS"
32 63 #define MRSAS_RELDATE "July 30, 2012"
33 64
34 65 #define MRSAS_TRUE 1
35 66 #define MRSAS_FALSE 0
36 67
37 68 #define ADAPTER_RESET_NOT_REQUIRED 0
38 69 #define ADAPTER_RESET_REQUIRED 1
39 70
40 -#define PDSUPPORT 1
71 +#define PDSUPPORT 1
41 72
42 -#define SWAP_BYTES(w) ((((w)>>8)&0xFF) | (((w)&0xFF)<<8))
43 -#define BIG_ENDIAN(d) (SWAP_BYTES((d) >> 16) | (SWAP_BYTES(d) << 16))
44 73 /*
45 74 * MegaRAID SAS2.0 device id conversion definitions.
46 75 */
47 76 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT)
48 -#define MRSAS_GET_BOUNDARY_ALIGNED_LEN(len, new_len, boundary_len) { \
49 - int rem; \
50 - rem = (len / boundary_len); \
51 - if ((rem * boundary_len) != len) { \
52 - new_len = len + ((rem + 1) * boundary_len - len); \
53 - } else { \
54 - new_len = len; \
55 - } \
56 -} \
77 +#define MRSAS_GET_BOUNDARY_ALIGNED_LEN(len, new_len, boundary_len) { \
78 + int rem; \
79 + rem = (len / boundary_len); \
80 + if ((rem * boundary_len) != len) { \
81 + new_len = len + ((rem + 1) * boundary_len - len); \
82 + } else { \
83 + new_len = len; \
84 + } \
85 +}
57 86
58 87
59 88 /*
60 89 * MegaRAID SAS2.0 supported controllers
61 90 */
62 91 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078
63 92 #define PCI_DEVICE_ID_LSI_2108V 0x0079
64 93 #define PCI_DEVICE_ID_LSI_TBOLT 0x005b
65 94 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
66 95
67 96 /*
68 97 * Register Index for 2108 Controllers.
69 98 */
70 99 #define REGISTER_SET_IO_2108 (2)
71 100
72 101 #define MRSAS_MAX_SGE_CNT 0x50
73 102 #define MRSAS_APP_RESERVED_CMDS 32
74 103
75 104 #define MRSAS_IOCTL_DRIVER 0x12341234
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76 105 #define MRSAS_IOCTL_FIRMWARE 0x12345678
77 106 #define MRSAS_IOCTL_AEN 0x87654321
78 107
79 108 #define MRSAS_1_SECOND 1000000
80 109
81 110 #ifdef PDSUPPORT
82 111
83 112 #define UNCONFIGURED_GOOD 0x0
84 113 #define PD_SYSTEM 0x40
85 114 #define MR_EVT_PD_STATE_CHANGE 0x0072
86 -#define MR_EVT_PD_REMOVED_EXT 0x00f8
115 +#define MR_EVT_PD_REMOVED_EXT 0x00f8
87 116 #define MR_EVT_PD_INSERTED_EXT 0x00f7
88 117 #define MR_DCMD_PD_GET_INFO 0x02020000
89 118 #define MRSAS_TBOLT_PD_LUN 1
90 119 #define MRSAS_TBOLT_PD_TGT_MAX 255
91 120 #define MRSAS_TBOLT_GET_PD_MAX(s) ((s)->mr_tbolt_pd_max)
92 121
93 122 #endif
94 123
95 124 /* Raid Context Flags */
96 -#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
97 -#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
98 -typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
99 - MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
100 - MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1
125 +#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
126 +#define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
127 +typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
128 + MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
129 + MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1
101 130 } MR_RAID_FLAGS_IO_SUB_TYPE;
102 131
103 132 /* Dynamic Enumeration Flags */
104 133 #define MRSAS_LD_LUN 0
105 134 #define WWN_STRLEN 17
106 135 #define LD_SYNC_BIT 1
107 136 #define LD_SYNC_SHIFT 14
108 137 /* ThunderBolt (TB) specific */
109 138 #define MRSAS_THUNDERBOLT_MSG_SIZE 256
110 139 #define MRSAS_THUNDERBOLT_MAX_COMMANDS 1024
111 140 #define MRSAS_THUNDERBOLT_MAX_REPLY_COUNT 1024
112 141 #define MRSAS_THUNDERBOLT_REPLY_SIZE 8
113 142 #define MRSAS_THUNDERBOLT_MAX_CHAIN_COUNT 1
114 143
115 144 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
116 145 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1
117 146
118 147 #define MR_EVT_LD_FAST_PATH_IO_STATUS_CHANGED (0xFFFF)
119 148
120 149 #define MR_INTERNAL_MFI_FRAMES_SMID 1
121 150 #define MR_CTRL_EVENT_WAIT_SMID 2
122 151 #define MR_INTERNAL_DRIVER_RESET_SMID 3
123 152
124 153
125 154 /*
126 155 * =====================================
127 156 * MegaRAID SAS2.0 MFI firmware definitions
128 157 * =====================================
129 158 */
130 159 /*
131 160 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for
132 161 * protocol between the software and firmware. Commands are issued using
133 162 * "message frames"
134 163 */
135 164
136 165 /*
137 166 * FW posts its state in upper 4 bits of outbound_msg_0 register
138 167 */
139 168 #define MFI_STATE_MASK 0xF0000000
140 169 #define MFI_STATE_UNDEFINED 0x00000000
141 170 #define MFI_STATE_BB_INIT 0x10000000
142 171 #define MFI_STATE_FW_INIT 0x40000000
143 172 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
144 173 #define MFI_STATE_FW_INIT_2 0x70000000
145 174 #define MFI_STATE_DEVICE_SCAN 0x80000000
146 175 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
147 176 #define MFI_STATE_FLUSH_CACHE 0xA0000000
148 177 #define MFI_STATE_READY 0xB0000000
149 178 #define MFI_STATE_OPERATIONAL 0xC0000000
150 179 #define MFI_STATE_FAULT 0xF0000000
151 180
152 181 #define MRMFI_FRAME_SIZE 64
153 182
154 183 /*
155 184 * During FW init, clear pending cmds & reset state using inbound_msg_0
156 185 *
157 186 * ABORT : Abort all pending cmds
158 187 * READY : Move from OPERATIONAL to READY state; discard queue info
159 188 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
160 189 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
161 190 */
162 191 #define MFI_INIT_ABORT 0x00000001
163 192 #define MFI_INIT_READY 0x00000002
164 193 #define MFI_INIT_MFIMODE 0x00000004
165 194 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
166 195 #define MFI_INIT_HOTPLUG 0x00000010
167 196 #define MFI_STOP_ADP 0x00000020
168 197 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
169 198
170 199 /*
171 200 * MFI frame flags
172 201 */
173 202 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
174 203 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
175 204 #define MFI_FRAME_SGL32 0x0000
176 205 #define MFI_FRAME_SGL64 0x0002
177 206 #define MFI_FRAME_SENSE32 0x0000
178 207 #define MFI_FRAME_SENSE64 0x0004
179 208 #define MFI_FRAME_DIR_NONE 0x0000
180 209 #define MFI_FRAME_DIR_WRITE 0x0008
181 210 #define MFI_FRAME_DIR_READ 0x0010
182 211 #define MFI_FRAME_DIR_BOTH 0x0018
183 212 #define MFI_FRAME_IEEE 0x0020
184 213
185 214 /*
186 215 * Definition for cmd_status
187 216 */
188 217 #define MFI_CMD_STATUS_POLL_MODE 0xFF
189 218 #define MFI_CMD_STATUS_SYNC_MODE 0xFF
190 219
191 220 /*
192 221 * MFI command opcodes
193 222 */
194 223 #define MFI_CMD_OP_INIT 0x00
195 224 #define MFI_CMD_OP_LD_READ 0x01
196 225 #define MFI_CMD_OP_LD_WRITE 0x02
197 226 #define MFI_CMD_OP_LD_SCSI 0x03
198 227 #define MFI_CMD_OP_PD_SCSI 0x04
199 228 #define MFI_CMD_OP_DCMD 0x05
200 229 #define MFI_CMD_OP_ABORT 0x06
201 230 #define MFI_CMD_OP_SMP 0x07
202 231 #define MFI_CMD_OP_STP 0x08
203 232
204 233 #define MR_DCMD_CTRL_GET_INFO 0x01010000
205 234
206 235 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
207 236 #define MR_FLUSH_CTRL_CACHE 0x01
208 237 #define MR_FLUSH_DISK_CACHE 0x02
209 238
210 239 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
211 240 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01
212 241
213 242 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
214 243 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
215 244 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
216 245 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
217 246
218 247 /*
219 248 * Solaris Specific MAX values
220 249 */
221 250 #define MAX_SGL 24
222 251
223 252 /*
224 253 * MFI command completion codes
225 254 */
226 255 enum MFI_STAT {
227 256 MFI_STAT_OK = 0x00,
228 257 MFI_STAT_INVALID_CMD = 0x01,
229 258 MFI_STAT_INVALID_DCMD = 0x02,
230 259 MFI_STAT_INVALID_PARAMETER = 0x03,
231 260 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
232 261 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
233 262 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
234 263 MFI_STAT_APP_IN_USE = 0x07,
235 264 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
236 265 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
237 266 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
238 267 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
239 268 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
240 269 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
241 270 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
242 271 MFI_STAT_FLASH_BUSY = 0x0f,
243 272 MFI_STAT_FLASH_ERROR = 0x10,
244 273 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
245 274 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
246 275 MFI_STAT_FLASH_NOT_OPEN = 0x13,
247 276 MFI_STAT_FLASH_NOT_STARTED = 0x14,
248 277 MFI_STAT_FLUSH_FAILED = 0x15,
249 278 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
250 279 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
251 280 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
252 281 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
253 282 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
254 283 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
255 284 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
256 285 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
257 286 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
258 287 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
259 288 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
260 289 MFI_STAT_MFC_HW_ERROR = 0x21,
261 290 MFI_STAT_NO_HW_PRESENT = 0x22,
262 291 MFI_STAT_NOT_FOUND = 0x23,
263 292 MFI_STAT_NOT_IN_ENCL = 0x24,
264 293 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
265 294 MFI_STAT_PD_TYPE_WRONG = 0x26,
266 295 MFI_STAT_PR_DISABLED = 0x27,
267 296 MFI_STAT_ROW_INDEX_INVALID = 0x28,
268 297 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
269 298 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
270 299 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
271 300 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
272 301 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
273 302 MFI_STAT_SCSI_IO_FAILED = 0x2e,
274 303 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
275 304 MFI_STAT_SHUTDOWN_FAILED = 0x30,
276 305 MFI_STAT_TIME_NOT_SET = 0x31,
277 306 MFI_STAT_WRONG_STATE = 0x32,
278 307 MFI_STAT_LD_OFFLINE = 0x33,
279 308 MFI_STAT_INVALID_STATUS = 0xFF
280 309 };
281 310
282 311 enum MR_EVT_CLASS {
283 312 MR_EVT_CLASS_DEBUG = -2,
284 313 MR_EVT_CLASS_PROGRESS = -1,
285 314 MR_EVT_CLASS_INFO = 0,
286 315 MR_EVT_CLASS_WARNING = 1,
287 316 MR_EVT_CLASS_CRITICAL = 2,
288 317 MR_EVT_CLASS_FATAL = 3,
289 318 MR_EVT_CLASS_DEAD = 4
290 319 };
291 320
292 321 enum MR_EVT_LOCALE {
293 322 MR_EVT_LOCALE_LD = 0x0001,
294 323 MR_EVT_LOCALE_PD = 0x0002,
295 324 MR_EVT_LOCALE_ENCL = 0x0004,
296 325 MR_EVT_LOCALE_BBU = 0x0008,
297 326 MR_EVT_LOCALE_SAS = 0x0010,
298 327 MR_EVT_LOCALE_CTRL = 0x0020,
299 328 MR_EVT_LOCALE_CONFIG = 0x0040,
300 329 MR_EVT_LOCALE_CLUSTER = 0x0080,
301 330 MR_EVT_LOCALE_ALL = 0xffff
302 331 };
303 332
304 333 enum MR_EVT_ARGS {
305 334 MR_EVT_ARGS_NONE,
306 335 MR_EVT_ARGS_CDB_SENSE,
307 336 MR_EVT_ARGS_LD,
308 337 MR_EVT_ARGS_LD_COUNT,
309 338 MR_EVT_ARGS_LD_LBA,
310 339 MR_EVT_ARGS_LD_OWNER,
311 340 MR_EVT_ARGS_LD_LBA_PD_LBA,
312 341 MR_EVT_ARGS_LD_PROG,
313 342 MR_EVT_ARGS_LD_STATE,
314 343 MR_EVT_ARGS_LD_STRIP,
315 344 MR_EVT_ARGS_PD,
316 345 MR_EVT_ARGS_PD_ERR,
317 346 MR_EVT_ARGS_PD_LBA,
318 347 MR_EVT_ARGS_PD_LBA_LD,
319 348 MR_EVT_ARGS_PD_PROG,
320 349 MR_EVT_ARGS_PD_STATE,
321 350 MR_EVT_ARGS_PCI,
322 351 MR_EVT_ARGS_RATE,
323 352 MR_EVT_ARGS_STR,
324 353 MR_EVT_ARGS_TIME,
325 354 MR_EVT_ARGS_ECC
326 355 };
327 356
328 357 #define MR_EVT_CFG_CLEARED 0x0004
329 358 #define MR_EVT_LD_CREATED 0x008a
330 359 #define MR_EVT_LD_DELETED 0x008b
331 360 #define MR_EVT_CFG_FP_CHANGE 0x017B
332 361
333 362 enum LD_STATE {
334 363 LD_OFFLINE = 0,
335 364 LD_PARTIALLY_DEGRADED = 1,
336 365 LD_DEGRADED = 2,
337 366 LD_OPTIMAL = 3,
338 367 LD_INVALID = 0xFF
339 368 };
340 369
341 370 enum MRSAS_EVT {
342 371 MRSAS_EVT_CONFIG_TGT = 0,
343 372 MRSAS_EVT_UNCONFIG_TGT = 1,
344 373 MRSAS_EVT_UNCONFIG_SMP = 2
345 374 };
346 375
347 376 #define DMA_OBJ_ALLOCATED 1
348 377 #define DMA_OBJ_REALLOCATED 2
349 378 #define DMA_OBJ_FREED 3
350 379
351 380 /*
352 381 * dma_obj_t - Our DMA object
353 382 * @param buffer : kernel virtual address
354 383 * @param size : size of the data to be allocated
355 384 * @param acc_handle : access handle
356 385 * @param dma_handle : dma handle
357 386 * @param dma_cookie : scatter-gather list
358 387 * @param dma_attr : dma attributes for this buffer
359 388 *
360 389 * Our DMA object. The caller must initialize the size and dma attributes
361 390 * (dma_attr) fields before allocating the resources.
362 391 */
363 392 typedef struct {
364 393 caddr_t buffer;
365 394 uint32_t size;
366 395 ddi_acc_handle_t acc_handle;
367 396 ddi_dma_handle_t dma_handle;
368 397 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT];
369 398 ddi_dma_attr_t dma_attr;
370 399 uint8_t status;
371 400 uint8_t reserved[3];
372 401 } dma_obj_t;
373 402
374 403 struct mrsas_eventinfo {
375 404 struct mrsas_instance *instance;
376 405 int tgt;
377 406 int lun;
378 407 int event;
379 408 uint64_t wwn;
380 409 };
381 410
382 411 struct mrsas_ld {
383 412 dev_info_t *dip;
384 413 uint8_t lun_type;
385 414 uint8_t flag;
386 415 uint8_t reserved[2];
387 416 };
388 417
389 418
390 419 #ifdef PDSUPPORT
391 420 struct mrsas_tbolt_pd {
392 421 dev_info_t *dip;
393 422 uint8_t lun_type;
394 423 uint8_t dev_id;
395 424 uint8_t flag;
396 425 uint8_t reserved;
397 426 };
398 427 struct mrsas_tbolt_pd_info {
399 428 uint16_t deviceId;
400 429 uint16_t seqNum;
401 430 uint8_t inquiryData[96];
402 431 uint8_t vpdPage83[64];
403 432 uint8_t notSupported;
404 433 uint8_t scsiDevType;
405 434 uint8_t a;
406 435 uint8_t device_speed;
407 436 uint32_t mediaerrcnt;
408 437 uint32_t other;
409 438 uint32_t pred;
410 439 uint32_t lastpred;
411 440 uint16_t fwState;
412 441 uint8_t disabled;
413 442 uint8_t linkspwwd;
414 443 uint32_t ddfType;
415 444 struct {
416 445 uint8_t count;
417 446 uint8_t isPathBroken;
418 447 uint8_t connectorIndex[2];
419 448 uint8_t reserved[4];
420 449 uint64_t sasAddr[2];
421 450 uint8_t reserved2[16];
422 451 } pathInfo;
423 452 };
424 453 #endif
425 454
426 455 typedef struct mrsas_instance {
427 456 uint32_t *producer;
428 457 uint32_t *consumer;
429 458
430 459 uint32_t *reply_queue;
431 460 dma_obj_t mfi_internal_dma_obj;
432 461 uint16_t adapterresetinprogress;
433 462 uint16_t deadadapter;
434 463 /* ThunderBolt (TB) specific */
435 464 dma_obj_t mpi2_frame_pool_dma_obj;
436 465 dma_obj_t request_desc_dma_obj;
437 466 dma_obj_t reply_desc_dma_obj;
438 467 dma_obj_t ld_map_obj[2];
439 468
440 469 uint8_t init_id;
441 470 uint8_t flag_ieee;
442 471 uint8_t disable_online_ctrl_reset;
443 472 uint8_t fw_fault_count_after_ocr;
444 473
445 474 uint16_t max_num_sge;
446 475 uint16_t max_fw_cmds;
447 476 uint32_t max_sectors_per_req;
448 477
449 478 struct mrsas_cmd **cmd_list;
450 479
451 480 mlist_t cmd_pool_list;
452 481 kmutex_t cmd_pool_mtx;
453 482 kmutex_t sync_map_mtx;
454 483
455 484 mlist_t app_cmd_pool_list;
456 485 kmutex_t app_cmd_pool_mtx;
457 486 mlist_t cmd_app_pool_list;
458 487 kmutex_t cmd_app_pool_mtx;
459 488
460 489
461 490 mlist_t cmd_pend_list;
462 491 kmutex_t cmd_pend_mtx;
463 492
464 493 dma_obj_t mfi_evt_detail_obj;
465 494 struct mrsas_cmd *aen_cmd;
466 495
467 496 uint32_t aen_seq_num;
468 497 uint32_t aen_class_locale_word;
469 498
470 499 scsi_hba_tran_t *tran;
471 500
472 501 kcondvar_t int_cmd_cv;
473 502 kmutex_t int_cmd_mtx;
474 503
475 504 kcondvar_t aen_cmd_cv;
476 505 kmutex_t aen_cmd_mtx;
477 506
478 507 kcondvar_t abort_cmd_cv;
479 508 kmutex_t abort_cmd_mtx;
480 509
481 510 kmutex_t reg_write_mtx;
482 511 kmutex_t chip_mtx;
483 512
484 513 dev_info_t *dip;
485 514 ddi_acc_handle_t pci_handle;
486 515
487 516 timeout_id_t timeout_id;
488 517 uint32_t unique_id;
489 518 uint16_t fw_outstanding;
490 519 caddr_t regmap;
491 520 ddi_acc_handle_t regmap_handle;
492 521 uint8_t isr_level;
493 522 ddi_iblock_cookie_t iblock_cookie;
494 523 ddi_iblock_cookie_t soft_iblock_cookie;
495 524 ddi_softintr_t soft_intr_id;
496 525 uint8_t softint_running;
497 526 uint8_t tbolt_softint_running;
498 527 kmutex_t completed_pool_mtx;
499 528 mlist_t completed_pool_list;
500 529
501 530 caddr_t internal_buf;
502 531 uint32_t internal_buf_dmac_add;
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503 532 uint32_t internal_buf_size;
504 533
505 534 uint16_t vendor_id;
506 535 uint16_t device_id;
507 536 uint16_t subsysvid;
508 537 uint16_t subsysid;
509 538 int instance;
510 539 int baseaddress;
511 540 char iocnode[16];
512 541
513 - /*Driver resources unroll flags.
514 - The flag is set for resources that are needed to be free'd at detach() time */
515 -
516 - struct _unroll {
517 - uint8_t softs; // The software state was allocated.
518 - uint8_t regs; // Controller registers mapped.
519 - uint8_t intr; // Interrupt handler added.
520 - uint8_t reqs; // Request structs allocated.
521 - uint8_t mutexs; // Mutex's allocated.
522 - uint8_t taskq; // Task q's created.
523 - uint8_t tran; // Tran struct allocated
524 - uint8_t tranSetup; // Tran attached to the ddi.
525 - uint8_t devctl; // Device nodes for cfgadm created.
526 - uint8_t scsictl; // Device nodes for cfgadm created.
527 - uint8_t ioctl; // Device nodes for ioctl's created.
528 - uint8_t timer; // Timer started.
529 - uint8_t aenPend; // AEN cmd pending f/w.
530 - uint8_t mapUpdate_pend; // LD MAP update cmd pending f/w.
531 - uint8_t soft_isr;
532 - uint8_t ldlist_buff;
533 - uint8_t pdlist_buff;
534 - uint8_t syncCmd;
535 - uint8_t verBuff;
536 - uint8_t alloc_space_mfi;
537 - uint8_t alloc_space_mpi2;
542 + int fm_capabilities;
543 + /*
544 + * Driver resources unroll flags. The flag is set for resources that
545 + * are needed to be free'd at detach() time.
546 + */
547 + struct _unroll {
548 + uint8_t softs; /* The software state was allocated. */
549 + uint8_t regs; /* Controller registers mapped. */
550 + uint8_t intr; /* Interrupt handler added. */
551 + uint8_t reqs; /* Request structs allocated. */
552 + uint8_t mutexs; /* Mutex's allocated. */
553 + uint8_t taskq; /* Task q's created. */
554 + uint8_t tran; /* Tran struct allocated */
555 + uint8_t tranSetup; /* Tran attached to the ddi. */
556 + uint8_t devctl; /* Device nodes for cfgadm created. */
557 + uint8_t scsictl; /* Device nodes for cfgadm created. */
558 + uint8_t ioctl; /* Device nodes for ioctl's created. */
559 + uint8_t timer; /* Timer started. */
560 + uint8_t aenPend; /* AEN cmd pending f/w. */
561 + uint8_t mapUpdate_pend; /* LD MAP update cmd pending f/w. */
562 + uint8_t soft_isr; /* Soft interrupt handler allocated. */
563 + uint8_t ldlist_buff; /* Logical disk list allocated. */
564 + uint8_t pdlist_buff; /* Physical disk list allocated. */
565 + uint8_t syncCmd; /* Sync map command allocated. */
566 + uint8_t verBuff; /* 2108 MFI buffer allocated. */
567 + uint8_t alloc_space_mfi; /* Allocated space for 2108 MFI. */
568 + uint8_t alloc_space_mpi2; /* Allocated space for 2208 MPI2. */
538 569 } unroll;
539 570
540 571
541 572 /* function template pointer */
542 573 struct mrsas_function_template *func_ptr;
543 574
544 575
545 576 /* MSI interrupts specific */
546 - ddi_intr_handle_t *intr_htable; //Interrupt handle array
547 - size_t intr_htable_size; //Interrupt handle array size
577 + ddi_intr_handle_t *intr_htable; /* Interrupt handle array */
578 + size_t intr_htable_size; /* Int. handle array size */
548 579 int intr_type;
549 580 int intr_cnt;
550 581 uint_t intr_pri;
551 582 int intr_cap;
552 583
553 584 ddi_taskq_t *taskq;
554 585 struct mrsas_ld *mr_ld_list;
555 586 kmutex_t config_dev_mtx;
556 587 /* ThunderBolt (TB) specific */
557 588 ddi_softintr_t tbolt_soft_intr_id;
558 589
559 590 #ifdef PDSUPPORT
560 591 uint32_t mr_tbolt_pd_max;
561 592 struct mrsas_tbolt_pd *mr_tbolt_pd_list;
562 593 #endif
563 594
564 595 uint8_t fast_path_io;
565 596
566 597 uint16_t tbolt;
567 598 uint16_t reply_read_index;
568 - uint16_t reply_size; // Single Reply structure size
569 - uint16_t raid_io_msg_size; // Single message size
599 + uint16_t reply_size; /* Single Reply struct size */
600 + uint16_t raid_io_msg_size; /* Single message size */
570 601 uint32_t io_request_frames_phy;
571 602 uint8_t *io_request_frames;
572 - MRSAS_REQUEST_DESCRIPTOR_UNION *request_message_pool; // Virtual address of request desc frame pool
573 - uint32_t request_message_pool_phy; // Physical address of request desc frame pool
574 - MPI2_REPLY_DESCRIPTORS_UNION *reply_frame_pool; // Virtual address of reply Frame
575 - uint32_t reply_frame_pool_phy; // Physical address of reply Frame
576 - uint8_t *reply_pool_limit; // Last reply frame address
577 - uint32_t reply_pool_limit_phy; // Physical address of Last reply frame
578 - uint32_t reply_q_depth; // Reply Queue Depth
603 + /* Virtual address of request desc frame pool */
604 + MRSAS_REQUEST_DESCRIPTOR_UNION *request_message_pool;
605 + /* Physical address of request desc frame pool */
606 + uint32_t request_message_pool_phy;
607 + /* Virtual address of reply Frame */
608 + MPI2_REPLY_DESCRIPTORS_UNION *reply_frame_pool;
609 + /* Physical address of reply Frame */
610 + uint32_t reply_frame_pool_phy;
611 + uint8_t *reply_pool_limit; /* Last reply frame address */
612 + /* Physical address of Last reply frame */
613 + uint32_t reply_pool_limit_phy;
614 + uint32_t reply_q_depth; /* Reply Queue Depth */
579 615 uint8_t max_sge_in_main_msg;
580 616 uint8_t max_sge_in_chain;
581 617 uint8_t chain_offset_io_req;
582 618 uint8_t chain_offset_mpt_msg;
583 619 MR_FW_RAID_MAP_ALL *ld_map[2];
584 620 uint32_t ld_map_phy[2];
585 621 uint32_t size_map_info;
586 622 uint64_t map_id;
587 623 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
588 624 struct mrsas_cmd *map_update_cmd;
589 625 uint32_t SyncRequired;
590 626 kmutex_t ocr_flags_mtx;
591 - dma_obj_t drv_ver_dma_obj;
627 + dma_obj_t drv_ver_dma_obj;
592 628 } mrsas_t;
593 629
594 630
595 631 /*
596 632 * Function templates for various controller specific functions
597 633 */
598 634 struct mrsas_function_template {
599 635 uint32_t (*read_fw_status_reg)(struct mrsas_instance *);
600 636 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *);
601 637 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
602 638 struct mrsas_cmd *);
603 639 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
604 640 struct mrsas_cmd *);
605 641 void (*enable_intr)(struct mrsas_instance *);
606 642 void (*disable_intr)(struct mrsas_instance *);
607 643 int (*intr_ack)(struct mrsas_instance *);
608 644 int (*init_adapter)(struct mrsas_instance *);
609 -// int (*reset_adapter)(struct mrsas_instance *);
645 +/* int (*reset_adapter)(struct mrsas_instance *); */
610 646 };
611 647
612 648 /*
613 649 * ### Helper routines ###
614 650 */
615 651
616 652 /*
617 653 * con_log() - console log routine
618 654 * @param level : indicates the severity of the message.
619 655 * @fparam mt : format string
620 656 *
621 657 * con_log displays the error messages on the console based on the current
622 658 * debug level. Also it attaches the appropriate kernel severity level with
623 659 * the message.
624 660 *
625 661 *
626 662 * console messages debug levels
627 663 */
628 664 #define CL_NONE 0 /* No debug information */
629 665 #define CL_ANN 1 /* print unconditionally, announcements */
630 -#define CL_ANN1 2 /* No o/p */
666 +#define CL_ANN1 2 /* No-op */
631 667 #define CL_DLEVEL1 3 /* debug level 1, informative */
632 668 #define CL_DLEVEL2 4 /* debug level 2, verbose */
633 669 #define CL_DLEVEL3 5 /* debug level 3, very verbose */
634 670
635 671 #ifdef __SUNPRO_C
636 -#define __func__ __FUNCTION__ //""
672 +#define __func__ ""
637 673 #endif
638 674
639 675 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
640 676
641 677 /*
642 678 * ### SCSA definitions ###
643 679 */
644 680 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target)
645 681 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun)
646 682 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran)
647 683 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
648 684
649 685 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private)
650 686 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap))
651 687
652 688 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private)
653 689 #define CMD2PKT(sp) ((sp)->cmd_pkt)
654 690 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request))
655 691
656 692 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address)
657 693 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran)
658 694 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd)))
659 695
660 696 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */
661 697 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */
662 698 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */
663 699
664 700 /*
665 701 * ### Data structures for ioctl inteface and internal commands ###
666 702 */
667 703
668 704 /*
669 705 * Data direction flags
670 706 */
671 707 #define UIOC_RD 0x00001
672 708 #define UIOC_WR 0x00002
673 709
674 710 #define SCP2HOST(scp) (scp)->device->host /* to host */
675 711 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */
676 712 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */
677 713 #define SCP2TARGET(scp) (scp)->device->id /* to target */
678 714 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */
679 715
680 716 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
681 717 #define SCP2ADAPTER(scp) \
682 718 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
683 719
684 720 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \
685 721 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0
686 722 #define MRDRV_IS_LOGICAL(ap) \
687 723 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0
688 724 #define MAP_DEVICE_ID(instance, ap) \
689 725 (ap->a_target)
690 726
691 727 #define HIGH_LEVEL_INTR 1
692 728 #define NORMAL_LEVEL_INTR 0
693 729
694 730 #define IO_TIMEOUT_VAL 0
695 731 #define IO_RETRY_COUNT 3
696 732 #define MAX_FW_RESET_COUNT 3
697 733 /*
698 734 * scsa_cmd - Per-command mr private data
699 735 * @param cmd_dmahandle : dma handle
700 736 * @param cmd_dmacookies : current dma cookies
701 737 * @param cmd_pkt : scsi_pkt reference
702 738 * @param cmd_dmacount : dma count
703 739 * @param cmd_cookie : next cookie
704 740 * @param cmd_ncookies : cookies per window
705 741 * @param cmd_cookiecnt : cookies per sub-win
706 742 * @param cmd_nwin : number of dma windows
707 743 * @param cmd_curwin : current dma window
708 744 * @param cmd_dma_offset : current window offset
709 745 * @param cmd_dma_len : current window length
710 746 * @param cmd_flags : private flags
711 747 * @param cmd_cdblen : length of cdb
712 748 * @param cmd_scblen : length of scb
713 749 * @param cmd_buf : command buffer
714 750 * @param channel : channel for scsi sub-system
715 751 * @param target : target for scsi sub-system
716 752 * @param lun : LUN for scsi sub-system
717 753 *
718 754 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E)
719 755 * - Pointed to by pkt_ha_private field in scsi_pkt
720 756 */
721 757 struct scsa_cmd {
722 758 ddi_dma_handle_t cmd_dmahandle;
723 759 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT];
724 760 struct scsi_pkt *cmd_pkt;
725 761 ulong_t cmd_dmacount;
726 762 uint_t cmd_cookie;
727 763 uint_t cmd_ncookies;
728 764 uint_t cmd_cookiecnt;
729 765 uint_t cmd_nwin;
730 766 uint_t cmd_curwin;
731 767 off_t cmd_dma_offset;
732 768 ulong_t cmd_dma_len;
733 769 ulong_t cmd_flags;
734 770 uint_t cmd_cdblen;
735 771 uint_t cmd_scblen;
736 772 struct buf *cmd_buf;
737 773 ushort_t device_id;
738 774 uchar_t islogical;
739 775 uchar_t lun;
740 776 struct mrsas_device *mrsas_dev;
741 777 };
742 778
743 779
744 780 struct mrsas_cmd {
745 781 /*
746 782 * ThunderBolt(TB) We would be needing to have a placeholder
747 783 * for RAID_MSG_IO_REQUEST inside this structure. We are
748 784 * supposed to embed the mr_frame inside the RAID_MSG and post
749 785 * it down to the firmware.
750 786 */
751 787 union mrsas_frame *frame;
752 788 uint32_t frame_phys_addr;
753 789 uint8_t *sense;
754 790 uint8_t *sense1;
755 791 uint32_t sense_phys_addr;
756 792 uint32_t sense_phys_addr1;
757 793 dma_obj_t frame_dma_obj;
758 794 uint8_t frame_dma_obj_status;
759 795 uint32_t index;
760 796 uint8_t sync_cmd;
761 797 uint8_t cmd_status;
762 798 uint16_t abort_aen;
763 799 mlist_t list;
764 800 uint32_t frame_count;
765 801 struct scsa_cmd *cmd;
766 802 struct scsi_pkt *pkt;
767 803 Mpi2RaidSCSIIORequest_t *scsi_io_request;
768 804 Mpi2SGEIOUnion_t *sgl;
769 805 uint32_t sgl_phys_addr;
770 806 uint32_t scsi_io_request_phys_addr;
771 807 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
772 808 uint16_t SMID;
773 809 uint16_t retry_count_for_ocr;
774 810 uint16_t drv_pkt_time;
775 811 uint16_t load_balance_flag;
776 812
777 813 };
778 814
779 815 #define MAX_MGMT_ADAPTERS 1024
780 816 #define IOC_SIGNATURE "MR-SAS"
781 817
782 818 #define IOC_CMD_FIRMWARE 0x0
783 819 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000
784 820 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
785 821 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
786 822 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300
787 823
788 824
789 825 #define MRSAS_MAX_SENSE_LENGTH 32
790 826
791 827 struct mrsas_mgmt_info {
792 828
793 829 uint16_t count;
794 830 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS];
795 831 uint16_t map[MAX_MGMT_ADAPTERS];
796 832 int max_index;
797 833 };
798 834
799 835
800 836 #pragma pack(1)
801 837 /*
802 838 * SAS controller properties
803 839 */
804 840 struct mrsas_ctrl_prop {
805 841 uint16_t seq_num;
806 842 uint16_t pred_fail_poll_interval;
807 843 uint16_t intr_throttle_count;
808 844 uint16_t intr_throttle_timeouts;
809 845
810 846 uint8_t rebuild_rate;
811 847 uint8_t patrol_read_rate;
812 848 uint8_t bgi_rate;
813 849 uint8_t cc_rate;
814 850 uint8_t recon_rate;
815 851
816 852 uint8_t cache_flush_interval;
817 853
818 854 uint8_t spinup_drv_count;
819 855 uint8_t spinup_delay;
820 856
821 857 uint8_t cluster_enable;
822 858 uint8_t coercion_mode;
823 859 uint8_t alarm_enable;
824 860
825 861 uint8_t reserved_1[13];
826 862 uint32_t on_off_properties;
827 863 uint8_t reserved_4[28];
828 864 };
829 865
830 866
831 867 /*
832 868 * SAS controller information
833 869 */
834 870 struct mrsas_ctrl_info {
835 871 /* PCI device information */
836 872 struct {
837 873 uint16_t vendor_id;
838 874 uint16_t device_id;
839 875 uint16_t sub_vendor_id;
840 876 uint16_t sub_device_id;
841 877 uint8_t reserved[24];
842 878 } pci;
843 879
844 880 /* Host interface information */
845 881 struct {
846 882 uint8_t PCIX : 1;
847 883 uint8_t PCIE : 1;
848 884 uint8_t iSCSI : 1;
849 885 uint8_t SAS_3G : 1;
850 886 uint8_t reserved_0 : 4;
851 887 uint8_t reserved_1[6];
852 888 uint8_t port_count;
853 889 uint64_t port_addr[8];
854 890 } host_interface;
855 891
856 892 /* Device (backend) interface information */
857 893 struct {
858 894 uint8_t SPI : 1;
859 895 uint8_t SAS_3G : 1;
860 896 uint8_t SATA_1_5G : 1;
861 897 uint8_t SATA_3G : 1;
862 898 uint8_t reserved_0 : 4;
863 899 uint8_t reserved_1[6];
864 900 uint8_t port_count;
865 901 uint64_t port_addr[8];
866 902 } device_interface;
867 903
868 904 /* List of components residing in flash. All str are null terminated */
869 905 uint32_t image_check_word;
870 906 uint32_t image_component_count;
871 907
872 908 struct {
873 909 char name[8];
874 910 char version[32];
875 911 char build_date[16];
876 912 char built_time[16];
877 913 } image_component[8];
878 914
879 915 /*
880 916 * List of flash components that have been flashed on the card, but
881 917 * are not in use, pending reset of the adapter. This list will be
882 918 * empty if a flash operation has not occurred. All stings are null
883 919 * terminated
884 920 */
885 921 uint32_t pending_image_component_count;
886 922
887 923 struct {
888 924 char name[8];
889 925 char version[32];
890 926 char build_date[16];
891 927 char build_time[16];
892 928 } pending_image_component[8];
893 929
894 930 uint8_t max_arms;
895 931 uint8_t max_spans;
896 932 uint8_t max_arrays;
897 933 uint8_t max_lds;
898 934
899 935 char product_name[80];
900 936 char serial_no[32];
901 937
902 938 /*
903 939 * Other physical/controller/operation information. Indicates the
904 940 * presence of the hardware
905 941 */
906 942 struct {
907 943 uint32_t bbu : 1;
908 944 uint32_t alarm : 1;
909 945 uint32_t nvram : 1;
910 946 uint32_t uart : 1;
911 947 uint32_t reserved : 28;
912 948 } hw_present;
913 949
914 950 uint32_t current_fw_time;
915 951
916 952 /* Maximum data transfer sizes */
917 953 uint16_t max_concurrent_cmds;
918 954 uint16_t max_sge_count;
919 955 uint32_t max_request_size;
920 956
921 957 /* Logical and physical device counts */
922 958 uint16_t ld_present_count;
923 959 uint16_t ld_degraded_count;
924 960 uint16_t ld_offline_count;
925 961
926 962 uint16_t pd_present_count;
927 963 uint16_t pd_disk_present_count;
928 964 uint16_t pd_disk_pred_failure_count;
929 965 uint16_t pd_disk_failed_count;
930 966
931 967 /* Memory size information */
932 968 uint16_t nvram_size;
933 969 uint16_t memory_size;
934 970 uint16_t flash_size;
935 971
936 972 /* Error counters */
937 973 uint16_t mem_correctable_error_count;
938 974 uint16_t mem_uncorrectable_error_count;
939 975
940 976 /* Cluster information */
941 977 uint8_t cluster_permitted;
942 978 uint8_t cluster_active;
943 979 uint8_t reserved_1[2];
944 980
945 981 /* Controller capabilities structures */
946 982 struct {
947 983 uint32_t raid_level_0 : 1;
948 984 uint32_t raid_level_1 : 1;
949 985 uint32_t raid_level_5 : 1;
950 986 uint32_t raid_level_1E : 1;
951 987 uint32_t reserved : 28;
952 988 } raid_levels;
953 989
954 990 struct {
955 991 uint32_t rbld_rate : 1;
956 992 uint32_t cc_rate : 1;
957 993 uint32_t bgi_rate : 1;
958 994 uint32_t recon_rate : 1;
959 995 uint32_t patrol_rate : 1;
960 996 uint32_t alarm_control : 1;
961 997 uint32_t cluster_supported : 1;
962 998 uint32_t bbu : 1;
963 999 uint32_t spanning_allowed : 1;
964 1000 uint32_t dedicated_hotspares : 1;
965 1001 uint32_t revertible_hotspares : 1;
966 1002 uint32_t foreign_config_import : 1;
967 1003 uint32_t self_diagnostic : 1;
968 1004 uint32_t reserved : 19;
969 1005 } adapter_operations;
970 1006
971 1007 struct {
972 1008 uint32_t read_policy : 1;
973 1009 uint32_t write_policy : 1;
974 1010 uint32_t io_policy : 1;
975 1011 uint32_t access_policy : 1;
976 1012 uint32_t reserved : 28;
977 1013 } ld_operations;
978 1014
979 1015 struct {
980 1016 uint8_t min;
981 1017 uint8_t max;
982 1018 uint8_t reserved[2];
983 1019 } stripe_size_operations;
984 1020
985 1021 struct {
986 1022 uint32_t force_online : 1;
987 1023 uint32_t force_offline : 1;
988 1024 uint32_t force_rebuild : 1;
989 1025 uint32_t reserved : 29;
990 1026 } pd_operations;
991 1027
992 1028 struct {
993 1029 uint32_t ctrl_supports_sas : 1;
994 1030 uint32_t ctrl_supports_sata : 1;
995 1031 uint32_t allow_mix_in_encl : 1;
996 1032 uint32_t allow_mix_in_ld : 1;
997 1033 uint32_t allow_sata_in_cluster : 1;
998 1034 uint32_t reserved : 27;
999 1035 } pd_mix_support;
1000 1036
1001 1037 /* Include the controller properties (changeable items) */
1002 1038 uint8_t reserved_2[12];
1003 1039 struct mrsas_ctrl_prop properties;
1004 1040
1005 1041 uint8_t pad[0x800 - 0x640];
1006 1042 };
1007 1043
1008 1044 /*
1009 1045 * ==================================
1010 1046 * MegaRAID SAS2.0 driver definitions
1011 1047 * ==================================
1012 1048 */
1013 1049 #define MRDRV_MAX_NUM_CMD 1024
1014 1050
1015 1051 #define MRDRV_MAX_PD_CHANNELS 2
1016 1052 #define MRDRV_MAX_LD_CHANNELS 2
1017 1053 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \
1018 1054 MRDRV_MAX_LD_CHANNELS)
1019 1055 #define MRDRV_MAX_DEV_PER_CHANNEL 128
1020 1056 #define MRDRV_DEFAULT_INIT_ID -1
1021 1057 #define MRDRV_MAX_CMD_PER_LUN 1000
1022 1058 #define MRDRV_MAX_LUN 1
1023 1059 #define MRDRV_MAX_LD 64
1024 1060
1025 1061 #define MRDRV_RESET_WAIT_TIME 300
1026 1062 #define MRDRV_RESET_NOTICE_INTERVAL 5
1027 1063
1028 1064 #define MRSAS_IOCTL_CMD 0
1029 1065
1030 1066 #define MRDRV_TGT_VALID 1
1031 1067
1032 1068 /*
1033 1069 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1034 1070 * SGLs based on the size of dma_addr_t
1035 1071 */
1036 1072 #define IS_DMA64 (sizeof (dma_addr_t) == 8)
1037 1073
1038 1074 #define RESERVED0_REGISTER 0x00 /* XScale */
1039 1075 #define IB_MSG_0_OFF 0x10 /* XScale */
1040 1076 #define OB_MSG_0_OFF 0x18 /* XScale */
1041 1077 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */
1042 1078 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */
1043 1079 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */
1044 1080 #define IB_QPORT_OFF 0x40 /* XScale & ROC */
1045 1081 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */
1046 1082 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */
1047 1083 #define OB_INTR_MASK 0xFFFFFFFF
1048 1084 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF
1049 1085 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1050 1086 #define OB_SCRATCH_PAD_2_OFF 0xB4
1051 1087 #define WRITE_TBOLT_SEQ_OFF 0x00000004
1052 1088 #define DIAG_TBOLT_RESET_ADAPTER 0x00000004
1053 1089 #define HOST_TBOLT_DIAG_OFF 0x00000008
1054 1090 #define RESET_TBOLT_STATUS_OFF 0x000003C3
1055 1091 #define WRITE_SEQ_OFF 0x000000FC
1056 1092 #define HOST_DIAG_OFF 0x000000F8
1057 1093 #define DIAG_RESET_ADAPTER 0x00000004
1058 1094 #define DIAG_WRITE_ENABLE 0x00000080
1059 1095 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1060 1096
1061 1097 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \
1062 1098 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v))
1063 1099
1064 1100 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \
1065 1101 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF))
1066 1102
1067 1103 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \
1068 1104 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v))
1069 1105
1070 1106 #define IB_LOW_QPORT 0xC0
1071 1107 #define IB_HIGH_QPORT 0xC4
1072 1108 #define OB_DOORBELL_REGISTER 0x9C /* 1078 implementation */
1073 1109
1074 1110 /*
1075 1111 * All MFI register set macros accept mrsas_register_set*
1076 1112 */
1077 1113 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \
1078 1114 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
1079 1115
1080 1116 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \
1081 1117 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
1082 1118
1083 1119 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \
1084 1120 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
1085 1121
1086 1122 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \
1087 1123 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
1088 1124
1089 1125 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \
1090 1126 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
1091 1127
1092 1128 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \
1093 1129 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
1094 1130
1095 1131 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \
1096 1132 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
1097 1133
1098 1134 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \
1099 1135 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
1100 1136
1101 1137 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1102 1138 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
1103 1139
1104 1140 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
1105 1141 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
1106 1142 (v))
1107 1143
1108 1144 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \
1109 1145 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
1110 1146
1111 1147 /* Thunderbolt specific registers */
1112 1148 #define RD_OB_SCRATCH_PAD_2(instance) ddi_get32((instance)->regmap_handle, \
1113 1149 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_2_OFF))
1114 1150
1115 1151 #define WR_TBOLT_IB_WRITE_SEQ(v, instance) \
1116 1152 ddi_put32((instance)->regmap_handle, \
1117 1153 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_TBOLT_SEQ_OFF), (v))
1118 1154
1119 1155 #define RD_TBOLT_HOST_DIAG(instance) ddi_get32((instance)->regmap_handle, \
1120 1156 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF))
1121 1157
1122 1158 #define WR_TBOLT_HOST_DIAG(v, instance) ddi_put32((instance)->regmap_handle, \
1123 1159 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF), (v))
1124 1160
1125 1161 #define RD_TBOLT_RESET_STAT(instance) ddi_get32((instance)->regmap_handle, \
1126 1162 (uint32_t *)((uintptr_t)(instance)->regmap + RESET_TBOLT_STATUS_OFF))
1127 1163
1128 1164
1129 1165 #define WR_MPI2_REPLY_POST_INDEX(v, instance)\
1130 1166 ddi_put32((instance)->regmap_handle,\
1131 1167 (uint32_t *)\
1132 1168 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET),\
1133 1169 (v))
1134 1170
1135 1171
1136 1172 #define RD_MPI2_REPLY_POST_INDEX(instance)\
1137 1173 ddi_get32((instance)->regmap_handle,\
1138 1174 (uint32_t *)\
1139 1175 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET))
1140 1176
1141 1177 #define WR_IB_LOW_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1142 1178 (uint32_t *)((uintptr_t)(instance)->regmap + IB_LOW_QPORT), (v))
1143 1179
1144 1180 #define WR_IB_HIGH_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1145 1181 (uint32_t *)((uintptr_t)(instance)->regmap + IB_HIGH_QPORT), (v))
1146 1182
1147 1183 #define WR_OB_DOORBELL_REGISTER_CLEAR(v, instance)\
1148 1184 ddi_put32((instance)->regmap_handle,\
1149 1185 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_REGISTER), \
1150 1186 (v))
1151 1187
1152 1188 #define WR_RESERVED0_REGISTER(v, instance) ddi_put32((instance)->regmap_handle,\
1153 1189 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER), \
1154 1190 (v))
1155 1191
1156 1192 #define RD_RESERVED0_REGISTER(instance) ddi_get32((instance)->regmap_handle, \
1157 1193 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER))
1158 1194
1159 1195
1160 1196
1161 1197 /*
1162 1198 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
1163 1199 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
1164 1200 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
1165 1201 */
1166 1202 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1167 1203
1168 1204 /*
1169 1205 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also
1170 1206 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
1171 1207 * been set in this flag along with bit 1.
1172 1208 */
1173 1209 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001
1174 1210 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005
1175 1211
1176 1212 /* Fusion interrupt mask */
1177 1213 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008)
1178 1214
1179 1215 #define MFI_POLL_TIMEOUT_SECS 60
1180 1216
1181 1217 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \
1182 1218 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
1183 1219 #define MFI_DISABLE_INTR(instance) \
1184 1220 { \
1185 1221 uint32_t disable = 1; \
1186 1222 uint32_t mask = ddi_get32((instance)->regmap_handle, \
1187 1223 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
1188 1224 mask &= ~disable; \
1189 1225 ddi_put32((instance)->regmap_handle, (uint32_t *) \
1190 1226 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \
1191 1227 }
1192 1228
1193 1229 /* By default, the firmware programs for 8 Kbytes of memory */
1194 1230 #define DEFAULT_MFI_MEM_SZ 8192
1195 1231 #define MINIMUM_MFI_MEM_SZ 4096
1196 1232
1197 1233 /* DCMD Message Frame MAILBOX0-11 */
1198 1234 #define DCMD_MBOX_SZ 12
1199 1235
1200 1236 /*
1201 1237 * on_off_property of mrsas_ctrl_prop
1202 1238 * bit0-9, 11-31 are reserved
1203 1239 */
1204 1240 #define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */
1205 1241
1206 1242 struct mrsas_register_set {
1207 1243 uint32_t reserved_0[4]; /* 0000h */
1208 1244
1209 1245 uint32_t inbound_msg_0; /* 0010h */
1210 1246 uint32_t inbound_msg_1; /* 0014h */
1211 1247 uint32_t outbound_msg_0; /* 0018h */
1212 1248 uint32_t outbound_msg_1; /* 001Ch */
1213 1249
1214 1250 uint32_t inbound_doorbell; /* 0020h */
1215 1251 uint32_t inbound_intr_status; /* 0024h */
1216 1252 uint32_t inbound_intr_mask; /* 0028h */
1217 1253
1218 1254 uint32_t outbound_doorbell; /* 002Ch */
1219 1255 uint32_t outbound_intr_status; /* 0030h */
1220 1256 uint32_t outbound_intr_mask; /* 0034h */
1221 1257
1222 1258 uint32_t reserved_1[2]; /* 0038h */
1223 1259
1224 1260 uint32_t inbound_queue_port; /* 0040h */
1225 1261 uint32_t outbound_queue_port; /* 0044h */
1226 1262
1227 1263 uint32_t reserved_2[22]; /* 0048h */
1228 1264
1229 1265 uint32_t outbound_doorbell_clear; /* 00A0h */
1230 1266
1231 1267 uint32_t reserved_3[3]; /* 00A4h */
1232 1268
1233 1269 uint32_t outbound_scratch_pad; /* 00B0h */
1234 1270
1235 1271 uint32_t reserved_4[3]; /* 00B4h */
1236 1272
1237 1273 uint32_t inbound_low_queue_port; /* 00C0h */
1238 1274
1239 1275 uint32_t inbound_high_queue_port; /* 00C4h */
1240 1276
1241 1277 uint32_t reserved_5; /* 00C8h */
1242 1278 uint32_t index_registers[820]; /* 00CCh */
1243 1279 };
1244 1280
1245 1281 struct mrsas_sge32 {
1246 1282 uint32_t phys_addr;
1247 1283 uint32_t length;
1248 1284 };
1249 1285
1250 1286 struct mrsas_sge64 {
1251 1287 uint64_t phys_addr;
1252 1288 uint32_t length;
1253 1289 };
1254 1290
1255 1291 struct mrsas_sge_ieee {
1256 1292 uint64_t phys_addr;
1257 1293 uint32_t length;
1258 1294 uint32_t flag;
1259 1295 };
1260 1296
1261 1297 union mrsas_sgl {
1262 1298 struct mrsas_sge32 sge32[1];
1263 1299 struct mrsas_sge64 sge64[1];
1264 1300 struct mrsas_sge_ieee sge_ieee[1];
1265 1301 };
1266 1302
1267 1303 struct mrsas_header {
1268 1304 uint8_t cmd; /* 00h */
1269 1305 uint8_t sense_len; /* 01h */
1270 1306 uint8_t cmd_status; /* 02h */
1271 1307 uint8_t scsi_status; /* 03h */
1272 1308
1273 1309 uint8_t target_id; /* 04h */
1274 1310 uint8_t lun; /* 05h */
1275 1311 uint8_t cdb_len; /* 06h */
1276 1312 uint8_t sge_count; /* 07h */
1277 1313
1278 1314 uint32_t context; /* 08h */
1279 1315 uint8_t req_id; /* 0Ch */
1280 1316 uint8_t msgvector; /* 0Dh */
1281 1317 uint16_t pad_0; /* 0Eh */
1282 1318
1283 1319 uint16_t flags; /* 10h */
1284 1320 uint16_t timeout; /* 12h */
1285 1321 uint32_t data_xferlen; /* 14h */
1286 1322 };
1287 1323
1288 1324 union mrsas_sgl_frame {
1289 1325 struct mrsas_sge32 sge32[8];
1290 1326 struct mrsas_sge64 sge64[5];
1291 1327 };
1292 1328
1293 1329 struct mrsas_init_frame {
1294 1330 uint8_t cmd; /* 00h */
1295 1331 uint8_t reserved_0; /* 01h */
1296 1332 uint8_t cmd_status; /* 02h */
1297 1333
1298 1334 uint8_t reserved_1; /* 03h */
1299 1335 uint32_t reserved_2; /* 04h */
1300 1336
1301 1337 uint32_t context; /* 08h */
1302 1338 uint8_t req_id; /* 0Ch */
1303 1339 uint8_t msgvector; /* 0Dh */
1304 1340 uint16_t pad_0; /* 0Eh */
1305 1341
1306 1342 uint16_t flags; /* 10h */
1307 1343 uint16_t reserved_3; /* 12h */
1308 1344 uint32_t data_xfer_len; /* 14h */
1309 1345
1310 1346 uint32_t queue_info_new_phys_addr_lo; /* 18h */
1311 1347 uint32_t queue_info_new_phys_addr_hi; /* 1Ch */
1312 1348 uint32_t queue_info_old_phys_addr_lo; /* 20h */
1313 1349 uint32_t queue_info_old_phys_addr_hi; /* 24h */
1314 1350 uint64_t driverversion; /* 28h */
1315 1351 uint32_t reserved_4[4]; /* 30h */
1316 1352 };
1317 1353
1318 1354 struct mrsas_init_queue_info {
1319 1355 uint32_t init_flags; /* 00h */
1320 1356 uint32_t reply_queue_entries; /* 04h */
1321 1357
1322 1358 uint32_t reply_queue_start_phys_addr_lo; /* 08h */
1323 1359 uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */
1324 1360 uint32_t producer_index_phys_addr_lo; /* 10h */
1325 1361 uint32_t producer_index_phys_addr_hi; /* 14h */
1326 1362 uint32_t consumer_index_phys_addr_lo; /* 18h */
1327 1363 uint32_t consumer_index_phys_addr_hi; /* 1Ch */
1328 1364 };
1329 1365
1330 1366 struct mrsas_io_frame {
1331 1367 uint8_t cmd; /* 00h */
1332 1368 uint8_t sense_len; /* 01h */
1333 1369 uint8_t cmd_status; /* 02h */
1334 1370 uint8_t scsi_status; /* 03h */
1335 1371
1336 1372 uint8_t target_id; /* 04h */
1337 1373 uint8_t access_byte; /* 05h */
1338 1374 uint8_t reserved_0; /* 06h */
1339 1375 uint8_t sge_count; /* 07h */
1340 1376
1341 1377 uint32_t context; /* 08h */
1342 1378 uint8_t req_id; /* 0Ch */
1343 1379 uint8_t msgvector; /* 0Dh */
1344 1380 uint16_t pad_0; /* 0Eh */
1345 1381
1346 1382 uint16_t flags; /* 10h */
1347 1383 uint16_t timeout; /* 12h */
1348 1384 uint32_t lba_count; /* 14h */
1349 1385
1350 1386 uint32_t sense_buf_phys_addr_lo; /* 18h */
1351 1387 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1352 1388
1353 1389 uint32_t start_lba_lo; /* 20h */
1354 1390 uint32_t start_lba_hi; /* 24h */
1355 1391
1356 1392 union mrsas_sgl sgl; /* 28h */
1357 1393 };
1358 1394
1359 1395 struct mrsas_pthru_frame {
1360 1396 uint8_t cmd; /* 00h */
1361 1397 uint8_t sense_len; /* 01h */
1362 1398 uint8_t cmd_status; /* 02h */
1363 1399 uint8_t scsi_status; /* 03h */
1364 1400
1365 1401 uint8_t target_id; /* 04h */
1366 1402 uint8_t lun; /* 05h */
1367 1403 uint8_t cdb_len; /* 06h */
1368 1404 uint8_t sge_count; /* 07h */
1369 1405
1370 1406 uint32_t context; /* 08h */
1371 1407 uint8_t req_id; /* 0Ch */
1372 1408 uint8_t msgvector; /* 0Dh */
1373 1409 uint16_t pad_0; /* 0Eh */
1374 1410
1375 1411 uint16_t flags; /* 10h */
1376 1412 uint16_t timeout; /* 12h */
1377 1413 uint32_t data_xfer_len; /* 14h */
1378 1414
1379 1415 uint32_t sense_buf_phys_addr_lo; /* 18h */
1380 1416 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1381 1417
1382 1418 uint8_t cdb[16]; /* 20h */
1383 1419 union mrsas_sgl sgl; /* 30h */
1384 1420 };
1385 1421
1386 1422 struct mrsas_dcmd_frame {
1387 1423 uint8_t cmd; /* 00h */
1388 1424 uint8_t reserved_0; /* 01h */
1389 1425 uint8_t cmd_status; /* 02h */
1390 1426 uint8_t reserved_1[4]; /* 03h */
1391 1427 uint8_t sge_count; /* 07h */
1392 1428
1393 1429 uint32_t context; /* 08h */
1394 1430 uint8_t req_id; /* 0Ch */
1395 1431 uint8_t msgvector; /* 0Dh */
1396 1432 uint16_t pad_0; /* 0Eh */
1397 1433
1398 1434 uint16_t flags; /* 10h */
1399 1435 uint16_t timeout; /* 12h */
1400 1436
1401 1437 uint32_t data_xfer_len; /* 14h */
1402 1438 uint32_t opcode; /* 18h */
1403 1439
1404 1440 /* uint8_t mbox[DCMD_MBOX_SZ]; */ /* 1Ch */
1405 1441 union { /* 1Ch */
1406 1442 uint8_t b[DCMD_MBOX_SZ];
1407 1443 uint16_t s[6];
1408 1444 uint32_t w[3];
1409 1445 } mbox;
1410 1446
1411 1447 union mrsas_sgl sgl; /* 28h */
1412 1448 };
1413 1449
1414 1450 struct mrsas_abort_frame {
1415 1451 uint8_t cmd; /* 00h */
1416 1452 uint8_t reserved_0; /* 01h */
1417 1453 uint8_t cmd_status; /* 02h */
1418 1454
1419 1455 uint8_t reserved_1; /* 03h */
1420 1456 uint32_t reserved_2; /* 04h */
1421 1457
1422 1458 uint32_t context; /* 08h */
1423 1459 uint8_t req_id; /* 0Ch */
1424 1460 uint8_t msgvector; /* 0Dh */
1425 1461 uint16_t pad_0; /* 0Eh */
1426 1462
1427 1463 uint16_t flags; /* 10h */
1428 1464 uint16_t reserved_3; /* 12h */
1429 1465 uint32_t reserved_4; /* 14h */
1430 1466
1431 1467 uint32_t abort_context; /* 18h */
1432 1468 uint32_t pad_1; /* 1Ch */
1433 1469
1434 1470 uint32_t abort_mfi_phys_addr_lo; /* 20h */
1435 1471 uint32_t abort_mfi_phys_addr_hi; /* 24h */
1436 1472
1437 1473 uint32_t reserved_5[6]; /* 28h */
1438 1474 };
1439 1475
1440 1476 struct mrsas_smp_frame {
1441 1477 uint8_t cmd; /* 00h */
1442 1478 uint8_t reserved_1; /* 01h */
1443 1479 uint8_t cmd_status; /* 02h */
1444 1480 uint8_t connection_status; /* 03h */
1445 1481
1446 1482 uint8_t reserved_2[3]; /* 04h */
1447 1483 uint8_t sge_count; /* 07h */
1448 1484
1449 1485 uint32_t context; /* 08h */
1450 1486 uint8_t req_id; /* 0Ch */
1451 1487 uint8_t msgvector; /* 0Dh */
1452 1488 uint16_t pad_0; /* 0Eh */
1453 1489
1454 1490 uint16_t flags; /* 10h */
1455 1491 uint16_t timeout; /* 12h */
1456 1492
1457 1493 uint32_t data_xfer_len; /* 14h */
1458 1494
1459 1495 uint64_t sas_addr; /* 20h */
1460 1496
1461 1497 union mrsas_sgl sgl[2]; /* 28h */
1462 1498 };
1463 1499
1464 1500 struct mrsas_stp_frame {
1465 1501 uint8_t cmd; /* 00h */
1466 1502 uint8_t reserved_1; /* 01h */
1467 1503 uint8_t cmd_status; /* 02h */
1468 1504 uint8_t connection_status; /* 03h */
1469 1505
1470 1506 uint8_t target_id; /* 04h */
1471 1507 uint8_t reserved_2[2]; /* 04h */
1472 1508 uint8_t sge_count; /* 07h */
1473 1509
1474 1510 uint32_t context; /* 08h */
1475 1511 uint8_t req_id; /* 0Ch */
1476 1512 uint8_t msgvector; /* 0Dh */
1477 1513 uint16_t pad_0; /* 0Eh */
1478 1514
1479 1515 uint16_t flags; /* 10h */
1480 1516 uint16_t timeout; /* 12h */
1481 1517
1482 1518 uint32_t data_xfer_len; /* 14h */
1483 1519
1484 1520 uint16_t fis[10]; /* 28h */
1485 1521 uint32_t stp_flags; /* 3C */
1486 1522 union mrsas_sgl sgl; /* 40 */
1487 1523 };
1488 1524
1489 1525 union mrsas_frame {
1490 1526 struct mrsas_header hdr;
1491 1527 struct mrsas_init_frame init;
1492 1528 struct mrsas_io_frame io;
1493 1529 struct mrsas_pthru_frame pthru;
1494 1530 struct mrsas_dcmd_frame dcmd;
1495 1531 struct mrsas_abort_frame abort;
1496 1532 struct mrsas_smp_frame smp;
1497 1533 struct mrsas_stp_frame stp;
1498 1534
1499 1535 uint8_t raw_bytes[64];
1500 1536 };
1501 1537
1502 1538 typedef struct mrsas_pd_address {
1503 1539 uint16_t device_id;
1504 1540 uint16_t encl_id;
1505 1541
1506 1542 union {
1507 1543 struct {
1508 1544 uint8_t encl_index;
1509 1545 uint8_t slot_number;
1510 1546 } pd_address;
1511 1547 struct {
1512 1548 uint8_t encl_position;
1513 1549 uint8_t encl_connector_index;
1514 1550 } encl_address;
1515 1551 }address;
1516 1552
1517 1553 uint8_t scsi_dev_type;
1518 1554
1519 1555 union {
1520 1556 uint8_t port_bitmap;
1521 1557 uint8_t port_numbers;
1522 1558 } connected;
1523 1559
1524 1560 uint64_t sas_addr[2];
1525 1561 } mrsas_pd_address_t;
1526 1562
1527 1563 union mrsas_evt_class_locale {
1528 1564 struct {
1529 1565 uint16_t locale;
1530 1566 uint8_t reserved;
1531 1567 int8_t class;
1532 1568 } members;
1533 1569
1534 1570 uint32_t word;
1535 1571 };
1536 1572
1537 1573 struct mrsas_evt_log_info {
1538 1574 uint32_t newest_seq_num;
1539 1575 uint32_t oldest_seq_num;
1540 1576 uint32_t clear_seq_num;
1541 1577 uint32_t shutdown_seq_num;
1542 1578 uint32_t boot_seq_num;
1543 1579 };
1544 1580
1545 1581 struct mrsas_progress {
1546 1582 uint16_t progress;
1547 1583 uint16_t elapsed_seconds;
1548 1584 };
1549 1585
1550 1586 struct mrsas_evtarg_ld {
1551 1587 uint16_t target_id;
1552 1588 uint8_t ld_index;
1553 1589 uint8_t reserved;
1554 1590 };
1555 1591
1556 1592 struct mrsas_evtarg_pd {
1557 1593 uint16_t device_id;
1558 1594 uint8_t encl_index;
1559 1595 uint8_t slot_number;
1560 1596 };
1561 1597
1562 1598 struct mrsas_evt_detail {
1563 1599 uint32_t seq_num;
1564 1600 uint32_t time_stamp;
1565 1601 uint32_t code;
1566 1602 union mrsas_evt_class_locale cl;
1567 1603 uint8_t arg_type;
1568 1604 uint8_t reserved1[15];
1569 1605
1570 1606 union {
1571 1607 struct {
1572 1608 struct mrsas_evtarg_pd pd;
1573 1609 uint8_t cdb_length;
1574 1610 uint8_t sense_length;
1575 1611 uint8_t reserved[2];
1576 1612 uint8_t cdb[16];
1577 1613 uint8_t sense[64];
1578 1614 } cdbSense;
1579 1615
1580 1616 struct mrsas_evtarg_ld ld;
1581 1617
1582 1618 struct {
1583 1619 struct mrsas_evtarg_ld ld;
1584 1620 uint64_t count;
1585 1621 } ld_count;
1586 1622
1587 1623 struct {
1588 1624 uint64_t lba;
1589 1625 struct mrsas_evtarg_ld ld;
1590 1626 } ld_lba;
1591 1627
1592 1628 struct {
1593 1629 struct mrsas_evtarg_ld ld;
1594 1630 uint32_t prevOwner;
1595 1631 uint32_t newOwner;
1596 1632 } ld_owner;
1597 1633
1598 1634 struct {
1599 1635 uint64_t ld_lba;
1600 1636 uint64_t pd_lba;
1601 1637 struct mrsas_evtarg_ld ld;
1602 1638 struct mrsas_evtarg_pd pd;
1603 1639 } ld_lba_pd_lba;
1604 1640
1605 1641 struct {
1606 1642 struct mrsas_evtarg_ld ld;
1607 1643 struct mrsas_progress prog;
1608 1644 } ld_prog;
1609 1645
1610 1646 struct {
1611 1647 struct mrsas_evtarg_ld ld;
1612 1648 uint32_t prev_state;
1613 1649 uint32_t new_state;
1614 1650 } ld_state;
1615 1651
1616 1652 struct {
1617 1653 uint64_t strip;
1618 1654 struct mrsas_evtarg_ld ld;
1619 1655 } ld_strip;
1620 1656
1621 1657 struct mrsas_evtarg_pd pd;
1622 1658
1623 1659 struct {
1624 1660 struct mrsas_evtarg_pd pd;
1625 1661 uint32_t err;
1626 1662 } pd_err;
1627 1663
1628 1664 struct {
1629 1665 uint64_t lba;
1630 1666 struct mrsas_evtarg_pd pd;
1631 1667 } pd_lba;
1632 1668
1633 1669 struct {
1634 1670 uint64_t lba;
1635 1671 struct mrsas_evtarg_pd pd;
1636 1672 struct mrsas_evtarg_ld ld;
1637 1673 } pd_lba_ld;
1638 1674
1639 1675 struct {
1640 1676 struct mrsas_evtarg_pd pd;
1641 1677 struct mrsas_progress prog;
1642 1678 } pd_prog;
1643 1679
1644 1680 struct {
1645 1681 struct mrsas_evtarg_pd pd;
1646 1682 uint32_t prevState;
1647 1683 uint32_t newState;
1648 1684 } pd_state;
1649 1685
1650 1686 struct {
1651 1687 uint16_t vendorId;
1652 1688 uint16_t deviceId;
1653 1689 uint16_t subVendorId;
1654 1690 uint16_t subDeviceId;
1655 1691 } pci;
1656 1692
1657 1693 uint32_t rate;
1658 1694 char str[96];
1659 1695
1660 1696 struct {
1661 1697 uint32_t rtc;
1662 1698 uint32_t elapsedSeconds;
1663 1699 } time;
1664 1700
1665 1701 struct {
1666 1702 uint32_t ecar;
1667 1703 uint32_t elog;
1668 1704 char str[64];
1669 1705 } ecc;
1670 1706
1671 1707 mrsas_pd_address_t pd_addr;
1672 1708
1673 1709 uint8_t b[96];
1674 1710 uint16_t s[48];
1675 1711 uint32_t w[24];
1676 1712 uint64_t d[12];
1677 1713 } args;
1678 1714
1679 1715 char description[128];
1680 1716
1681 1717 };
1682 1718
1683 1719 /* only 63 are usable by the application */
1684 1720 #define MAX_LOGICAL_DRIVES 64
1685 1721 /* only 255 physical devices may be used */
1686 1722 #define MAX_PHYSICAL_DEVICES 256
1687 1723 #define MAX_PD_PER_ENCLOSURE 64
1688 1724 /* maximum disks per array */
1689 1725 #define MAX_ROW_SIZE 32
1690 1726 /* maximum spans per logical drive */
1691 1727 #define MAX_SPAN_DEPTH 8
1692 1728 /* maximum number of arrays a hot spare may be dedicated to */
1693 1729 #define MAX_ARRAYS_DEDICATED 16
1694 1730 /* maximum number of arrays which may exist */
1695 1731 #define MAX_ARRAYS 128
1696 1732 /* maximum number of foreign configs that may ha managed at once */
1697 1733 #define MAX_FOREIGN_CONFIGS 8
1698 1734 /* maximum spares (global and dedicated combined) */
1699 1735 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES
1700 1736 /* maximum possible Target IDs (i.e. 0 to 63) */
1701 1737 #define MAX_TARGET_ID 63
1702 1738 /* maximum number of supported enclosures */
1703 1739 #define MAX_ENCLOSURES 32
1704 1740 /* maximum number of PHYs per controller */
1705 1741 #define MAX_PHYS_PER_CONTROLLER 16
1706 1742 /* maximum number of LDs per array (due to DDF limitations) */
1707 1743 #define MAX_LDS_PER_ARRAY 16
1708 1744
1709 1745 /*
1710 1746 * -----------------------------------------------------------------------------
1711 1747 * -----------------------------------------------------------------------------
1712 1748 *
1713 1749 * Logical Drive commands
1714 1750 *
1715 1751 * -----------------------------------------------------------------------------
1716 1752 * -----------------------------------------------------------------------------
1717 1753 */
1718 1754 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */
1719 1755
1720 1756 /*
1721 1757 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST
1722 1758 * dcmd.mbox - reserved
1723 1759 * dcmd.sge IN - ptr to returned MR_LD_LIST structure
1724 1760 * Desc: Return the logical drive list structure
1725 1761 * Status: No error
1726 1762 */
1727 1763
1728 1764 /*
1729 1765 * defines the logical drive reference structure
1730 1766 */
1731 1767 typedef union _MR_LD_REF { /* LD reference structure */
1732 1768 struct {
1733 1769 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */
1734 1770 uint8_t reserved; /* reserved for in line with MR_PD_REF */
1735 1771 uint16_t seqNum; /* Sequence Number */
1736 1772 } ld_ref;
1737 1773 uint32_t ref; /* shorthand reference to full 32-bits */
1738 1774 } MR_LD_REF; /* 4 bytes */
1739 1775
1740 1776 /*
1741 1777 * defines the logical drive list structure
1742 1778 */
1743 1779 typedef struct _MR_LD_LIST {
1744 1780 uint32_t ldCount; /* number of LDs */
1745 1781 uint32_t reserved; /* pad to 8-byte boundary */
1746 1782 struct {
1747 1783 MR_LD_REF ref; /* LD reference */
1748 1784 uint8_t state; /* current LD state (MR_LD_STATE) */
1749 1785 uint8_t reserved[3]; /* pad to 8-byte boundary */
1750 1786 uint64_t size; /* LD size */
1751 1787 } ldList[MAX_LOGICAL_DRIVES];
1752 1788 } MR_LD_LIST;
1753 1789
1754 1790 struct mrsas_drv_ver {
1755 1791 uint8_t signature[12];
1756 1792 uint8_t os_name[16];
1757 1793 uint8_t os_ver[12];
1758 1794 uint8_t drv_name[20];
1759 1795 uint8_t drv_ver[32];
1760 1796 uint8_t drv_rel_date[20];
1761 1797 };
1762 1798
1763 1799 #define PCI_TYPE0_ADDRESSES 6
1764 1800 #define PCI_TYPE1_ADDRESSES 2
1765 1801 #define PCI_TYPE2_ADDRESSES 5
1766 1802
1767 1803 struct mrsas_pci_common_header {
1768 1804 uint16_t vendorID; /* (ro) */
1769 1805 uint16_t deviceID; /* (ro) */
1770 1806 uint16_t command; /* Device control */
1771 1807 uint16_t status;
1772 1808 uint8_t revisionID; /* (ro) */
1773 1809 uint8_t progIf; /* (ro) */
1774 1810 uint8_t subClass; /* (ro) */
1775 1811 uint8_t baseClass; /* (ro) */
1776 1812 uint8_t cacheLineSize; /* (ro+) */
1777 1813 uint8_t latencyTimer; /* (ro+) */
1778 1814 uint8_t headerType; /* (ro) */
1779 1815 uint8_t bist; /* Built in self test */
1780 1816
1781 1817 union {
1782 1818 struct {
1783 1819 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES];
1784 1820 uint32_t cis;
1785 1821 uint16_t subVendorID;
1786 1822 uint16_t subSystemID;
1787 1823 uint32_t romBaseAddress;
1788 1824 uint8_t capabilitiesPtr;
1789 1825 uint8_t reserved1[3];
1790 1826 uint32_t reserved2;
1791 1827 uint8_t interruptLine;
1792 1828 uint8_t interruptPin; /* (ro) */
1793 1829 uint8_t minimumGrant; /* (ro) */
1794 1830 uint8_t maximumLatency; /* (ro) */
1795 1831 } type_0;
1796 1832
1797 1833 struct {
1798 1834 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES];
1799 1835 uint8_t primaryBus;
1800 1836 uint8_t secondaryBus;
1801 1837 uint8_t subordinateBus;
1802 1838 uint8_t secondaryLatency;
1803 1839 uint8_t ioBase;
1804 1840 uint8_t ioLimit;
1805 1841 uint16_t secondaryStatus;
1806 1842 uint16_t memoryBase;
1807 1843 uint16_t memoryLimit;
1808 1844 uint16_t prefetchBase;
1809 1845 uint16_t prefetchLimit;
1810 1846 uint32_t prefetchBaseUpper32;
1811 1847 uint32_t prefetchLimitUpper32;
1812 1848 uint16_t ioBaseUpper16;
1813 1849 uint16_t ioLimitUpper16;
1814 1850 uint8_t capabilitiesPtr;
1815 1851 uint8_t reserved1[3];
1816 1852 uint32_t romBaseAddress;
1817 1853 uint8_t interruptLine;
1818 1854 uint8_t interruptPin;
1819 1855 uint16_t bridgeControl;
1820 1856 } type_1;
1821 1857
1822 1858 struct {
1823 1859 uint32_t socketRegistersBaseAddress;
1824 1860 uint8_t capabilitiesPtr;
1825 1861 uint8_t reserved;
1826 1862 uint16_t secondaryStatus;
1827 1863 uint8_t primaryBus;
1828 1864 uint8_t secondaryBus;
1829 1865 uint8_t subordinateBus;
1830 1866 uint8_t secondaryLatency;
1831 1867 struct {
1832 1868 uint32_t base;
1833 1869 uint32_t limit;
1834 1870 } range[PCI_TYPE2_ADDRESSES-1];
1835 1871 uint8_t interruptLine;
1836 1872 uint8_t interruptPin;
1837 1873 uint16_t bridgeControl;
1838 1874 } type_2;
1839 1875 } header;
1840 1876 };
1841 1877
1842 1878 struct mrsas_pci_link_capability {
1843 1879 union {
1844 1880 struct {
1845 1881 uint32_t linkSpeed :4;
1846 1882 uint32_t linkWidth :6;
1847 1883 uint32_t aspmSupport :2;
1848 1884 uint32_t losExitLatency :3;
1849 1885 uint32_t l1ExitLatency :3;
1850 1886 uint32_t rsvdp :6;
1851 1887 uint32_t portNumber :8;
1852 1888 } bits;
1853 1889
1854 1890 uint32_t asUlong;
1855 1891 } cap;
1856 1892
1857 1893 };
1858 1894
1859 1895 struct mrsas_pci_link_status_capability {
1860 1896 union {
1861 1897 struct {
1862 1898 uint16_t linkSpeed :4;
1863 1899 uint16_t negotiatedLinkWidth :6;
1864 1900 uint16_t linkTrainingError :1;
1865 1901 uint16_t linkTraning :1;
1866 1902 uint16_t slotClockConfig :1;
1867 1903 uint16_t rsvdZ :3;
1868 1904 } bits;
1869 1905
1870 1906 uint16_t asUshort;
1871 1907 } stat_cap;
1872 1908
1873 1909 uint16_t reserved;
1874 1910
1875 1911 };
1876 1912
1877 1913 struct mrsas_pci_capabilities {
1878 1914 struct mrsas_pci_link_capability linkCapability;
1879 1915 struct mrsas_pci_link_status_capability linkStatusCapability;
1880 1916 };
1881 1917
1882 1918 struct mrsas_pci_information
1883 1919 {
1884 1920 uint32_t busNumber;
1885 1921 uint8_t deviceNumber;
1886 1922 uint8_t functionNumber;
1887 1923 uint8_t interruptVector;
1888 1924 uint8_t reserved;
1889 1925 struct mrsas_pci_common_header pciHeaderInfo;
1890 1926 struct mrsas_pci_capabilities capability;
1891 1927 uint8_t reserved2[32];
1892 1928 };
1893 1929
1894 1930 struct mrsas_ioctl {
1895 1931 uint16_t version;
1896 1932 uint16_t controller_id;
1897 1933 uint8_t signature[8];
1898 1934 uint32_t reserved_1;
1899 1935 uint32_t control_code;
1900 1936 uint32_t reserved_2[2];
1901 1937 uint8_t frame[64];
1902 1938 union mrsas_sgl_frame sgl_frame;
1903 1939 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH];
1904 1940 uint8_t data[1];
1905 1941 };
1906 1942
1907 1943 struct mrsas_aen {
1908 1944 uint16_t host_no;
1909 1945 uint16_t cmd_status;
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1910 1946 uint32_t seq_num;
1911 1947 uint32_t class_locale_word;
1912 1948 };
1913 1949
1914 1950 #pragma pack()
1915 1951
1916 1952 #ifndef DDI_VENDOR_LSI
1917 1953 #define DDI_VENDOR_LSI "LSI"
1918 1954 #endif /* DDI_VENDOR_LSI */
1919 1955
1920 -static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
1921 -static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t);
1922 -static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t);
1923 -int mrsas_quiesce(dev_info_t *);
1924 -static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t);
1925 -static int mrsas_open(dev_t *, int, int, cred_t *);
1926 -static int mrsas_close(dev_t, int, int, cred_t *);
1927 -static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
1956 +int mrsas_config_scsi_device(struct mrsas_instance *,
1957 + struct scsi_device *, dev_info_t **);
1928 1958
1929 -static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *,
1930 - scsi_hba_tran_t *, struct scsi_device *);
1931 -static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register
1932 - struct scsi_pkt *, struct buf *, int, int, int, int,
1933 - int (*)(), caddr_t);
1934 -static int mrsas_tran_start(struct scsi_address *,
1935 - register struct scsi_pkt *);
1936 -static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *);
1937 -static int mrsas_tran_reset(struct scsi_address *, int);
1938 -static int mrsas_tran_bus_reset(dev_info_t *, int);
1939 -static int mrsas_tran_getcap(struct scsi_address *, char *, int);
1940 -static int mrsas_tran_setcap(struct scsi_address *, char *, int, int);
1941 -static void mrsas_tran_destroy_pkt(struct scsi_address *,
1942 - struct scsi_pkt *);
1943 -static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *);
1944 -static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *);
1945 -static int mrsas_tran_quiesce(dev_info_t *dip);
1946 -static int mrsas_tran_unquiesce(dev_info_t *dip);
1947 -static uint_t mrsas_isr();
1948 -static uint_t mrsas_softintr();
1949 -
1950 -static struct mrsas_cmd *get_mfi_pkt(struct mrsas_instance *);
1951 -static void return_mfi_pkt(struct mrsas_instance *,
1952 - struct mrsas_cmd *);
1953 -
1954 -static void free_space_for_mfi(struct mrsas_instance *);
1955 -static int mrsas_tbolt_alloc_additional_dma_buffer
1956 -(struct mrsas_instance *);
1957 -int mrsas_tbolt_sync_map_info(struct mrsas_instance *instance);
1958 -static int alloc_additional_dma_buffer(struct mrsas_instance *);
1959 -static uint32_t read_fw_status_reg_ppc(struct mrsas_instance *);
1960 -static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *);
1961 -static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *,
1962 - struct mrsas_cmd *);
1963 -static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *,
1964 - struct mrsas_cmd *);
1965 -static void enable_intr_ppc(struct mrsas_instance *);
1966 -static void disable_intr_ppc(struct mrsas_instance *);
1967 -static int intr_ack_ppc(struct mrsas_instance *);
1968 -int mfi_state_transition_to_ready(struct mrsas_instance *);
1969 -static void flush_cache(struct mrsas_instance *instance);
1970 -void display_scsi_inquiry(caddr_t);
1971 -static int start_mfi_aen(struct mrsas_instance *instance);
1972 -static int handle_drv_ioctl(struct mrsas_instance *instance,
1973 - struct mrsas_ioctl *ioctl, int mode);
1974 -static int handle_mfi_ioctl(struct mrsas_instance *instance,
1975 - struct mrsas_ioctl *ioctl, int mode);
1976 -static int handle_mfi_aen(struct mrsas_instance *instance,
1977 - struct mrsas_aen *aen);
1978 -void fill_up_drv_ver(struct mrsas_drv_ver *dv);
1979 -static struct mrsas_cmd *build_cmd(struct mrsas_instance *instance,
1980 - struct scsi_address *ap, struct scsi_pkt *pkt,
1981 - uchar_t *cmd_done);
1982 -static struct mrsas_cmd *mrsas_tbolt_build_cmd(struct mrsas_instance *instance,
1983 - struct scsi_address *ap, struct scsi_pkt *pkt,
1984 - uchar_t *cmd_done);
1985 -static int wait_for_outstanding(struct mrsas_instance *instance);
1986 -static int register_mfi_aen(struct mrsas_instance *instance,
1987 - uint32_t seq_num, uint32_t class_locale_word);
1988 -static int issue_mfi_pthru(struct mrsas_instance *instance, struct
1989 - mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1990 -static int issue_mfi_dcmd(struct mrsas_instance *instance, struct
1991 - mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1992 -static int issue_mfi_smp(struct mrsas_instance *instance, struct
1993 - mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1994 -static int issue_mfi_stp(struct mrsas_instance *instance, struct
1995 - mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
1996 -static int abort_aen_cmd(struct mrsas_instance *instance,
1997 - struct mrsas_cmd *cmd_to_abort);
1998 -
1999 -
2000 -static void mrsas_rem_intrs(struct mrsas_instance *instance);
2001 -static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type);
2002 -
2003 -static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *,
2004 - scsi_hba_tran_t *, struct scsi_device *);
2005 -static int mrsas_tran_bus_config(dev_info_t *, uint_t,
2006 - ddi_bus_config_op_t, void *, dev_info_t **);
2007 -static int mrsas_parse_devname(char *, int *, int *);
2008 -static int mrsas_config_all_devices(struct mrsas_instance *);
2009 -int mrsas_config_scsi_device(struct mrsas_instance *,
2010 - struct scsi_device *, dev_info_t **);
2011 -static int mrsas_config_ld(struct mrsas_instance *, uint16_t,
2012 - uint8_t, dev_info_t **);
2013 -
2014 1959 #ifdef PDSUPPORT
2015 -int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t,
2016 - uint8_t, dev_info_t **);
2017 -static void mrsas_tbolt_get_pd_info(struct mrsas_instance *,
2018 - struct mrsas_tbolt_pd_info *, int);
1960 +int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t,
1961 + uint8_t, dev_info_t **);
2019 1962 #endif
2020 1963
2021 -dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t,
2022 - uint8_t);
2023 -static int mrsas_name_node(dev_info_t *, char *, int);
2024 -static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *);
2025 -int mrsas_service_evt(struct mrsas_instance *, int, int, int,
2026 - uint64_t);
2027 -static void free_additional_dma_buffer(struct mrsas_instance *);
2028 -
2029 -struct mrsas_cmd *get_raid_msg_pkt(struct mrsas_instance *);
1964 +dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, uint8_t);
1965 +int mrsas_service_evt(struct mrsas_instance *, int, int, int, uint64_t);
2030 1966 void return_raid_msg_pkt(struct mrsas_instance *, struct mrsas_cmd *);
2031 1967 struct mrsas_cmd *get_raid_msg_mfi_pkt(struct mrsas_instance *);
2032 1968 void return_raid_msg_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
2033 1969
2034 1970 int alloc_space_for_mpi2(struct mrsas_instance *);
2035 -int alloc_additional_dma_buffer(struct mrsas_instance *);
1971 +void fill_up_drv_ver(struct mrsas_drv_ver *dv);
2036 1972
2037 1973 int mrsas_issue_init_mpi2(struct mrsas_instance *);
2038 1974 struct scsi_pkt *mrsas_tbolt_tran_init_pkt(struct scsi_address *, register
2039 1975 struct scsi_pkt *, struct buf *, int, int, int, int,
2040 1976 int (*)(), caddr_t);
2041 1977 int mrsas_tbolt_tran_start(struct scsi_address *,
2042 1978 register struct scsi_pkt *);
2043 1979 uint32_t tbolt_read_fw_status_reg(struct mrsas_instance *);
2044 1980 void tbolt_issue_cmd(struct mrsas_cmd *, struct mrsas_instance *);
2045 1981 int tbolt_issue_cmd_in_poll_mode(struct mrsas_instance *,
2046 1982 struct mrsas_cmd *);
2047 1983 int tbolt_issue_cmd_in_sync_mode(struct mrsas_instance *,
2048 1984 struct mrsas_cmd *);
2049 1985 void tbolt_enable_intr(struct mrsas_instance *);
2050 1986 void tbolt_disable_intr(struct mrsas_instance *);
2051 1987 int tbolt_intr_ack(struct mrsas_instance *);
2052 1988 uint_t mr_sas_tbolt_process_outstanding_cmd(struct mrsas_instance *);
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2053 1989 uint_t tbolt_softintr();
2054 1990 int mrsas_tbolt_dma(struct mrsas_instance *, uint32_t, int, int (*)());
2055 1991 int mrsas_check_dma_handle(ddi_dma_handle_t handle);
2056 1992 int mrsas_check_acc_handle(ddi_acc_handle_t handle);
2057 1993 int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
2058 1994 struct buf *, int, int (*)());
2059 1995 int mrsas_dma_move(struct mrsas_instance *,
2060 1996 struct scsi_pkt *, struct buf *);
2061 1997 int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
2062 1998 uchar_t);
2063 -int mrsas_tbolt_ioc_init(struct mrsas_instance *, dma_obj_t *,
2064 - ddi_acc_handle_t);
2065 -int mrsas_tbolt_prepare_pkt(struct scsa_cmd *);
2066 1999 void mr_sas_tbolt_build_mfi_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2067 2000 int mrsas_dma_alloc_dmd(struct mrsas_instance *, dma_obj_t *);
2068 -int mr_sas_tbolt_build_sgl(struct mrsas_instance *,
2069 - struct scsa_cmd *,
2070 - struct mrsas_cmd *,
2071 - Mpi2RaidSCSIIORequest_t *,
2072 - uint32_t *);
2073 2001 void tbolt_complete_cmd_in_sync_mode(struct mrsas_instance *,
2074 2002 struct mrsas_cmd *);
2075 2003 int alloc_req_rep_desc(struct mrsas_instance *);
2076 -static void complete_cmd_in_sync_mode(struct mrsas_instance *,
2077 - struct mrsas_cmd *);
2078 -static void io_timeout_checker(void *instance);
2079 -static int mrsas_kill_adapter(struct mrsas_instance *);
2080 2004 int mrsas_mode_sense_build(struct scsi_pkt *);
2081 2005 void push_pending_mfi_pkt(struct mrsas_instance *,
2082 2006 struct mrsas_cmd *);
2083 -static int mrsas_issue_init_mfi(struct mrsas_instance *);
2084 -int mrsas_issue_pending_cmds(struct mrsas_instance *);
2007 +int mrsas_issue_pending_cmds(struct mrsas_instance *);
2085 2008 int mrsas_print_pending_cmds(struct mrsas_instance *);
2086 2009 int mrsas_complete_pending_cmds(struct mrsas_instance *);
2087 -static int mrsas_reset_ppc(struct mrsas_instance *);
2088 -static uint32_t mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *);
2089 2010
2090 -MRSAS_REQUEST_DESCRIPTOR_UNION *\
2091 - mr_sas_get_request_descriptor(struct mrsas_instance *,
2092 - uint16_t, struct mrsas_cmd *);
2093 -
2094 2011 int create_mfi_frame_pool(struct mrsas_instance *);
2095 2012 void destroy_mfi_frame_pool(struct mrsas_instance *);
2096 2013 int create_mfi_mpi_frame_pool(struct mrsas_instance *);
2097 2014 void destroy_mfi_mpi_frame_pool(struct mrsas_instance *);
2098 2015 int create_mpi2_frame_pool(struct mrsas_instance *);
2099 2016 void destroy_mpi2_frame_pool(struct mrsas_instance *);
2100 2017 int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
2101 2018 void mrsas_tbolt_free_additional_dma_buffer(struct mrsas_instance *);
2102 2019 void free_req_desc_pool(struct mrsas_instance *);
2103 2020 void free_space_for_mpi2(struct mrsas_instance *);
2104 2021 void mrsas_dump_reply_desc(struct mrsas_instance *);
2105 2022 void tbolt_complete_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2106 -void io_timeout_checker(void *);
2107 2023 void display_scsi_inquiry(caddr_t);
2108 2024 void service_mfi_aen(struct mrsas_instance *, struct mrsas_cmd *);
2109 2025 int mrsas_mode_sense_build(struct scsi_pkt *);
2110 2026 int mrsas_tbolt_get_ld_map_info(struct mrsas_instance *);
2111 -void mrsas_tbolt_set_pd_lba(U8 cdb[], uint8_t *cdb_len, U64 start_blk, U32 num_blocks, U8 DifCapable);
2112 -U8 mrsas_tbolt_check_map_info(struct mrsas_instance *);
2113 2027 struct mrsas_cmd *mrsas_tbolt_build_poll_cmd(struct mrsas_instance *,
2114 2028 struct scsi_address *, struct scsi_pkt *, uchar_t *);
2115 2029 int mrsas_tbolt_reset_ppc(struct mrsas_instance *instance);
2116 -int mrsas_tbolt_kill_adapter(struct mrsas_instance *instance);
2030 +void mrsas_tbolt_kill_adapter(struct mrsas_instance *instance);
2117 2031 int abort_syncmap_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2118 -void mrsas_tbolt_prepare_cdb(struct mrsas_instance *instance, U8 cdb[],struct IO_REQUEST_INFO *,
2119 - Mpi2RaidSCSIIORequest_t *, U32);
2032 +void mrsas_tbolt_prepare_cdb(struct mrsas_instance *instance, U8 cdb[],
2033 + struct IO_REQUEST_INFO *, Mpi2RaidSCSIIORequest_t *, U32);
2120 2034
2121 2035
2122 -static int
2123 -mrsas_undo_resources (dev_info_t *dip, struct mrsas_instance *instance);
2036 +int mrsas_init_adapter_ppc(struct mrsas_instance *instance);
2037 +int mrsas_init_adapter_tbolt(struct mrsas_instance *instance);
2038 +int mrsas_init_adapter(struct mrsas_instance *instance);
2124 2039
2125 -int mrsas_init_adapter_ppc (struct mrsas_instance *instance);
2126 -int mrsas_init_adapter_tbolt (struct mrsas_instance *instance);
2127 -int mrsas_init_adapter (struct mrsas_instance *instance);
2128 -
2129 2040 int mrsas_alloc_cmd_pool(struct mrsas_instance *instance);
2130 2041 void mrsas_free_cmd_pool(struct mrsas_instance *instance);
2131 2042
2132 -void mrsas_print_cmd_details(struct mrsas_instance *, struct mrsas_cmd *, int );
2043 +void mrsas_print_cmd_details(struct mrsas_instance *, struct mrsas_cmd *, int);
2044 +struct mrsas_cmd *get_raid_msg_pkt(struct mrsas_instance *);
2133 2045
2046 +int mfi_state_transition_to_ready(struct mrsas_instance *);
2047 +
2048 +
2049 +/* FMA functions. */
2050 +int mrsas_common_check(struct mrsas_instance *, struct mrsas_cmd *);
2051 +void mrsas_fm_ereport(struct mrsas_instance *, char *);
2052 +
2053 +
2134 2054 #ifdef __cplusplus
2135 2055 }
2136 2056 #endif
2137 2057
2138 2058 #endif /* _MR_SAS_H_ */
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