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--- old/usr/src/uts/common/io/mr_sas/mr_sas.h
+++ new/usr/src/uts/common/io/mr_sas/mr_sas.h
1 1 /*
2 2 * mr_sas.h: header for mr_sas
3 3 *
4 4 * Solaris MegaRAID driver for SAS2.0 controllers
5 5 * Copyright (c) 2008-2012, LSI Logic Corporation.
6 6 * All rights reserved.
7 7 *
8 8 * Version:
9 9 * Author:
10 10 * Swaminathan K S
11 11 * Arun Chandrashekhar
12 12 * Manju R
13 13 * Rasheed
14 14 * Shakeel Bukhari
15 15 *
16 16 * Redistribution and use in source and binary forms, with or without
17 17 * modification, are permitted provided that the following conditions are met:
18 18 *
19 19 * 1. Redistributions of source code must retain the above copyright notice,
20 20 * this list of conditions and the following disclaimer.
21 21 *
22 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 23 * this list of conditions and the following disclaimer in the documentation
24 24 * and/or other materials provided with the distribution.
25 25 *
26 26 * 3. Neither the name of the author nor the names of its contributors may be
27 27 * used to endorse or promote products derived from this software without
28 28 * specific prior written permission.
29 29 *
30 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
34 34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
36 36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
37 37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
38 38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
40 40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41 41 * DAMAGE.
42 42 */
43 43
44 44 /*
45 45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
46 46 */
47 47
48 48 #ifndef _MR_SAS_H_
49 49 #define _MR_SAS_H_
50 50
51 51 #ifdef __cplusplus
52 52 extern "C" {
53 53 #endif
54 54
55 55 #include <sys/scsi/scsi.h>
56 56 #include "mr_sas_list.h"
57 57 #include "ld_pd_map.h"
58 58
59 59 /*
60 60 * MegaRAID SAS2.0 Driver meta data
61 61 */
62 62 #define MRSAS_VERSION "6.503.00.00ILLUMOS"
63 63 #define MRSAS_RELDATE "July 30, 2012"
64 64
65 65 #define MRSAS_TRUE 1
66 66 #define MRSAS_FALSE 0
67 67
68 68 #define ADAPTER_RESET_NOT_REQUIRED 0
69 69 #define ADAPTER_RESET_REQUIRED 1
70 70
71 71 #define PDSUPPORT 1
72 72
73 73 /*
74 74 * MegaRAID SAS2.0 device id conversion definitions.
75 75 */
76 76 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT)
77 77 #define MRSAS_GET_BOUNDARY_ALIGNED_LEN(len, new_len, boundary_len) { \
78 78 int rem; \
79 79 rem = (len / boundary_len); \
80 80 if ((rem * boundary_len) != len) { \
81 81 new_len = len + ((rem + 1) * boundary_len - len); \
82 82 } else { \
83 83 new_len = len; \
84 84 } \
85 85 }
86 86
87 87
88 88 /*
89 89 * MegaRAID SAS2.0 supported controllers
90 90 */
91 91 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078
92 92 #define PCI_DEVICE_ID_LSI_2108V 0x0079
93 93 #define PCI_DEVICE_ID_LSI_TBOLT 0x005b
94 94 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
95 95
96 96 /*
97 97 * Register Index for 2108 Controllers.
98 98 */
99 99 #define REGISTER_SET_IO_2108 (2)
100 100
101 101 #define MRSAS_MAX_SGE_CNT 0x50
102 102 #define MRSAS_APP_RESERVED_CMDS 32
103 103
104 104 #define MRSAS_IOCTL_DRIVER 0x12341234
105 105 #define MRSAS_IOCTL_FIRMWARE 0x12345678
106 106 #define MRSAS_IOCTL_AEN 0x87654321
107 107
108 108 #define MRSAS_1_SECOND 1000000
109 109
110 110 #ifdef PDSUPPORT
111 111
112 112 #define UNCONFIGURED_GOOD 0x0
113 113 #define PD_SYSTEM 0x40
114 114 #define MR_EVT_PD_STATE_CHANGE 0x0072
115 115 #define MR_EVT_PD_REMOVED_EXT 0x00f8
116 116 #define MR_EVT_PD_INSERTED_EXT 0x00f7
117 117 #define MR_DCMD_PD_GET_INFO 0x02020000
118 118 #define MRSAS_TBOLT_PD_LUN 1
119 119 #define MRSAS_TBOLT_PD_TGT_MAX 255
120 120 #define MRSAS_TBOLT_GET_PD_MAX(s) ((s)->mr_tbolt_pd_max)
121 121
122 122 #endif
123 123
124 124 /* Raid Context Flags */
125 125 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
126 126 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
127 127 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
128 128 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
129 129 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1
130 130 } MR_RAID_FLAGS_IO_SUB_TYPE;
131 131
132 132 /* Dynamic Enumeration Flags */
133 133 #define MRSAS_LD_LUN 0
134 134 #define WWN_STRLEN 17
135 135 #define LD_SYNC_BIT 1
136 136 #define LD_SYNC_SHIFT 14
137 137 /* ThunderBolt (TB) specific */
138 138 #define MRSAS_THUNDERBOLT_MSG_SIZE 256
139 139 #define MRSAS_THUNDERBOLT_MAX_COMMANDS 1024
140 140 #define MRSAS_THUNDERBOLT_MAX_REPLY_COUNT 1024
141 141 #define MRSAS_THUNDERBOLT_REPLY_SIZE 8
142 142 #define MRSAS_THUNDERBOLT_MAX_CHAIN_COUNT 1
143 143
144 144 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
145 145 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1
146 146
147 147 #define MR_EVT_LD_FAST_PATH_IO_STATUS_CHANGED (0xFFFF)
148 148
149 149 #define MR_INTERNAL_MFI_FRAMES_SMID 1
150 150 #define MR_CTRL_EVENT_WAIT_SMID 2
151 151 #define MR_INTERNAL_DRIVER_RESET_SMID 3
152 152
153 153
154 154 /*
155 155 * =====================================
156 156 * MegaRAID SAS2.0 MFI firmware definitions
157 157 * =====================================
158 158 */
159 159 /*
160 160 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for
161 161 * protocol between the software and firmware. Commands are issued using
162 162 * "message frames"
163 163 */
164 164
165 165 /*
166 166 * FW posts its state in upper 4 bits of outbound_msg_0 register
167 167 */
168 168 #define MFI_STATE_MASK 0xF0000000
169 169 #define MFI_STATE_UNDEFINED 0x00000000
170 170 #define MFI_STATE_BB_INIT 0x10000000
171 171 #define MFI_STATE_FW_INIT 0x40000000
172 172 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
173 173 #define MFI_STATE_FW_INIT_2 0x70000000
174 174 #define MFI_STATE_DEVICE_SCAN 0x80000000
175 175 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
176 176 #define MFI_STATE_FLUSH_CACHE 0xA0000000
177 177 #define MFI_STATE_READY 0xB0000000
178 178 #define MFI_STATE_OPERATIONAL 0xC0000000
179 179 #define MFI_STATE_FAULT 0xF0000000
180 180
181 181 #define MRMFI_FRAME_SIZE 64
182 182
183 183 /*
184 184 * During FW init, clear pending cmds & reset state using inbound_msg_0
185 185 *
186 186 * ABORT : Abort all pending cmds
187 187 * READY : Move from OPERATIONAL to READY state; discard queue info
188 188 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
189 189 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
190 190 */
191 191 #define MFI_INIT_ABORT 0x00000001
192 192 #define MFI_INIT_READY 0x00000002
193 193 #define MFI_INIT_MFIMODE 0x00000004
194 194 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
195 195 #define MFI_INIT_HOTPLUG 0x00000010
196 196 #define MFI_STOP_ADP 0x00000020
197 197 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
198 198
199 199 /*
200 200 * MFI frame flags
201 201 */
202 202 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
203 203 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
204 204 #define MFI_FRAME_SGL32 0x0000
205 205 #define MFI_FRAME_SGL64 0x0002
206 206 #define MFI_FRAME_SENSE32 0x0000
207 207 #define MFI_FRAME_SENSE64 0x0004
208 208 #define MFI_FRAME_DIR_NONE 0x0000
209 209 #define MFI_FRAME_DIR_WRITE 0x0008
210 210 #define MFI_FRAME_DIR_READ 0x0010
211 211 #define MFI_FRAME_DIR_BOTH 0x0018
212 212 #define MFI_FRAME_IEEE 0x0020
213 213
214 214 /*
215 215 * Definition for cmd_status
216 216 */
217 217 #define MFI_CMD_STATUS_POLL_MODE 0xFF
218 218 #define MFI_CMD_STATUS_SYNC_MODE 0xFF
219 219
220 220 /*
221 221 * MFI command opcodes
222 222 */
223 223 #define MFI_CMD_OP_INIT 0x00
224 224 #define MFI_CMD_OP_LD_READ 0x01
225 225 #define MFI_CMD_OP_LD_WRITE 0x02
226 226 #define MFI_CMD_OP_LD_SCSI 0x03
227 227 #define MFI_CMD_OP_PD_SCSI 0x04
228 228 #define MFI_CMD_OP_DCMD 0x05
229 229 #define MFI_CMD_OP_ABORT 0x06
230 230 #define MFI_CMD_OP_SMP 0x07
231 231 #define MFI_CMD_OP_STP 0x08
232 232
233 233 #define MR_DCMD_CTRL_GET_INFO 0x01010000
234 234
235 235 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
236 236 #define MR_FLUSH_CTRL_CACHE 0x01
237 237 #define MR_FLUSH_DISK_CACHE 0x02
238 238
239 239 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
240 240 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01
241 241
242 242 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
243 243 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
244 244 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
245 245 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
246 246
247 247 /*
248 248 * Solaris Specific MAX values
249 249 */
250 250 #define MAX_SGL 24
251 251
252 252 /*
253 253 * MFI command completion codes
254 254 */
255 255 enum MFI_STAT {
256 256 MFI_STAT_OK = 0x00,
257 257 MFI_STAT_INVALID_CMD = 0x01,
258 258 MFI_STAT_INVALID_DCMD = 0x02,
259 259 MFI_STAT_INVALID_PARAMETER = 0x03,
260 260 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
261 261 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
262 262 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
263 263 MFI_STAT_APP_IN_USE = 0x07,
264 264 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
265 265 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
266 266 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
267 267 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
268 268 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
269 269 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
270 270 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
271 271 MFI_STAT_FLASH_BUSY = 0x0f,
272 272 MFI_STAT_FLASH_ERROR = 0x10,
273 273 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
274 274 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
275 275 MFI_STAT_FLASH_NOT_OPEN = 0x13,
276 276 MFI_STAT_FLASH_NOT_STARTED = 0x14,
277 277 MFI_STAT_FLUSH_FAILED = 0x15,
278 278 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
279 279 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
280 280 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
281 281 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
282 282 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
283 283 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
284 284 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
285 285 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
286 286 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
287 287 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
288 288 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
289 289 MFI_STAT_MFC_HW_ERROR = 0x21,
290 290 MFI_STAT_NO_HW_PRESENT = 0x22,
291 291 MFI_STAT_NOT_FOUND = 0x23,
292 292 MFI_STAT_NOT_IN_ENCL = 0x24,
293 293 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
294 294 MFI_STAT_PD_TYPE_WRONG = 0x26,
295 295 MFI_STAT_PR_DISABLED = 0x27,
296 296 MFI_STAT_ROW_INDEX_INVALID = 0x28,
297 297 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
298 298 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
299 299 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
300 300 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
301 301 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
302 302 MFI_STAT_SCSI_IO_FAILED = 0x2e,
303 303 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
304 304 MFI_STAT_SHUTDOWN_FAILED = 0x30,
305 305 MFI_STAT_TIME_NOT_SET = 0x31,
306 306 MFI_STAT_WRONG_STATE = 0x32,
307 307 MFI_STAT_LD_OFFLINE = 0x33,
308 308 MFI_STAT_INVALID_STATUS = 0xFF
309 309 };
310 310
311 311 enum MR_EVT_CLASS {
312 312 MR_EVT_CLASS_DEBUG = -2,
313 313 MR_EVT_CLASS_PROGRESS = -1,
314 314 MR_EVT_CLASS_INFO = 0,
315 315 MR_EVT_CLASS_WARNING = 1,
316 316 MR_EVT_CLASS_CRITICAL = 2,
317 317 MR_EVT_CLASS_FATAL = 3,
318 318 MR_EVT_CLASS_DEAD = 4
319 319 };
320 320
321 321 enum MR_EVT_LOCALE {
322 322 MR_EVT_LOCALE_LD = 0x0001,
323 323 MR_EVT_LOCALE_PD = 0x0002,
324 324 MR_EVT_LOCALE_ENCL = 0x0004,
325 325 MR_EVT_LOCALE_BBU = 0x0008,
326 326 MR_EVT_LOCALE_SAS = 0x0010,
327 327 MR_EVT_LOCALE_CTRL = 0x0020,
328 328 MR_EVT_LOCALE_CONFIG = 0x0040,
329 329 MR_EVT_LOCALE_CLUSTER = 0x0080,
330 330 MR_EVT_LOCALE_ALL = 0xffff
331 331 };
332 332
333 333 enum MR_EVT_ARGS {
334 334 MR_EVT_ARGS_NONE,
335 335 MR_EVT_ARGS_CDB_SENSE,
336 336 MR_EVT_ARGS_LD,
337 337 MR_EVT_ARGS_LD_COUNT,
338 338 MR_EVT_ARGS_LD_LBA,
339 339 MR_EVT_ARGS_LD_OWNER,
340 340 MR_EVT_ARGS_LD_LBA_PD_LBA,
341 341 MR_EVT_ARGS_LD_PROG,
342 342 MR_EVT_ARGS_LD_STATE,
343 343 MR_EVT_ARGS_LD_STRIP,
344 344 MR_EVT_ARGS_PD,
345 345 MR_EVT_ARGS_PD_ERR,
346 346 MR_EVT_ARGS_PD_LBA,
347 347 MR_EVT_ARGS_PD_LBA_LD,
348 348 MR_EVT_ARGS_PD_PROG,
349 349 MR_EVT_ARGS_PD_STATE,
350 350 MR_EVT_ARGS_PCI,
351 351 MR_EVT_ARGS_RATE,
352 352 MR_EVT_ARGS_STR,
353 353 MR_EVT_ARGS_TIME,
354 354 MR_EVT_ARGS_ECC
355 355 };
356 356
357 357 #define MR_EVT_CFG_CLEARED 0x0004
358 358 #define MR_EVT_LD_CREATED 0x008a
359 359 #define MR_EVT_LD_DELETED 0x008b
360 360 #define MR_EVT_CFG_FP_CHANGE 0x017B
361 361
362 362 enum LD_STATE {
363 363 LD_OFFLINE = 0,
364 364 LD_PARTIALLY_DEGRADED = 1,
365 365 LD_DEGRADED = 2,
366 366 LD_OPTIMAL = 3,
367 367 LD_INVALID = 0xFF
368 368 };
369 369
370 370 enum MRSAS_EVT {
371 371 MRSAS_EVT_CONFIG_TGT = 0,
372 372 MRSAS_EVT_UNCONFIG_TGT = 1,
373 373 MRSAS_EVT_UNCONFIG_SMP = 2
374 374 };
375 375
376 376 #define DMA_OBJ_ALLOCATED 1
377 377 #define DMA_OBJ_REALLOCATED 2
378 378 #define DMA_OBJ_FREED 3
379 379
380 380 /*
381 381 * dma_obj_t - Our DMA object
382 382 * @param buffer : kernel virtual address
383 383 * @param size : size of the data to be allocated
384 384 * @param acc_handle : access handle
385 385 * @param dma_handle : dma handle
386 386 * @param dma_cookie : scatter-gather list
387 387 * @param dma_attr : dma attributes for this buffer
388 388 *
389 389 * Our DMA object. The caller must initialize the size and dma attributes
390 390 * (dma_attr) fields before allocating the resources.
391 391 */
392 392 typedef struct {
393 393 caddr_t buffer;
394 394 uint32_t size;
395 395 ddi_acc_handle_t acc_handle;
396 396 ddi_dma_handle_t dma_handle;
397 397 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT];
398 398 ddi_dma_attr_t dma_attr;
399 399 uint8_t status;
400 400 uint8_t reserved[3];
401 401 } dma_obj_t;
402 402
403 403 struct mrsas_eventinfo {
404 404 struct mrsas_instance *instance;
405 405 int tgt;
406 406 int lun;
407 407 int event;
408 408 uint64_t wwn;
409 409 };
410 410
411 411 struct mrsas_ld {
412 412 dev_info_t *dip;
413 413 uint8_t lun_type;
414 414 uint8_t flag;
415 415 uint8_t reserved[2];
416 416 };
417 417
418 418
419 419 #ifdef PDSUPPORT
420 420 struct mrsas_tbolt_pd {
421 421 dev_info_t *dip;
422 422 uint8_t lun_type;
423 423 uint8_t dev_id;
424 424 uint8_t flag;
425 425 uint8_t reserved;
426 426 };
427 427 struct mrsas_tbolt_pd_info {
428 428 uint16_t deviceId;
429 429 uint16_t seqNum;
430 430 uint8_t inquiryData[96];
431 431 uint8_t vpdPage83[64];
432 432 uint8_t notSupported;
433 433 uint8_t scsiDevType;
434 434 uint8_t a;
435 435 uint8_t device_speed;
436 436 uint32_t mediaerrcnt;
437 437 uint32_t other;
438 438 uint32_t pred;
439 439 uint32_t lastpred;
440 440 uint16_t fwState;
441 441 uint8_t disabled;
442 442 uint8_t linkspwwd;
443 443 uint32_t ddfType;
444 444 struct {
445 445 uint8_t count;
446 446 uint8_t isPathBroken;
447 447 uint8_t connectorIndex[2];
448 448 uint8_t reserved[4];
449 449 uint64_t sasAddr[2];
450 450 uint8_t reserved2[16];
451 451 } pathInfo;
452 452 };
453 453 #endif
454 454
455 455 typedef struct mrsas_instance {
456 456 uint32_t *producer;
457 457 uint32_t *consumer;
458 458
459 459 uint32_t *reply_queue;
460 460 dma_obj_t mfi_internal_dma_obj;
461 461 uint16_t adapterresetinprogress;
462 462 uint16_t deadadapter;
463 463 /* ThunderBolt (TB) specific */
464 464 dma_obj_t mpi2_frame_pool_dma_obj;
465 465 dma_obj_t request_desc_dma_obj;
466 466 dma_obj_t reply_desc_dma_obj;
467 467 dma_obj_t ld_map_obj[2];
468 468
469 469 uint8_t init_id;
470 470 uint8_t flag_ieee;
471 471 uint8_t disable_online_ctrl_reset;
472 472 uint8_t fw_fault_count_after_ocr;
473 473
474 474 uint16_t max_num_sge;
475 475 uint16_t max_fw_cmds;
476 476 uint32_t max_sectors_per_req;
477 477
478 478 struct mrsas_cmd **cmd_list;
479 479
480 480 mlist_t cmd_pool_list;
481 481 kmutex_t cmd_pool_mtx;
482 482 kmutex_t sync_map_mtx;
483 483
484 484 mlist_t app_cmd_pool_list;
485 485 kmutex_t app_cmd_pool_mtx;
486 486 mlist_t cmd_app_pool_list;
487 487 kmutex_t cmd_app_pool_mtx;
488 488
489 489
490 490 mlist_t cmd_pend_list;
491 491 kmutex_t cmd_pend_mtx;
492 492
493 493 dma_obj_t mfi_evt_detail_obj;
494 494 struct mrsas_cmd *aen_cmd;
495 495
496 496 uint32_t aen_seq_num;
497 497 uint32_t aen_class_locale_word;
498 498
499 499 scsi_hba_tran_t *tran;
500 500
501 501 kcondvar_t int_cmd_cv;
502 502 kmutex_t int_cmd_mtx;
503 503
504 504 kcondvar_t aen_cmd_cv;
505 505 kmutex_t aen_cmd_mtx;
506 506
507 507 kcondvar_t abort_cmd_cv;
508 508 kmutex_t abort_cmd_mtx;
509 509
510 510 kmutex_t reg_write_mtx;
511 511 kmutex_t chip_mtx;
512 512
513 513 dev_info_t *dip;
514 514 ddi_acc_handle_t pci_handle;
515 515
516 516 timeout_id_t timeout_id;
517 517 uint32_t unique_id;
518 518 uint16_t fw_outstanding;
519 519 caddr_t regmap;
520 520 ddi_acc_handle_t regmap_handle;
521 521 uint8_t isr_level;
522 522 ddi_iblock_cookie_t iblock_cookie;
523 523 ddi_iblock_cookie_t soft_iblock_cookie;
524 524 ddi_softintr_t soft_intr_id;
525 525 uint8_t softint_running;
526 526 uint8_t tbolt_softint_running;
527 527 kmutex_t completed_pool_mtx;
528 528 mlist_t completed_pool_list;
529 529
530 530 caddr_t internal_buf;
531 531 uint32_t internal_buf_dmac_add;
532 532 uint32_t internal_buf_size;
533 533
534 534 uint16_t vendor_id;
535 535 uint16_t device_id;
536 536 uint16_t subsysvid;
537 537 uint16_t subsysid;
538 538 int instance;
539 539 int baseaddress;
540 540 char iocnode[16];
541 541
542 542 int fm_capabilities;
543 543 /*
544 544 * Driver resources unroll flags. The flag is set for resources that
545 545 * are needed to be free'd at detach() time.
546 546 */
547 547 struct _unroll {
548 548 uint8_t softs; /* The software state was allocated. */
549 549 uint8_t regs; /* Controller registers mapped. */
550 550 uint8_t intr; /* Interrupt handler added. */
551 551 uint8_t reqs; /* Request structs allocated. */
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552 552 uint8_t mutexs; /* Mutex's allocated. */
553 553 uint8_t taskq; /* Task q's created. */
554 554 uint8_t tran; /* Tran struct allocated */
555 555 uint8_t tranSetup; /* Tran attached to the ddi. */
556 556 uint8_t devctl; /* Device nodes for cfgadm created. */
557 557 uint8_t scsictl; /* Device nodes for cfgadm created. */
558 558 uint8_t ioctl; /* Device nodes for ioctl's created. */
559 559 uint8_t timer; /* Timer started. */
560 560 uint8_t aenPend; /* AEN cmd pending f/w. */
561 561 uint8_t mapUpdate_pend; /* LD MAP update cmd pending f/w. */
562 - uint8_t soft_isr;
563 - uint8_t ldlist_buff;
564 - uint8_t pdlist_buff;
565 - uint8_t syncCmd;
566 - uint8_t verBuff;
567 - uint8_t alloc_space_mfi;
568 - uint8_t alloc_space_mpi2;
562 + uint8_t soft_isr; /* Soft interrupt handler allocated. */
563 + uint8_t ldlist_buff; /* Logical disk list allocated. */
564 + uint8_t pdlist_buff; /* Physical disk list allocated. */
565 + uint8_t syncCmd; /* Sync map command allocated. */
566 + uint8_t verBuff; /* 2108 MFI buffer allocated. */
567 + uint8_t alloc_space_mfi; /* Allocated space for 2108 MFI. */
568 + uint8_t alloc_space_mpi2; /* Allocated space for 2208 MPI2. */
569 569 } unroll;
570 570
571 571
572 572 /* function template pointer */
573 573 struct mrsas_function_template *func_ptr;
574 574
575 575
576 576 /* MSI interrupts specific */
577 577 ddi_intr_handle_t *intr_htable; /* Interrupt handle array */
578 578 size_t intr_htable_size; /* Int. handle array size */
579 579 int intr_type;
580 580 int intr_cnt;
581 581 uint_t intr_pri;
582 582 int intr_cap;
583 583
584 584 ddi_taskq_t *taskq;
585 585 struct mrsas_ld *mr_ld_list;
586 586 kmutex_t config_dev_mtx;
587 587 /* ThunderBolt (TB) specific */
588 588 ddi_softintr_t tbolt_soft_intr_id;
589 589
590 590 #ifdef PDSUPPORT
591 591 uint32_t mr_tbolt_pd_max;
592 592 struct mrsas_tbolt_pd *mr_tbolt_pd_list;
593 593 #endif
594 594
595 595 uint8_t fast_path_io;
596 596
597 597 uint16_t tbolt;
598 598 uint16_t reply_read_index;
599 599 uint16_t reply_size; /* Single Reply struct size */
600 600 uint16_t raid_io_msg_size; /* Single message size */
601 601 uint32_t io_request_frames_phy;
602 602 uint8_t *io_request_frames;
603 603 /* Virtual address of request desc frame pool */
604 604 MRSAS_REQUEST_DESCRIPTOR_UNION *request_message_pool;
605 605 /* Physical address of request desc frame pool */
606 606 uint32_t request_message_pool_phy;
607 607 /* Virtual address of reply Frame */
608 608 MPI2_REPLY_DESCRIPTORS_UNION *reply_frame_pool;
609 609 /* Physical address of reply Frame */
610 610 uint32_t reply_frame_pool_phy;
611 611 uint8_t *reply_pool_limit; /* Last reply frame address */
612 612 /* Physical address of Last reply frame */
613 613 uint32_t reply_pool_limit_phy;
614 614 uint32_t reply_q_depth; /* Reply Queue Depth */
615 615 uint8_t max_sge_in_main_msg;
616 616 uint8_t max_sge_in_chain;
617 617 uint8_t chain_offset_io_req;
618 618 uint8_t chain_offset_mpt_msg;
619 619 MR_FW_RAID_MAP_ALL *ld_map[2];
620 620 uint32_t ld_map_phy[2];
621 621 uint32_t size_map_info;
622 622 uint64_t map_id;
623 623 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
624 624 struct mrsas_cmd *map_update_cmd;
625 625 uint32_t SyncRequired;
626 626 kmutex_t ocr_flags_mtx;
627 627 dma_obj_t drv_ver_dma_obj;
628 628 } mrsas_t;
629 629
630 630
631 631 /*
632 632 * Function templates for various controller specific functions
633 633 */
634 634 struct mrsas_function_template {
635 635 uint32_t (*read_fw_status_reg)(struct mrsas_instance *);
636 636 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *);
637 637 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
638 638 struct mrsas_cmd *);
639 639 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
640 640 struct mrsas_cmd *);
641 641 void (*enable_intr)(struct mrsas_instance *);
642 642 void (*disable_intr)(struct mrsas_instance *);
643 643 int (*intr_ack)(struct mrsas_instance *);
644 644 int (*init_adapter)(struct mrsas_instance *);
645 645 /* int (*reset_adapter)(struct mrsas_instance *); */
646 646 };
647 647
648 648 /*
649 649 * ### Helper routines ###
650 650 */
651 651
652 652 /*
653 653 * con_log() - console log routine
654 654 * @param level : indicates the severity of the message.
655 655 * @fparam mt : format string
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656 656 *
657 657 * con_log displays the error messages on the console based on the current
658 658 * debug level. Also it attaches the appropriate kernel severity level with
659 659 * the message.
660 660 *
661 661 *
662 662 * console messages debug levels
663 663 */
664 664 #define CL_NONE 0 /* No debug information */
665 665 #define CL_ANN 1 /* print unconditionally, announcements */
666 -#define CL_ANN1 2 /* No o/p */
666 +#define CL_ANN1 2 /* No-op */
667 667 #define CL_DLEVEL1 3 /* debug level 1, informative */
668 668 #define CL_DLEVEL2 4 /* debug level 2, verbose */
669 669 #define CL_DLEVEL3 5 /* debug level 3, very verbose */
670 670
671 671 #ifdef __SUNPRO_C
672 672 #define __func__ ""
673 673 #endif
674 674
675 675 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
676 676
677 677 /*
678 678 * ### SCSA definitions ###
679 679 */
680 680 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target)
681 681 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun)
682 682 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran)
683 683 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
684 684
685 685 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private)
686 686 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap))
687 687
688 688 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private)
689 689 #define CMD2PKT(sp) ((sp)->cmd_pkt)
690 690 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request))
691 691
692 692 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address)
693 693 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran)
694 694 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd)))
695 695
696 696 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */
697 697 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */
698 698 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */
699 699
700 700 /*
701 701 * ### Data structures for ioctl inteface and internal commands ###
702 702 */
703 703
704 704 /*
705 705 * Data direction flags
706 706 */
707 707 #define UIOC_RD 0x00001
708 708 #define UIOC_WR 0x00002
709 709
710 710 #define SCP2HOST(scp) (scp)->device->host /* to host */
711 711 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */
712 712 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */
713 713 #define SCP2TARGET(scp) (scp)->device->id /* to target */
714 714 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */
715 715
716 716 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
717 717 #define SCP2ADAPTER(scp) \
718 718 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
719 719
720 720 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \
721 721 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0
722 722 #define MRDRV_IS_LOGICAL(ap) \
723 723 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0
724 724 #define MAP_DEVICE_ID(instance, ap) \
725 725 (ap->a_target)
726 726
727 727 #define HIGH_LEVEL_INTR 1
728 728 #define NORMAL_LEVEL_INTR 0
729 729
730 730 #define IO_TIMEOUT_VAL 0
731 731 #define IO_RETRY_COUNT 3
732 732 #define MAX_FW_RESET_COUNT 3
733 733 /*
734 734 * scsa_cmd - Per-command mr private data
735 735 * @param cmd_dmahandle : dma handle
736 736 * @param cmd_dmacookies : current dma cookies
737 737 * @param cmd_pkt : scsi_pkt reference
738 738 * @param cmd_dmacount : dma count
739 739 * @param cmd_cookie : next cookie
740 740 * @param cmd_ncookies : cookies per window
741 741 * @param cmd_cookiecnt : cookies per sub-win
742 742 * @param cmd_nwin : number of dma windows
743 743 * @param cmd_curwin : current dma window
744 744 * @param cmd_dma_offset : current window offset
745 745 * @param cmd_dma_len : current window length
746 746 * @param cmd_flags : private flags
747 747 * @param cmd_cdblen : length of cdb
748 748 * @param cmd_scblen : length of scb
749 749 * @param cmd_buf : command buffer
750 750 * @param channel : channel for scsi sub-system
751 751 * @param target : target for scsi sub-system
752 752 * @param lun : LUN for scsi sub-system
753 753 *
754 754 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E)
755 755 * - Pointed to by pkt_ha_private field in scsi_pkt
756 756 */
757 757 struct scsa_cmd {
758 758 ddi_dma_handle_t cmd_dmahandle;
759 759 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT];
760 760 struct scsi_pkt *cmd_pkt;
761 761 ulong_t cmd_dmacount;
762 762 uint_t cmd_cookie;
763 763 uint_t cmd_ncookies;
764 764 uint_t cmd_cookiecnt;
765 765 uint_t cmd_nwin;
766 766 uint_t cmd_curwin;
767 767 off_t cmd_dma_offset;
768 768 ulong_t cmd_dma_len;
769 769 ulong_t cmd_flags;
770 770 uint_t cmd_cdblen;
771 771 uint_t cmd_scblen;
772 772 struct buf *cmd_buf;
773 773 ushort_t device_id;
774 774 uchar_t islogical;
775 775 uchar_t lun;
776 776 struct mrsas_device *mrsas_dev;
777 777 };
778 778
779 779
780 780 struct mrsas_cmd {
781 781 /*
782 782 * ThunderBolt(TB) We would be needing to have a placeholder
783 783 * for RAID_MSG_IO_REQUEST inside this structure. We are
784 784 * supposed to embed the mr_frame inside the RAID_MSG and post
785 785 * it down to the firmware.
786 786 */
787 787 union mrsas_frame *frame;
788 788 uint32_t frame_phys_addr;
789 789 uint8_t *sense;
790 790 uint8_t *sense1;
791 791 uint32_t sense_phys_addr;
792 792 uint32_t sense_phys_addr1;
793 793 dma_obj_t frame_dma_obj;
794 794 uint8_t frame_dma_obj_status;
795 795 uint32_t index;
796 796 uint8_t sync_cmd;
797 797 uint8_t cmd_status;
798 798 uint16_t abort_aen;
799 799 mlist_t list;
800 800 uint32_t frame_count;
801 801 struct scsa_cmd *cmd;
802 802 struct scsi_pkt *pkt;
803 803 Mpi2RaidSCSIIORequest_t *scsi_io_request;
804 804 Mpi2SGEIOUnion_t *sgl;
805 805 uint32_t sgl_phys_addr;
806 806 uint32_t scsi_io_request_phys_addr;
807 807 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
808 808 uint16_t SMID;
809 809 uint16_t retry_count_for_ocr;
810 810 uint16_t drv_pkt_time;
811 811 uint16_t load_balance_flag;
812 812
813 813 };
814 814
815 815 #define MAX_MGMT_ADAPTERS 1024
816 816 #define IOC_SIGNATURE "MR-SAS"
817 817
818 818 #define IOC_CMD_FIRMWARE 0x0
819 819 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000
820 820 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
821 821 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
822 822 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300
823 823
824 824
825 825 #define MRSAS_MAX_SENSE_LENGTH 32
826 826
827 827 struct mrsas_mgmt_info {
828 828
829 829 uint16_t count;
830 830 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS];
831 831 uint16_t map[MAX_MGMT_ADAPTERS];
832 832 int max_index;
833 833 };
834 834
835 835
836 836 #pragma pack(1)
837 837 /*
838 838 * SAS controller properties
839 839 */
840 840 struct mrsas_ctrl_prop {
841 841 uint16_t seq_num;
842 842 uint16_t pred_fail_poll_interval;
843 843 uint16_t intr_throttle_count;
844 844 uint16_t intr_throttle_timeouts;
845 845
846 846 uint8_t rebuild_rate;
847 847 uint8_t patrol_read_rate;
848 848 uint8_t bgi_rate;
849 849 uint8_t cc_rate;
850 850 uint8_t recon_rate;
851 851
852 852 uint8_t cache_flush_interval;
853 853
854 854 uint8_t spinup_drv_count;
855 855 uint8_t spinup_delay;
856 856
857 857 uint8_t cluster_enable;
858 858 uint8_t coercion_mode;
859 859 uint8_t alarm_enable;
860 860
861 861 uint8_t reserved_1[13];
862 862 uint32_t on_off_properties;
863 863 uint8_t reserved_4[28];
864 864 };
865 865
866 866
867 867 /*
868 868 * SAS controller information
869 869 */
870 870 struct mrsas_ctrl_info {
871 871 /* PCI device information */
872 872 struct {
873 873 uint16_t vendor_id;
874 874 uint16_t device_id;
875 875 uint16_t sub_vendor_id;
876 876 uint16_t sub_device_id;
877 877 uint8_t reserved[24];
878 878 } pci;
879 879
880 880 /* Host interface information */
881 881 struct {
882 882 uint8_t PCIX : 1;
883 883 uint8_t PCIE : 1;
884 884 uint8_t iSCSI : 1;
885 885 uint8_t SAS_3G : 1;
886 886 uint8_t reserved_0 : 4;
887 887 uint8_t reserved_1[6];
888 888 uint8_t port_count;
889 889 uint64_t port_addr[8];
890 890 } host_interface;
891 891
892 892 /* Device (backend) interface information */
893 893 struct {
894 894 uint8_t SPI : 1;
895 895 uint8_t SAS_3G : 1;
896 896 uint8_t SATA_1_5G : 1;
897 897 uint8_t SATA_3G : 1;
898 898 uint8_t reserved_0 : 4;
899 899 uint8_t reserved_1[6];
900 900 uint8_t port_count;
901 901 uint64_t port_addr[8];
902 902 } device_interface;
903 903
904 904 /* List of components residing in flash. All str are null terminated */
905 905 uint32_t image_check_word;
906 906 uint32_t image_component_count;
907 907
908 908 struct {
909 909 char name[8];
910 910 char version[32];
911 911 char build_date[16];
912 912 char built_time[16];
913 913 } image_component[8];
914 914
915 915 /*
916 916 * List of flash components that have been flashed on the card, but
917 917 * are not in use, pending reset of the adapter. This list will be
918 918 * empty if a flash operation has not occurred. All stings are null
919 919 * terminated
920 920 */
921 921 uint32_t pending_image_component_count;
922 922
923 923 struct {
924 924 char name[8];
925 925 char version[32];
926 926 char build_date[16];
927 927 char build_time[16];
928 928 } pending_image_component[8];
929 929
930 930 uint8_t max_arms;
931 931 uint8_t max_spans;
932 932 uint8_t max_arrays;
933 933 uint8_t max_lds;
934 934
935 935 char product_name[80];
936 936 char serial_no[32];
937 937
938 938 /*
939 939 * Other physical/controller/operation information. Indicates the
940 940 * presence of the hardware
941 941 */
942 942 struct {
943 943 uint32_t bbu : 1;
944 944 uint32_t alarm : 1;
945 945 uint32_t nvram : 1;
946 946 uint32_t uart : 1;
947 947 uint32_t reserved : 28;
948 948 } hw_present;
949 949
950 950 uint32_t current_fw_time;
951 951
952 952 /* Maximum data transfer sizes */
953 953 uint16_t max_concurrent_cmds;
954 954 uint16_t max_sge_count;
955 955 uint32_t max_request_size;
956 956
957 957 /* Logical and physical device counts */
958 958 uint16_t ld_present_count;
959 959 uint16_t ld_degraded_count;
960 960 uint16_t ld_offline_count;
961 961
962 962 uint16_t pd_present_count;
963 963 uint16_t pd_disk_present_count;
964 964 uint16_t pd_disk_pred_failure_count;
965 965 uint16_t pd_disk_failed_count;
966 966
967 967 /* Memory size information */
968 968 uint16_t nvram_size;
969 969 uint16_t memory_size;
970 970 uint16_t flash_size;
971 971
972 972 /* Error counters */
973 973 uint16_t mem_correctable_error_count;
974 974 uint16_t mem_uncorrectable_error_count;
975 975
976 976 /* Cluster information */
977 977 uint8_t cluster_permitted;
978 978 uint8_t cluster_active;
979 979 uint8_t reserved_1[2];
980 980
981 981 /* Controller capabilities structures */
982 982 struct {
983 983 uint32_t raid_level_0 : 1;
984 984 uint32_t raid_level_1 : 1;
985 985 uint32_t raid_level_5 : 1;
986 986 uint32_t raid_level_1E : 1;
987 987 uint32_t reserved : 28;
988 988 } raid_levels;
989 989
990 990 struct {
991 991 uint32_t rbld_rate : 1;
992 992 uint32_t cc_rate : 1;
993 993 uint32_t bgi_rate : 1;
994 994 uint32_t recon_rate : 1;
995 995 uint32_t patrol_rate : 1;
996 996 uint32_t alarm_control : 1;
997 997 uint32_t cluster_supported : 1;
998 998 uint32_t bbu : 1;
999 999 uint32_t spanning_allowed : 1;
1000 1000 uint32_t dedicated_hotspares : 1;
1001 1001 uint32_t revertible_hotspares : 1;
1002 1002 uint32_t foreign_config_import : 1;
1003 1003 uint32_t self_diagnostic : 1;
1004 1004 uint32_t reserved : 19;
1005 1005 } adapter_operations;
1006 1006
1007 1007 struct {
1008 1008 uint32_t read_policy : 1;
1009 1009 uint32_t write_policy : 1;
1010 1010 uint32_t io_policy : 1;
1011 1011 uint32_t access_policy : 1;
1012 1012 uint32_t reserved : 28;
1013 1013 } ld_operations;
1014 1014
1015 1015 struct {
1016 1016 uint8_t min;
1017 1017 uint8_t max;
1018 1018 uint8_t reserved[2];
1019 1019 } stripe_size_operations;
1020 1020
1021 1021 struct {
1022 1022 uint32_t force_online : 1;
1023 1023 uint32_t force_offline : 1;
1024 1024 uint32_t force_rebuild : 1;
1025 1025 uint32_t reserved : 29;
1026 1026 } pd_operations;
1027 1027
1028 1028 struct {
1029 1029 uint32_t ctrl_supports_sas : 1;
1030 1030 uint32_t ctrl_supports_sata : 1;
1031 1031 uint32_t allow_mix_in_encl : 1;
1032 1032 uint32_t allow_mix_in_ld : 1;
1033 1033 uint32_t allow_sata_in_cluster : 1;
1034 1034 uint32_t reserved : 27;
1035 1035 } pd_mix_support;
1036 1036
1037 1037 /* Include the controller properties (changeable items) */
1038 1038 uint8_t reserved_2[12];
1039 1039 struct mrsas_ctrl_prop properties;
1040 1040
1041 1041 uint8_t pad[0x800 - 0x640];
1042 1042 };
1043 1043
1044 1044 /*
1045 1045 * ==================================
1046 1046 * MegaRAID SAS2.0 driver definitions
1047 1047 * ==================================
1048 1048 */
1049 1049 #define MRDRV_MAX_NUM_CMD 1024
1050 1050
1051 1051 #define MRDRV_MAX_PD_CHANNELS 2
1052 1052 #define MRDRV_MAX_LD_CHANNELS 2
1053 1053 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \
1054 1054 MRDRV_MAX_LD_CHANNELS)
1055 1055 #define MRDRV_MAX_DEV_PER_CHANNEL 128
1056 1056 #define MRDRV_DEFAULT_INIT_ID -1
1057 1057 #define MRDRV_MAX_CMD_PER_LUN 1000
1058 1058 #define MRDRV_MAX_LUN 1
1059 1059 #define MRDRV_MAX_LD 64
1060 1060
1061 1061 #define MRDRV_RESET_WAIT_TIME 300
1062 1062 #define MRDRV_RESET_NOTICE_INTERVAL 5
1063 1063
1064 1064 #define MRSAS_IOCTL_CMD 0
1065 1065
1066 1066 #define MRDRV_TGT_VALID 1
1067 1067
1068 1068 /*
1069 1069 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1070 1070 * SGLs based on the size of dma_addr_t
1071 1071 */
1072 1072 #define IS_DMA64 (sizeof (dma_addr_t) == 8)
1073 1073
1074 1074 #define RESERVED0_REGISTER 0x00 /* XScale */
1075 1075 #define IB_MSG_0_OFF 0x10 /* XScale */
1076 1076 #define OB_MSG_0_OFF 0x18 /* XScale */
1077 1077 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */
1078 1078 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */
1079 1079 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */
1080 1080 #define IB_QPORT_OFF 0x40 /* XScale & ROC */
1081 1081 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */
1082 1082 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */
1083 1083 #define OB_INTR_MASK 0xFFFFFFFF
1084 1084 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF
1085 1085 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1086 1086 #define OB_SCRATCH_PAD_2_OFF 0xB4
1087 1087 #define WRITE_TBOLT_SEQ_OFF 0x00000004
1088 1088 #define DIAG_TBOLT_RESET_ADAPTER 0x00000004
1089 1089 #define HOST_TBOLT_DIAG_OFF 0x00000008
1090 1090 #define RESET_TBOLT_STATUS_OFF 0x000003C3
1091 1091 #define WRITE_SEQ_OFF 0x000000FC
1092 1092 #define HOST_DIAG_OFF 0x000000F8
1093 1093 #define DIAG_RESET_ADAPTER 0x00000004
1094 1094 #define DIAG_WRITE_ENABLE 0x00000080
1095 1095 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1096 1096
1097 1097 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \
1098 1098 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v))
1099 1099
1100 1100 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \
1101 1101 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF))
1102 1102
1103 1103 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \
1104 1104 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v))
1105 1105
1106 1106 #define IB_LOW_QPORT 0xC0
1107 1107 #define IB_HIGH_QPORT 0xC4
1108 1108 #define OB_DOORBELL_REGISTER 0x9C /* 1078 implementation */
1109 1109
1110 1110 /*
1111 1111 * All MFI register set macros accept mrsas_register_set*
1112 1112 */
1113 1113 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \
1114 1114 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
1115 1115
1116 1116 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \
1117 1117 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
1118 1118
1119 1119 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \
1120 1120 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
1121 1121
1122 1122 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \
1123 1123 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
1124 1124
1125 1125 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \
1126 1126 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
1127 1127
1128 1128 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \
1129 1129 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
1130 1130
1131 1131 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \
1132 1132 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
1133 1133
1134 1134 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \
1135 1135 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
1136 1136
1137 1137 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1138 1138 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
1139 1139
1140 1140 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
1141 1141 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
1142 1142 (v))
1143 1143
1144 1144 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \
1145 1145 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
1146 1146
1147 1147 /* Thunderbolt specific registers */
1148 1148 #define RD_OB_SCRATCH_PAD_2(instance) ddi_get32((instance)->regmap_handle, \
1149 1149 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_2_OFF))
1150 1150
1151 1151 #define WR_TBOLT_IB_WRITE_SEQ(v, instance) \
1152 1152 ddi_put32((instance)->regmap_handle, \
1153 1153 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_TBOLT_SEQ_OFF), (v))
1154 1154
1155 1155 #define RD_TBOLT_HOST_DIAG(instance) ddi_get32((instance)->regmap_handle, \
1156 1156 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF))
1157 1157
1158 1158 #define WR_TBOLT_HOST_DIAG(v, instance) ddi_put32((instance)->regmap_handle, \
1159 1159 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF), (v))
1160 1160
1161 1161 #define RD_TBOLT_RESET_STAT(instance) ddi_get32((instance)->regmap_handle, \
1162 1162 (uint32_t *)((uintptr_t)(instance)->regmap + RESET_TBOLT_STATUS_OFF))
1163 1163
1164 1164
1165 1165 #define WR_MPI2_REPLY_POST_INDEX(v, instance)\
1166 1166 ddi_put32((instance)->regmap_handle,\
1167 1167 (uint32_t *)\
1168 1168 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET),\
1169 1169 (v))
1170 1170
1171 1171
1172 1172 #define RD_MPI2_REPLY_POST_INDEX(instance)\
1173 1173 ddi_get32((instance)->regmap_handle,\
1174 1174 (uint32_t *)\
1175 1175 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET))
1176 1176
1177 1177 #define WR_IB_LOW_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1178 1178 (uint32_t *)((uintptr_t)(instance)->regmap + IB_LOW_QPORT), (v))
1179 1179
1180 1180 #define WR_IB_HIGH_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1181 1181 (uint32_t *)((uintptr_t)(instance)->regmap + IB_HIGH_QPORT), (v))
1182 1182
1183 1183 #define WR_OB_DOORBELL_REGISTER_CLEAR(v, instance)\
1184 1184 ddi_put32((instance)->regmap_handle,\
1185 1185 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_REGISTER), \
1186 1186 (v))
1187 1187
1188 1188 #define WR_RESERVED0_REGISTER(v, instance) ddi_put32((instance)->regmap_handle,\
1189 1189 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER), \
1190 1190 (v))
1191 1191
1192 1192 #define RD_RESERVED0_REGISTER(instance) ddi_get32((instance)->regmap_handle, \
1193 1193 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER))
1194 1194
1195 1195
1196 1196
1197 1197 /*
1198 1198 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
1199 1199 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
1200 1200 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
1201 1201 */
1202 1202 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1203 1203
1204 1204 /*
1205 1205 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also
1206 1206 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
1207 1207 * been set in this flag along with bit 1.
1208 1208 */
1209 1209 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001
1210 1210 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005
1211 1211
1212 1212 /* Fusion interrupt mask */
1213 1213 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008)
1214 1214
1215 1215 #define MFI_POLL_TIMEOUT_SECS 60
1216 1216
1217 1217 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \
1218 1218 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
1219 1219 #define MFI_DISABLE_INTR(instance) \
1220 1220 { \
1221 1221 uint32_t disable = 1; \
1222 1222 uint32_t mask = ddi_get32((instance)->regmap_handle, \
1223 1223 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
1224 1224 mask &= ~disable; \
1225 1225 ddi_put32((instance)->regmap_handle, (uint32_t *) \
1226 1226 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \
1227 1227 }
1228 1228
1229 1229 /* By default, the firmware programs for 8 Kbytes of memory */
1230 1230 #define DEFAULT_MFI_MEM_SZ 8192
1231 1231 #define MINIMUM_MFI_MEM_SZ 4096
1232 1232
1233 1233 /* DCMD Message Frame MAILBOX0-11 */
1234 1234 #define DCMD_MBOX_SZ 12
1235 1235
1236 1236 /*
1237 1237 * on_off_property of mrsas_ctrl_prop
1238 1238 * bit0-9, 11-31 are reserved
1239 1239 */
1240 1240 #define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */
1241 1241
1242 1242 struct mrsas_register_set {
1243 1243 uint32_t reserved_0[4]; /* 0000h */
1244 1244
1245 1245 uint32_t inbound_msg_0; /* 0010h */
1246 1246 uint32_t inbound_msg_1; /* 0014h */
1247 1247 uint32_t outbound_msg_0; /* 0018h */
1248 1248 uint32_t outbound_msg_1; /* 001Ch */
1249 1249
1250 1250 uint32_t inbound_doorbell; /* 0020h */
1251 1251 uint32_t inbound_intr_status; /* 0024h */
1252 1252 uint32_t inbound_intr_mask; /* 0028h */
1253 1253
1254 1254 uint32_t outbound_doorbell; /* 002Ch */
1255 1255 uint32_t outbound_intr_status; /* 0030h */
1256 1256 uint32_t outbound_intr_mask; /* 0034h */
1257 1257
1258 1258 uint32_t reserved_1[2]; /* 0038h */
1259 1259
1260 1260 uint32_t inbound_queue_port; /* 0040h */
1261 1261 uint32_t outbound_queue_port; /* 0044h */
1262 1262
1263 1263 uint32_t reserved_2[22]; /* 0048h */
1264 1264
1265 1265 uint32_t outbound_doorbell_clear; /* 00A0h */
1266 1266
1267 1267 uint32_t reserved_3[3]; /* 00A4h */
1268 1268
1269 1269 uint32_t outbound_scratch_pad; /* 00B0h */
1270 1270
1271 1271 uint32_t reserved_4[3]; /* 00B4h */
1272 1272
1273 1273 uint32_t inbound_low_queue_port; /* 00C0h */
1274 1274
1275 1275 uint32_t inbound_high_queue_port; /* 00C4h */
1276 1276
1277 1277 uint32_t reserved_5; /* 00C8h */
1278 1278 uint32_t index_registers[820]; /* 00CCh */
1279 1279 };
1280 1280
1281 1281 struct mrsas_sge32 {
1282 1282 uint32_t phys_addr;
1283 1283 uint32_t length;
1284 1284 };
1285 1285
1286 1286 struct mrsas_sge64 {
1287 1287 uint64_t phys_addr;
1288 1288 uint32_t length;
1289 1289 };
1290 1290
1291 1291 struct mrsas_sge_ieee {
1292 1292 uint64_t phys_addr;
1293 1293 uint32_t length;
1294 1294 uint32_t flag;
1295 1295 };
1296 1296
1297 1297 union mrsas_sgl {
1298 1298 struct mrsas_sge32 sge32[1];
1299 1299 struct mrsas_sge64 sge64[1];
1300 1300 struct mrsas_sge_ieee sge_ieee[1];
1301 1301 };
1302 1302
1303 1303 struct mrsas_header {
1304 1304 uint8_t cmd; /* 00h */
1305 1305 uint8_t sense_len; /* 01h */
1306 1306 uint8_t cmd_status; /* 02h */
1307 1307 uint8_t scsi_status; /* 03h */
1308 1308
1309 1309 uint8_t target_id; /* 04h */
1310 1310 uint8_t lun; /* 05h */
1311 1311 uint8_t cdb_len; /* 06h */
1312 1312 uint8_t sge_count; /* 07h */
1313 1313
1314 1314 uint32_t context; /* 08h */
1315 1315 uint8_t req_id; /* 0Ch */
1316 1316 uint8_t msgvector; /* 0Dh */
1317 1317 uint16_t pad_0; /* 0Eh */
1318 1318
1319 1319 uint16_t flags; /* 10h */
1320 1320 uint16_t timeout; /* 12h */
1321 1321 uint32_t data_xferlen; /* 14h */
1322 1322 };
1323 1323
1324 1324 union mrsas_sgl_frame {
1325 1325 struct mrsas_sge32 sge32[8];
1326 1326 struct mrsas_sge64 sge64[5];
1327 1327 };
1328 1328
1329 1329 struct mrsas_init_frame {
1330 1330 uint8_t cmd; /* 00h */
1331 1331 uint8_t reserved_0; /* 01h */
1332 1332 uint8_t cmd_status; /* 02h */
1333 1333
1334 1334 uint8_t reserved_1; /* 03h */
1335 1335 uint32_t reserved_2; /* 04h */
1336 1336
1337 1337 uint32_t context; /* 08h */
1338 1338 uint8_t req_id; /* 0Ch */
1339 1339 uint8_t msgvector; /* 0Dh */
1340 1340 uint16_t pad_0; /* 0Eh */
1341 1341
1342 1342 uint16_t flags; /* 10h */
1343 1343 uint16_t reserved_3; /* 12h */
1344 1344 uint32_t data_xfer_len; /* 14h */
1345 1345
1346 1346 uint32_t queue_info_new_phys_addr_lo; /* 18h */
1347 1347 uint32_t queue_info_new_phys_addr_hi; /* 1Ch */
1348 1348 uint32_t queue_info_old_phys_addr_lo; /* 20h */
1349 1349 uint32_t queue_info_old_phys_addr_hi; /* 24h */
1350 1350 uint64_t driverversion; /* 28h */
1351 1351 uint32_t reserved_4[4]; /* 30h */
1352 1352 };
1353 1353
1354 1354 struct mrsas_init_queue_info {
1355 1355 uint32_t init_flags; /* 00h */
1356 1356 uint32_t reply_queue_entries; /* 04h */
1357 1357
1358 1358 uint32_t reply_queue_start_phys_addr_lo; /* 08h */
1359 1359 uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */
1360 1360 uint32_t producer_index_phys_addr_lo; /* 10h */
1361 1361 uint32_t producer_index_phys_addr_hi; /* 14h */
1362 1362 uint32_t consumer_index_phys_addr_lo; /* 18h */
1363 1363 uint32_t consumer_index_phys_addr_hi; /* 1Ch */
1364 1364 };
1365 1365
1366 1366 struct mrsas_io_frame {
1367 1367 uint8_t cmd; /* 00h */
1368 1368 uint8_t sense_len; /* 01h */
1369 1369 uint8_t cmd_status; /* 02h */
1370 1370 uint8_t scsi_status; /* 03h */
1371 1371
1372 1372 uint8_t target_id; /* 04h */
1373 1373 uint8_t access_byte; /* 05h */
1374 1374 uint8_t reserved_0; /* 06h */
1375 1375 uint8_t sge_count; /* 07h */
1376 1376
1377 1377 uint32_t context; /* 08h */
1378 1378 uint8_t req_id; /* 0Ch */
1379 1379 uint8_t msgvector; /* 0Dh */
1380 1380 uint16_t pad_0; /* 0Eh */
1381 1381
1382 1382 uint16_t flags; /* 10h */
1383 1383 uint16_t timeout; /* 12h */
1384 1384 uint32_t lba_count; /* 14h */
1385 1385
1386 1386 uint32_t sense_buf_phys_addr_lo; /* 18h */
1387 1387 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1388 1388
1389 1389 uint32_t start_lba_lo; /* 20h */
1390 1390 uint32_t start_lba_hi; /* 24h */
1391 1391
1392 1392 union mrsas_sgl sgl; /* 28h */
1393 1393 };
1394 1394
1395 1395 struct mrsas_pthru_frame {
1396 1396 uint8_t cmd; /* 00h */
1397 1397 uint8_t sense_len; /* 01h */
1398 1398 uint8_t cmd_status; /* 02h */
1399 1399 uint8_t scsi_status; /* 03h */
1400 1400
1401 1401 uint8_t target_id; /* 04h */
1402 1402 uint8_t lun; /* 05h */
1403 1403 uint8_t cdb_len; /* 06h */
1404 1404 uint8_t sge_count; /* 07h */
1405 1405
1406 1406 uint32_t context; /* 08h */
1407 1407 uint8_t req_id; /* 0Ch */
1408 1408 uint8_t msgvector; /* 0Dh */
1409 1409 uint16_t pad_0; /* 0Eh */
1410 1410
1411 1411 uint16_t flags; /* 10h */
1412 1412 uint16_t timeout; /* 12h */
1413 1413 uint32_t data_xfer_len; /* 14h */
1414 1414
1415 1415 uint32_t sense_buf_phys_addr_lo; /* 18h */
1416 1416 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1417 1417
1418 1418 uint8_t cdb[16]; /* 20h */
1419 1419 union mrsas_sgl sgl; /* 30h */
1420 1420 };
1421 1421
1422 1422 struct mrsas_dcmd_frame {
1423 1423 uint8_t cmd; /* 00h */
1424 1424 uint8_t reserved_0; /* 01h */
1425 1425 uint8_t cmd_status; /* 02h */
1426 1426 uint8_t reserved_1[4]; /* 03h */
1427 1427 uint8_t sge_count; /* 07h */
1428 1428
1429 1429 uint32_t context; /* 08h */
1430 1430 uint8_t req_id; /* 0Ch */
1431 1431 uint8_t msgvector; /* 0Dh */
1432 1432 uint16_t pad_0; /* 0Eh */
1433 1433
1434 1434 uint16_t flags; /* 10h */
1435 1435 uint16_t timeout; /* 12h */
1436 1436
1437 1437 uint32_t data_xfer_len; /* 14h */
1438 1438 uint32_t opcode; /* 18h */
1439 1439
1440 1440 /* uint8_t mbox[DCMD_MBOX_SZ]; */ /* 1Ch */
1441 1441 union { /* 1Ch */
1442 1442 uint8_t b[DCMD_MBOX_SZ];
1443 1443 uint16_t s[6];
1444 1444 uint32_t w[3];
1445 1445 } mbox;
1446 1446
1447 1447 union mrsas_sgl sgl; /* 28h */
1448 1448 };
1449 1449
1450 1450 struct mrsas_abort_frame {
1451 1451 uint8_t cmd; /* 00h */
1452 1452 uint8_t reserved_0; /* 01h */
1453 1453 uint8_t cmd_status; /* 02h */
1454 1454
1455 1455 uint8_t reserved_1; /* 03h */
1456 1456 uint32_t reserved_2; /* 04h */
1457 1457
1458 1458 uint32_t context; /* 08h */
1459 1459 uint8_t req_id; /* 0Ch */
1460 1460 uint8_t msgvector; /* 0Dh */
1461 1461 uint16_t pad_0; /* 0Eh */
1462 1462
1463 1463 uint16_t flags; /* 10h */
1464 1464 uint16_t reserved_3; /* 12h */
1465 1465 uint32_t reserved_4; /* 14h */
1466 1466
1467 1467 uint32_t abort_context; /* 18h */
1468 1468 uint32_t pad_1; /* 1Ch */
1469 1469
1470 1470 uint32_t abort_mfi_phys_addr_lo; /* 20h */
1471 1471 uint32_t abort_mfi_phys_addr_hi; /* 24h */
1472 1472
1473 1473 uint32_t reserved_5[6]; /* 28h */
1474 1474 };
1475 1475
1476 1476 struct mrsas_smp_frame {
1477 1477 uint8_t cmd; /* 00h */
1478 1478 uint8_t reserved_1; /* 01h */
1479 1479 uint8_t cmd_status; /* 02h */
1480 1480 uint8_t connection_status; /* 03h */
1481 1481
1482 1482 uint8_t reserved_2[3]; /* 04h */
1483 1483 uint8_t sge_count; /* 07h */
1484 1484
1485 1485 uint32_t context; /* 08h */
1486 1486 uint8_t req_id; /* 0Ch */
1487 1487 uint8_t msgvector; /* 0Dh */
1488 1488 uint16_t pad_0; /* 0Eh */
1489 1489
1490 1490 uint16_t flags; /* 10h */
1491 1491 uint16_t timeout; /* 12h */
1492 1492
1493 1493 uint32_t data_xfer_len; /* 14h */
1494 1494
1495 1495 uint64_t sas_addr; /* 20h */
1496 1496
1497 1497 union mrsas_sgl sgl[2]; /* 28h */
1498 1498 };
1499 1499
1500 1500 struct mrsas_stp_frame {
1501 1501 uint8_t cmd; /* 00h */
1502 1502 uint8_t reserved_1; /* 01h */
1503 1503 uint8_t cmd_status; /* 02h */
1504 1504 uint8_t connection_status; /* 03h */
1505 1505
1506 1506 uint8_t target_id; /* 04h */
1507 1507 uint8_t reserved_2[2]; /* 04h */
1508 1508 uint8_t sge_count; /* 07h */
1509 1509
1510 1510 uint32_t context; /* 08h */
1511 1511 uint8_t req_id; /* 0Ch */
1512 1512 uint8_t msgvector; /* 0Dh */
1513 1513 uint16_t pad_0; /* 0Eh */
1514 1514
1515 1515 uint16_t flags; /* 10h */
1516 1516 uint16_t timeout; /* 12h */
1517 1517
1518 1518 uint32_t data_xfer_len; /* 14h */
1519 1519
1520 1520 uint16_t fis[10]; /* 28h */
1521 1521 uint32_t stp_flags; /* 3C */
1522 1522 union mrsas_sgl sgl; /* 40 */
1523 1523 };
1524 1524
1525 1525 union mrsas_frame {
1526 1526 struct mrsas_header hdr;
1527 1527 struct mrsas_init_frame init;
1528 1528 struct mrsas_io_frame io;
1529 1529 struct mrsas_pthru_frame pthru;
1530 1530 struct mrsas_dcmd_frame dcmd;
1531 1531 struct mrsas_abort_frame abort;
1532 1532 struct mrsas_smp_frame smp;
1533 1533 struct mrsas_stp_frame stp;
1534 1534
1535 1535 uint8_t raw_bytes[64];
1536 1536 };
1537 1537
1538 1538 typedef struct mrsas_pd_address {
1539 1539 uint16_t device_id;
1540 1540 uint16_t encl_id;
1541 1541
1542 1542 union {
1543 1543 struct {
1544 1544 uint8_t encl_index;
1545 1545 uint8_t slot_number;
1546 1546 } pd_address;
1547 1547 struct {
1548 1548 uint8_t encl_position;
1549 1549 uint8_t encl_connector_index;
1550 1550 } encl_address;
1551 1551 }address;
1552 1552
1553 1553 uint8_t scsi_dev_type;
1554 1554
1555 1555 union {
1556 1556 uint8_t port_bitmap;
1557 1557 uint8_t port_numbers;
1558 1558 } connected;
1559 1559
1560 1560 uint64_t sas_addr[2];
1561 1561 } mrsas_pd_address_t;
1562 1562
1563 1563 union mrsas_evt_class_locale {
1564 1564 struct {
1565 1565 uint16_t locale;
1566 1566 uint8_t reserved;
1567 1567 int8_t class;
1568 1568 } members;
1569 1569
1570 1570 uint32_t word;
1571 1571 };
1572 1572
1573 1573 struct mrsas_evt_log_info {
1574 1574 uint32_t newest_seq_num;
1575 1575 uint32_t oldest_seq_num;
1576 1576 uint32_t clear_seq_num;
1577 1577 uint32_t shutdown_seq_num;
1578 1578 uint32_t boot_seq_num;
1579 1579 };
1580 1580
1581 1581 struct mrsas_progress {
1582 1582 uint16_t progress;
1583 1583 uint16_t elapsed_seconds;
1584 1584 };
1585 1585
1586 1586 struct mrsas_evtarg_ld {
1587 1587 uint16_t target_id;
1588 1588 uint8_t ld_index;
1589 1589 uint8_t reserved;
1590 1590 };
1591 1591
1592 1592 struct mrsas_evtarg_pd {
1593 1593 uint16_t device_id;
1594 1594 uint8_t encl_index;
1595 1595 uint8_t slot_number;
1596 1596 };
1597 1597
1598 1598 struct mrsas_evt_detail {
1599 1599 uint32_t seq_num;
1600 1600 uint32_t time_stamp;
1601 1601 uint32_t code;
1602 1602 union mrsas_evt_class_locale cl;
1603 1603 uint8_t arg_type;
1604 1604 uint8_t reserved1[15];
1605 1605
1606 1606 union {
1607 1607 struct {
1608 1608 struct mrsas_evtarg_pd pd;
1609 1609 uint8_t cdb_length;
1610 1610 uint8_t sense_length;
1611 1611 uint8_t reserved[2];
1612 1612 uint8_t cdb[16];
1613 1613 uint8_t sense[64];
1614 1614 } cdbSense;
1615 1615
1616 1616 struct mrsas_evtarg_ld ld;
1617 1617
1618 1618 struct {
1619 1619 struct mrsas_evtarg_ld ld;
1620 1620 uint64_t count;
1621 1621 } ld_count;
1622 1622
1623 1623 struct {
1624 1624 uint64_t lba;
1625 1625 struct mrsas_evtarg_ld ld;
1626 1626 } ld_lba;
1627 1627
1628 1628 struct {
1629 1629 struct mrsas_evtarg_ld ld;
1630 1630 uint32_t prevOwner;
1631 1631 uint32_t newOwner;
1632 1632 } ld_owner;
1633 1633
1634 1634 struct {
1635 1635 uint64_t ld_lba;
1636 1636 uint64_t pd_lba;
1637 1637 struct mrsas_evtarg_ld ld;
1638 1638 struct mrsas_evtarg_pd pd;
1639 1639 } ld_lba_pd_lba;
1640 1640
1641 1641 struct {
1642 1642 struct mrsas_evtarg_ld ld;
1643 1643 struct mrsas_progress prog;
1644 1644 } ld_prog;
1645 1645
1646 1646 struct {
1647 1647 struct mrsas_evtarg_ld ld;
1648 1648 uint32_t prev_state;
1649 1649 uint32_t new_state;
1650 1650 } ld_state;
1651 1651
1652 1652 struct {
1653 1653 uint64_t strip;
1654 1654 struct mrsas_evtarg_ld ld;
1655 1655 } ld_strip;
1656 1656
1657 1657 struct mrsas_evtarg_pd pd;
1658 1658
1659 1659 struct {
1660 1660 struct mrsas_evtarg_pd pd;
1661 1661 uint32_t err;
1662 1662 } pd_err;
1663 1663
1664 1664 struct {
1665 1665 uint64_t lba;
1666 1666 struct mrsas_evtarg_pd pd;
1667 1667 } pd_lba;
1668 1668
1669 1669 struct {
1670 1670 uint64_t lba;
1671 1671 struct mrsas_evtarg_pd pd;
1672 1672 struct mrsas_evtarg_ld ld;
1673 1673 } pd_lba_ld;
1674 1674
1675 1675 struct {
1676 1676 struct mrsas_evtarg_pd pd;
1677 1677 struct mrsas_progress prog;
1678 1678 } pd_prog;
1679 1679
1680 1680 struct {
1681 1681 struct mrsas_evtarg_pd pd;
1682 1682 uint32_t prevState;
1683 1683 uint32_t newState;
1684 1684 } pd_state;
1685 1685
1686 1686 struct {
1687 1687 uint16_t vendorId;
1688 1688 uint16_t deviceId;
1689 1689 uint16_t subVendorId;
1690 1690 uint16_t subDeviceId;
1691 1691 } pci;
1692 1692
1693 1693 uint32_t rate;
1694 1694 char str[96];
1695 1695
1696 1696 struct {
1697 1697 uint32_t rtc;
1698 1698 uint32_t elapsedSeconds;
1699 1699 } time;
1700 1700
1701 1701 struct {
1702 1702 uint32_t ecar;
1703 1703 uint32_t elog;
1704 1704 char str[64];
1705 1705 } ecc;
1706 1706
1707 1707 mrsas_pd_address_t pd_addr;
1708 1708
1709 1709 uint8_t b[96];
1710 1710 uint16_t s[48];
1711 1711 uint32_t w[24];
1712 1712 uint64_t d[12];
1713 1713 } args;
1714 1714
1715 1715 char description[128];
1716 1716
1717 1717 };
1718 1718
1719 1719 /* only 63 are usable by the application */
1720 1720 #define MAX_LOGICAL_DRIVES 64
1721 1721 /* only 255 physical devices may be used */
1722 1722 #define MAX_PHYSICAL_DEVICES 256
1723 1723 #define MAX_PD_PER_ENCLOSURE 64
1724 1724 /* maximum disks per array */
1725 1725 #define MAX_ROW_SIZE 32
1726 1726 /* maximum spans per logical drive */
1727 1727 #define MAX_SPAN_DEPTH 8
1728 1728 /* maximum number of arrays a hot spare may be dedicated to */
1729 1729 #define MAX_ARRAYS_DEDICATED 16
1730 1730 /* maximum number of arrays which may exist */
1731 1731 #define MAX_ARRAYS 128
1732 1732 /* maximum number of foreign configs that may ha managed at once */
1733 1733 #define MAX_FOREIGN_CONFIGS 8
1734 1734 /* maximum spares (global and dedicated combined) */
1735 1735 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES
1736 1736 /* maximum possible Target IDs (i.e. 0 to 63) */
1737 1737 #define MAX_TARGET_ID 63
1738 1738 /* maximum number of supported enclosures */
1739 1739 #define MAX_ENCLOSURES 32
1740 1740 /* maximum number of PHYs per controller */
1741 1741 #define MAX_PHYS_PER_CONTROLLER 16
1742 1742 /* maximum number of LDs per array (due to DDF limitations) */
1743 1743 #define MAX_LDS_PER_ARRAY 16
1744 1744
1745 1745 /*
1746 1746 * -----------------------------------------------------------------------------
1747 1747 * -----------------------------------------------------------------------------
1748 1748 *
1749 1749 * Logical Drive commands
1750 1750 *
1751 1751 * -----------------------------------------------------------------------------
1752 1752 * -----------------------------------------------------------------------------
1753 1753 */
1754 1754 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */
1755 1755
1756 1756 /*
1757 1757 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST
1758 1758 * dcmd.mbox - reserved
1759 1759 * dcmd.sge IN - ptr to returned MR_LD_LIST structure
1760 1760 * Desc: Return the logical drive list structure
1761 1761 * Status: No error
1762 1762 */
1763 1763
1764 1764 /*
1765 1765 * defines the logical drive reference structure
1766 1766 */
1767 1767 typedef union _MR_LD_REF { /* LD reference structure */
1768 1768 struct {
1769 1769 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */
1770 1770 uint8_t reserved; /* reserved for in line with MR_PD_REF */
1771 1771 uint16_t seqNum; /* Sequence Number */
1772 1772 } ld_ref;
1773 1773 uint32_t ref; /* shorthand reference to full 32-bits */
1774 1774 } MR_LD_REF; /* 4 bytes */
1775 1775
1776 1776 /*
1777 1777 * defines the logical drive list structure
1778 1778 */
1779 1779 typedef struct _MR_LD_LIST {
1780 1780 uint32_t ldCount; /* number of LDs */
1781 1781 uint32_t reserved; /* pad to 8-byte boundary */
1782 1782 struct {
1783 1783 MR_LD_REF ref; /* LD reference */
1784 1784 uint8_t state; /* current LD state (MR_LD_STATE) */
1785 1785 uint8_t reserved[3]; /* pad to 8-byte boundary */
1786 1786 uint64_t size; /* LD size */
1787 1787 } ldList[MAX_LOGICAL_DRIVES];
1788 1788 } MR_LD_LIST;
1789 1789
1790 1790 struct mrsas_drv_ver {
1791 1791 uint8_t signature[12];
1792 1792 uint8_t os_name[16];
1793 1793 uint8_t os_ver[12];
1794 1794 uint8_t drv_name[20];
1795 1795 uint8_t drv_ver[32];
1796 1796 uint8_t drv_rel_date[20];
1797 1797 };
1798 1798
1799 1799 #define PCI_TYPE0_ADDRESSES 6
1800 1800 #define PCI_TYPE1_ADDRESSES 2
1801 1801 #define PCI_TYPE2_ADDRESSES 5
1802 1802
1803 1803 struct mrsas_pci_common_header {
1804 1804 uint16_t vendorID; /* (ro) */
1805 1805 uint16_t deviceID; /* (ro) */
1806 1806 uint16_t command; /* Device control */
1807 1807 uint16_t status;
1808 1808 uint8_t revisionID; /* (ro) */
1809 1809 uint8_t progIf; /* (ro) */
1810 1810 uint8_t subClass; /* (ro) */
1811 1811 uint8_t baseClass; /* (ro) */
1812 1812 uint8_t cacheLineSize; /* (ro+) */
1813 1813 uint8_t latencyTimer; /* (ro+) */
1814 1814 uint8_t headerType; /* (ro) */
1815 1815 uint8_t bist; /* Built in self test */
1816 1816
1817 1817 union {
1818 1818 struct {
1819 1819 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES];
1820 1820 uint32_t cis;
1821 1821 uint16_t subVendorID;
1822 1822 uint16_t subSystemID;
1823 1823 uint32_t romBaseAddress;
1824 1824 uint8_t capabilitiesPtr;
1825 1825 uint8_t reserved1[3];
1826 1826 uint32_t reserved2;
1827 1827 uint8_t interruptLine;
1828 1828 uint8_t interruptPin; /* (ro) */
1829 1829 uint8_t minimumGrant; /* (ro) */
1830 1830 uint8_t maximumLatency; /* (ro) */
1831 1831 } type_0;
1832 1832
1833 1833 struct {
1834 1834 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES];
1835 1835 uint8_t primaryBus;
1836 1836 uint8_t secondaryBus;
1837 1837 uint8_t subordinateBus;
1838 1838 uint8_t secondaryLatency;
1839 1839 uint8_t ioBase;
1840 1840 uint8_t ioLimit;
1841 1841 uint16_t secondaryStatus;
1842 1842 uint16_t memoryBase;
1843 1843 uint16_t memoryLimit;
1844 1844 uint16_t prefetchBase;
1845 1845 uint16_t prefetchLimit;
1846 1846 uint32_t prefetchBaseUpper32;
1847 1847 uint32_t prefetchLimitUpper32;
1848 1848 uint16_t ioBaseUpper16;
1849 1849 uint16_t ioLimitUpper16;
1850 1850 uint8_t capabilitiesPtr;
1851 1851 uint8_t reserved1[3];
1852 1852 uint32_t romBaseAddress;
1853 1853 uint8_t interruptLine;
1854 1854 uint8_t interruptPin;
1855 1855 uint16_t bridgeControl;
1856 1856 } type_1;
1857 1857
1858 1858 struct {
1859 1859 uint32_t socketRegistersBaseAddress;
1860 1860 uint8_t capabilitiesPtr;
1861 1861 uint8_t reserved;
1862 1862 uint16_t secondaryStatus;
1863 1863 uint8_t primaryBus;
1864 1864 uint8_t secondaryBus;
1865 1865 uint8_t subordinateBus;
1866 1866 uint8_t secondaryLatency;
1867 1867 struct {
1868 1868 uint32_t base;
1869 1869 uint32_t limit;
1870 1870 } range[PCI_TYPE2_ADDRESSES-1];
1871 1871 uint8_t interruptLine;
1872 1872 uint8_t interruptPin;
1873 1873 uint16_t bridgeControl;
1874 1874 } type_2;
1875 1875 } header;
1876 1876 };
1877 1877
1878 1878 struct mrsas_pci_link_capability {
1879 1879 union {
1880 1880 struct {
1881 1881 uint32_t linkSpeed :4;
1882 1882 uint32_t linkWidth :6;
1883 1883 uint32_t aspmSupport :2;
1884 1884 uint32_t losExitLatency :3;
1885 1885 uint32_t l1ExitLatency :3;
1886 1886 uint32_t rsvdp :6;
1887 1887 uint32_t portNumber :8;
1888 1888 } bits;
1889 1889
1890 1890 uint32_t asUlong;
1891 1891 } cap;
1892 1892
1893 1893 };
1894 1894
1895 1895 struct mrsas_pci_link_status_capability {
1896 1896 union {
1897 1897 struct {
1898 1898 uint16_t linkSpeed :4;
1899 1899 uint16_t negotiatedLinkWidth :6;
1900 1900 uint16_t linkTrainingError :1;
1901 1901 uint16_t linkTraning :1;
1902 1902 uint16_t slotClockConfig :1;
1903 1903 uint16_t rsvdZ :3;
1904 1904 } bits;
1905 1905
1906 1906 uint16_t asUshort;
1907 1907 } stat_cap;
1908 1908
1909 1909 uint16_t reserved;
1910 1910
1911 1911 };
1912 1912
1913 1913 struct mrsas_pci_capabilities {
1914 1914 struct mrsas_pci_link_capability linkCapability;
1915 1915 struct mrsas_pci_link_status_capability linkStatusCapability;
1916 1916 };
1917 1917
1918 1918 struct mrsas_pci_information
1919 1919 {
1920 1920 uint32_t busNumber;
1921 1921 uint8_t deviceNumber;
1922 1922 uint8_t functionNumber;
1923 1923 uint8_t interruptVector;
1924 1924 uint8_t reserved;
1925 1925 struct mrsas_pci_common_header pciHeaderInfo;
1926 1926 struct mrsas_pci_capabilities capability;
1927 1927 uint8_t reserved2[32];
1928 1928 };
1929 1929
1930 1930 struct mrsas_ioctl {
1931 1931 uint16_t version;
1932 1932 uint16_t controller_id;
1933 1933 uint8_t signature[8];
1934 1934 uint32_t reserved_1;
1935 1935 uint32_t control_code;
1936 1936 uint32_t reserved_2[2];
1937 1937 uint8_t frame[64];
1938 1938 union mrsas_sgl_frame sgl_frame;
1939 1939 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH];
1940 1940 uint8_t data[1];
1941 1941 };
1942 1942
1943 1943 struct mrsas_aen {
1944 1944 uint16_t host_no;
1945 1945 uint16_t cmd_status;
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1946 1946 uint32_t seq_num;
1947 1947 uint32_t class_locale_word;
1948 1948 };
1949 1949
1950 1950 #pragma pack()
1951 1951
1952 1952 #ifndef DDI_VENDOR_LSI
1953 1953 #define DDI_VENDOR_LSI "LSI"
1954 1954 #endif /* DDI_VENDOR_LSI */
1955 1955
1956 -int mrsas_config_scsi_device(struct mrsas_instance *,
1957 - struct scsi_device *, dev_info_t **);
1956 +int mrsas_config_scsi_device(struct mrsas_instance *,
1957 + struct scsi_device *, dev_info_t **);
1958 1958
1959 1959 #ifdef PDSUPPORT
1960 -int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t,
1961 - uint8_t, dev_info_t **);
1960 +int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t,
1961 + uint8_t, dev_info_t **);
1962 1962 #endif
1963 1963
1964 -dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t,
1965 - uint8_t);
1966 -int mrsas_service_evt(struct mrsas_instance *, int, int, int,
1967 - uint64_t);
1964 +dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, uint8_t);
1965 +int mrsas_service_evt(struct mrsas_instance *, int, int, int, uint64_t);
1968 1966 void return_raid_msg_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1969 1967 struct mrsas_cmd *get_raid_msg_mfi_pkt(struct mrsas_instance *);
1970 1968 void return_raid_msg_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1971 1969
1972 1970 int alloc_space_for_mpi2(struct mrsas_instance *);
1973 1971 void fill_up_drv_ver(struct mrsas_drv_ver *dv);
1974 1972
1975 1973 int mrsas_issue_init_mpi2(struct mrsas_instance *);
1976 1974 struct scsi_pkt *mrsas_tbolt_tran_init_pkt(struct scsi_address *, register
1977 1975 struct scsi_pkt *, struct buf *, int, int, int, int,
1978 1976 int (*)(), caddr_t);
1979 1977 int mrsas_tbolt_tran_start(struct scsi_address *,
1980 1978 register struct scsi_pkt *);
1981 1979 uint32_t tbolt_read_fw_status_reg(struct mrsas_instance *);
1982 1980 void tbolt_issue_cmd(struct mrsas_cmd *, struct mrsas_instance *);
1983 1981 int tbolt_issue_cmd_in_poll_mode(struct mrsas_instance *,
1984 1982 struct mrsas_cmd *);
1985 1983 int tbolt_issue_cmd_in_sync_mode(struct mrsas_instance *,
1986 1984 struct mrsas_cmd *);
1987 1985 void tbolt_enable_intr(struct mrsas_instance *);
1988 1986 void tbolt_disable_intr(struct mrsas_instance *);
1989 1987 int tbolt_intr_ack(struct mrsas_instance *);
1990 1988 uint_t mr_sas_tbolt_process_outstanding_cmd(struct mrsas_instance *);
1991 1989 uint_t tbolt_softintr();
1992 1990 int mrsas_tbolt_dma(struct mrsas_instance *, uint32_t, int, int (*)());
1993 1991 int mrsas_check_dma_handle(ddi_dma_handle_t handle);
1994 1992 int mrsas_check_acc_handle(ddi_acc_handle_t handle);
1995 1993 int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
1996 1994 struct buf *, int, int (*)());
1997 1995 int mrsas_dma_move(struct mrsas_instance *,
1998 1996 struct scsi_pkt *, struct buf *);
1999 1997 int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
2000 1998 uchar_t);
2001 1999 void mr_sas_tbolt_build_mfi_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2002 2000 int mrsas_dma_alloc_dmd(struct mrsas_instance *, dma_obj_t *);
2003 2001 void tbolt_complete_cmd_in_sync_mode(struct mrsas_instance *,
2004 2002 struct mrsas_cmd *);
2005 2003 int alloc_req_rep_desc(struct mrsas_instance *);
2006 2004 int mrsas_mode_sense_build(struct scsi_pkt *);
2007 2005 void push_pending_mfi_pkt(struct mrsas_instance *,
2008 2006 struct mrsas_cmd *);
2009 2007 int mrsas_issue_pending_cmds(struct mrsas_instance *);
2010 2008 int mrsas_print_pending_cmds(struct mrsas_instance *);
2011 2009 int mrsas_complete_pending_cmds(struct mrsas_instance *);
2012 2010
2013 2011 int create_mfi_frame_pool(struct mrsas_instance *);
2014 2012 void destroy_mfi_frame_pool(struct mrsas_instance *);
2015 2013 int create_mfi_mpi_frame_pool(struct mrsas_instance *);
2016 2014 void destroy_mfi_mpi_frame_pool(struct mrsas_instance *);
2017 2015 int create_mpi2_frame_pool(struct mrsas_instance *);
2018 2016 void destroy_mpi2_frame_pool(struct mrsas_instance *);
2019 2017 int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
2020 2018 void mrsas_tbolt_free_additional_dma_buffer(struct mrsas_instance *);
2021 2019 void free_req_desc_pool(struct mrsas_instance *);
2022 2020 void free_space_for_mpi2(struct mrsas_instance *);
2023 2021 void mrsas_dump_reply_desc(struct mrsas_instance *);
2024 2022 void tbolt_complete_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2025 2023 void display_scsi_inquiry(caddr_t);
2026 2024 void service_mfi_aen(struct mrsas_instance *, struct mrsas_cmd *);
2027 2025 int mrsas_mode_sense_build(struct scsi_pkt *);
2028 2026 int mrsas_tbolt_get_ld_map_info(struct mrsas_instance *);
2029 2027 struct mrsas_cmd *mrsas_tbolt_build_poll_cmd(struct mrsas_instance *,
2030 2028 struct scsi_address *, struct scsi_pkt *, uchar_t *);
2031 2029 int mrsas_tbolt_reset_ppc(struct mrsas_instance *instance);
2032 2030 void mrsas_tbolt_kill_adapter(struct mrsas_instance *instance);
2033 2031 int abort_syncmap_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2034 2032 void mrsas_tbolt_prepare_cdb(struct mrsas_instance *instance, U8 cdb[],
2035 2033 struct IO_REQUEST_INFO *, Mpi2RaidSCSIIORequest_t *, U32);
2036 2034
2037 2035
2038 2036 int mrsas_init_adapter_ppc(struct mrsas_instance *instance);
2039 2037 int mrsas_init_adapter_tbolt(struct mrsas_instance *instance);
2040 2038 int mrsas_init_adapter(struct mrsas_instance *instance);
2041 2039
2042 2040 int mrsas_alloc_cmd_pool(struct mrsas_instance *instance);
2043 2041 void mrsas_free_cmd_pool(struct mrsas_instance *instance);
2044 2042
2045 2043 void mrsas_print_cmd_details(struct mrsas_instance *, struct mrsas_cmd *, int);
2046 2044 struct mrsas_cmd *get_raid_msg_pkt(struct mrsas_instance *);
2047 2045
2048 2046 int mfi_state_transition_to_ready(struct mrsas_instance *);
2049 2047
2050 2048
2051 2049 /* FMA functions. */
2052 2050 int mrsas_common_check(struct mrsas_instance *, struct mrsas_cmd *);
2053 2051 void mrsas_fm_ereport(struct mrsas_instance *, char *);
2054 2052
2055 2053
2056 2054 #ifdef __cplusplus
2057 2055 }
2058 2056 #endif
2059 2057
2060 2058 #endif /* _MR_SAS_H_ */
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