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3500 Support LSI SAS2008 (Falcon) Skinny FW for mr_sas(7D)
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--- old/usr/src/uts/common/io/mr_sas/mr_sas.h
+++ new/usr/src/uts/common/io/mr_sas/mr_sas.h
1 1 /*
2 2 * mr_sas.h: header for mr_sas
3 3 *
4 4 * Solaris MegaRAID driver for SAS2.0 controllers
5 5 * Copyright (c) 2008-2012, LSI Logic Corporation.
6 6 * All rights reserved.
7 7 *
8 8 * Version:
9 9 * Author:
10 10 * Swaminathan K S
11 11 * Arun Chandrashekhar
12 12 * Manju R
13 13 * Rasheed
14 14 * Shakeel Bukhari
15 15 *
16 16 * Redistribution and use in source and binary forms, with or without
17 17 * modification, are permitted provided that the following conditions are met:
18 18 *
19 19 * 1. Redistributions of source code must retain the above copyright notice,
20 20 * this list of conditions and the following disclaimer.
21 21 *
22 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 23 * this list of conditions and the following disclaimer in the documentation
24 24 * and/or other materials provided with the distribution.
25 25 *
26 26 * 3. Neither the name of the author nor the names of its contributors may be
27 27 * used to endorse or promote products derived from this software without
28 28 * specific prior written permission.
29 29 *
30 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
34 34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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36 36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
37 37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
38 38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
40 40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41 41 * DAMAGE.
42 42 */
43 43
44 44 /*
45 45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
46 + * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
46 47 */
47 48
48 49 #ifndef _MR_SAS_H_
49 50 #define _MR_SAS_H_
50 51
51 52 #ifdef __cplusplus
52 53 extern "C" {
53 54 #endif
54 55
55 56 #include <sys/scsi/scsi.h>
56 57 #include "mr_sas_list.h"
57 58 #include "ld_pd_map.h"
58 59
59 60 /*
60 61 * MegaRAID SAS2.0 Driver meta data
61 62 */
62 63 #define MRSAS_VERSION "6.503.00.00ILLUMOS"
63 64 #define MRSAS_RELDATE "July 30, 2012"
64 65
65 66 #define MRSAS_TRUE 1
66 67 #define MRSAS_FALSE 0
67 68
68 69 #define ADAPTER_RESET_NOT_REQUIRED 0
69 70 #define ADAPTER_RESET_REQUIRED 1
70 71
71 72 #define PDSUPPORT 1
72 73
73 74 /*
74 75 * MegaRAID SAS2.0 device id conversion definitions.
75 76 */
76 77 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT)
77 78 #define MRSAS_GET_BOUNDARY_ALIGNED_LEN(len, new_len, boundary_len) { \
78 79 int rem; \
79 80 rem = (len / boundary_len); \
80 81 if ((rem * boundary_len) != len) { \
81 82 new_len = len + ((rem + 1) * boundary_len - len); \
82 83 } else { \
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83 84 new_len = len; \
84 85 } \
85 86 }
86 87
87 88
88 89 /*
89 90 * MegaRAID SAS2.0 supported controllers
90 91 */
91 92 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078
92 93 #define PCI_DEVICE_ID_LSI_2108V 0x0079
94 +#define PCI_DEVICE_ID_LSI_SKINNY 0x0071
95 +#define PCI_DEVICE_ID_LSI_SKINNY_NEW 0x0073
93 96 #define PCI_DEVICE_ID_LSI_TBOLT 0x005b
94 97 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
95 98
96 99 /*
97 100 * Register Index for 2108 Controllers.
98 101 */
99 102 #define REGISTER_SET_IO_2108 (2)
100 103
101 104 #define MRSAS_MAX_SGE_CNT 0x50
102 105 #define MRSAS_APP_RESERVED_CMDS 32
106 +#define MRSAS_APP_MIN_RESERVED_CMDS 4
103 107
104 108 #define MRSAS_IOCTL_DRIVER 0x12341234
105 109 #define MRSAS_IOCTL_FIRMWARE 0x12345678
106 110 #define MRSAS_IOCTL_AEN 0x87654321
107 111
108 112 #define MRSAS_1_SECOND 1000000
109 113
110 114 #ifdef PDSUPPORT
111 115
112 116 #define UNCONFIGURED_GOOD 0x0
113 117 #define PD_SYSTEM 0x40
114 118 #define MR_EVT_PD_STATE_CHANGE 0x0072
115 119 #define MR_EVT_PD_REMOVED_EXT 0x00f8
116 120 #define MR_EVT_PD_INSERTED_EXT 0x00f7
117 121 #define MR_DCMD_PD_GET_INFO 0x02020000
118 122 #define MRSAS_TBOLT_PD_LUN 1
119 123 #define MRSAS_TBOLT_PD_TGT_MAX 255
120 124 #define MRSAS_TBOLT_GET_PD_MAX(s) ((s)->mr_tbolt_pd_max)
121 125
122 126 #endif
123 127
124 128 /* Raid Context Flags */
125 129 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
126 130 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
127 131 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
128 132 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
129 133 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1
130 134 } MR_RAID_FLAGS_IO_SUB_TYPE;
131 135
132 136 /* Dynamic Enumeration Flags */
133 137 #define MRSAS_LD_LUN 0
134 138 #define WWN_STRLEN 17
135 139 #define LD_SYNC_BIT 1
136 140 #define LD_SYNC_SHIFT 14
137 141 /* ThunderBolt (TB) specific */
138 142 #define MRSAS_THUNDERBOLT_MSG_SIZE 256
139 143 #define MRSAS_THUNDERBOLT_MAX_COMMANDS 1024
140 144 #define MRSAS_THUNDERBOLT_MAX_REPLY_COUNT 1024
141 145 #define MRSAS_THUNDERBOLT_REPLY_SIZE 8
142 146 #define MRSAS_THUNDERBOLT_MAX_CHAIN_COUNT 1
143 147
144 148 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
145 149 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1
146 150
147 151 #define MR_EVT_LD_FAST_PATH_IO_STATUS_CHANGED (0xFFFF)
148 152
149 153 #define MR_INTERNAL_MFI_FRAMES_SMID 1
150 154 #define MR_CTRL_EVENT_WAIT_SMID 2
151 155 #define MR_INTERNAL_DRIVER_RESET_SMID 3
152 156
153 157
154 158 /*
155 159 * =====================================
156 160 * MegaRAID SAS2.0 MFI firmware definitions
157 161 * =====================================
158 162 */
159 163 /*
160 164 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for
161 165 * protocol between the software and firmware. Commands are issued using
162 166 * "message frames"
163 167 */
164 168
165 169 /*
166 170 * FW posts its state in upper 4 bits of outbound_msg_0 register
167 171 */
168 172 #define MFI_STATE_MASK 0xF0000000
169 173 #define MFI_STATE_UNDEFINED 0x00000000
170 174 #define MFI_STATE_BB_INIT 0x10000000
171 175 #define MFI_STATE_FW_INIT 0x40000000
172 176 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
173 177 #define MFI_STATE_FW_INIT_2 0x70000000
174 178 #define MFI_STATE_DEVICE_SCAN 0x80000000
175 179 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
176 180 #define MFI_STATE_FLUSH_CACHE 0xA0000000
177 181 #define MFI_STATE_READY 0xB0000000
178 182 #define MFI_STATE_OPERATIONAL 0xC0000000
179 183 #define MFI_STATE_FAULT 0xF0000000
180 184
181 185 #define MRMFI_FRAME_SIZE 64
182 186
183 187 /*
184 188 * During FW init, clear pending cmds & reset state using inbound_msg_0
185 189 *
186 190 * ABORT : Abort all pending cmds
187 191 * READY : Move from OPERATIONAL to READY state; discard queue info
188 192 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
189 193 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
190 194 */
191 195 #define MFI_INIT_ABORT 0x00000001
192 196 #define MFI_INIT_READY 0x00000002
193 197 #define MFI_INIT_MFIMODE 0x00000004
194 198 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
195 199 #define MFI_INIT_HOTPLUG 0x00000010
196 200 #define MFI_STOP_ADP 0x00000020
197 201 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
198 202
199 203 /*
200 204 * MFI frame flags
201 205 */
202 206 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
203 207 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
204 208 #define MFI_FRAME_SGL32 0x0000
205 209 #define MFI_FRAME_SGL64 0x0002
206 210 #define MFI_FRAME_SENSE32 0x0000
207 211 #define MFI_FRAME_SENSE64 0x0004
208 212 #define MFI_FRAME_DIR_NONE 0x0000
209 213 #define MFI_FRAME_DIR_WRITE 0x0008
210 214 #define MFI_FRAME_DIR_READ 0x0010
211 215 #define MFI_FRAME_DIR_BOTH 0x0018
212 216 #define MFI_FRAME_IEEE 0x0020
213 217
214 218 /*
215 219 * Definition for cmd_status
216 220 */
217 221 #define MFI_CMD_STATUS_POLL_MODE 0xFF
218 222 #define MFI_CMD_STATUS_SYNC_MODE 0xFF
219 223
220 224 /*
221 225 * MFI command opcodes
222 226 */
223 227 #define MFI_CMD_OP_INIT 0x00
224 228 #define MFI_CMD_OP_LD_READ 0x01
225 229 #define MFI_CMD_OP_LD_WRITE 0x02
226 230 #define MFI_CMD_OP_LD_SCSI 0x03
227 231 #define MFI_CMD_OP_PD_SCSI 0x04
228 232 #define MFI_CMD_OP_DCMD 0x05
229 233 #define MFI_CMD_OP_ABORT 0x06
230 234 #define MFI_CMD_OP_SMP 0x07
231 235 #define MFI_CMD_OP_STP 0x08
232 236
233 237 #define MR_DCMD_CTRL_GET_INFO 0x01010000
234 238
235 239 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
236 240 #define MR_FLUSH_CTRL_CACHE 0x01
237 241 #define MR_FLUSH_DISK_CACHE 0x02
238 242
239 243 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
240 244 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01
241 245
242 246 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
243 247 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
244 248 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
245 249 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
246 250
247 251 /*
248 252 * Solaris Specific MAX values
249 253 */
250 254 #define MAX_SGL 24
251 255
252 256 /*
253 257 * MFI command completion codes
254 258 */
255 259 enum MFI_STAT {
256 260 MFI_STAT_OK = 0x00,
257 261 MFI_STAT_INVALID_CMD = 0x01,
258 262 MFI_STAT_INVALID_DCMD = 0x02,
259 263 MFI_STAT_INVALID_PARAMETER = 0x03,
260 264 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
261 265 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
262 266 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
263 267 MFI_STAT_APP_IN_USE = 0x07,
264 268 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
265 269 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
266 270 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
267 271 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
268 272 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
269 273 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
270 274 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
271 275 MFI_STAT_FLASH_BUSY = 0x0f,
272 276 MFI_STAT_FLASH_ERROR = 0x10,
273 277 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
274 278 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
275 279 MFI_STAT_FLASH_NOT_OPEN = 0x13,
276 280 MFI_STAT_FLASH_NOT_STARTED = 0x14,
277 281 MFI_STAT_FLUSH_FAILED = 0x15,
278 282 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
279 283 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
280 284 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
281 285 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
282 286 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
283 287 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
284 288 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
285 289 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
286 290 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
287 291 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
288 292 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
289 293 MFI_STAT_MFC_HW_ERROR = 0x21,
290 294 MFI_STAT_NO_HW_PRESENT = 0x22,
291 295 MFI_STAT_NOT_FOUND = 0x23,
292 296 MFI_STAT_NOT_IN_ENCL = 0x24,
293 297 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
294 298 MFI_STAT_PD_TYPE_WRONG = 0x26,
295 299 MFI_STAT_PR_DISABLED = 0x27,
296 300 MFI_STAT_ROW_INDEX_INVALID = 0x28,
297 301 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
298 302 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
299 303 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
300 304 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
301 305 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
302 306 MFI_STAT_SCSI_IO_FAILED = 0x2e,
303 307 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
304 308 MFI_STAT_SHUTDOWN_FAILED = 0x30,
305 309 MFI_STAT_TIME_NOT_SET = 0x31,
306 310 MFI_STAT_WRONG_STATE = 0x32,
307 311 MFI_STAT_LD_OFFLINE = 0x33,
308 312 MFI_STAT_INVALID_STATUS = 0xFF
309 313 };
310 314
311 315 enum MR_EVT_CLASS {
312 316 MR_EVT_CLASS_DEBUG = -2,
313 317 MR_EVT_CLASS_PROGRESS = -1,
314 318 MR_EVT_CLASS_INFO = 0,
315 319 MR_EVT_CLASS_WARNING = 1,
316 320 MR_EVT_CLASS_CRITICAL = 2,
317 321 MR_EVT_CLASS_FATAL = 3,
318 322 MR_EVT_CLASS_DEAD = 4
319 323 };
320 324
321 325 enum MR_EVT_LOCALE {
322 326 MR_EVT_LOCALE_LD = 0x0001,
323 327 MR_EVT_LOCALE_PD = 0x0002,
324 328 MR_EVT_LOCALE_ENCL = 0x0004,
325 329 MR_EVT_LOCALE_BBU = 0x0008,
326 330 MR_EVT_LOCALE_SAS = 0x0010,
327 331 MR_EVT_LOCALE_CTRL = 0x0020,
328 332 MR_EVT_LOCALE_CONFIG = 0x0040,
329 333 MR_EVT_LOCALE_CLUSTER = 0x0080,
330 334 MR_EVT_LOCALE_ALL = 0xffff
331 335 };
332 336
333 337 enum MR_EVT_ARGS {
334 338 MR_EVT_ARGS_NONE,
335 339 MR_EVT_ARGS_CDB_SENSE,
336 340 MR_EVT_ARGS_LD,
337 341 MR_EVT_ARGS_LD_COUNT,
338 342 MR_EVT_ARGS_LD_LBA,
339 343 MR_EVT_ARGS_LD_OWNER,
340 344 MR_EVT_ARGS_LD_LBA_PD_LBA,
341 345 MR_EVT_ARGS_LD_PROG,
342 346 MR_EVT_ARGS_LD_STATE,
343 347 MR_EVT_ARGS_LD_STRIP,
344 348 MR_EVT_ARGS_PD,
345 349 MR_EVT_ARGS_PD_ERR,
346 350 MR_EVT_ARGS_PD_LBA,
347 351 MR_EVT_ARGS_PD_LBA_LD,
348 352 MR_EVT_ARGS_PD_PROG,
349 353 MR_EVT_ARGS_PD_STATE,
350 354 MR_EVT_ARGS_PCI,
351 355 MR_EVT_ARGS_RATE,
352 356 MR_EVT_ARGS_STR,
353 357 MR_EVT_ARGS_TIME,
354 358 MR_EVT_ARGS_ECC
355 359 };
356 360
357 361 #define MR_EVT_CFG_CLEARED 0x0004
358 362 #define MR_EVT_LD_CREATED 0x008a
359 363 #define MR_EVT_LD_DELETED 0x008b
360 364 #define MR_EVT_CFG_FP_CHANGE 0x017B
361 365
362 366 enum LD_STATE {
363 367 LD_OFFLINE = 0,
364 368 LD_PARTIALLY_DEGRADED = 1,
365 369 LD_DEGRADED = 2,
366 370 LD_OPTIMAL = 3,
367 371 LD_INVALID = 0xFF
368 372 };
369 373
370 374 enum MRSAS_EVT {
371 375 MRSAS_EVT_CONFIG_TGT = 0,
372 376 MRSAS_EVT_UNCONFIG_TGT = 1,
373 377 MRSAS_EVT_UNCONFIG_SMP = 2
374 378 };
375 379
376 380 #define DMA_OBJ_ALLOCATED 1
377 381 #define DMA_OBJ_REALLOCATED 2
378 382 #define DMA_OBJ_FREED 3
379 383
380 384 /*
381 385 * dma_obj_t - Our DMA object
382 386 * @param buffer : kernel virtual address
383 387 * @param size : size of the data to be allocated
384 388 * @param acc_handle : access handle
385 389 * @param dma_handle : dma handle
386 390 * @param dma_cookie : scatter-gather list
387 391 * @param dma_attr : dma attributes for this buffer
388 392 *
389 393 * Our DMA object. The caller must initialize the size and dma attributes
390 394 * (dma_attr) fields before allocating the resources.
391 395 */
392 396 typedef struct {
393 397 caddr_t buffer;
394 398 uint32_t size;
395 399 ddi_acc_handle_t acc_handle;
396 400 ddi_dma_handle_t dma_handle;
397 401 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT];
398 402 ddi_dma_attr_t dma_attr;
399 403 uint8_t status;
400 404 uint8_t reserved[3];
401 405 } dma_obj_t;
402 406
403 407 struct mrsas_eventinfo {
404 408 struct mrsas_instance *instance;
405 409 int tgt;
406 410 int lun;
407 411 int event;
408 412 uint64_t wwn;
409 413 };
410 414
411 415 struct mrsas_ld {
412 416 dev_info_t *dip;
413 417 uint8_t lun_type;
414 418 uint8_t flag;
415 419 uint8_t reserved[2];
416 420 };
417 421
418 422
419 423 #ifdef PDSUPPORT
420 424 struct mrsas_tbolt_pd {
421 425 dev_info_t *dip;
422 426 uint8_t lun_type;
423 427 uint8_t dev_id;
424 428 uint8_t flag;
425 429 uint8_t reserved;
426 430 };
427 431 struct mrsas_tbolt_pd_info {
428 432 uint16_t deviceId;
429 433 uint16_t seqNum;
430 434 uint8_t inquiryData[96];
431 435 uint8_t vpdPage83[64];
432 436 uint8_t notSupported;
433 437 uint8_t scsiDevType;
434 438 uint8_t a;
435 439 uint8_t device_speed;
436 440 uint32_t mediaerrcnt;
437 441 uint32_t other;
438 442 uint32_t pred;
439 443 uint32_t lastpred;
440 444 uint16_t fwState;
441 445 uint8_t disabled;
442 446 uint8_t linkspwwd;
443 447 uint32_t ddfType;
444 448 struct {
445 449 uint8_t count;
446 450 uint8_t isPathBroken;
447 451 uint8_t connectorIndex[2];
448 452 uint8_t reserved[4];
449 453 uint64_t sasAddr[2];
450 454 uint8_t reserved2[16];
451 455 } pathInfo;
452 456 };
453 457 #endif
454 458
455 459 typedef struct mrsas_instance {
456 460 uint32_t *producer;
457 461 uint32_t *consumer;
458 462
459 463 uint32_t *reply_queue;
460 464 dma_obj_t mfi_internal_dma_obj;
461 465 uint16_t adapterresetinprogress;
462 466 uint16_t deadadapter;
463 467 /* ThunderBolt (TB) specific */
464 468 dma_obj_t mpi2_frame_pool_dma_obj;
465 469 dma_obj_t request_desc_dma_obj;
466 470 dma_obj_t reply_desc_dma_obj;
467 471 dma_obj_t ld_map_obj[2];
468 472
469 473 uint8_t init_id;
470 474 uint8_t flag_ieee;
471 475 uint8_t disable_online_ctrl_reset;
472 476 uint8_t fw_fault_count_after_ocr;
473 477
474 478 uint16_t max_num_sge;
475 479 uint16_t max_fw_cmds;
476 480 uint32_t max_sectors_per_req;
477 481
478 482 struct mrsas_cmd **cmd_list;
479 483
480 484 mlist_t cmd_pool_list;
481 485 kmutex_t cmd_pool_mtx;
482 486 kmutex_t sync_map_mtx;
483 487
484 488 mlist_t app_cmd_pool_list;
485 489 kmutex_t app_cmd_pool_mtx;
486 490 mlist_t cmd_app_pool_list;
487 491 kmutex_t cmd_app_pool_mtx;
488 492
489 493
490 494 mlist_t cmd_pend_list;
491 495 kmutex_t cmd_pend_mtx;
492 496
493 497 dma_obj_t mfi_evt_detail_obj;
494 498 struct mrsas_cmd *aen_cmd;
495 499
496 500 uint32_t aen_seq_num;
497 501 uint32_t aen_class_locale_word;
498 502
499 503 scsi_hba_tran_t *tran;
500 504
501 505 kcondvar_t int_cmd_cv;
502 506 kmutex_t int_cmd_mtx;
503 507
504 508 kcondvar_t aen_cmd_cv;
505 509 kmutex_t aen_cmd_mtx;
506 510
507 511 kcondvar_t abort_cmd_cv;
508 512 kmutex_t abort_cmd_mtx;
509 513
510 514 kmutex_t reg_write_mtx;
511 515 kmutex_t chip_mtx;
512 516
513 517 dev_info_t *dip;
514 518 ddi_acc_handle_t pci_handle;
515 519
516 520 timeout_id_t timeout_id;
517 521 uint32_t unique_id;
518 522 uint16_t fw_outstanding;
519 523 caddr_t regmap;
520 524 ddi_acc_handle_t regmap_handle;
521 525 uint8_t isr_level;
522 526 ddi_iblock_cookie_t iblock_cookie;
523 527 ddi_iblock_cookie_t soft_iblock_cookie;
524 528 ddi_softintr_t soft_intr_id;
525 529 uint8_t softint_running;
526 530 uint8_t tbolt_softint_running;
527 531 kmutex_t completed_pool_mtx;
528 532 mlist_t completed_pool_list;
529 533
530 534 caddr_t internal_buf;
531 535 uint32_t internal_buf_dmac_add;
532 536 uint32_t internal_buf_size;
533 537
534 538 uint16_t vendor_id;
535 539 uint16_t device_id;
536 540 uint16_t subsysvid;
537 541 uint16_t subsysid;
538 542 int instance;
539 543 int baseaddress;
540 544 char iocnode[16];
541 545
542 546 int fm_capabilities;
543 547 /*
544 548 * Driver resources unroll flags. The flag is set for resources that
545 549 * are needed to be free'd at detach() time.
546 550 */
547 551 struct _unroll {
548 552 uint8_t softs; /* The software state was allocated. */
549 553 uint8_t regs; /* Controller registers mapped. */
550 554 uint8_t intr; /* Interrupt handler added. */
551 555 uint8_t reqs; /* Request structs allocated. */
552 556 uint8_t mutexs; /* Mutex's allocated. */
553 557 uint8_t taskq; /* Task q's created. */
554 558 uint8_t tran; /* Tran struct allocated */
555 559 uint8_t tranSetup; /* Tran attached to the ddi. */
556 560 uint8_t devctl; /* Device nodes for cfgadm created. */
557 561 uint8_t scsictl; /* Device nodes for cfgadm created. */
558 562 uint8_t ioctl; /* Device nodes for ioctl's created. */
559 563 uint8_t timer; /* Timer started. */
560 564 uint8_t aenPend; /* AEN cmd pending f/w. */
561 565 uint8_t mapUpdate_pend; /* LD MAP update cmd pending f/w. */
562 566 uint8_t soft_isr; /* Soft interrupt handler allocated. */
563 567 uint8_t ldlist_buff; /* Logical disk list allocated. */
564 568 uint8_t pdlist_buff; /* Physical disk list allocated. */
565 569 uint8_t syncCmd; /* Sync map command allocated. */
566 570 uint8_t verBuff; /* 2108 MFI buffer allocated. */
567 571 uint8_t alloc_space_mfi; /* Allocated space for 2108 MFI. */
568 572 uint8_t alloc_space_mpi2; /* Allocated space for 2208 MPI2. */
569 573 } unroll;
570 574
571 575
572 576 /* function template pointer */
573 577 struct mrsas_function_template *func_ptr;
574 578
575 579
576 580 /* MSI interrupts specific */
577 581 ddi_intr_handle_t *intr_htable; /* Interrupt handle array */
578 582 size_t intr_htable_size; /* Int. handle array size */
579 583 int intr_type;
580 584 int intr_cnt;
581 585 uint_t intr_pri;
582 586 int intr_cap;
583 587
584 588 ddi_taskq_t *taskq;
585 589 struct mrsas_ld *mr_ld_list;
586 590 kmutex_t config_dev_mtx;
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587 591 /* ThunderBolt (TB) specific */
588 592 ddi_softintr_t tbolt_soft_intr_id;
589 593
590 594 #ifdef PDSUPPORT
591 595 uint32_t mr_tbolt_pd_max;
592 596 struct mrsas_tbolt_pd *mr_tbolt_pd_list;
593 597 #endif
594 598
595 599 uint8_t fast_path_io;
596 600
597 - uint16_t tbolt;
601 + uint8_t skinny;
602 + uint8_t tbolt;
598 603 uint16_t reply_read_index;
599 604 uint16_t reply_size; /* Single Reply struct size */
600 605 uint16_t raid_io_msg_size; /* Single message size */
601 606 uint32_t io_request_frames_phy;
602 607 uint8_t *io_request_frames;
603 608 /* Virtual address of request desc frame pool */
604 609 MRSAS_REQUEST_DESCRIPTOR_UNION *request_message_pool;
605 610 /* Physical address of request desc frame pool */
606 611 uint32_t request_message_pool_phy;
607 612 /* Virtual address of reply Frame */
608 613 MPI2_REPLY_DESCRIPTORS_UNION *reply_frame_pool;
609 614 /* Physical address of reply Frame */
610 615 uint32_t reply_frame_pool_phy;
611 616 uint8_t *reply_pool_limit; /* Last reply frame address */
612 617 /* Physical address of Last reply frame */
613 618 uint32_t reply_pool_limit_phy;
614 619 uint32_t reply_q_depth; /* Reply Queue Depth */
615 620 uint8_t max_sge_in_main_msg;
616 621 uint8_t max_sge_in_chain;
617 622 uint8_t chain_offset_io_req;
618 623 uint8_t chain_offset_mpt_msg;
619 624 MR_FW_RAID_MAP_ALL *ld_map[2];
620 625 uint32_t ld_map_phy[2];
621 626 uint32_t size_map_info;
622 627 uint64_t map_id;
623 628 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
624 629 struct mrsas_cmd *map_update_cmd;
625 630 uint32_t SyncRequired;
626 631 kmutex_t ocr_flags_mtx;
627 632 dma_obj_t drv_ver_dma_obj;
628 633 } mrsas_t;
629 634
630 635
631 636 /*
632 637 * Function templates for various controller specific functions
633 638 */
634 639 struct mrsas_function_template {
635 640 uint32_t (*read_fw_status_reg)(struct mrsas_instance *);
636 641 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *);
637 642 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
638 643 struct mrsas_cmd *);
639 644 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
640 645 struct mrsas_cmd *);
641 646 void (*enable_intr)(struct mrsas_instance *);
642 647 void (*disable_intr)(struct mrsas_instance *);
643 648 int (*intr_ack)(struct mrsas_instance *);
644 649 int (*init_adapter)(struct mrsas_instance *);
645 650 /* int (*reset_adapter)(struct mrsas_instance *); */
646 651 };
647 652
648 653 /*
649 654 * ### Helper routines ###
650 655 */
651 656
652 657 /*
653 658 * con_log() - console log routine
654 659 * @param level : indicates the severity of the message.
655 660 * @fparam mt : format string
656 661 *
657 662 * con_log displays the error messages on the console based on the current
658 663 * debug level. Also it attaches the appropriate kernel severity level with
659 664 * the message.
660 665 *
661 666 *
662 667 * console messages debug levels
663 668 */
664 669 #define CL_NONE 0 /* No debug information */
665 670 #define CL_ANN 1 /* print unconditionally, announcements */
666 671 #define CL_ANN1 2 /* No-op */
667 672 #define CL_DLEVEL1 3 /* debug level 1, informative */
668 673 #define CL_DLEVEL2 4 /* debug level 2, verbose */
669 674 #define CL_DLEVEL3 5 /* debug level 3, very verbose */
670 675
671 676 #ifdef __SUNPRO_C
672 677 #define __func__ ""
673 678 #endif
674 679
675 680 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
676 681
677 682 /*
678 683 * ### SCSA definitions ###
679 684 */
680 685 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target)
681 686 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun)
682 687 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran)
683 688 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
684 689
685 690 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private)
686 691 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap))
687 692
688 693 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private)
689 694 #define CMD2PKT(sp) ((sp)->cmd_pkt)
690 695 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request))
691 696
692 697 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address)
693 698 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran)
694 699 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd)))
695 700
696 701 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */
697 702 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */
698 703 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */
699 704
700 705 /*
701 706 * ### Data structures for ioctl inteface and internal commands ###
702 707 */
703 708
704 709 /*
705 710 * Data direction flags
706 711 */
707 712 #define UIOC_RD 0x00001
708 713 #define UIOC_WR 0x00002
709 714
710 715 #define SCP2HOST(scp) (scp)->device->host /* to host */
711 716 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */
712 717 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */
713 718 #define SCP2TARGET(scp) (scp)->device->id /* to target */
714 719 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */
715 720
716 721 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
717 722 #define SCP2ADAPTER(scp) \
718 723 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
719 724
720 725 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \
721 726 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0
722 727 #define MRDRV_IS_LOGICAL(ap) \
723 728 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0
724 729 #define MAP_DEVICE_ID(instance, ap) \
725 730 (ap->a_target)
726 731
727 732 #define HIGH_LEVEL_INTR 1
728 733 #define NORMAL_LEVEL_INTR 0
729 734
730 735 #define IO_TIMEOUT_VAL 0
731 736 #define IO_RETRY_COUNT 3
732 737 #define MAX_FW_RESET_COUNT 3
733 738 /*
734 739 * scsa_cmd - Per-command mr private data
735 740 * @param cmd_dmahandle : dma handle
736 741 * @param cmd_dmacookies : current dma cookies
737 742 * @param cmd_pkt : scsi_pkt reference
738 743 * @param cmd_dmacount : dma count
739 744 * @param cmd_cookie : next cookie
740 745 * @param cmd_ncookies : cookies per window
741 746 * @param cmd_cookiecnt : cookies per sub-win
742 747 * @param cmd_nwin : number of dma windows
743 748 * @param cmd_curwin : current dma window
744 749 * @param cmd_dma_offset : current window offset
745 750 * @param cmd_dma_len : current window length
746 751 * @param cmd_flags : private flags
747 752 * @param cmd_cdblen : length of cdb
748 753 * @param cmd_scblen : length of scb
749 754 * @param cmd_buf : command buffer
750 755 * @param channel : channel for scsi sub-system
751 756 * @param target : target for scsi sub-system
752 757 * @param lun : LUN for scsi sub-system
753 758 *
754 759 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E)
755 760 * - Pointed to by pkt_ha_private field in scsi_pkt
756 761 */
757 762 struct scsa_cmd {
758 763 ddi_dma_handle_t cmd_dmahandle;
759 764 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT];
760 765 struct scsi_pkt *cmd_pkt;
761 766 ulong_t cmd_dmacount;
762 767 uint_t cmd_cookie;
763 768 uint_t cmd_ncookies;
764 769 uint_t cmd_cookiecnt;
765 770 uint_t cmd_nwin;
766 771 uint_t cmd_curwin;
767 772 off_t cmd_dma_offset;
768 773 ulong_t cmd_dma_len;
769 774 ulong_t cmd_flags;
770 775 uint_t cmd_cdblen;
771 776 uint_t cmd_scblen;
772 777 struct buf *cmd_buf;
773 778 ushort_t device_id;
774 779 uchar_t islogical;
775 780 uchar_t lun;
776 781 struct mrsas_device *mrsas_dev;
777 782 };
778 783
779 784
780 785 struct mrsas_cmd {
781 786 /*
782 787 * ThunderBolt(TB) We would be needing to have a placeholder
783 788 * for RAID_MSG_IO_REQUEST inside this structure. We are
784 789 * supposed to embed the mr_frame inside the RAID_MSG and post
785 790 * it down to the firmware.
786 791 */
787 792 union mrsas_frame *frame;
788 793 uint32_t frame_phys_addr;
789 794 uint8_t *sense;
790 795 uint8_t *sense1;
791 796 uint32_t sense_phys_addr;
792 797 uint32_t sense_phys_addr1;
793 798 dma_obj_t frame_dma_obj;
794 799 uint8_t frame_dma_obj_status;
795 800 uint32_t index;
796 801 uint8_t sync_cmd;
797 802 uint8_t cmd_status;
798 803 uint16_t abort_aen;
799 804 mlist_t list;
800 805 uint32_t frame_count;
801 806 struct scsa_cmd *cmd;
802 807 struct scsi_pkt *pkt;
803 808 Mpi2RaidSCSIIORequest_t *scsi_io_request;
804 809 Mpi2SGEIOUnion_t *sgl;
805 810 uint32_t sgl_phys_addr;
806 811 uint32_t scsi_io_request_phys_addr;
807 812 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
808 813 uint16_t SMID;
809 814 uint16_t retry_count_for_ocr;
810 815 uint16_t drv_pkt_time;
811 816 uint16_t load_balance_flag;
812 817
813 818 };
814 819
815 820 #define MAX_MGMT_ADAPTERS 1024
816 821 #define IOC_SIGNATURE "MR-SAS"
817 822
818 823 #define IOC_CMD_FIRMWARE 0x0
819 824 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000
820 825 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
821 826 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
822 827 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300
823 828
824 829
825 830 #define MRSAS_MAX_SENSE_LENGTH 32
826 831
827 832 struct mrsas_mgmt_info {
828 833
829 834 uint16_t count;
830 835 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS];
831 836 uint16_t map[MAX_MGMT_ADAPTERS];
832 837 int max_index;
833 838 };
834 839
835 840
836 841 #pragma pack(1)
837 842 /*
838 843 * SAS controller properties
839 844 */
840 845 struct mrsas_ctrl_prop {
841 846 uint16_t seq_num;
842 847 uint16_t pred_fail_poll_interval;
843 848 uint16_t intr_throttle_count;
844 849 uint16_t intr_throttle_timeouts;
845 850
846 851 uint8_t rebuild_rate;
847 852 uint8_t patrol_read_rate;
848 853 uint8_t bgi_rate;
849 854 uint8_t cc_rate;
850 855 uint8_t recon_rate;
851 856
852 857 uint8_t cache_flush_interval;
853 858
854 859 uint8_t spinup_drv_count;
855 860 uint8_t spinup_delay;
856 861
857 862 uint8_t cluster_enable;
858 863 uint8_t coercion_mode;
859 864 uint8_t alarm_enable;
860 865
861 866 uint8_t reserved_1[13];
862 867 uint32_t on_off_properties;
863 868 uint8_t reserved_4[28];
864 869 };
865 870
866 871
867 872 /*
868 873 * SAS controller information
869 874 */
870 875 struct mrsas_ctrl_info {
871 876 /* PCI device information */
872 877 struct {
873 878 uint16_t vendor_id;
874 879 uint16_t device_id;
875 880 uint16_t sub_vendor_id;
876 881 uint16_t sub_device_id;
877 882 uint8_t reserved[24];
878 883 } pci;
879 884
880 885 /* Host interface information */
881 886 struct {
882 887 uint8_t PCIX : 1;
883 888 uint8_t PCIE : 1;
884 889 uint8_t iSCSI : 1;
885 890 uint8_t SAS_3G : 1;
886 891 uint8_t reserved_0 : 4;
887 892 uint8_t reserved_1[6];
888 893 uint8_t port_count;
889 894 uint64_t port_addr[8];
890 895 } host_interface;
891 896
892 897 /* Device (backend) interface information */
893 898 struct {
894 899 uint8_t SPI : 1;
895 900 uint8_t SAS_3G : 1;
896 901 uint8_t SATA_1_5G : 1;
897 902 uint8_t SATA_3G : 1;
898 903 uint8_t reserved_0 : 4;
899 904 uint8_t reserved_1[6];
900 905 uint8_t port_count;
901 906 uint64_t port_addr[8];
902 907 } device_interface;
903 908
904 909 /* List of components residing in flash. All str are null terminated */
905 910 uint32_t image_check_word;
906 911 uint32_t image_component_count;
907 912
908 913 struct {
909 914 char name[8];
910 915 char version[32];
911 916 char build_date[16];
912 917 char built_time[16];
913 918 } image_component[8];
914 919
915 920 /*
916 921 * List of flash components that have been flashed on the card, but
917 922 * are not in use, pending reset of the adapter. This list will be
918 923 * empty if a flash operation has not occurred. All stings are null
919 924 * terminated
920 925 */
921 926 uint32_t pending_image_component_count;
922 927
923 928 struct {
924 929 char name[8];
925 930 char version[32];
926 931 char build_date[16];
927 932 char build_time[16];
928 933 } pending_image_component[8];
929 934
930 935 uint8_t max_arms;
931 936 uint8_t max_spans;
932 937 uint8_t max_arrays;
933 938 uint8_t max_lds;
934 939
935 940 char product_name[80];
936 941 char serial_no[32];
937 942
938 943 /*
939 944 * Other physical/controller/operation information. Indicates the
940 945 * presence of the hardware
941 946 */
942 947 struct {
943 948 uint32_t bbu : 1;
944 949 uint32_t alarm : 1;
945 950 uint32_t nvram : 1;
946 951 uint32_t uart : 1;
947 952 uint32_t reserved : 28;
948 953 } hw_present;
949 954
950 955 uint32_t current_fw_time;
951 956
952 957 /* Maximum data transfer sizes */
953 958 uint16_t max_concurrent_cmds;
954 959 uint16_t max_sge_count;
955 960 uint32_t max_request_size;
956 961
957 962 /* Logical and physical device counts */
958 963 uint16_t ld_present_count;
959 964 uint16_t ld_degraded_count;
960 965 uint16_t ld_offline_count;
961 966
962 967 uint16_t pd_present_count;
963 968 uint16_t pd_disk_present_count;
964 969 uint16_t pd_disk_pred_failure_count;
965 970 uint16_t pd_disk_failed_count;
966 971
967 972 /* Memory size information */
968 973 uint16_t nvram_size;
969 974 uint16_t memory_size;
970 975 uint16_t flash_size;
971 976
972 977 /* Error counters */
973 978 uint16_t mem_correctable_error_count;
974 979 uint16_t mem_uncorrectable_error_count;
975 980
976 981 /* Cluster information */
977 982 uint8_t cluster_permitted;
978 983 uint8_t cluster_active;
979 984 uint8_t reserved_1[2];
980 985
981 986 /* Controller capabilities structures */
982 987 struct {
983 988 uint32_t raid_level_0 : 1;
984 989 uint32_t raid_level_1 : 1;
985 990 uint32_t raid_level_5 : 1;
986 991 uint32_t raid_level_1E : 1;
987 992 uint32_t reserved : 28;
988 993 } raid_levels;
989 994
990 995 struct {
991 996 uint32_t rbld_rate : 1;
992 997 uint32_t cc_rate : 1;
993 998 uint32_t bgi_rate : 1;
994 999 uint32_t recon_rate : 1;
995 1000 uint32_t patrol_rate : 1;
996 1001 uint32_t alarm_control : 1;
997 1002 uint32_t cluster_supported : 1;
998 1003 uint32_t bbu : 1;
999 1004 uint32_t spanning_allowed : 1;
1000 1005 uint32_t dedicated_hotspares : 1;
1001 1006 uint32_t revertible_hotspares : 1;
1002 1007 uint32_t foreign_config_import : 1;
1003 1008 uint32_t self_diagnostic : 1;
1004 1009 uint32_t reserved : 19;
1005 1010 } adapter_operations;
1006 1011
1007 1012 struct {
1008 1013 uint32_t read_policy : 1;
1009 1014 uint32_t write_policy : 1;
1010 1015 uint32_t io_policy : 1;
1011 1016 uint32_t access_policy : 1;
1012 1017 uint32_t reserved : 28;
1013 1018 } ld_operations;
1014 1019
1015 1020 struct {
1016 1021 uint8_t min;
1017 1022 uint8_t max;
1018 1023 uint8_t reserved[2];
1019 1024 } stripe_size_operations;
1020 1025
1021 1026 struct {
1022 1027 uint32_t force_online : 1;
1023 1028 uint32_t force_offline : 1;
1024 1029 uint32_t force_rebuild : 1;
1025 1030 uint32_t reserved : 29;
1026 1031 } pd_operations;
1027 1032
1028 1033 struct {
1029 1034 uint32_t ctrl_supports_sas : 1;
1030 1035 uint32_t ctrl_supports_sata : 1;
1031 1036 uint32_t allow_mix_in_encl : 1;
1032 1037 uint32_t allow_mix_in_ld : 1;
1033 1038 uint32_t allow_sata_in_cluster : 1;
1034 1039 uint32_t reserved : 27;
1035 1040 } pd_mix_support;
1036 1041
1037 1042 /* Include the controller properties (changeable items) */
1038 1043 uint8_t reserved_2[12];
1039 1044 struct mrsas_ctrl_prop properties;
1040 1045
1041 1046 uint8_t pad[0x800 - 0x640];
1042 1047 };
1043 1048
1044 1049 /*
1045 1050 * ==================================
1046 1051 * MegaRAID SAS2.0 driver definitions
1047 1052 * ==================================
1048 1053 */
1049 1054 #define MRDRV_MAX_NUM_CMD 1024
1050 1055
1051 1056 #define MRDRV_MAX_PD_CHANNELS 2
1052 1057 #define MRDRV_MAX_LD_CHANNELS 2
1053 1058 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \
1054 1059 MRDRV_MAX_LD_CHANNELS)
1055 1060 #define MRDRV_MAX_DEV_PER_CHANNEL 128
1056 1061 #define MRDRV_DEFAULT_INIT_ID -1
1057 1062 #define MRDRV_MAX_CMD_PER_LUN 1000
1058 1063 #define MRDRV_MAX_LUN 1
1059 1064 #define MRDRV_MAX_LD 64
1060 1065
1061 1066 #define MRDRV_RESET_WAIT_TIME 300
1062 1067 #define MRDRV_RESET_NOTICE_INTERVAL 5
1063 1068
1064 1069 #define MRSAS_IOCTL_CMD 0
1065 1070
1066 1071 #define MRDRV_TGT_VALID 1
1067 1072
1068 1073 /*
1069 1074 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1070 1075 * SGLs based on the size of dma_addr_t
1071 1076 */
1072 1077 #define IS_DMA64 (sizeof (dma_addr_t) == 8)
1073 1078
1074 1079 #define RESERVED0_REGISTER 0x00 /* XScale */
1075 1080 #define IB_MSG_0_OFF 0x10 /* XScale */
1076 1081 #define OB_MSG_0_OFF 0x18 /* XScale */
1077 1082 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */
1078 1083 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */
1079 1084 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */
1080 1085 #define IB_QPORT_OFF 0x40 /* XScale & ROC */
1081 1086 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */
1082 1087 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */
1083 1088 #define OB_INTR_MASK 0xFFFFFFFF
1084 1089 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF
1085 1090 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1086 1091 #define OB_SCRATCH_PAD_2_OFF 0xB4
1087 1092 #define WRITE_TBOLT_SEQ_OFF 0x00000004
1088 1093 #define DIAG_TBOLT_RESET_ADAPTER 0x00000004
1089 1094 #define HOST_TBOLT_DIAG_OFF 0x00000008
1090 1095 #define RESET_TBOLT_STATUS_OFF 0x000003C3
1091 1096 #define WRITE_SEQ_OFF 0x000000FC
1092 1097 #define HOST_DIAG_OFF 0x000000F8
1093 1098 #define DIAG_RESET_ADAPTER 0x00000004
1094 1099 #define DIAG_WRITE_ENABLE 0x00000080
1095 1100 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1096 1101
1097 1102 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \
1098 1103 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v))
1099 1104
1100 1105 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \
1101 1106 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF))
1102 1107
1103 1108 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \
1104 1109 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v))
1105 1110
1106 1111 #define IB_LOW_QPORT 0xC0
1107 1112 #define IB_HIGH_QPORT 0xC4
1108 1113 #define OB_DOORBELL_REGISTER 0x9C /* 1078 implementation */
1109 1114
1110 1115 /*
1111 1116 * All MFI register set macros accept mrsas_register_set*
1112 1117 */
1113 1118 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \
1114 1119 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
1115 1120
1116 1121 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \
1117 1122 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
1118 1123
1119 1124 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \
1120 1125 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
1121 1126
1122 1127 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \
1123 1128 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
1124 1129
1125 1130 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \
1126 1131 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
1127 1132
1128 1133 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \
1129 1134 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
1130 1135
1131 1136 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \
1132 1137 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
1133 1138
1134 1139 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \
1135 1140 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
1136 1141
1137 1142 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1138 1143 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
1139 1144
1140 1145 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
1141 1146 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
1142 1147 (v))
1143 1148
1144 1149 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \
1145 1150 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
1146 1151
1147 1152 /* Thunderbolt specific registers */
1148 1153 #define RD_OB_SCRATCH_PAD_2(instance) ddi_get32((instance)->regmap_handle, \
1149 1154 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_2_OFF))
1150 1155
1151 1156 #define WR_TBOLT_IB_WRITE_SEQ(v, instance) \
1152 1157 ddi_put32((instance)->regmap_handle, \
1153 1158 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_TBOLT_SEQ_OFF), (v))
1154 1159
1155 1160 #define RD_TBOLT_HOST_DIAG(instance) ddi_get32((instance)->regmap_handle, \
1156 1161 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF))
1157 1162
1158 1163 #define WR_TBOLT_HOST_DIAG(v, instance) ddi_put32((instance)->regmap_handle, \
1159 1164 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF), (v))
1160 1165
1161 1166 #define RD_TBOLT_RESET_STAT(instance) ddi_get32((instance)->regmap_handle, \
1162 1167 (uint32_t *)((uintptr_t)(instance)->regmap + RESET_TBOLT_STATUS_OFF))
1163 1168
1164 1169
1165 1170 #define WR_MPI2_REPLY_POST_INDEX(v, instance)\
1166 1171 ddi_put32((instance)->regmap_handle,\
1167 1172 (uint32_t *)\
1168 1173 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET),\
1169 1174 (v))
1170 1175
1171 1176
1172 1177 #define RD_MPI2_REPLY_POST_INDEX(instance)\
1173 1178 ddi_get32((instance)->regmap_handle,\
1174 1179 (uint32_t *)\
1175 1180 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET))
1176 1181
1177 1182 #define WR_IB_LOW_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1178 1183 (uint32_t *)((uintptr_t)(instance)->regmap + IB_LOW_QPORT), (v))
1179 1184
1180 1185 #define WR_IB_HIGH_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1181 1186 (uint32_t *)((uintptr_t)(instance)->regmap + IB_HIGH_QPORT), (v))
1182 1187
1183 1188 #define WR_OB_DOORBELL_REGISTER_CLEAR(v, instance)\
1184 1189 ddi_put32((instance)->regmap_handle,\
1185 1190 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_REGISTER), \
1186 1191 (v))
1187 1192
1188 1193 #define WR_RESERVED0_REGISTER(v, instance) ddi_put32((instance)->regmap_handle,\
1189 1194 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER), \
1190 1195 (v))
1191 1196
1192 1197 #define RD_RESERVED0_REGISTER(instance) ddi_get32((instance)->regmap_handle, \
1193 1198 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER))
1194 1199
1195 1200
1196 1201
1197 1202 /*
1198 1203 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
1199 1204 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
1200 1205 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
1201 1206 */
1202 1207 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1203 1208
1204 1209 /*
1205 1210 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also
1206 1211 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
1207 1212 * been set in this flag along with bit 1.
1208 1213 */
1209 1214 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001
1210 1215 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005
1211 1216
1212 1217 /* Fusion interrupt mask */
1213 1218 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008)
1214 1219
1215 1220 #define MFI_POLL_TIMEOUT_SECS 60
1216 1221
1217 1222 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \
1218 1223 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
1219 1224 #define MFI_DISABLE_INTR(instance) \
1220 1225 { \
1221 1226 uint32_t disable = 1; \
1222 1227 uint32_t mask = ddi_get32((instance)->regmap_handle, \
1223 1228 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
1224 1229 mask &= ~disable; \
1225 1230 ddi_put32((instance)->regmap_handle, (uint32_t *) \
1226 1231 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \
1227 1232 }
1228 1233
1229 1234 /* By default, the firmware programs for 8 Kbytes of memory */
1230 1235 #define DEFAULT_MFI_MEM_SZ 8192
1231 1236 #define MINIMUM_MFI_MEM_SZ 4096
1232 1237
1233 1238 /* DCMD Message Frame MAILBOX0-11 */
1234 1239 #define DCMD_MBOX_SZ 12
1235 1240
1236 1241 /*
1237 1242 * on_off_property of mrsas_ctrl_prop
1238 1243 * bit0-9, 11-31 are reserved
1239 1244 */
1240 1245 #define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */
1241 1246
1242 1247 struct mrsas_register_set {
1243 1248 uint32_t reserved_0[4]; /* 0000h */
1244 1249
1245 1250 uint32_t inbound_msg_0; /* 0010h */
1246 1251 uint32_t inbound_msg_1; /* 0014h */
1247 1252 uint32_t outbound_msg_0; /* 0018h */
1248 1253 uint32_t outbound_msg_1; /* 001Ch */
1249 1254
1250 1255 uint32_t inbound_doorbell; /* 0020h */
1251 1256 uint32_t inbound_intr_status; /* 0024h */
1252 1257 uint32_t inbound_intr_mask; /* 0028h */
1253 1258
1254 1259 uint32_t outbound_doorbell; /* 002Ch */
1255 1260 uint32_t outbound_intr_status; /* 0030h */
1256 1261 uint32_t outbound_intr_mask; /* 0034h */
1257 1262
1258 1263 uint32_t reserved_1[2]; /* 0038h */
1259 1264
1260 1265 uint32_t inbound_queue_port; /* 0040h */
1261 1266 uint32_t outbound_queue_port; /* 0044h */
1262 1267
1263 1268 uint32_t reserved_2[22]; /* 0048h */
1264 1269
1265 1270 uint32_t outbound_doorbell_clear; /* 00A0h */
1266 1271
1267 1272 uint32_t reserved_3[3]; /* 00A4h */
1268 1273
1269 1274 uint32_t outbound_scratch_pad; /* 00B0h */
1270 1275
1271 1276 uint32_t reserved_4[3]; /* 00B4h */
1272 1277
1273 1278 uint32_t inbound_low_queue_port; /* 00C0h */
1274 1279
1275 1280 uint32_t inbound_high_queue_port; /* 00C4h */
1276 1281
1277 1282 uint32_t reserved_5; /* 00C8h */
1278 1283 uint32_t index_registers[820]; /* 00CCh */
1279 1284 };
1280 1285
1281 1286 struct mrsas_sge32 {
1282 1287 uint32_t phys_addr;
1283 1288 uint32_t length;
1284 1289 };
1285 1290
1286 1291 struct mrsas_sge64 {
1287 1292 uint64_t phys_addr;
1288 1293 uint32_t length;
1289 1294 };
1290 1295
1291 1296 struct mrsas_sge_ieee {
1292 1297 uint64_t phys_addr;
1293 1298 uint32_t length;
1294 1299 uint32_t flag;
1295 1300 };
1296 1301
1297 1302 union mrsas_sgl {
1298 1303 struct mrsas_sge32 sge32[1];
1299 1304 struct mrsas_sge64 sge64[1];
1300 1305 struct mrsas_sge_ieee sge_ieee[1];
1301 1306 };
1302 1307
1303 1308 struct mrsas_header {
1304 1309 uint8_t cmd; /* 00h */
1305 1310 uint8_t sense_len; /* 01h */
1306 1311 uint8_t cmd_status; /* 02h */
1307 1312 uint8_t scsi_status; /* 03h */
1308 1313
1309 1314 uint8_t target_id; /* 04h */
1310 1315 uint8_t lun; /* 05h */
1311 1316 uint8_t cdb_len; /* 06h */
1312 1317 uint8_t sge_count; /* 07h */
1313 1318
1314 1319 uint32_t context; /* 08h */
1315 1320 uint8_t req_id; /* 0Ch */
1316 1321 uint8_t msgvector; /* 0Dh */
1317 1322 uint16_t pad_0; /* 0Eh */
1318 1323
1319 1324 uint16_t flags; /* 10h */
1320 1325 uint16_t timeout; /* 12h */
1321 1326 uint32_t data_xferlen; /* 14h */
1322 1327 };
1323 1328
1324 1329 union mrsas_sgl_frame {
1325 1330 struct mrsas_sge32 sge32[8];
1326 1331 struct mrsas_sge64 sge64[5];
1327 1332 };
1328 1333
1329 1334 struct mrsas_init_frame {
1330 1335 uint8_t cmd; /* 00h */
1331 1336 uint8_t reserved_0; /* 01h */
1332 1337 uint8_t cmd_status; /* 02h */
1333 1338
1334 1339 uint8_t reserved_1; /* 03h */
1335 1340 uint32_t reserved_2; /* 04h */
1336 1341
1337 1342 uint32_t context; /* 08h */
1338 1343 uint8_t req_id; /* 0Ch */
1339 1344 uint8_t msgvector; /* 0Dh */
1340 1345 uint16_t pad_0; /* 0Eh */
1341 1346
1342 1347 uint16_t flags; /* 10h */
1343 1348 uint16_t reserved_3; /* 12h */
1344 1349 uint32_t data_xfer_len; /* 14h */
1345 1350
1346 1351 uint32_t queue_info_new_phys_addr_lo; /* 18h */
1347 1352 uint32_t queue_info_new_phys_addr_hi; /* 1Ch */
1348 1353 uint32_t queue_info_old_phys_addr_lo; /* 20h */
1349 1354 uint32_t queue_info_old_phys_addr_hi; /* 24h */
1350 1355 uint64_t driverversion; /* 28h */
1351 1356 uint32_t reserved_4[4]; /* 30h */
1352 1357 };
1353 1358
1354 1359 struct mrsas_init_queue_info {
1355 1360 uint32_t init_flags; /* 00h */
1356 1361 uint32_t reply_queue_entries; /* 04h */
1357 1362
1358 1363 uint32_t reply_queue_start_phys_addr_lo; /* 08h */
1359 1364 uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */
1360 1365 uint32_t producer_index_phys_addr_lo; /* 10h */
1361 1366 uint32_t producer_index_phys_addr_hi; /* 14h */
1362 1367 uint32_t consumer_index_phys_addr_lo; /* 18h */
1363 1368 uint32_t consumer_index_phys_addr_hi; /* 1Ch */
1364 1369 };
1365 1370
1366 1371 struct mrsas_io_frame {
1367 1372 uint8_t cmd; /* 00h */
1368 1373 uint8_t sense_len; /* 01h */
1369 1374 uint8_t cmd_status; /* 02h */
1370 1375 uint8_t scsi_status; /* 03h */
1371 1376
1372 1377 uint8_t target_id; /* 04h */
1373 1378 uint8_t access_byte; /* 05h */
1374 1379 uint8_t reserved_0; /* 06h */
1375 1380 uint8_t sge_count; /* 07h */
1376 1381
1377 1382 uint32_t context; /* 08h */
1378 1383 uint8_t req_id; /* 0Ch */
1379 1384 uint8_t msgvector; /* 0Dh */
1380 1385 uint16_t pad_0; /* 0Eh */
1381 1386
1382 1387 uint16_t flags; /* 10h */
1383 1388 uint16_t timeout; /* 12h */
1384 1389 uint32_t lba_count; /* 14h */
1385 1390
1386 1391 uint32_t sense_buf_phys_addr_lo; /* 18h */
1387 1392 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1388 1393
1389 1394 uint32_t start_lba_lo; /* 20h */
1390 1395 uint32_t start_lba_hi; /* 24h */
1391 1396
1392 1397 union mrsas_sgl sgl; /* 28h */
1393 1398 };
1394 1399
1395 1400 struct mrsas_pthru_frame {
1396 1401 uint8_t cmd; /* 00h */
1397 1402 uint8_t sense_len; /* 01h */
1398 1403 uint8_t cmd_status; /* 02h */
1399 1404 uint8_t scsi_status; /* 03h */
1400 1405
1401 1406 uint8_t target_id; /* 04h */
1402 1407 uint8_t lun; /* 05h */
1403 1408 uint8_t cdb_len; /* 06h */
1404 1409 uint8_t sge_count; /* 07h */
1405 1410
1406 1411 uint32_t context; /* 08h */
1407 1412 uint8_t req_id; /* 0Ch */
1408 1413 uint8_t msgvector; /* 0Dh */
1409 1414 uint16_t pad_0; /* 0Eh */
1410 1415
1411 1416 uint16_t flags; /* 10h */
1412 1417 uint16_t timeout; /* 12h */
1413 1418 uint32_t data_xfer_len; /* 14h */
1414 1419
1415 1420 uint32_t sense_buf_phys_addr_lo; /* 18h */
1416 1421 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1417 1422
1418 1423 uint8_t cdb[16]; /* 20h */
1419 1424 union mrsas_sgl sgl; /* 30h */
1420 1425 };
1421 1426
1422 1427 struct mrsas_dcmd_frame {
1423 1428 uint8_t cmd; /* 00h */
1424 1429 uint8_t reserved_0; /* 01h */
1425 1430 uint8_t cmd_status; /* 02h */
1426 1431 uint8_t reserved_1[4]; /* 03h */
1427 1432 uint8_t sge_count; /* 07h */
1428 1433
1429 1434 uint32_t context; /* 08h */
1430 1435 uint8_t req_id; /* 0Ch */
1431 1436 uint8_t msgvector; /* 0Dh */
1432 1437 uint16_t pad_0; /* 0Eh */
1433 1438
1434 1439 uint16_t flags; /* 10h */
1435 1440 uint16_t timeout; /* 12h */
1436 1441
1437 1442 uint32_t data_xfer_len; /* 14h */
1438 1443 uint32_t opcode; /* 18h */
1439 1444
1440 1445 /* uint8_t mbox[DCMD_MBOX_SZ]; */ /* 1Ch */
1441 1446 union { /* 1Ch */
1442 1447 uint8_t b[DCMD_MBOX_SZ];
1443 1448 uint16_t s[6];
1444 1449 uint32_t w[3];
1445 1450 } mbox;
1446 1451
1447 1452 union mrsas_sgl sgl; /* 28h */
1448 1453 };
1449 1454
1450 1455 struct mrsas_abort_frame {
1451 1456 uint8_t cmd; /* 00h */
1452 1457 uint8_t reserved_0; /* 01h */
1453 1458 uint8_t cmd_status; /* 02h */
1454 1459
1455 1460 uint8_t reserved_1; /* 03h */
1456 1461 uint32_t reserved_2; /* 04h */
1457 1462
1458 1463 uint32_t context; /* 08h */
1459 1464 uint8_t req_id; /* 0Ch */
1460 1465 uint8_t msgvector; /* 0Dh */
1461 1466 uint16_t pad_0; /* 0Eh */
1462 1467
1463 1468 uint16_t flags; /* 10h */
1464 1469 uint16_t reserved_3; /* 12h */
1465 1470 uint32_t reserved_4; /* 14h */
1466 1471
1467 1472 uint32_t abort_context; /* 18h */
1468 1473 uint32_t pad_1; /* 1Ch */
1469 1474
1470 1475 uint32_t abort_mfi_phys_addr_lo; /* 20h */
1471 1476 uint32_t abort_mfi_phys_addr_hi; /* 24h */
1472 1477
1473 1478 uint32_t reserved_5[6]; /* 28h */
1474 1479 };
1475 1480
1476 1481 struct mrsas_smp_frame {
1477 1482 uint8_t cmd; /* 00h */
1478 1483 uint8_t reserved_1; /* 01h */
1479 1484 uint8_t cmd_status; /* 02h */
1480 1485 uint8_t connection_status; /* 03h */
1481 1486
1482 1487 uint8_t reserved_2[3]; /* 04h */
1483 1488 uint8_t sge_count; /* 07h */
1484 1489
1485 1490 uint32_t context; /* 08h */
1486 1491 uint8_t req_id; /* 0Ch */
1487 1492 uint8_t msgvector; /* 0Dh */
1488 1493 uint16_t pad_0; /* 0Eh */
1489 1494
1490 1495 uint16_t flags; /* 10h */
1491 1496 uint16_t timeout; /* 12h */
1492 1497
1493 1498 uint32_t data_xfer_len; /* 14h */
1494 1499
1495 1500 uint64_t sas_addr; /* 20h */
1496 1501
1497 1502 union mrsas_sgl sgl[2]; /* 28h */
1498 1503 };
1499 1504
1500 1505 struct mrsas_stp_frame {
1501 1506 uint8_t cmd; /* 00h */
1502 1507 uint8_t reserved_1; /* 01h */
1503 1508 uint8_t cmd_status; /* 02h */
1504 1509 uint8_t connection_status; /* 03h */
1505 1510
1506 1511 uint8_t target_id; /* 04h */
1507 1512 uint8_t reserved_2[2]; /* 04h */
1508 1513 uint8_t sge_count; /* 07h */
1509 1514
1510 1515 uint32_t context; /* 08h */
1511 1516 uint8_t req_id; /* 0Ch */
1512 1517 uint8_t msgvector; /* 0Dh */
1513 1518 uint16_t pad_0; /* 0Eh */
1514 1519
1515 1520 uint16_t flags; /* 10h */
1516 1521 uint16_t timeout; /* 12h */
1517 1522
1518 1523 uint32_t data_xfer_len; /* 14h */
1519 1524
1520 1525 uint16_t fis[10]; /* 28h */
1521 1526 uint32_t stp_flags; /* 3C */
1522 1527 union mrsas_sgl sgl; /* 40 */
1523 1528 };
1524 1529
1525 1530 union mrsas_frame {
1526 1531 struct mrsas_header hdr;
1527 1532 struct mrsas_init_frame init;
1528 1533 struct mrsas_io_frame io;
1529 1534 struct mrsas_pthru_frame pthru;
1530 1535 struct mrsas_dcmd_frame dcmd;
1531 1536 struct mrsas_abort_frame abort;
1532 1537 struct mrsas_smp_frame smp;
1533 1538 struct mrsas_stp_frame stp;
1534 1539
1535 1540 uint8_t raw_bytes[64];
1536 1541 };
1537 1542
1538 1543 typedef struct mrsas_pd_address {
1539 1544 uint16_t device_id;
1540 1545 uint16_t encl_id;
1541 1546
1542 1547 union {
1543 1548 struct {
1544 1549 uint8_t encl_index;
1545 1550 uint8_t slot_number;
1546 1551 } pd_address;
1547 1552 struct {
1548 1553 uint8_t encl_position;
1549 1554 uint8_t encl_connector_index;
1550 1555 } encl_address;
1551 1556 }address;
1552 1557
1553 1558 uint8_t scsi_dev_type;
1554 1559
1555 1560 union {
1556 1561 uint8_t port_bitmap;
1557 1562 uint8_t port_numbers;
1558 1563 } connected;
1559 1564
1560 1565 uint64_t sas_addr[2];
1561 1566 } mrsas_pd_address_t;
1562 1567
1563 1568 union mrsas_evt_class_locale {
1564 1569 struct {
1565 1570 uint16_t locale;
1566 1571 uint8_t reserved;
1567 1572 int8_t class;
1568 1573 } members;
1569 1574
1570 1575 uint32_t word;
1571 1576 };
1572 1577
1573 1578 struct mrsas_evt_log_info {
1574 1579 uint32_t newest_seq_num;
1575 1580 uint32_t oldest_seq_num;
1576 1581 uint32_t clear_seq_num;
1577 1582 uint32_t shutdown_seq_num;
1578 1583 uint32_t boot_seq_num;
1579 1584 };
1580 1585
1581 1586 struct mrsas_progress {
1582 1587 uint16_t progress;
1583 1588 uint16_t elapsed_seconds;
1584 1589 };
1585 1590
1586 1591 struct mrsas_evtarg_ld {
1587 1592 uint16_t target_id;
1588 1593 uint8_t ld_index;
1589 1594 uint8_t reserved;
1590 1595 };
1591 1596
1592 1597 struct mrsas_evtarg_pd {
1593 1598 uint16_t device_id;
1594 1599 uint8_t encl_index;
1595 1600 uint8_t slot_number;
1596 1601 };
1597 1602
1598 1603 struct mrsas_evt_detail {
1599 1604 uint32_t seq_num;
1600 1605 uint32_t time_stamp;
1601 1606 uint32_t code;
1602 1607 union mrsas_evt_class_locale cl;
1603 1608 uint8_t arg_type;
1604 1609 uint8_t reserved1[15];
1605 1610
1606 1611 union {
1607 1612 struct {
1608 1613 struct mrsas_evtarg_pd pd;
1609 1614 uint8_t cdb_length;
1610 1615 uint8_t sense_length;
1611 1616 uint8_t reserved[2];
1612 1617 uint8_t cdb[16];
1613 1618 uint8_t sense[64];
1614 1619 } cdbSense;
1615 1620
1616 1621 struct mrsas_evtarg_ld ld;
1617 1622
1618 1623 struct {
1619 1624 struct mrsas_evtarg_ld ld;
1620 1625 uint64_t count;
1621 1626 } ld_count;
1622 1627
1623 1628 struct {
1624 1629 uint64_t lba;
1625 1630 struct mrsas_evtarg_ld ld;
1626 1631 } ld_lba;
1627 1632
1628 1633 struct {
1629 1634 struct mrsas_evtarg_ld ld;
1630 1635 uint32_t prevOwner;
1631 1636 uint32_t newOwner;
1632 1637 } ld_owner;
1633 1638
1634 1639 struct {
1635 1640 uint64_t ld_lba;
1636 1641 uint64_t pd_lba;
1637 1642 struct mrsas_evtarg_ld ld;
1638 1643 struct mrsas_evtarg_pd pd;
1639 1644 } ld_lba_pd_lba;
1640 1645
1641 1646 struct {
1642 1647 struct mrsas_evtarg_ld ld;
1643 1648 struct mrsas_progress prog;
1644 1649 } ld_prog;
1645 1650
1646 1651 struct {
1647 1652 struct mrsas_evtarg_ld ld;
1648 1653 uint32_t prev_state;
1649 1654 uint32_t new_state;
1650 1655 } ld_state;
1651 1656
1652 1657 struct {
1653 1658 uint64_t strip;
1654 1659 struct mrsas_evtarg_ld ld;
1655 1660 } ld_strip;
1656 1661
1657 1662 struct mrsas_evtarg_pd pd;
1658 1663
1659 1664 struct {
1660 1665 struct mrsas_evtarg_pd pd;
1661 1666 uint32_t err;
1662 1667 } pd_err;
1663 1668
1664 1669 struct {
1665 1670 uint64_t lba;
1666 1671 struct mrsas_evtarg_pd pd;
1667 1672 } pd_lba;
1668 1673
1669 1674 struct {
1670 1675 uint64_t lba;
1671 1676 struct mrsas_evtarg_pd pd;
1672 1677 struct mrsas_evtarg_ld ld;
1673 1678 } pd_lba_ld;
1674 1679
1675 1680 struct {
1676 1681 struct mrsas_evtarg_pd pd;
1677 1682 struct mrsas_progress prog;
1678 1683 } pd_prog;
1679 1684
1680 1685 struct {
1681 1686 struct mrsas_evtarg_pd pd;
1682 1687 uint32_t prevState;
1683 1688 uint32_t newState;
1684 1689 } pd_state;
1685 1690
1686 1691 struct {
1687 1692 uint16_t vendorId;
1688 1693 uint16_t deviceId;
1689 1694 uint16_t subVendorId;
1690 1695 uint16_t subDeviceId;
1691 1696 } pci;
1692 1697
1693 1698 uint32_t rate;
1694 1699 char str[96];
1695 1700
1696 1701 struct {
1697 1702 uint32_t rtc;
1698 1703 uint32_t elapsedSeconds;
1699 1704 } time;
1700 1705
1701 1706 struct {
1702 1707 uint32_t ecar;
1703 1708 uint32_t elog;
1704 1709 char str[64];
1705 1710 } ecc;
1706 1711
1707 1712 mrsas_pd_address_t pd_addr;
1708 1713
1709 1714 uint8_t b[96];
1710 1715 uint16_t s[48];
1711 1716 uint32_t w[24];
1712 1717 uint64_t d[12];
1713 1718 } args;
1714 1719
1715 1720 char description[128];
1716 1721
1717 1722 };
1718 1723
1719 1724 /* only 63 are usable by the application */
1720 1725 #define MAX_LOGICAL_DRIVES 64
1721 1726 /* only 255 physical devices may be used */
1722 1727 #define MAX_PHYSICAL_DEVICES 256
1723 1728 #define MAX_PD_PER_ENCLOSURE 64
1724 1729 /* maximum disks per array */
1725 1730 #define MAX_ROW_SIZE 32
1726 1731 /* maximum spans per logical drive */
1727 1732 #define MAX_SPAN_DEPTH 8
1728 1733 /* maximum number of arrays a hot spare may be dedicated to */
1729 1734 #define MAX_ARRAYS_DEDICATED 16
1730 1735 /* maximum number of arrays which may exist */
1731 1736 #define MAX_ARRAYS 128
1732 1737 /* maximum number of foreign configs that may ha managed at once */
1733 1738 #define MAX_FOREIGN_CONFIGS 8
1734 1739 /* maximum spares (global and dedicated combined) */
1735 1740 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES
1736 1741 /* maximum possible Target IDs (i.e. 0 to 63) */
1737 1742 #define MAX_TARGET_ID 63
1738 1743 /* maximum number of supported enclosures */
1739 1744 #define MAX_ENCLOSURES 32
1740 1745 /* maximum number of PHYs per controller */
1741 1746 #define MAX_PHYS_PER_CONTROLLER 16
1742 1747 /* maximum number of LDs per array (due to DDF limitations) */
1743 1748 #define MAX_LDS_PER_ARRAY 16
1744 1749
1745 1750 /*
1746 1751 * -----------------------------------------------------------------------------
1747 1752 * -----------------------------------------------------------------------------
1748 1753 *
1749 1754 * Logical Drive commands
1750 1755 *
1751 1756 * -----------------------------------------------------------------------------
1752 1757 * -----------------------------------------------------------------------------
1753 1758 */
1754 1759 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */
1755 1760
1756 1761 /*
1757 1762 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST
1758 1763 * dcmd.mbox - reserved
1759 1764 * dcmd.sge IN - ptr to returned MR_LD_LIST structure
1760 1765 * Desc: Return the logical drive list structure
1761 1766 * Status: No error
1762 1767 */
1763 1768
1764 1769 /*
1765 1770 * defines the logical drive reference structure
1766 1771 */
1767 1772 typedef union _MR_LD_REF { /* LD reference structure */
1768 1773 struct {
1769 1774 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */
1770 1775 uint8_t reserved; /* reserved for in line with MR_PD_REF */
1771 1776 uint16_t seqNum; /* Sequence Number */
1772 1777 } ld_ref;
1773 1778 uint32_t ref; /* shorthand reference to full 32-bits */
1774 1779 } MR_LD_REF; /* 4 bytes */
1775 1780
1776 1781 /*
1777 1782 * defines the logical drive list structure
1778 1783 */
1779 1784 typedef struct _MR_LD_LIST {
1780 1785 uint32_t ldCount; /* number of LDs */
1781 1786 uint32_t reserved; /* pad to 8-byte boundary */
1782 1787 struct {
1783 1788 MR_LD_REF ref; /* LD reference */
1784 1789 uint8_t state; /* current LD state (MR_LD_STATE) */
1785 1790 uint8_t reserved[3]; /* pad to 8-byte boundary */
1786 1791 uint64_t size; /* LD size */
1787 1792 } ldList[MAX_LOGICAL_DRIVES];
1788 1793 } MR_LD_LIST;
1789 1794
1790 1795 struct mrsas_drv_ver {
1791 1796 uint8_t signature[12];
1792 1797 uint8_t os_name[16];
1793 1798 uint8_t os_ver[12];
1794 1799 uint8_t drv_name[20];
1795 1800 uint8_t drv_ver[32];
1796 1801 uint8_t drv_rel_date[20];
1797 1802 };
1798 1803
1799 1804 #define PCI_TYPE0_ADDRESSES 6
1800 1805 #define PCI_TYPE1_ADDRESSES 2
1801 1806 #define PCI_TYPE2_ADDRESSES 5
1802 1807
1803 1808 struct mrsas_pci_common_header {
1804 1809 uint16_t vendorID; /* (ro) */
1805 1810 uint16_t deviceID; /* (ro) */
1806 1811 uint16_t command; /* Device control */
1807 1812 uint16_t status;
1808 1813 uint8_t revisionID; /* (ro) */
1809 1814 uint8_t progIf; /* (ro) */
1810 1815 uint8_t subClass; /* (ro) */
1811 1816 uint8_t baseClass; /* (ro) */
1812 1817 uint8_t cacheLineSize; /* (ro+) */
1813 1818 uint8_t latencyTimer; /* (ro+) */
1814 1819 uint8_t headerType; /* (ro) */
1815 1820 uint8_t bist; /* Built in self test */
1816 1821
1817 1822 union {
1818 1823 struct {
1819 1824 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES];
1820 1825 uint32_t cis;
1821 1826 uint16_t subVendorID;
1822 1827 uint16_t subSystemID;
1823 1828 uint32_t romBaseAddress;
1824 1829 uint8_t capabilitiesPtr;
1825 1830 uint8_t reserved1[3];
1826 1831 uint32_t reserved2;
1827 1832 uint8_t interruptLine;
1828 1833 uint8_t interruptPin; /* (ro) */
1829 1834 uint8_t minimumGrant; /* (ro) */
1830 1835 uint8_t maximumLatency; /* (ro) */
1831 1836 } type_0;
1832 1837
1833 1838 struct {
1834 1839 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES];
1835 1840 uint8_t primaryBus;
1836 1841 uint8_t secondaryBus;
1837 1842 uint8_t subordinateBus;
1838 1843 uint8_t secondaryLatency;
1839 1844 uint8_t ioBase;
1840 1845 uint8_t ioLimit;
1841 1846 uint16_t secondaryStatus;
1842 1847 uint16_t memoryBase;
1843 1848 uint16_t memoryLimit;
1844 1849 uint16_t prefetchBase;
1845 1850 uint16_t prefetchLimit;
1846 1851 uint32_t prefetchBaseUpper32;
1847 1852 uint32_t prefetchLimitUpper32;
1848 1853 uint16_t ioBaseUpper16;
1849 1854 uint16_t ioLimitUpper16;
1850 1855 uint8_t capabilitiesPtr;
1851 1856 uint8_t reserved1[3];
1852 1857 uint32_t romBaseAddress;
1853 1858 uint8_t interruptLine;
1854 1859 uint8_t interruptPin;
1855 1860 uint16_t bridgeControl;
1856 1861 } type_1;
1857 1862
1858 1863 struct {
1859 1864 uint32_t socketRegistersBaseAddress;
1860 1865 uint8_t capabilitiesPtr;
1861 1866 uint8_t reserved;
1862 1867 uint16_t secondaryStatus;
1863 1868 uint8_t primaryBus;
1864 1869 uint8_t secondaryBus;
1865 1870 uint8_t subordinateBus;
1866 1871 uint8_t secondaryLatency;
1867 1872 struct {
1868 1873 uint32_t base;
1869 1874 uint32_t limit;
1870 1875 } range[PCI_TYPE2_ADDRESSES-1];
1871 1876 uint8_t interruptLine;
1872 1877 uint8_t interruptPin;
1873 1878 uint16_t bridgeControl;
1874 1879 } type_2;
1875 1880 } header;
1876 1881 };
1877 1882
1878 1883 struct mrsas_pci_link_capability {
1879 1884 union {
1880 1885 struct {
1881 1886 uint32_t linkSpeed :4;
1882 1887 uint32_t linkWidth :6;
1883 1888 uint32_t aspmSupport :2;
1884 1889 uint32_t losExitLatency :3;
1885 1890 uint32_t l1ExitLatency :3;
1886 1891 uint32_t rsvdp :6;
1887 1892 uint32_t portNumber :8;
1888 1893 } bits;
1889 1894
1890 1895 uint32_t asUlong;
1891 1896 } cap;
1892 1897
1893 1898 };
1894 1899
1895 1900 struct mrsas_pci_link_status_capability {
1896 1901 union {
1897 1902 struct {
1898 1903 uint16_t linkSpeed :4;
1899 1904 uint16_t negotiatedLinkWidth :6;
1900 1905 uint16_t linkTrainingError :1;
1901 1906 uint16_t linkTraning :1;
1902 1907 uint16_t slotClockConfig :1;
1903 1908 uint16_t rsvdZ :3;
1904 1909 } bits;
1905 1910
1906 1911 uint16_t asUshort;
1907 1912 } stat_cap;
1908 1913
1909 1914 uint16_t reserved;
1910 1915
1911 1916 };
1912 1917
1913 1918 struct mrsas_pci_capabilities {
1914 1919 struct mrsas_pci_link_capability linkCapability;
1915 1920 struct mrsas_pci_link_status_capability linkStatusCapability;
1916 1921 };
1917 1922
1918 1923 struct mrsas_pci_information
1919 1924 {
1920 1925 uint32_t busNumber;
1921 1926 uint8_t deviceNumber;
1922 1927 uint8_t functionNumber;
1923 1928 uint8_t interruptVector;
1924 1929 uint8_t reserved;
1925 1930 struct mrsas_pci_common_header pciHeaderInfo;
1926 1931 struct mrsas_pci_capabilities capability;
1927 1932 uint8_t reserved2[32];
1928 1933 };
1929 1934
1930 1935 struct mrsas_ioctl {
1931 1936 uint16_t version;
1932 1937 uint16_t controller_id;
1933 1938 uint8_t signature[8];
1934 1939 uint32_t reserved_1;
1935 1940 uint32_t control_code;
1936 1941 uint32_t reserved_2[2];
1937 1942 uint8_t frame[64];
1938 1943 union mrsas_sgl_frame sgl_frame;
1939 1944 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH];
1940 1945 uint8_t data[1];
1941 1946 };
1942 1947
1943 1948 struct mrsas_aen {
1944 1949 uint16_t host_no;
1945 1950 uint16_t cmd_status;
1946 1951 uint32_t seq_num;
1947 1952 uint32_t class_locale_word;
1948 1953 };
1949 1954
1950 1955 #pragma pack()
1951 1956
1952 1957 #ifndef DDI_VENDOR_LSI
1953 1958 #define DDI_VENDOR_LSI "LSI"
1954 1959 #endif /* DDI_VENDOR_LSI */
1955 1960
1956 1961 int mrsas_config_scsi_device(struct mrsas_instance *,
1957 1962 struct scsi_device *, dev_info_t **);
1958 1963
1959 1964 #ifdef PDSUPPORT
1960 1965 int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t,
1961 1966 uint8_t, dev_info_t **);
1962 1967 #endif
1963 1968
1964 1969 dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, uint8_t);
1965 1970 int mrsas_service_evt(struct mrsas_instance *, int, int, int, uint64_t);
1966 1971 void return_raid_msg_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1967 1972 struct mrsas_cmd *get_raid_msg_mfi_pkt(struct mrsas_instance *);
1968 1973 void return_raid_msg_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1969 1974
1970 1975 int alloc_space_for_mpi2(struct mrsas_instance *);
1971 1976 void fill_up_drv_ver(struct mrsas_drv_ver *dv);
1972 1977
1973 1978 int mrsas_issue_init_mpi2(struct mrsas_instance *);
1974 1979 struct scsi_pkt *mrsas_tbolt_tran_init_pkt(struct scsi_address *, register
1975 1980 struct scsi_pkt *, struct buf *, int, int, int, int,
1976 1981 int (*)(), caddr_t);
1977 1982 int mrsas_tbolt_tran_start(struct scsi_address *,
1978 1983 register struct scsi_pkt *);
1979 1984 uint32_t tbolt_read_fw_status_reg(struct mrsas_instance *);
1980 1985 void tbolt_issue_cmd(struct mrsas_cmd *, struct mrsas_instance *);
1981 1986 int tbolt_issue_cmd_in_poll_mode(struct mrsas_instance *,
1982 1987 struct mrsas_cmd *);
1983 1988 int tbolt_issue_cmd_in_sync_mode(struct mrsas_instance *,
1984 1989 struct mrsas_cmd *);
1985 1990 void tbolt_enable_intr(struct mrsas_instance *);
1986 1991 void tbolt_disable_intr(struct mrsas_instance *);
1987 1992 int tbolt_intr_ack(struct mrsas_instance *);
1988 1993 uint_t mr_sas_tbolt_process_outstanding_cmd(struct mrsas_instance *);
1989 1994 uint_t tbolt_softintr();
1990 1995 int mrsas_tbolt_dma(struct mrsas_instance *, uint32_t, int, int (*)());
1991 1996 int mrsas_check_dma_handle(ddi_dma_handle_t handle);
1992 1997 int mrsas_check_acc_handle(ddi_acc_handle_t handle);
1993 1998 int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
1994 1999 struct buf *, int, int (*)());
1995 2000 int mrsas_dma_move(struct mrsas_instance *,
1996 2001 struct scsi_pkt *, struct buf *);
1997 2002 int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
1998 2003 uchar_t);
1999 2004 void mr_sas_tbolt_build_mfi_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2000 2005 int mrsas_dma_alloc_dmd(struct mrsas_instance *, dma_obj_t *);
2001 2006 void tbolt_complete_cmd_in_sync_mode(struct mrsas_instance *,
2002 2007 struct mrsas_cmd *);
2003 2008 int alloc_req_rep_desc(struct mrsas_instance *);
2004 2009 int mrsas_mode_sense_build(struct scsi_pkt *);
2005 2010 void push_pending_mfi_pkt(struct mrsas_instance *,
2006 2011 struct mrsas_cmd *);
2007 2012 int mrsas_issue_pending_cmds(struct mrsas_instance *);
2008 2013 int mrsas_print_pending_cmds(struct mrsas_instance *);
2009 2014 int mrsas_complete_pending_cmds(struct mrsas_instance *);
2010 2015
2011 2016 int create_mfi_frame_pool(struct mrsas_instance *);
2012 2017 void destroy_mfi_frame_pool(struct mrsas_instance *);
2013 2018 int create_mfi_mpi_frame_pool(struct mrsas_instance *);
2014 2019 void destroy_mfi_mpi_frame_pool(struct mrsas_instance *);
2015 2020 int create_mpi2_frame_pool(struct mrsas_instance *);
2016 2021 void destroy_mpi2_frame_pool(struct mrsas_instance *);
2017 2022 int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
2018 2023 void mrsas_tbolt_free_additional_dma_buffer(struct mrsas_instance *);
2019 2024 void free_req_desc_pool(struct mrsas_instance *);
2020 2025 void free_space_for_mpi2(struct mrsas_instance *);
2021 2026 void mrsas_dump_reply_desc(struct mrsas_instance *);
2022 2027 void tbolt_complete_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2023 2028 void display_scsi_inquiry(caddr_t);
2024 2029 void service_mfi_aen(struct mrsas_instance *, struct mrsas_cmd *);
2025 2030 int mrsas_mode_sense_build(struct scsi_pkt *);
2026 2031 int mrsas_tbolt_get_ld_map_info(struct mrsas_instance *);
2027 2032 struct mrsas_cmd *mrsas_tbolt_build_poll_cmd(struct mrsas_instance *,
2028 2033 struct scsi_address *, struct scsi_pkt *, uchar_t *);
2029 2034 int mrsas_tbolt_reset_ppc(struct mrsas_instance *instance);
2030 2035 void mrsas_tbolt_kill_adapter(struct mrsas_instance *instance);
2031 2036 int abort_syncmap_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2032 2037 void mrsas_tbolt_prepare_cdb(struct mrsas_instance *instance, U8 cdb[],
2033 2038 struct IO_REQUEST_INFO *, Mpi2RaidSCSIIORequest_t *, U32);
2034 2039
2035 2040
2036 2041 int mrsas_init_adapter_ppc(struct mrsas_instance *instance);
2037 2042 int mrsas_init_adapter_tbolt(struct mrsas_instance *instance);
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2038 2043 int mrsas_init_adapter(struct mrsas_instance *instance);
2039 2044
2040 2045 int mrsas_alloc_cmd_pool(struct mrsas_instance *instance);
2041 2046 void mrsas_free_cmd_pool(struct mrsas_instance *instance);
2042 2047
2043 2048 void mrsas_print_cmd_details(struct mrsas_instance *, struct mrsas_cmd *, int);
2044 2049 struct mrsas_cmd *get_raid_msg_pkt(struct mrsas_instance *);
2045 2050
2046 2051 int mfi_state_transition_to_ready(struct mrsas_instance *);
2047 2052
2053 +struct mrsas_cmd *mrsas_get_mfi_pkt(struct mrsas_instance *);
2054 +void mrsas_return_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
2048 2055
2056 +
2049 2057 /* FMA functions. */
2050 2058 int mrsas_common_check(struct mrsas_instance *, struct mrsas_cmd *);
2051 2059 void mrsas_fm_ereport(struct mrsas_instance *, char *);
2052 2060
2053 2061
2054 2062 #ifdef __cplusplus
2055 2063 }
2056 2064 #endif
2057 2065
2058 2066 #endif /* _MR_SAS_H_ */
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