1 /*
2 * mr_sas.h: header for mr_sas
3 *
4 * Solaris MegaRAID driver for SAS2.0 controllers
5 * Copyright (c) 2008-2012, LSI Logic Corporation.
6 * All rights reserved.
7 *
8 * Version:
9 * Author:
10 * Swaminathan K S
11 * Arun Chandrashekhar
12 * Manju R
13 * Rasheed
14 * Shakeel Bukhari
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions are met:
18 *
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 *
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 *
26 * 3. Neither the name of the author nor the names of its contributors may be
27 * used to endorse or promote products derived from this software without
28 * specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41 * DAMAGE.
42 */
43
44 /*
45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
46 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
47 */
48
49 #ifndef _MR_SAS_H_
50 #define _MR_SAS_H_
51
52 #ifdef __cplusplus
53 extern "C" {
54 #endif
55
56 #include <sys/scsi/scsi.h>
57 #include "mr_sas_list.h"
58 #include "ld_pd_map.h"
59
60 /*
61 * MegaRAID SAS2.0 Driver meta data
62 */
63 #define MRSAS_VERSION "6.503.00.00ILLUMOS"
64 #define MRSAS_RELDATE "July 30, 2012"
65
66 #define MRSAS_TRUE 1
67 #define MRSAS_FALSE 0
68
69 #define ADAPTER_RESET_NOT_REQUIRED 0
70 #define ADAPTER_RESET_REQUIRED 1
71
72 #define PDSUPPORT 1
73
74 /*
75 * MegaRAID SAS2.0 device id conversion definitions.
76 */
77 #define INST2LSIRDCTL(x) ((x) << INST_MINOR_SHIFT)
78 #define MRSAS_GET_BOUNDARY_ALIGNED_LEN(len, new_len, boundary_len) { \
79 int rem; \
80 rem = (len / boundary_len); \
81 if ((rem * boundary_len) != len) { \
82 new_len = len + ((rem + 1) * boundary_len - len); \
83 } else { \
84 new_len = len; \
85 } \
86 }
87
88
89 /*
90 * MegaRAID SAS2.0 supported controllers
91 */
92 #define PCI_DEVICE_ID_LSI_2108VDE 0x0078
93 #define PCI_DEVICE_ID_LSI_2108V 0x0079
94 #define PCI_DEVICE_ID_LSI_SKINNY 0x0071
95 #define PCI_DEVICE_ID_LSI_SKINNY_NEW 0x0073
96 #define PCI_DEVICE_ID_LSI_TBOLT 0x005b
97 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
98
99 /*
100 * Register Index for 2108 Controllers.
101 */
102 #define REGISTER_SET_IO_2108 (2)
103
104 #define MRSAS_MAX_SGE_CNT 0x50
105 #define MRSAS_APP_RESERVED_CMDS 32
106 #define MRSAS_APP_MIN_RESERVED_CMDS 4
107
108 #define MRSAS_IOCTL_DRIVER 0x12341234
109 #define MRSAS_IOCTL_FIRMWARE 0x12345678
110 #define MRSAS_IOCTL_AEN 0x87654321
111
112 #define MRSAS_1_SECOND 1000000
113
114 #ifdef PDSUPPORT
115
116 #define UNCONFIGURED_GOOD 0x0
117 #define PD_SYSTEM 0x40
118 #define MR_EVT_PD_STATE_CHANGE 0x0072
119 #define MR_EVT_PD_REMOVED_EXT 0x00f8
120 #define MR_EVT_PD_INSERTED_EXT 0x00f7
121 #define MR_DCMD_PD_GET_INFO 0x02020000
122 #define MRSAS_TBOLT_PD_LUN 1
123 #define MRSAS_TBOLT_PD_TGT_MAX 255
124 #define MRSAS_TBOLT_GET_PD_MAX(s) ((s)->mr_tbolt_pd_max)
125
126 #endif
127
128 /* Raid Context Flags */
129 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
130 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
131 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
132 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
133 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1
134 } MR_RAID_FLAGS_IO_SUB_TYPE;
135
136 /* Dynamic Enumeration Flags */
137 #define MRSAS_LD_LUN 0
138 #define WWN_STRLEN 17
139 #define LD_SYNC_BIT 1
140 #define LD_SYNC_SHIFT 14
141 /* ThunderBolt (TB) specific */
142 #define MRSAS_THUNDERBOLT_MSG_SIZE 256
143 #define MRSAS_THUNDERBOLT_MAX_COMMANDS 1024
144 #define MRSAS_THUNDERBOLT_MAX_REPLY_COUNT 1024
145 #define MRSAS_THUNDERBOLT_REPLY_SIZE 8
146 #define MRSAS_THUNDERBOLT_MAX_CHAIN_COUNT 1
147
148 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
149 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1
150
151 #define MR_EVT_LD_FAST_PATH_IO_STATUS_CHANGED (0xFFFF)
152
153 #define MR_INTERNAL_MFI_FRAMES_SMID 1
154 #define MR_CTRL_EVENT_WAIT_SMID 2
155 #define MR_INTERNAL_DRIVER_RESET_SMID 3
156
157
158 /*
159 * =====================================
160 * MegaRAID SAS2.0 MFI firmware definitions
161 * =====================================
162 */
163 /*
164 * MFI stands for MegaRAID SAS2.0 FW Interface. This is just a moniker for
165 * protocol between the software and firmware. Commands are issued using
166 * "message frames"
167 */
168
169 /*
170 * FW posts its state in upper 4 bits of outbound_msg_0 register
171 */
172 #define MFI_STATE_MASK 0xF0000000
173 #define MFI_STATE_UNDEFINED 0x00000000
174 #define MFI_STATE_BB_INIT 0x10000000
175 #define MFI_STATE_FW_INIT 0x40000000
176 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
177 #define MFI_STATE_FW_INIT_2 0x70000000
178 #define MFI_STATE_DEVICE_SCAN 0x80000000
179 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
180 #define MFI_STATE_FLUSH_CACHE 0xA0000000
181 #define MFI_STATE_READY 0xB0000000
182 #define MFI_STATE_OPERATIONAL 0xC0000000
183 #define MFI_STATE_FAULT 0xF0000000
184
185 #define MRMFI_FRAME_SIZE 64
186
187 /*
188 * During FW init, clear pending cmds & reset state using inbound_msg_0
189 *
190 * ABORT : Abort all pending cmds
191 * READY : Move from OPERATIONAL to READY state; discard queue info
192 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
193 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
194 */
195 #define MFI_INIT_ABORT 0x00000001
196 #define MFI_INIT_READY 0x00000002
197 #define MFI_INIT_MFIMODE 0x00000004
198 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
199 #define MFI_INIT_HOTPLUG 0x00000010
200 #define MFI_STOP_ADP 0x00000020
201 #define MFI_RESET_FLAGS MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
202
203 /*
204 * MFI frame flags
205 */
206 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
207 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
208 #define MFI_FRAME_SGL32 0x0000
209 #define MFI_FRAME_SGL64 0x0002
210 #define MFI_FRAME_SENSE32 0x0000
211 #define MFI_FRAME_SENSE64 0x0004
212 #define MFI_FRAME_DIR_NONE 0x0000
213 #define MFI_FRAME_DIR_WRITE 0x0008
214 #define MFI_FRAME_DIR_READ 0x0010
215 #define MFI_FRAME_DIR_BOTH 0x0018
216 #define MFI_FRAME_IEEE 0x0020
217
218 /*
219 * Definition for cmd_status
220 */
221 #define MFI_CMD_STATUS_POLL_MODE 0xFF
222 #define MFI_CMD_STATUS_SYNC_MODE 0xFF
223
224 /*
225 * MFI command opcodes
226 */
227 #define MFI_CMD_OP_INIT 0x00
228 #define MFI_CMD_OP_LD_READ 0x01
229 #define MFI_CMD_OP_LD_WRITE 0x02
230 #define MFI_CMD_OP_LD_SCSI 0x03
231 #define MFI_CMD_OP_PD_SCSI 0x04
232 #define MFI_CMD_OP_DCMD 0x05
233 #define MFI_CMD_OP_ABORT 0x06
234 #define MFI_CMD_OP_SMP 0x07
235 #define MFI_CMD_OP_STP 0x08
236
237 #define MR_DCMD_CTRL_GET_INFO 0x01010000
238
239 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
240 #define MR_FLUSH_CTRL_CACHE 0x01
241 #define MR_FLUSH_DISK_CACHE 0x02
242
243 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
244 #define MRSAS_ENABLE_DRIVE_SPINDOWN 0x01
245
246 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
247 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
248 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
249 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
250
251 /*
252 * Solaris Specific MAX values
253 */
254 #define MAX_SGL 24
255
256 /*
257 * MFI command completion codes
258 */
259 enum MFI_STAT {
260 MFI_STAT_OK = 0x00,
261 MFI_STAT_INVALID_CMD = 0x01,
262 MFI_STAT_INVALID_DCMD = 0x02,
263 MFI_STAT_INVALID_PARAMETER = 0x03,
264 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
265 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
266 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
267 MFI_STAT_APP_IN_USE = 0x07,
268 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
269 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
270 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
271 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
272 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
273 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
274 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
275 MFI_STAT_FLASH_BUSY = 0x0f,
276 MFI_STAT_FLASH_ERROR = 0x10,
277 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
278 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
279 MFI_STAT_FLASH_NOT_OPEN = 0x13,
280 MFI_STAT_FLASH_NOT_STARTED = 0x14,
281 MFI_STAT_FLUSH_FAILED = 0x15,
282 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
283 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
284 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
285 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
286 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
287 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
288 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
289 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
290 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
291 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
292 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
293 MFI_STAT_MFC_HW_ERROR = 0x21,
294 MFI_STAT_NO_HW_PRESENT = 0x22,
295 MFI_STAT_NOT_FOUND = 0x23,
296 MFI_STAT_NOT_IN_ENCL = 0x24,
297 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
298 MFI_STAT_PD_TYPE_WRONG = 0x26,
299 MFI_STAT_PR_DISABLED = 0x27,
300 MFI_STAT_ROW_INDEX_INVALID = 0x28,
301 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
302 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
303 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
304 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
305 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
306 MFI_STAT_SCSI_IO_FAILED = 0x2e,
307 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
308 MFI_STAT_SHUTDOWN_FAILED = 0x30,
309 MFI_STAT_TIME_NOT_SET = 0x31,
310 MFI_STAT_WRONG_STATE = 0x32,
311 MFI_STAT_LD_OFFLINE = 0x33,
312 MFI_STAT_INVALID_STATUS = 0xFF
313 };
314
315 enum MR_EVT_CLASS {
316 MR_EVT_CLASS_DEBUG = -2,
317 MR_EVT_CLASS_PROGRESS = -1,
318 MR_EVT_CLASS_INFO = 0,
319 MR_EVT_CLASS_WARNING = 1,
320 MR_EVT_CLASS_CRITICAL = 2,
321 MR_EVT_CLASS_FATAL = 3,
322 MR_EVT_CLASS_DEAD = 4
323 };
324
325 enum MR_EVT_LOCALE {
326 MR_EVT_LOCALE_LD = 0x0001,
327 MR_EVT_LOCALE_PD = 0x0002,
328 MR_EVT_LOCALE_ENCL = 0x0004,
329 MR_EVT_LOCALE_BBU = 0x0008,
330 MR_EVT_LOCALE_SAS = 0x0010,
331 MR_EVT_LOCALE_CTRL = 0x0020,
332 MR_EVT_LOCALE_CONFIG = 0x0040,
333 MR_EVT_LOCALE_CLUSTER = 0x0080,
334 MR_EVT_LOCALE_ALL = 0xffff
335 };
336
337 enum MR_EVT_ARGS {
338 MR_EVT_ARGS_NONE,
339 MR_EVT_ARGS_CDB_SENSE,
340 MR_EVT_ARGS_LD,
341 MR_EVT_ARGS_LD_COUNT,
342 MR_EVT_ARGS_LD_LBA,
343 MR_EVT_ARGS_LD_OWNER,
344 MR_EVT_ARGS_LD_LBA_PD_LBA,
345 MR_EVT_ARGS_LD_PROG,
346 MR_EVT_ARGS_LD_STATE,
347 MR_EVT_ARGS_LD_STRIP,
348 MR_EVT_ARGS_PD,
349 MR_EVT_ARGS_PD_ERR,
350 MR_EVT_ARGS_PD_LBA,
351 MR_EVT_ARGS_PD_LBA_LD,
352 MR_EVT_ARGS_PD_PROG,
353 MR_EVT_ARGS_PD_STATE,
354 MR_EVT_ARGS_PCI,
355 MR_EVT_ARGS_RATE,
356 MR_EVT_ARGS_STR,
357 MR_EVT_ARGS_TIME,
358 MR_EVT_ARGS_ECC
359 };
360
361 #define MR_EVT_CFG_CLEARED 0x0004
362 #define MR_EVT_LD_CREATED 0x008a
363 #define MR_EVT_LD_DELETED 0x008b
364 #define MR_EVT_CFG_FP_CHANGE 0x017B
365
366 enum LD_STATE {
367 LD_OFFLINE = 0,
368 LD_PARTIALLY_DEGRADED = 1,
369 LD_DEGRADED = 2,
370 LD_OPTIMAL = 3,
371 LD_INVALID = 0xFF
372 };
373
374 enum MRSAS_EVT {
375 MRSAS_EVT_CONFIG_TGT = 0,
376 MRSAS_EVT_UNCONFIG_TGT = 1,
377 MRSAS_EVT_UNCONFIG_SMP = 2
378 };
379
380 #define DMA_OBJ_ALLOCATED 1
381 #define DMA_OBJ_REALLOCATED 2
382 #define DMA_OBJ_FREED 3
383
384 /*
385 * dma_obj_t - Our DMA object
386 * @param buffer : kernel virtual address
387 * @param size : size of the data to be allocated
388 * @param acc_handle : access handle
389 * @param dma_handle : dma handle
390 * @param dma_cookie : scatter-gather list
391 * @param dma_attr : dma attributes for this buffer
392 *
393 * Our DMA object. The caller must initialize the size and dma attributes
394 * (dma_attr) fields before allocating the resources.
395 */
396 typedef struct {
397 caddr_t buffer;
398 uint32_t size;
399 ddi_acc_handle_t acc_handle;
400 ddi_dma_handle_t dma_handle;
401 ddi_dma_cookie_t dma_cookie[MRSAS_MAX_SGE_CNT];
402 ddi_dma_attr_t dma_attr;
403 uint8_t status;
404 uint8_t reserved[3];
405 } dma_obj_t;
406
407 struct mrsas_eventinfo {
408 struct mrsas_instance *instance;
409 int tgt;
410 int lun;
411 int event;
412 uint64_t wwn;
413 };
414
415 struct mrsas_ld {
416 dev_info_t *dip;
417 uint8_t lun_type;
418 uint8_t flag;
419 uint8_t reserved[2];
420 };
421
422
423 #ifdef PDSUPPORT
424 struct mrsas_tbolt_pd {
425 dev_info_t *dip;
426 uint8_t lun_type;
427 uint8_t dev_id;
428 uint8_t flag;
429 uint8_t reserved;
430 };
431 struct mrsas_tbolt_pd_info {
432 uint16_t deviceId;
433 uint16_t seqNum;
434 uint8_t inquiryData[96];
435 uint8_t vpdPage83[64];
436 uint8_t notSupported;
437 uint8_t scsiDevType;
438 uint8_t a;
439 uint8_t device_speed;
440 uint32_t mediaerrcnt;
441 uint32_t other;
442 uint32_t pred;
443 uint32_t lastpred;
444 uint16_t fwState;
445 uint8_t disabled;
446 uint8_t linkspwwd;
447 uint32_t ddfType;
448 struct {
449 uint8_t count;
450 uint8_t isPathBroken;
451 uint8_t connectorIndex[2];
452 uint8_t reserved[4];
453 uint64_t sasAddr[2];
454 uint8_t reserved2[16];
455 } pathInfo;
456 };
457 #endif
458
459 typedef struct mrsas_instance {
460 uint32_t *producer;
461 uint32_t *consumer;
462
463 uint32_t *reply_queue;
464 dma_obj_t mfi_internal_dma_obj;
465 uint16_t adapterresetinprogress;
466 uint16_t deadadapter;
467 /* ThunderBolt (TB) specific */
468 dma_obj_t mpi2_frame_pool_dma_obj;
469 dma_obj_t request_desc_dma_obj;
470 dma_obj_t reply_desc_dma_obj;
471 dma_obj_t ld_map_obj[2];
472
473 uint8_t init_id;
474 uint8_t flag_ieee;
475 uint8_t disable_online_ctrl_reset;
476 uint8_t fw_fault_count_after_ocr;
477
478 uint16_t max_num_sge;
479 uint16_t max_fw_cmds;
480 uint32_t max_sectors_per_req;
481
482 struct mrsas_cmd **cmd_list;
483
484 mlist_t cmd_pool_list;
485 kmutex_t cmd_pool_mtx;
486 kmutex_t sync_map_mtx;
487
488 mlist_t app_cmd_pool_list;
489 kmutex_t app_cmd_pool_mtx;
490 mlist_t cmd_app_pool_list;
491 kmutex_t cmd_app_pool_mtx;
492
493
494 mlist_t cmd_pend_list;
495 kmutex_t cmd_pend_mtx;
496
497 dma_obj_t mfi_evt_detail_obj;
498 struct mrsas_cmd *aen_cmd;
499
500 uint32_t aen_seq_num;
501 uint32_t aen_class_locale_word;
502
503 scsi_hba_tran_t *tran;
504
505 kcondvar_t int_cmd_cv;
506 kmutex_t int_cmd_mtx;
507
508 kcondvar_t aen_cmd_cv;
509 kmutex_t aen_cmd_mtx;
510
511 kcondvar_t abort_cmd_cv;
512 kmutex_t abort_cmd_mtx;
513
514 kmutex_t reg_write_mtx;
515 kmutex_t chip_mtx;
516
517 dev_info_t *dip;
518 ddi_acc_handle_t pci_handle;
519
520 timeout_id_t timeout_id;
521 uint32_t unique_id;
522 uint16_t fw_outstanding;
523 caddr_t regmap;
524 ddi_acc_handle_t regmap_handle;
525 uint8_t isr_level;
526 ddi_iblock_cookie_t iblock_cookie;
527 ddi_iblock_cookie_t soft_iblock_cookie;
528 ddi_softintr_t soft_intr_id;
529 uint8_t softint_running;
530 uint8_t tbolt_softint_running;
531 kmutex_t completed_pool_mtx;
532 mlist_t completed_pool_list;
533
534 caddr_t internal_buf;
535 uint32_t internal_buf_dmac_add;
536 uint32_t internal_buf_size;
537
538 uint16_t vendor_id;
539 uint16_t device_id;
540 uint16_t subsysvid;
541 uint16_t subsysid;
542 int instance;
543 int baseaddress;
544 char iocnode[16];
545
546 int fm_capabilities;
547 /*
548 * Driver resources unroll flags. The flag is set for resources that
549 * are needed to be free'd at detach() time.
550 */
551 struct _unroll {
552 uint8_t softs; /* The software state was allocated. */
553 uint8_t regs; /* Controller registers mapped. */
554 uint8_t intr; /* Interrupt handler added. */
555 uint8_t reqs; /* Request structs allocated. */
556 uint8_t mutexs; /* Mutex's allocated. */
557 uint8_t taskq; /* Task q's created. */
558 uint8_t tran; /* Tran struct allocated */
559 uint8_t tranSetup; /* Tran attached to the ddi. */
560 uint8_t devctl; /* Device nodes for cfgadm created. */
561 uint8_t scsictl; /* Device nodes for cfgadm created. */
562 uint8_t ioctl; /* Device nodes for ioctl's created. */
563 uint8_t timer; /* Timer started. */
564 uint8_t aenPend; /* AEN cmd pending f/w. */
565 uint8_t mapUpdate_pend; /* LD MAP update cmd pending f/w. */
566 uint8_t soft_isr; /* Soft interrupt handler allocated. */
567 uint8_t ldlist_buff; /* Logical disk list allocated. */
568 uint8_t pdlist_buff; /* Physical disk list allocated. */
569 uint8_t syncCmd; /* Sync map command allocated. */
570 uint8_t verBuff; /* 2108 MFI buffer allocated. */
571 uint8_t alloc_space_mfi; /* Allocated space for 2108 MFI. */
572 uint8_t alloc_space_mpi2; /* Allocated space for 2208 MPI2. */
573 } unroll;
574
575
576 /* function template pointer */
577 struct mrsas_function_template *func_ptr;
578
579
580 /* MSI interrupts specific */
581 ddi_intr_handle_t *intr_htable; /* Interrupt handle array */
582 size_t intr_htable_size; /* Int. handle array size */
583 int intr_type;
584 int intr_cnt;
585 uint_t intr_pri;
586 int intr_cap;
587
588 ddi_taskq_t *taskq;
589 struct mrsas_ld *mr_ld_list;
590 kmutex_t config_dev_mtx;
591 /* ThunderBolt (TB) specific */
592 ddi_softintr_t tbolt_soft_intr_id;
593
594 #ifdef PDSUPPORT
595 uint32_t mr_tbolt_pd_max;
596 struct mrsas_tbolt_pd *mr_tbolt_pd_list;
597 #endif
598
599 uint8_t fast_path_io;
600
601 uint8_t skinny;
602 uint8_t tbolt;
603 uint16_t reply_read_index;
604 uint16_t reply_size; /* Single Reply struct size */
605 uint16_t raid_io_msg_size; /* Single message size */
606 uint32_t io_request_frames_phy;
607 uint8_t *io_request_frames;
608 /* Virtual address of request desc frame pool */
609 MRSAS_REQUEST_DESCRIPTOR_UNION *request_message_pool;
610 /* Physical address of request desc frame pool */
611 uint32_t request_message_pool_phy;
612 /* Virtual address of reply Frame */
613 MPI2_REPLY_DESCRIPTORS_UNION *reply_frame_pool;
614 /* Physical address of reply Frame */
615 uint32_t reply_frame_pool_phy;
616 uint8_t *reply_pool_limit; /* Last reply frame address */
617 /* Physical address of Last reply frame */
618 uint32_t reply_pool_limit_phy;
619 uint32_t reply_q_depth; /* Reply Queue Depth */
620 uint8_t max_sge_in_main_msg;
621 uint8_t max_sge_in_chain;
622 uint8_t chain_offset_io_req;
623 uint8_t chain_offset_mpt_msg;
624 MR_FW_RAID_MAP_ALL *ld_map[2];
625 uint32_t ld_map_phy[2];
626 uint32_t size_map_info;
627 uint64_t map_id;
628 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
629 struct mrsas_cmd *map_update_cmd;
630 uint32_t SyncRequired;
631 kmutex_t ocr_flags_mtx;
632 dma_obj_t drv_ver_dma_obj;
633 } mrsas_t;
634
635
636 /*
637 * Function templates for various controller specific functions
638 */
639 struct mrsas_function_template {
640 uint32_t (*read_fw_status_reg)(struct mrsas_instance *);
641 void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *);
642 int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
643 struct mrsas_cmd *);
644 int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
645 struct mrsas_cmd *);
646 void (*enable_intr)(struct mrsas_instance *);
647 void (*disable_intr)(struct mrsas_instance *);
648 int (*intr_ack)(struct mrsas_instance *);
649 int (*init_adapter)(struct mrsas_instance *);
650 /* int (*reset_adapter)(struct mrsas_instance *); */
651 };
652
653 /*
654 * ### Helper routines ###
655 */
656
657 /*
658 * con_log() - console log routine
659 * @param level : indicates the severity of the message.
660 * @fparam mt : format string
661 *
662 * con_log displays the error messages on the console based on the current
663 * debug level. Also it attaches the appropriate kernel severity level with
664 * the message.
665 *
666 *
667 * console messages debug levels
668 */
669 #define CL_NONE 0 /* No debug information */
670 #define CL_ANN 1 /* print unconditionally, announcements */
671 #define CL_ANN1 2 /* No-op */
672 #define CL_DLEVEL1 3 /* debug level 1, informative */
673 #define CL_DLEVEL2 4 /* debug level 2, verbose */
674 #define CL_DLEVEL3 5 /* debug level 3, very verbose */
675
676 #ifdef __SUNPRO_C
677 #define __func__ ""
678 #endif
679
680 #define con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
681
682 /*
683 * ### SCSA definitions ###
684 */
685 #define PKT2TGT(pkt) ((pkt)->pkt_address.a_target)
686 #define PKT2LUN(pkt) ((pkt)->pkt_address.a_lun)
687 #define PKT2TRAN(pkt) ((pkt)->pkt_adress.a_hba_tran)
688 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
689
690 #define TRAN2MR(tran) (struct mrsas_instance *)(tran)->tran_hba_private)
691 #define ADDR2MR(ap) (TRAN2MR(ADDR2TRAN(ap))
692
693 #define PKT2CMD(pkt) ((struct scsa_cmd *)(pkt)->pkt_ha_private)
694 #define CMD2PKT(sp) ((sp)->cmd_pkt)
695 #define PKT2REQ(pkt) (&(PKT2CMD(pkt)->request))
696
697 #define CMD2ADDR(cmd) (&CMD2PKT(cmd)->pkt_address)
698 #define CMD2TRAN(cmd) (CMD2PKT(cmd)->pkt_address.a_hba_tran)
699 #define CMD2MR(cmd) (TRAN2MR(CMD2TRAN(cmd)))
700
701 #define CFLAG_DMAVALID 0x0001 /* requires a dma operation */
702 #define CFLAG_DMASEND 0x0002 /* Transfer from the device */
703 #define CFLAG_CONSISTENT 0x0040 /* consistent data transfer */
704
705 /*
706 * ### Data structures for ioctl inteface and internal commands ###
707 */
708
709 /*
710 * Data direction flags
711 */
712 #define UIOC_RD 0x00001
713 #define UIOC_WR 0x00002
714
715 #define SCP2HOST(scp) (scp)->device->host /* to host */
716 #define SCP2HOSTDATA(scp) SCP2HOST(scp)->hostdata /* to soft state */
717 #define SCP2CHANNEL(scp) (scp)->device->channel /* to channel */
718 #define SCP2TARGET(scp) (scp)->device->id /* to target */
719 #define SCP2LUN(scp) (scp)->device->lun /* to LUN */
720
721 #define SCSIHOST2ADAP(host) (((caddr_t *)(host->hostdata))[0])
722 #define SCP2ADAPTER(scp) \
723 (struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
724
725 #define MRDRV_IS_LOGICAL_SCSA(instance, acmd) \
726 (acmd->device_id < MRDRV_MAX_LD) ? 1 : 0
727 #define MRDRV_IS_LOGICAL(ap) \
728 ((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0
729 #define MAP_DEVICE_ID(instance, ap) \
730 (ap->a_target)
731
732 #define HIGH_LEVEL_INTR 1
733 #define NORMAL_LEVEL_INTR 0
734
735 #define IO_TIMEOUT_VAL 0
736 #define IO_RETRY_COUNT 3
737 #define MAX_FW_RESET_COUNT 3
738 /*
739 * scsa_cmd - Per-command mr private data
740 * @param cmd_dmahandle : dma handle
741 * @param cmd_dmacookies : current dma cookies
742 * @param cmd_pkt : scsi_pkt reference
743 * @param cmd_dmacount : dma count
744 * @param cmd_cookie : next cookie
745 * @param cmd_ncookies : cookies per window
746 * @param cmd_cookiecnt : cookies per sub-win
747 * @param cmd_nwin : number of dma windows
748 * @param cmd_curwin : current dma window
749 * @param cmd_dma_offset : current window offset
750 * @param cmd_dma_len : current window length
751 * @param cmd_flags : private flags
752 * @param cmd_cdblen : length of cdb
753 * @param cmd_scblen : length of scb
754 * @param cmd_buf : command buffer
755 * @param channel : channel for scsi sub-system
756 * @param target : target for scsi sub-system
757 * @param lun : LUN for scsi sub-system
758 *
759 * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E)
760 * - Pointed to by pkt_ha_private field in scsi_pkt
761 */
762 struct scsa_cmd {
763 ddi_dma_handle_t cmd_dmahandle;
764 ddi_dma_cookie_t cmd_dmacookies[MRSAS_MAX_SGE_CNT];
765 struct scsi_pkt *cmd_pkt;
766 ulong_t cmd_dmacount;
767 uint_t cmd_cookie;
768 uint_t cmd_ncookies;
769 uint_t cmd_cookiecnt;
770 uint_t cmd_nwin;
771 uint_t cmd_curwin;
772 off_t cmd_dma_offset;
773 ulong_t cmd_dma_len;
774 ulong_t cmd_flags;
775 uint_t cmd_cdblen;
776 uint_t cmd_scblen;
777 struct buf *cmd_buf;
778 ushort_t device_id;
779 uchar_t islogical;
780 uchar_t lun;
781 struct mrsas_device *mrsas_dev;
782 };
783
784
785 struct mrsas_cmd {
786 /*
787 * ThunderBolt(TB) We would be needing to have a placeholder
788 * for RAID_MSG_IO_REQUEST inside this structure. We are
789 * supposed to embed the mr_frame inside the RAID_MSG and post
790 * it down to the firmware.
791 */
792 union mrsas_frame *frame;
793 uint32_t frame_phys_addr;
794 uint8_t *sense;
795 uint8_t *sense1;
796 uint32_t sense_phys_addr;
797 uint32_t sense_phys_addr1;
798 dma_obj_t frame_dma_obj;
799 uint8_t frame_dma_obj_status;
800 uint32_t index;
801 uint8_t sync_cmd;
802 uint8_t cmd_status;
803 uint16_t abort_aen;
804 mlist_t list;
805 uint32_t frame_count;
806 struct scsa_cmd *cmd;
807 struct scsi_pkt *pkt;
808 Mpi2RaidSCSIIORequest_t *scsi_io_request;
809 Mpi2SGEIOUnion_t *sgl;
810 uint32_t sgl_phys_addr;
811 uint32_t scsi_io_request_phys_addr;
812 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc;
813 uint16_t SMID;
814 uint16_t retry_count_for_ocr;
815 uint16_t drv_pkt_time;
816 uint16_t load_balance_flag;
817
818 };
819
820 #define MAX_MGMT_ADAPTERS 1024
821 #define IOC_SIGNATURE "MR-SAS"
822
823 #define IOC_CMD_FIRMWARE 0x0
824 #define MRSAS_DRIVER_IOCTL_COMMON 0xF0010000
825 #define MRSAS_DRIVER_IOCTL_DRIVER_VERSION 0xF0010100
826 #define MRSAS_DRIVER_IOCTL_PCI_INFORMATION 0xF0010200
827 #define MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS 0xF0010300
828
829
830 #define MRSAS_MAX_SENSE_LENGTH 32
831
832 struct mrsas_mgmt_info {
833
834 uint16_t count;
835 struct mrsas_instance *instance[MAX_MGMT_ADAPTERS];
836 uint16_t map[MAX_MGMT_ADAPTERS];
837 int max_index;
838 };
839
840
841 #pragma pack(1)
842 /*
843 * SAS controller properties
844 */
845 struct mrsas_ctrl_prop {
846 uint16_t seq_num;
847 uint16_t pred_fail_poll_interval;
848 uint16_t intr_throttle_count;
849 uint16_t intr_throttle_timeouts;
850
851 uint8_t rebuild_rate;
852 uint8_t patrol_read_rate;
853 uint8_t bgi_rate;
854 uint8_t cc_rate;
855 uint8_t recon_rate;
856
857 uint8_t cache_flush_interval;
858
859 uint8_t spinup_drv_count;
860 uint8_t spinup_delay;
861
862 uint8_t cluster_enable;
863 uint8_t coercion_mode;
864 uint8_t alarm_enable;
865
866 uint8_t reserved_1[13];
867 uint32_t on_off_properties;
868 uint8_t reserved_4[28];
869 };
870
871
872 /*
873 * SAS controller information
874 */
875 struct mrsas_ctrl_info {
876 /* PCI device information */
877 struct {
878 uint16_t vendor_id;
879 uint16_t device_id;
880 uint16_t sub_vendor_id;
881 uint16_t sub_device_id;
882 uint8_t reserved[24];
883 } pci;
884
885 /* Host interface information */
886 struct {
887 uint8_t PCIX : 1;
888 uint8_t PCIE : 1;
889 uint8_t iSCSI : 1;
890 uint8_t SAS_3G : 1;
891 uint8_t reserved_0 : 4;
892 uint8_t reserved_1[6];
893 uint8_t port_count;
894 uint64_t port_addr[8];
895 } host_interface;
896
897 /* Device (backend) interface information */
898 struct {
899 uint8_t SPI : 1;
900 uint8_t SAS_3G : 1;
901 uint8_t SATA_1_5G : 1;
902 uint8_t SATA_3G : 1;
903 uint8_t reserved_0 : 4;
904 uint8_t reserved_1[6];
905 uint8_t port_count;
906 uint64_t port_addr[8];
907 } device_interface;
908
909 /* List of components residing in flash. All str are null terminated */
910 uint32_t image_check_word;
911 uint32_t image_component_count;
912
913 struct {
914 char name[8];
915 char version[32];
916 char build_date[16];
917 char built_time[16];
918 } image_component[8];
919
920 /*
921 * List of flash components that have been flashed on the card, but
922 * are not in use, pending reset of the adapter. This list will be
923 * empty if a flash operation has not occurred. All stings are null
924 * terminated
925 */
926 uint32_t pending_image_component_count;
927
928 struct {
929 char name[8];
930 char version[32];
931 char build_date[16];
932 char build_time[16];
933 } pending_image_component[8];
934
935 uint8_t max_arms;
936 uint8_t max_spans;
937 uint8_t max_arrays;
938 uint8_t max_lds;
939
940 char product_name[80];
941 char serial_no[32];
942
943 /*
944 * Other physical/controller/operation information. Indicates the
945 * presence of the hardware
946 */
947 struct {
948 uint32_t bbu : 1;
949 uint32_t alarm : 1;
950 uint32_t nvram : 1;
951 uint32_t uart : 1;
952 uint32_t reserved : 28;
953 } hw_present;
954
955 uint32_t current_fw_time;
956
957 /* Maximum data transfer sizes */
958 uint16_t max_concurrent_cmds;
959 uint16_t max_sge_count;
960 uint32_t max_request_size;
961
962 /* Logical and physical device counts */
963 uint16_t ld_present_count;
964 uint16_t ld_degraded_count;
965 uint16_t ld_offline_count;
966
967 uint16_t pd_present_count;
968 uint16_t pd_disk_present_count;
969 uint16_t pd_disk_pred_failure_count;
970 uint16_t pd_disk_failed_count;
971
972 /* Memory size information */
973 uint16_t nvram_size;
974 uint16_t memory_size;
975 uint16_t flash_size;
976
977 /* Error counters */
978 uint16_t mem_correctable_error_count;
979 uint16_t mem_uncorrectable_error_count;
980
981 /* Cluster information */
982 uint8_t cluster_permitted;
983 uint8_t cluster_active;
984 uint8_t reserved_1[2];
985
986 /* Controller capabilities structures */
987 struct {
988 uint32_t raid_level_0 : 1;
989 uint32_t raid_level_1 : 1;
990 uint32_t raid_level_5 : 1;
991 uint32_t raid_level_1E : 1;
992 uint32_t reserved : 28;
993 } raid_levels;
994
995 struct {
996 uint32_t rbld_rate : 1;
997 uint32_t cc_rate : 1;
998 uint32_t bgi_rate : 1;
999 uint32_t recon_rate : 1;
1000 uint32_t patrol_rate : 1;
1001 uint32_t alarm_control : 1;
1002 uint32_t cluster_supported : 1;
1003 uint32_t bbu : 1;
1004 uint32_t spanning_allowed : 1;
1005 uint32_t dedicated_hotspares : 1;
1006 uint32_t revertible_hotspares : 1;
1007 uint32_t foreign_config_import : 1;
1008 uint32_t self_diagnostic : 1;
1009 uint32_t reserved : 19;
1010 } adapter_operations;
1011
1012 struct {
1013 uint32_t read_policy : 1;
1014 uint32_t write_policy : 1;
1015 uint32_t io_policy : 1;
1016 uint32_t access_policy : 1;
1017 uint32_t reserved : 28;
1018 } ld_operations;
1019
1020 struct {
1021 uint8_t min;
1022 uint8_t max;
1023 uint8_t reserved[2];
1024 } stripe_size_operations;
1025
1026 struct {
1027 uint32_t force_online : 1;
1028 uint32_t force_offline : 1;
1029 uint32_t force_rebuild : 1;
1030 uint32_t reserved : 29;
1031 } pd_operations;
1032
1033 struct {
1034 uint32_t ctrl_supports_sas : 1;
1035 uint32_t ctrl_supports_sata : 1;
1036 uint32_t allow_mix_in_encl : 1;
1037 uint32_t allow_mix_in_ld : 1;
1038 uint32_t allow_sata_in_cluster : 1;
1039 uint32_t reserved : 27;
1040 } pd_mix_support;
1041
1042 /* Include the controller properties (changeable items) */
1043 uint8_t reserved_2[12];
1044 struct mrsas_ctrl_prop properties;
1045
1046 uint8_t pad[0x800 - 0x640];
1047 };
1048
1049 /*
1050 * ==================================
1051 * MegaRAID SAS2.0 driver definitions
1052 * ==================================
1053 */
1054 #define MRDRV_MAX_NUM_CMD 1024
1055
1056 #define MRDRV_MAX_PD_CHANNELS 2
1057 #define MRDRV_MAX_LD_CHANNELS 2
1058 #define MRDRV_MAX_CHANNELS (MRDRV_MAX_PD_CHANNELS + \
1059 MRDRV_MAX_LD_CHANNELS)
1060 #define MRDRV_MAX_DEV_PER_CHANNEL 128
1061 #define MRDRV_DEFAULT_INIT_ID -1
1062 #define MRDRV_MAX_CMD_PER_LUN 1000
1063 #define MRDRV_MAX_LUN 1
1064 #define MRDRV_MAX_LD 64
1065
1066 #define MRDRV_RESET_WAIT_TIME 300
1067 #define MRDRV_RESET_NOTICE_INTERVAL 5
1068
1069 #define MRSAS_IOCTL_CMD 0
1070
1071 #define MRDRV_TGT_VALID 1
1072
1073 /*
1074 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1075 * SGLs based on the size of dma_addr_t
1076 */
1077 #define IS_DMA64 (sizeof (dma_addr_t) == 8)
1078
1079 #define RESERVED0_REGISTER 0x00 /* XScale */
1080 #define IB_MSG_0_OFF 0x10 /* XScale */
1081 #define OB_MSG_0_OFF 0x18 /* XScale */
1082 #define IB_DOORBELL_OFF 0x20 /* XScale & ROC */
1083 #define OB_INTR_STATUS_OFF 0x30 /* XScale & ROC */
1084 #define OB_INTR_MASK_OFF 0x34 /* XScale & ROC */
1085 #define IB_QPORT_OFF 0x40 /* XScale & ROC */
1086 #define OB_DOORBELL_CLEAR_OFF 0xA0 /* ROC */
1087 #define OB_SCRATCH_PAD_0_OFF 0xB0 /* ROC */
1088 #define OB_INTR_MASK 0xFFFFFFFF
1089 #define OB_DOORBELL_CLEAR_MASK 0xFFFFFFFF
1090 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1091 #define OB_SCRATCH_PAD_2_OFF 0xB4
1092 #define WRITE_TBOLT_SEQ_OFF 0x00000004
1093 #define DIAG_TBOLT_RESET_ADAPTER 0x00000004
1094 #define HOST_TBOLT_DIAG_OFF 0x00000008
1095 #define RESET_TBOLT_STATUS_OFF 0x000003C3
1096 #define WRITE_SEQ_OFF 0x000000FC
1097 #define HOST_DIAG_OFF 0x000000F8
1098 #define DIAG_RESET_ADAPTER 0x00000004
1099 #define DIAG_WRITE_ENABLE 0x00000080
1100 #define SYSTOIOP_INTERRUPT_MASK 0x80000000
1101
1102 #define WR_IB_WRITE_SEQ(v, instance) ddi_put32((instance)->regmap_handle, \
1103 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v))
1104
1105 #define RD_OB_DRWE(instance) ddi_get32((instance)->regmap_handle, \
1106 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF))
1107
1108 #define WR_IB_DRWE(v, instance) ddi_put32((instance)->regmap_handle, \
1109 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v))
1110
1111 #define IB_LOW_QPORT 0xC0
1112 #define IB_HIGH_QPORT 0xC4
1113 #define OB_DOORBELL_REGISTER 0x9C /* 1078 implementation */
1114
1115 /*
1116 * All MFI register set macros accept mrsas_register_set*
1117 */
1118 #define WR_IB_MSG_0(v, instance) ddi_put32((instance)->regmap_handle, \
1119 (uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
1120
1121 #define RD_OB_MSG_0(instance) ddi_get32((instance)->regmap_handle, \
1122 (uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
1123
1124 #define WR_IB_DOORBELL(v, instance) ddi_put32((instance)->regmap_handle, \
1125 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
1126
1127 #define RD_IB_DOORBELL(instance) ddi_get32((instance)->regmap_handle, \
1128 (uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
1129
1130 #define WR_OB_INTR_STATUS(v, instance) ddi_put32((instance)->regmap_handle, \
1131 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
1132
1133 #define RD_OB_INTR_STATUS(instance) ddi_get32((instance)->regmap_handle, \
1134 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
1135
1136 #define WR_OB_INTR_MASK(v, instance) ddi_put32((instance)->regmap_handle, \
1137 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
1138
1139 #define RD_OB_INTR_MASK(instance) ddi_get32((instance)->regmap_handle, \
1140 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
1141
1142 #define WR_IB_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1143 (uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
1144
1145 #define WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
1146 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
1147 (v))
1148
1149 #define RD_OB_SCRATCH_PAD_0(instance) ddi_get32((instance)->regmap_handle, \
1150 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
1151
1152 /* Thunderbolt specific registers */
1153 #define RD_OB_SCRATCH_PAD_2(instance) ddi_get32((instance)->regmap_handle, \
1154 (uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_2_OFF))
1155
1156 #define WR_TBOLT_IB_WRITE_SEQ(v, instance) \
1157 ddi_put32((instance)->regmap_handle, \
1158 (uint32_t *)((uintptr_t)(instance)->regmap + WRITE_TBOLT_SEQ_OFF), (v))
1159
1160 #define RD_TBOLT_HOST_DIAG(instance) ddi_get32((instance)->regmap_handle, \
1161 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF))
1162
1163 #define WR_TBOLT_HOST_DIAG(v, instance) ddi_put32((instance)->regmap_handle, \
1164 (uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF), (v))
1165
1166 #define RD_TBOLT_RESET_STAT(instance) ddi_get32((instance)->regmap_handle, \
1167 (uint32_t *)((uintptr_t)(instance)->regmap + RESET_TBOLT_STATUS_OFF))
1168
1169
1170 #define WR_MPI2_REPLY_POST_INDEX(v, instance)\
1171 ddi_put32((instance)->regmap_handle,\
1172 (uint32_t *)\
1173 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET),\
1174 (v))
1175
1176
1177 #define RD_MPI2_REPLY_POST_INDEX(instance)\
1178 ddi_get32((instance)->regmap_handle,\
1179 (uint32_t *)\
1180 ((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET))
1181
1182 #define WR_IB_LOW_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1183 (uint32_t *)((uintptr_t)(instance)->regmap + IB_LOW_QPORT), (v))
1184
1185 #define WR_IB_HIGH_QPORT(v, instance) ddi_put32((instance)->regmap_handle, \
1186 (uint32_t *)((uintptr_t)(instance)->regmap + IB_HIGH_QPORT), (v))
1187
1188 #define WR_OB_DOORBELL_REGISTER_CLEAR(v, instance)\
1189 ddi_put32((instance)->regmap_handle,\
1190 (uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_REGISTER), \
1191 (v))
1192
1193 #define WR_RESERVED0_REGISTER(v, instance) ddi_put32((instance)->regmap_handle,\
1194 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER), \
1195 (v))
1196
1197 #define RD_RESERVED0_REGISTER(instance) ddi_get32((instance)->regmap_handle, \
1198 (uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER))
1199
1200
1201
1202 /*
1203 * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
1204 * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
1205 * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
1206 */
1207 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1208
1209 /*
1210 * This MFI_REPLY_2108_MESSAGE_INTR flag is used also
1211 * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
1212 * been set in this flag along with bit 1.
1213 */
1214 #define MFI_REPLY_2108_MESSAGE_INTR 0x00000001
1215 #define MFI_REPLY_2108_MESSAGE_INTR_MASK 0x00000005
1216
1217 /* Fusion interrupt mask */
1218 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000008)
1219
1220 #define MFI_POLL_TIMEOUT_SECS 60
1221
1222 #define MFI_ENABLE_INTR(instance) ddi_put32((instance)->regmap_handle, \
1223 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
1224 #define MFI_DISABLE_INTR(instance) \
1225 { \
1226 uint32_t disable = 1; \
1227 uint32_t mask = ddi_get32((instance)->regmap_handle, \
1228 (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
1229 mask &= ~disable; \
1230 ddi_put32((instance)->regmap_handle, (uint32_t *) \
1231 (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask); \
1232 }
1233
1234 /* By default, the firmware programs for 8 Kbytes of memory */
1235 #define DEFAULT_MFI_MEM_SZ 8192
1236 #define MINIMUM_MFI_MEM_SZ 4096
1237
1238 /* DCMD Message Frame MAILBOX0-11 */
1239 #define DCMD_MBOX_SZ 12
1240
1241 /*
1242 * on_off_property of mrsas_ctrl_prop
1243 * bit0-9, 11-31 are reserved
1244 */
1245 #define DISABLE_OCR_PROP_FLAG 0x00000400 /* bit 10 */
1246
1247 struct mrsas_register_set {
1248 uint32_t reserved_0[4]; /* 0000h */
1249
1250 uint32_t inbound_msg_0; /* 0010h */
1251 uint32_t inbound_msg_1; /* 0014h */
1252 uint32_t outbound_msg_0; /* 0018h */
1253 uint32_t outbound_msg_1; /* 001Ch */
1254
1255 uint32_t inbound_doorbell; /* 0020h */
1256 uint32_t inbound_intr_status; /* 0024h */
1257 uint32_t inbound_intr_mask; /* 0028h */
1258
1259 uint32_t outbound_doorbell; /* 002Ch */
1260 uint32_t outbound_intr_status; /* 0030h */
1261 uint32_t outbound_intr_mask; /* 0034h */
1262
1263 uint32_t reserved_1[2]; /* 0038h */
1264
1265 uint32_t inbound_queue_port; /* 0040h */
1266 uint32_t outbound_queue_port; /* 0044h */
1267
1268 uint32_t reserved_2[22]; /* 0048h */
1269
1270 uint32_t outbound_doorbell_clear; /* 00A0h */
1271
1272 uint32_t reserved_3[3]; /* 00A4h */
1273
1274 uint32_t outbound_scratch_pad; /* 00B0h */
1275
1276 uint32_t reserved_4[3]; /* 00B4h */
1277
1278 uint32_t inbound_low_queue_port; /* 00C0h */
1279
1280 uint32_t inbound_high_queue_port; /* 00C4h */
1281
1282 uint32_t reserved_5; /* 00C8h */
1283 uint32_t index_registers[820]; /* 00CCh */
1284 };
1285
1286 struct mrsas_sge32 {
1287 uint32_t phys_addr;
1288 uint32_t length;
1289 };
1290
1291 struct mrsas_sge64 {
1292 uint64_t phys_addr;
1293 uint32_t length;
1294 };
1295
1296 struct mrsas_sge_ieee {
1297 uint64_t phys_addr;
1298 uint32_t length;
1299 uint32_t flag;
1300 };
1301
1302 union mrsas_sgl {
1303 struct mrsas_sge32 sge32[1];
1304 struct mrsas_sge64 sge64[1];
1305 struct mrsas_sge_ieee sge_ieee[1];
1306 };
1307
1308 struct mrsas_header {
1309 uint8_t cmd; /* 00h */
1310 uint8_t sense_len; /* 01h */
1311 uint8_t cmd_status; /* 02h */
1312 uint8_t scsi_status; /* 03h */
1313
1314 uint8_t target_id; /* 04h */
1315 uint8_t lun; /* 05h */
1316 uint8_t cdb_len; /* 06h */
1317 uint8_t sge_count; /* 07h */
1318
1319 uint32_t context; /* 08h */
1320 uint8_t req_id; /* 0Ch */
1321 uint8_t msgvector; /* 0Dh */
1322 uint16_t pad_0; /* 0Eh */
1323
1324 uint16_t flags; /* 10h */
1325 uint16_t timeout; /* 12h */
1326 uint32_t data_xferlen; /* 14h */
1327 };
1328
1329 union mrsas_sgl_frame {
1330 struct mrsas_sge32 sge32[8];
1331 struct mrsas_sge64 sge64[5];
1332 };
1333
1334 struct mrsas_init_frame {
1335 uint8_t cmd; /* 00h */
1336 uint8_t reserved_0; /* 01h */
1337 uint8_t cmd_status; /* 02h */
1338
1339 uint8_t reserved_1; /* 03h */
1340 uint32_t reserved_2; /* 04h */
1341
1342 uint32_t context; /* 08h */
1343 uint8_t req_id; /* 0Ch */
1344 uint8_t msgvector; /* 0Dh */
1345 uint16_t pad_0; /* 0Eh */
1346
1347 uint16_t flags; /* 10h */
1348 uint16_t reserved_3; /* 12h */
1349 uint32_t data_xfer_len; /* 14h */
1350
1351 uint32_t queue_info_new_phys_addr_lo; /* 18h */
1352 uint32_t queue_info_new_phys_addr_hi; /* 1Ch */
1353 uint32_t queue_info_old_phys_addr_lo; /* 20h */
1354 uint32_t queue_info_old_phys_addr_hi; /* 24h */
1355 uint64_t driverversion; /* 28h */
1356 uint32_t reserved_4[4]; /* 30h */
1357 };
1358
1359 struct mrsas_init_queue_info {
1360 uint32_t init_flags; /* 00h */
1361 uint32_t reply_queue_entries; /* 04h */
1362
1363 uint32_t reply_queue_start_phys_addr_lo; /* 08h */
1364 uint32_t reply_queue_start_phys_addr_hi; /* 0Ch */
1365 uint32_t producer_index_phys_addr_lo; /* 10h */
1366 uint32_t producer_index_phys_addr_hi; /* 14h */
1367 uint32_t consumer_index_phys_addr_lo; /* 18h */
1368 uint32_t consumer_index_phys_addr_hi; /* 1Ch */
1369 };
1370
1371 struct mrsas_io_frame {
1372 uint8_t cmd; /* 00h */
1373 uint8_t sense_len; /* 01h */
1374 uint8_t cmd_status; /* 02h */
1375 uint8_t scsi_status; /* 03h */
1376
1377 uint8_t target_id; /* 04h */
1378 uint8_t access_byte; /* 05h */
1379 uint8_t reserved_0; /* 06h */
1380 uint8_t sge_count; /* 07h */
1381
1382 uint32_t context; /* 08h */
1383 uint8_t req_id; /* 0Ch */
1384 uint8_t msgvector; /* 0Dh */
1385 uint16_t pad_0; /* 0Eh */
1386
1387 uint16_t flags; /* 10h */
1388 uint16_t timeout; /* 12h */
1389 uint32_t lba_count; /* 14h */
1390
1391 uint32_t sense_buf_phys_addr_lo; /* 18h */
1392 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1393
1394 uint32_t start_lba_lo; /* 20h */
1395 uint32_t start_lba_hi; /* 24h */
1396
1397 union mrsas_sgl sgl; /* 28h */
1398 };
1399
1400 struct mrsas_pthru_frame {
1401 uint8_t cmd; /* 00h */
1402 uint8_t sense_len; /* 01h */
1403 uint8_t cmd_status; /* 02h */
1404 uint8_t scsi_status; /* 03h */
1405
1406 uint8_t target_id; /* 04h */
1407 uint8_t lun; /* 05h */
1408 uint8_t cdb_len; /* 06h */
1409 uint8_t sge_count; /* 07h */
1410
1411 uint32_t context; /* 08h */
1412 uint8_t req_id; /* 0Ch */
1413 uint8_t msgvector; /* 0Dh */
1414 uint16_t pad_0; /* 0Eh */
1415
1416 uint16_t flags; /* 10h */
1417 uint16_t timeout; /* 12h */
1418 uint32_t data_xfer_len; /* 14h */
1419
1420 uint32_t sense_buf_phys_addr_lo; /* 18h */
1421 uint32_t sense_buf_phys_addr_hi; /* 1Ch */
1422
1423 uint8_t cdb[16]; /* 20h */
1424 union mrsas_sgl sgl; /* 30h */
1425 };
1426
1427 struct mrsas_dcmd_frame {
1428 uint8_t cmd; /* 00h */
1429 uint8_t reserved_0; /* 01h */
1430 uint8_t cmd_status; /* 02h */
1431 uint8_t reserved_1[4]; /* 03h */
1432 uint8_t sge_count; /* 07h */
1433
1434 uint32_t context; /* 08h */
1435 uint8_t req_id; /* 0Ch */
1436 uint8_t msgvector; /* 0Dh */
1437 uint16_t pad_0; /* 0Eh */
1438
1439 uint16_t flags; /* 10h */
1440 uint16_t timeout; /* 12h */
1441
1442 uint32_t data_xfer_len; /* 14h */
1443 uint32_t opcode; /* 18h */
1444
1445 /* uint8_t mbox[DCMD_MBOX_SZ]; */ /* 1Ch */
1446 union { /* 1Ch */
1447 uint8_t b[DCMD_MBOX_SZ];
1448 uint16_t s[6];
1449 uint32_t w[3];
1450 } mbox;
1451
1452 union mrsas_sgl sgl; /* 28h */
1453 };
1454
1455 struct mrsas_abort_frame {
1456 uint8_t cmd; /* 00h */
1457 uint8_t reserved_0; /* 01h */
1458 uint8_t cmd_status; /* 02h */
1459
1460 uint8_t reserved_1; /* 03h */
1461 uint32_t reserved_2; /* 04h */
1462
1463 uint32_t context; /* 08h */
1464 uint8_t req_id; /* 0Ch */
1465 uint8_t msgvector; /* 0Dh */
1466 uint16_t pad_0; /* 0Eh */
1467
1468 uint16_t flags; /* 10h */
1469 uint16_t reserved_3; /* 12h */
1470 uint32_t reserved_4; /* 14h */
1471
1472 uint32_t abort_context; /* 18h */
1473 uint32_t pad_1; /* 1Ch */
1474
1475 uint32_t abort_mfi_phys_addr_lo; /* 20h */
1476 uint32_t abort_mfi_phys_addr_hi; /* 24h */
1477
1478 uint32_t reserved_5[6]; /* 28h */
1479 };
1480
1481 struct mrsas_smp_frame {
1482 uint8_t cmd; /* 00h */
1483 uint8_t reserved_1; /* 01h */
1484 uint8_t cmd_status; /* 02h */
1485 uint8_t connection_status; /* 03h */
1486
1487 uint8_t reserved_2[3]; /* 04h */
1488 uint8_t sge_count; /* 07h */
1489
1490 uint32_t context; /* 08h */
1491 uint8_t req_id; /* 0Ch */
1492 uint8_t msgvector; /* 0Dh */
1493 uint16_t pad_0; /* 0Eh */
1494
1495 uint16_t flags; /* 10h */
1496 uint16_t timeout; /* 12h */
1497
1498 uint32_t data_xfer_len; /* 14h */
1499
1500 uint64_t sas_addr; /* 20h */
1501
1502 union mrsas_sgl sgl[2]; /* 28h */
1503 };
1504
1505 struct mrsas_stp_frame {
1506 uint8_t cmd; /* 00h */
1507 uint8_t reserved_1; /* 01h */
1508 uint8_t cmd_status; /* 02h */
1509 uint8_t connection_status; /* 03h */
1510
1511 uint8_t target_id; /* 04h */
1512 uint8_t reserved_2[2]; /* 04h */
1513 uint8_t sge_count; /* 07h */
1514
1515 uint32_t context; /* 08h */
1516 uint8_t req_id; /* 0Ch */
1517 uint8_t msgvector; /* 0Dh */
1518 uint16_t pad_0; /* 0Eh */
1519
1520 uint16_t flags; /* 10h */
1521 uint16_t timeout; /* 12h */
1522
1523 uint32_t data_xfer_len; /* 14h */
1524
1525 uint16_t fis[10]; /* 28h */
1526 uint32_t stp_flags; /* 3C */
1527 union mrsas_sgl sgl; /* 40 */
1528 };
1529
1530 union mrsas_frame {
1531 struct mrsas_header hdr;
1532 struct mrsas_init_frame init;
1533 struct mrsas_io_frame io;
1534 struct mrsas_pthru_frame pthru;
1535 struct mrsas_dcmd_frame dcmd;
1536 struct mrsas_abort_frame abort;
1537 struct mrsas_smp_frame smp;
1538 struct mrsas_stp_frame stp;
1539
1540 uint8_t raw_bytes[64];
1541 };
1542
1543 typedef struct mrsas_pd_address {
1544 uint16_t device_id;
1545 uint16_t encl_id;
1546
1547 union {
1548 struct {
1549 uint8_t encl_index;
1550 uint8_t slot_number;
1551 } pd_address;
1552 struct {
1553 uint8_t encl_position;
1554 uint8_t encl_connector_index;
1555 } encl_address;
1556 }address;
1557
1558 uint8_t scsi_dev_type;
1559
1560 union {
1561 uint8_t port_bitmap;
1562 uint8_t port_numbers;
1563 } connected;
1564
1565 uint64_t sas_addr[2];
1566 } mrsas_pd_address_t;
1567
1568 union mrsas_evt_class_locale {
1569 struct {
1570 uint16_t locale;
1571 uint8_t reserved;
1572 int8_t class;
1573 } members;
1574
1575 uint32_t word;
1576 };
1577
1578 struct mrsas_evt_log_info {
1579 uint32_t newest_seq_num;
1580 uint32_t oldest_seq_num;
1581 uint32_t clear_seq_num;
1582 uint32_t shutdown_seq_num;
1583 uint32_t boot_seq_num;
1584 };
1585
1586 struct mrsas_progress {
1587 uint16_t progress;
1588 uint16_t elapsed_seconds;
1589 };
1590
1591 struct mrsas_evtarg_ld {
1592 uint16_t target_id;
1593 uint8_t ld_index;
1594 uint8_t reserved;
1595 };
1596
1597 struct mrsas_evtarg_pd {
1598 uint16_t device_id;
1599 uint8_t encl_index;
1600 uint8_t slot_number;
1601 };
1602
1603 struct mrsas_evt_detail {
1604 uint32_t seq_num;
1605 uint32_t time_stamp;
1606 uint32_t code;
1607 union mrsas_evt_class_locale cl;
1608 uint8_t arg_type;
1609 uint8_t reserved1[15];
1610
1611 union {
1612 struct {
1613 struct mrsas_evtarg_pd pd;
1614 uint8_t cdb_length;
1615 uint8_t sense_length;
1616 uint8_t reserved[2];
1617 uint8_t cdb[16];
1618 uint8_t sense[64];
1619 } cdbSense;
1620
1621 struct mrsas_evtarg_ld ld;
1622
1623 struct {
1624 struct mrsas_evtarg_ld ld;
1625 uint64_t count;
1626 } ld_count;
1627
1628 struct {
1629 uint64_t lba;
1630 struct mrsas_evtarg_ld ld;
1631 } ld_lba;
1632
1633 struct {
1634 struct mrsas_evtarg_ld ld;
1635 uint32_t prevOwner;
1636 uint32_t newOwner;
1637 } ld_owner;
1638
1639 struct {
1640 uint64_t ld_lba;
1641 uint64_t pd_lba;
1642 struct mrsas_evtarg_ld ld;
1643 struct mrsas_evtarg_pd pd;
1644 } ld_lba_pd_lba;
1645
1646 struct {
1647 struct mrsas_evtarg_ld ld;
1648 struct mrsas_progress prog;
1649 } ld_prog;
1650
1651 struct {
1652 struct mrsas_evtarg_ld ld;
1653 uint32_t prev_state;
1654 uint32_t new_state;
1655 } ld_state;
1656
1657 struct {
1658 uint64_t strip;
1659 struct mrsas_evtarg_ld ld;
1660 } ld_strip;
1661
1662 struct mrsas_evtarg_pd pd;
1663
1664 struct {
1665 struct mrsas_evtarg_pd pd;
1666 uint32_t err;
1667 } pd_err;
1668
1669 struct {
1670 uint64_t lba;
1671 struct mrsas_evtarg_pd pd;
1672 } pd_lba;
1673
1674 struct {
1675 uint64_t lba;
1676 struct mrsas_evtarg_pd pd;
1677 struct mrsas_evtarg_ld ld;
1678 } pd_lba_ld;
1679
1680 struct {
1681 struct mrsas_evtarg_pd pd;
1682 struct mrsas_progress prog;
1683 } pd_prog;
1684
1685 struct {
1686 struct mrsas_evtarg_pd pd;
1687 uint32_t prevState;
1688 uint32_t newState;
1689 } pd_state;
1690
1691 struct {
1692 uint16_t vendorId;
1693 uint16_t deviceId;
1694 uint16_t subVendorId;
1695 uint16_t subDeviceId;
1696 } pci;
1697
1698 uint32_t rate;
1699 char str[96];
1700
1701 struct {
1702 uint32_t rtc;
1703 uint32_t elapsedSeconds;
1704 } time;
1705
1706 struct {
1707 uint32_t ecar;
1708 uint32_t elog;
1709 char str[64];
1710 } ecc;
1711
1712 mrsas_pd_address_t pd_addr;
1713
1714 uint8_t b[96];
1715 uint16_t s[48];
1716 uint32_t w[24];
1717 uint64_t d[12];
1718 } args;
1719
1720 char description[128];
1721
1722 };
1723
1724 /* only 63 are usable by the application */
1725 #define MAX_LOGICAL_DRIVES 64
1726 /* only 255 physical devices may be used */
1727 #define MAX_PHYSICAL_DEVICES 256
1728 #define MAX_PD_PER_ENCLOSURE 64
1729 /* maximum disks per array */
1730 #define MAX_ROW_SIZE 32
1731 /* maximum spans per logical drive */
1732 #define MAX_SPAN_DEPTH 8
1733 /* maximum number of arrays a hot spare may be dedicated to */
1734 #define MAX_ARRAYS_DEDICATED 16
1735 /* maximum number of arrays which may exist */
1736 #define MAX_ARRAYS 128
1737 /* maximum number of foreign configs that may ha managed at once */
1738 #define MAX_FOREIGN_CONFIGS 8
1739 /* maximum spares (global and dedicated combined) */
1740 #define MAX_SPARES_FOR_THE_CONTROLLER MAX_PHYSICAL_DEVICES
1741 /* maximum possible Target IDs (i.e. 0 to 63) */
1742 #define MAX_TARGET_ID 63
1743 /* maximum number of supported enclosures */
1744 #define MAX_ENCLOSURES 32
1745 /* maximum number of PHYs per controller */
1746 #define MAX_PHYS_PER_CONTROLLER 16
1747 /* maximum number of LDs per array (due to DDF limitations) */
1748 #define MAX_LDS_PER_ARRAY 16
1749
1750 /*
1751 * -----------------------------------------------------------------------------
1752 * -----------------------------------------------------------------------------
1753 *
1754 * Logical Drive commands
1755 *
1756 * -----------------------------------------------------------------------------
1757 * -----------------------------------------------------------------------------
1758 */
1759 #define MR_DCMD_LD 0x03000000, /* Logical Device (LD) opcodes */
1760
1761 /*
1762 * Input: dcmd.opcode - MR_DCMD_LD_GET_LIST
1763 * dcmd.mbox - reserved
1764 * dcmd.sge IN - ptr to returned MR_LD_LIST structure
1765 * Desc: Return the logical drive list structure
1766 * Status: No error
1767 */
1768
1769 /*
1770 * defines the logical drive reference structure
1771 */
1772 typedef union _MR_LD_REF { /* LD reference structure */
1773 struct {
1774 uint8_t targetId; /* LD target id (0 to MAX_TARGET_ID) */
1775 uint8_t reserved; /* reserved for in line with MR_PD_REF */
1776 uint16_t seqNum; /* Sequence Number */
1777 } ld_ref;
1778 uint32_t ref; /* shorthand reference to full 32-bits */
1779 } MR_LD_REF; /* 4 bytes */
1780
1781 /*
1782 * defines the logical drive list structure
1783 */
1784 typedef struct _MR_LD_LIST {
1785 uint32_t ldCount; /* number of LDs */
1786 uint32_t reserved; /* pad to 8-byte boundary */
1787 struct {
1788 MR_LD_REF ref; /* LD reference */
1789 uint8_t state; /* current LD state (MR_LD_STATE) */
1790 uint8_t reserved[3]; /* pad to 8-byte boundary */
1791 uint64_t size; /* LD size */
1792 } ldList[MAX_LOGICAL_DRIVES];
1793 } MR_LD_LIST;
1794
1795 struct mrsas_drv_ver {
1796 uint8_t signature[12];
1797 uint8_t os_name[16];
1798 uint8_t os_ver[12];
1799 uint8_t drv_name[20];
1800 uint8_t drv_ver[32];
1801 uint8_t drv_rel_date[20];
1802 };
1803
1804 #define PCI_TYPE0_ADDRESSES 6
1805 #define PCI_TYPE1_ADDRESSES 2
1806 #define PCI_TYPE2_ADDRESSES 5
1807
1808 struct mrsas_pci_common_header {
1809 uint16_t vendorID; /* (ro) */
1810 uint16_t deviceID; /* (ro) */
1811 uint16_t command; /* Device control */
1812 uint16_t status;
1813 uint8_t revisionID; /* (ro) */
1814 uint8_t progIf; /* (ro) */
1815 uint8_t subClass; /* (ro) */
1816 uint8_t baseClass; /* (ro) */
1817 uint8_t cacheLineSize; /* (ro+) */
1818 uint8_t latencyTimer; /* (ro+) */
1819 uint8_t headerType; /* (ro) */
1820 uint8_t bist; /* Built in self test */
1821
1822 union {
1823 struct {
1824 uint32_t baseAddresses[PCI_TYPE0_ADDRESSES];
1825 uint32_t cis;
1826 uint16_t subVendorID;
1827 uint16_t subSystemID;
1828 uint32_t romBaseAddress;
1829 uint8_t capabilitiesPtr;
1830 uint8_t reserved1[3];
1831 uint32_t reserved2;
1832 uint8_t interruptLine;
1833 uint8_t interruptPin; /* (ro) */
1834 uint8_t minimumGrant; /* (ro) */
1835 uint8_t maximumLatency; /* (ro) */
1836 } type_0;
1837
1838 struct {
1839 uint32_t baseAddresses[PCI_TYPE1_ADDRESSES];
1840 uint8_t primaryBus;
1841 uint8_t secondaryBus;
1842 uint8_t subordinateBus;
1843 uint8_t secondaryLatency;
1844 uint8_t ioBase;
1845 uint8_t ioLimit;
1846 uint16_t secondaryStatus;
1847 uint16_t memoryBase;
1848 uint16_t memoryLimit;
1849 uint16_t prefetchBase;
1850 uint16_t prefetchLimit;
1851 uint32_t prefetchBaseUpper32;
1852 uint32_t prefetchLimitUpper32;
1853 uint16_t ioBaseUpper16;
1854 uint16_t ioLimitUpper16;
1855 uint8_t capabilitiesPtr;
1856 uint8_t reserved1[3];
1857 uint32_t romBaseAddress;
1858 uint8_t interruptLine;
1859 uint8_t interruptPin;
1860 uint16_t bridgeControl;
1861 } type_1;
1862
1863 struct {
1864 uint32_t socketRegistersBaseAddress;
1865 uint8_t capabilitiesPtr;
1866 uint8_t reserved;
1867 uint16_t secondaryStatus;
1868 uint8_t primaryBus;
1869 uint8_t secondaryBus;
1870 uint8_t subordinateBus;
1871 uint8_t secondaryLatency;
1872 struct {
1873 uint32_t base;
1874 uint32_t limit;
1875 } range[PCI_TYPE2_ADDRESSES-1];
1876 uint8_t interruptLine;
1877 uint8_t interruptPin;
1878 uint16_t bridgeControl;
1879 } type_2;
1880 } header;
1881 };
1882
1883 struct mrsas_pci_link_capability {
1884 union {
1885 struct {
1886 uint32_t linkSpeed :4;
1887 uint32_t linkWidth :6;
1888 uint32_t aspmSupport :2;
1889 uint32_t losExitLatency :3;
1890 uint32_t l1ExitLatency :3;
1891 uint32_t rsvdp :6;
1892 uint32_t portNumber :8;
1893 } bits;
1894
1895 uint32_t asUlong;
1896 } cap;
1897
1898 };
1899
1900 struct mrsas_pci_link_status_capability {
1901 union {
1902 struct {
1903 uint16_t linkSpeed :4;
1904 uint16_t negotiatedLinkWidth :6;
1905 uint16_t linkTrainingError :1;
1906 uint16_t linkTraning :1;
1907 uint16_t slotClockConfig :1;
1908 uint16_t rsvdZ :3;
1909 } bits;
1910
1911 uint16_t asUshort;
1912 } stat_cap;
1913
1914 uint16_t reserved;
1915
1916 };
1917
1918 struct mrsas_pci_capabilities {
1919 struct mrsas_pci_link_capability linkCapability;
1920 struct mrsas_pci_link_status_capability linkStatusCapability;
1921 };
1922
1923 struct mrsas_pci_information
1924 {
1925 uint32_t busNumber;
1926 uint8_t deviceNumber;
1927 uint8_t functionNumber;
1928 uint8_t interruptVector;
1929 uint8_t reserved;
1930 struct mrsas_pci_common_header pciHeaderInfo;
1931 struct mrsas_pci_capabilities capability;
1932 uint8_t reserved2[32];
1933 };
1934
1935 struct mrsas_ioctl {
1936 uint16_t version;
1937 uint16_t controller_id;
1938 uint8_t signature[8];
1939 uint32_t reserved_1;
1940 uint32_t control_code;
1941 uint32_t reserved_2[2];
1942 uint8_t frame[64];
1943 union mrsas_sgl_frame sgl_frame;
1944 uint8_t sense_buff[MRSAS_MAX_SENSE_LENGTH];
1945 uint8_t data[1];
1946 };
1947
1948 struct mrsas_aen {
1949 uint16_t host_no;
1950 uint16_t cmd_status;
1951 uint32_t seq_num;
1952 uint32_t class_locale_word;
1953 };
1954
1955 #pragma pack()
1956
1957 #ifndef DDI_VENDOR_LSI
1958 #define DDI_VENDOR_LSI "LSI"
1959 #endif /* DDI_VENDOR_LSI */
1960
1961 int mrsas_config_scsi_device(struct mrsas_instance *,
1962 struct scsi_device *, dev_info_t **);
1963
1964 #ifdef PDSUPPORT
1965 int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t,
1966 uint8_t, dev_info_t **);
1967 #endif
1968
1969 dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, uint8_t);
1970 int mrsas_service_evt(struct mrsas_instance *, int, int, int, uint64_t);
1971 void return_raid_msg_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1972 struct mrsas_cmd *get_raid_msg_mfi_pkt(struct mrsas_instance *);
1973 void return_raid_msg_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1974
1975 int alloc_space_for_mpi2(struct mrsas_instance *);
1976 void fill_up_drv_ver(struct mrsas_drv_ver *dv);
1977
1978 int mrsas_issue_init_mpi2(struct mrsas_instance *);
1979 struct scsi_pkt *mrsas_tbolt_tran_init_pkt(struct scsi_address *, register
1980 struct scsi_pkt *, struct buf *, int, int, int, int,
1981 int (*)(), caddr_t);
1982 int mrsas_tbolt_tran_start(struct scsi_address *,
1983 register struct scsi_pkt *);
1984 uint32_t tbolt_read_fw_status_reg(struct mrsas_instance *);
1985 void tbolt_issue_cmd(struct mrsas_cmd *, struct mrsas_instance *);
1986 int tbolt_issue_cmd_in_poll_mode(struct mrsas_instance *,
1987 struct mrsas_cmd *);
1988 int tbolt_issue_cmd_in_sync_mode(struct mrsas_instance *,
1989 struct mrsas_cmd *);
1990 void tbolt_enable_intr(struct mrsas_instance *);
1991 void tbolt_disable_intr(struct mrsas_instance *);
1992 int tbolt_intr_ack(struct mrsas_instance *);
1993 uint_t mr_sas_tbolt_process_outstanding_cmd(struct mrsas_instance *);
1994 uint_t tbolt_softintr();
1995 int mrsas_tbolt_dma(struct mrsas_instance *, uint32_t, int, int (*)());
1996 int mrsas_check_dma_handle(ddi_dma_handle_t handle);
1997 int mrsas_check_acc_handle(ddi_acc_handle_t handle);
1998 int mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
1999 struct buf *, int, int (*)());
2000 int mrsas_dma_move(struct mrsas_instance *,
2001 struct scsi_pkt *, struct buf *);
2002 int mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
2003 uchar_t);
2004 void mr_sas_tbolt_build_mfi_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2005 int mrsas_dma_alloc_dmd(struct mrsas_instance *, dma_obj_t *);
2006 void tbolt_complete_cmd_in_sync_mode(struct mrsas_instance *,
2007 struct mrsas_cmd *);
2008 int alloc_req_rep_desc(struct mrsas_instance *);
2009 int mrsas_mode_sense_build(struct scsi_pkt *);
2010 void push_pending_mfi_pkt(struct mrsas_instance *,
2011 struct mrsas_cmd *);
2012 int mrsas_issue_pending_cmds(struct mrsas_instance *);
2013 int mrsas_print_pending_cmds(struct mrsas_instance *);
2014 int mrsas_complete_pending_cmds(struct mrsas_instance *);
2015
2016 int create_mfi_frame_pool(struct mrsas_instance *);
2017 void destroy_mfi_frame_pool(struct mrsas_instance *);
2018 int create_mfi_mpi_frame_pool(struct mrsas_instance *);
2019 void destroy_mfi_mpi_frame_pool(struct mrsas_instance *);
2020 int create_mpi2_frame_pool(struct mrsas_instance *);
2021 void destroy_mpi2_frame_pool(struct mrsas_instance *);
2022 int mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
2023 void mrsas_tbolt_free_additional_dma_buffer(struct mrsas_instance *);
2024 void free_req_desc_pool(struct mrsas_instance *);
2025 void free_space_for_mpi2(struct mrsas_instance *);
2026 void mrsas_dump_reply_desc(struct mrsas_instance *);
2027 void tbolt_complete_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2028 void display_scsi_inquiry(caddr_t);
2029 void service_mfi_aen(struct mrsas_instance *, struct mrsas_cmd *);
2030 int mrsas_mode_sense_build(struct scsi_pkt *);
2031 int mrsas_tbolt_get_ld_map_info(struct mrsas_instance *);
2032 struct mrsas_cmd *mrsas_tbolt_build_poll_cmd(struct mrsas_instance *,
2033 struct scsi_address *, struct scsi_pkt *, uchar_t *);
2034 int mrsas_tbolt_reset_ppc(struct mrsas_instance *instance);
2035 void mrsas_tbolt_kill_adapter(struct mrsas_instance *instance);
2036 int abort_syncmap_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2037 void mrsas_tbolt_prepare_cdb(struct mrsas_instance *instance, U8 cdb[],
2038 struct IO_REQUEST_INFO *, Mpi2RaidSCSIIORequest_t *, U32);
2039
2040
2041 int mrsas_init_adapter_ppc(struct mrsas_instance *instance);
2042 int mrsas_init_adapter_tbolt(struct mrsas_instance *instance);
2043 int mrsas_init_adapter(struct mrsas_instance *instance);
2044
2045 int mrsas_alloc_cmd_pool(struct mrsas_instance *instance);
2046 void mrsas_free_cmd_pool(struct mrsas_instance *instance);
2047
2048 void mrsas_print_cmd_details(struct mrsas_instance *, struct mrsas_cmd *, int);
2049 struct mrsas_cmd *get_raid_msg_pkt(struct mrsas_instance *);
2050
2051 int mfi_state_transition_to_ready(struct mrsas_instance *);
2052
2053 struct mrsas_cmd *mrsas_get_mfi_pkt(struct mrsas_instance *);
2054 void mrsas_return_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
2055
2056
2057 /* FMA functions. */
2058 int mrsas_common_check(struct mrsas_instance *, struct mrsas_cmd *);
2059 void mrsas_fm_ereport(struct mrsas_instance *, char *);
2060
2061
2062 #ifdef __cplusplus
2063 }
2064 #endif
2065
2066 #endif /* _MR_SAS_H_ */