1 /*
2 * mr_sas.c: source for mr_sas driver
3 *
4 * Solaris MegaRAID device driver for SAS2.0 controllers
5 * Copyright (c) 2008-2012, LSI Logic Corporation.
6 * All rights reserved.
7 *
8 * Version:
9 * Author:
10 * Swaminathan K S
11 * Arun Chandrashekhar
12 * Manju R
13 * Rasheed
14 * Shakeel Bukhari
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions are met:
18 *
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 *
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 *
26 * 3. Neither the name of the author nor the names of its contributors may be
27 * used to endorse or promote products derived from this software without
28 * specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41 * DAMAGE.
42 */
43
44 /*
45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
46 * Copyright (c) 2011 Bayard G. Bell. All rights reserved.
47 * Copyright 2012 Nexenta System, Inc. All rights reserved.
48 */
49
50 #include <sys/types.h>
51 #include <sys/param.h>
52 #include <sys/file.h>
53 #include <sys/errno.h>
54 #include <sys/open.h>
55 #include <sys/cred.h>
56 #include <sys/modctl.h>
57 #include <sys/conf.h>
58 #include <sys/devops.h>
59 #include <sys/cmn_err.h>
60 #include <sys/kmem.h>
61 #include <sys/stat.h>
62 #include <sys/mkdev.h>
63 #include <sys/pci.h>
64 #include <sys/scsi/scsi.h>
65 #include <sys/ddi.h>
66 #include <sys/sunddi.h>
67 #include <sys/atomic.h>
68 #include <sys/signal.h>
69 #include <sys/byteorder.h>
70 #include <sys/sdt.h>
71 #include <sys/fs/dv_node.h> /* devfs_clean */
72
73 #include "mr_sas.h"
74
75 /*
76 * FMA header files
77 */
78 #include <sys/ddifm.h>
79 #include <sys/fm/protocol.h>
80 #include <sys/fm/util.h>
81 #include <sys/fm/io/ddi.h>
82
83 /*
84 * Local static data
85 */
86 static void *mrsas_state = NULL;
87 static volatile boolean_t mrsas_relaxed_ordering = B_TRUE;
88 volatile int debug_level_g = CL_NONE;
89 static volatile int msi_enable = 1;
90 static volatile int ctio_enable = 1;
91
92 /* Default Timeout value to issue online controller reset */
93 volatile int debug_timeout_g = 0xF0; /* 0xB4; */
94 /* Simulate consecutive firmware fault */
95 static volatile int debug_fw_faults_after_ocr_g = 0;
96 #ifdef OCRDEBUG
97 /* Simulate three consecutive timeout for an IO */
98 static volatile int debug_consecutive_timeout_after_ocr_g = 0;
99 #endif
100
101 #pragma weak scsi_hba_open
102 #pragma weak scsi_hba_close
103 #pragma weak scsi_hba_ioctl
104
105 /* Local static prototypes. */
106 static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
107 static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t);
108 #ifdef __sparc
109 static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t);
110 #else
111 static int mrsas_quiesce(dev_info_t *);
112 #endif
113 static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t);
114 static int mrsas_open(dev_t *, int, int, cred_t *);
115 static int mrsas_close(dev_t, int, int, cred_t *);
116 static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
117
118 static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *,
119 scsi_hba_tran_t *, struct scsi_device *);
120 static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register
121 struct scsi_pkt *, struct buf *, int, int, int, int,
122 int (*)(), caddr_t);
123 static int mrsas_tran_start(struct scsi_address *,
124 register struct scsi_pkt *);
125 static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *);
126 static int mrsas_tran_reset(struct scsi_address *, int);
127 static int mrsas_tran_getcap(struct scsi_address *, char *, int);
128 static int mrsas_tran_setcap(struct scsi_address *, char *, int, int);
129 static void mrsas_tran_destroy_pkt(struct scsi_address *,
130 struct scsi_pkt *);
131 static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *);
132 static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *);
133 static int mrsas_tran_quiesce(dev_info_t *dip);
134 static int mrsas_tran_unquiesce(dev_info_t *dip);
135 static uint_t mrsas_isr();
136 static uint_t mrsas_softintr();
137 static void mrsas_undo_resources(dev_info_t *, struct mrsas_instance *);
138 static struct mrsas_cmd *get_mfi_pkt(struct mrsas_instance *);
139 static void return_mfi_pkt(struct mrsas_instance *,
140 struct mrsas_cmd *);
141
142 static void free_space_for_mfi(struct mrsas_instance *);
143 static uint32_t read_fw_status_reg_ppc(struct mrsas_instance *);
144 static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *);
145 static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *,
146 struct mrsas_cmd *);
147 static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *,
148 struct mrsas_cmd *);
149 static void enable_intr_ppc(struct mrsas_instance *);
150 static void disable_intr_ppc(struct mrsas_instance *);
151 static int intr_ack_ppc(struct mrsas_instance *);
152 static void flush_cache(struct mrsas_instance *instance);
153 void display_scsi_inquiry(caddr_t);
154 static int start_mfi_aen(struct mrsas_instance *instance);
155 static int handle_drv_ioctl(struct mrsas_instance *instance,
156 struct mrsas_ioctl *ioctl, int mode);
157 static int handle_mfi_ioctl(struct mrsas_instance *instance,
158 struct mrsas_ioctl *ioctl, int mode);
159 static int handle_mfi_aen(struct mrsas_instance *instance,
160 struct mrsas_aen *aen);
161 static struct mrsas_cmd *build_cmd(struct mrsas_instance *,
162 struct scsi_address *, struct scsi_pkt *, uchar_t *);
163 static int alloc_additional_dma_buffer(struct mrsas_instance *);
164 static void complete_cmd_in_sync_mode(struct mrsas_instance *,
165 struct mrsas_cmd *);
166 static int mrsas_kill_adapter(struct mrsas_instance *);
167 static int mrsas_issue_init_mfi(struct mrsas_instance *);
168 static int mrsas_reset_ppc(struct mrsas_instance *);
169 static uint32_t mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *);
170 static int wait_for_outstanding(struct mrsas_instance *instance);
171 static int register_mfi_aen(struct mrsas_instance *instance,
172 uint32_t seq_num, uint32_t class_locale_word);
173 static int issue_mfi_pthru(struct mrsas_instance *instance, struct
174 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
175 static int issue_mfi_dcmd(struct mrsas_instance *instance, struct
176 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
177 static int issue_mfi_smp(struct mrsas_instance *instance, struct
178 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
179 static int issue_mfi_stp(struct mrsas_instance *instance, struct
180 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
181 static int abort_aen_cmd(struct mrsas_instance *instance,
182 struct mrsas_cmd *cmd_to_abort);
183
184 static void mrsas_rem_intrs(struct mrsas_instance *instance);
185 static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type);
186
187 static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *,
188 scsi_hba_tran_t *, struct scsi_device *);
189 static int mrsas_tran_bus_config(dev_info_t *, uint_t,
190 ddi_bus_config_op_t, void *, dev_info_t **);
191 static int mrsas_parse_devname(char *, int *, int *);
192 static int mrsas_config_all_devices(struct mrsas_instance *);
193 static int mrsas_config_ld(struct mrsas_instance *, uint16_t,
194 uint8_t, dev_info_t **);
195 static int mrsas_name_node(dev_info_t *, char *, int);
196 static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *);
197 static void free_additional_dma_buffer(struct mrsas_instance *);
198 static void io_timeout_checker(void *);
199 static void mrsas_fm_init(struct mrsas_instance *);
200 static void mrsas_fm_fini(struct mrsas_instance *);
201
202 static struct mrsas_function_template mrsas_function_template_ppc = {
203 .read_fw_status_reg = read_fw_status_reg_ppc,
204 .issue_cmd = issue_cmd_ppc,
205 .issue_cmd_in_sync_mode = issue_cmd_in_sync_mode_ppc,
206 .issue_cmd_in_poll_mode = issue_cmd_in_poll_mode_ppc,
207 .enable_intr = enable_intr_ppc,
208 .disable_intr = disable_intr_ppc,
209 .intr_ack = intr_ack_ppc,
210 .init_adapter = mrsas_init_adapter_ppc
211 };
212
213
214 static struct mrsas_function_template mrsas_function_template_fusion = {
215 .read_fw_status_reg = tbolt_read_fw_status_reg,
216 .issue_cmd = tbolt_issue_cmd,
217 .issue_cmd_in_sync_mode = tbolt_issue_cmd_in_sync_mode,
218 .issue_cmd_in_poll_mode = tbolt_issue_cmd_in_poll_mode,
219 .enable_intr = tbolt_enable_intr,
220 .disable_intr = tbolt_disable_intr,
221 .intr_ack = tbolt_intr_ack,
222 .init_adapter = mrsas_init_adapter_tbolt
223 };
224
225
226 ddi_dma_attr_t mrsas_generic_dma_attr = {
227 DMA_ATTR_V0, /* dma_attr_version */
228 0, /* low DMA address range */
229 0xFFFFFFFFU, /* high DMA address range */
230 0xFFFFFFFFU, /* DMA counter register */
231 8, /* DMA address alignment */
232 0x07, /* DMA burstsizes */
233 1, /* min DMA size */
234 0xFFFFFFFFU, /* max DMA size */
235 0xFFFFFFFFU, /* segment boundary */
236 MRSAS_MAX_SGE_CNT, /* dma_attr_sglen */
237 512, /* granularity of device */
238 0 /* bus specific DMA flags */
239 };
240
241 int32_t mrsas_max_cap_maxxfer = 0x1000000;
242
243 /*
244 * Fix for: Thunderbolt controller IO timeout when IO write size is 1MEG,
245 * Limit size to 256K
246 */
247 uint32_t mrsas_tbolt_max_cap_maxxfer = (512 * 512);
248
249 /*
250 * cb_ops contains base level routines
251 */
252 static struct cb_ops mrsas_cb_ops = {
253 mrsas_open, /* open */
254 mrsas_close, /* close */
255 nodev, /* strategy */
256 nodev, /* print */
257 nodev, /* dump */
258 nodev, /* read */
259 nodev, /* write */
260 mrsas_ioctl, /* ioctl */
261 nodev, /* devmap */
262 nodev, /* mmap */
263 nodev, /* segmap */
264 nochpoll, /* poll */
265 nodev, /* cb_prop_op */
266 0, /* streamtab */
267 D_NEW | D_HOTPLUG, /* cb_flag */
268 CB_REV, /* cb_rev */
269 nodev, /* cb_aread */
270 nodev /* cb_awrite */
271 };
272
273 /*
274 * dev_ops contains configuration routines
275 */
276 static struct dev_ops mrsas_ops = {
277 DEVO_REV, /* rev, */
278 0, /* refcnt */
279 mrsas_getinfo, /* getinfo */
280 nulldev, /* identify */
281 nulldev, /* probe */
282 mrsas_attach, /* attach */
283 mrsas_detach, /* detach */
284 #ifdef __sparc
285 mrsas_reset, /* reset */
286 #else /* __sparc */
287 nodev,
288 #endif /* __sparc */
289 &mrsas_cb_ops, /* char/block ops */
290 NULL, /* bus ops */
291 NULL, /* power */
292 #ifdef __sparc
293 ddi_quiesce_not_needed
294 #else /* __sparc */
295 mrsas_quiesce /* quiesce */
296 #endif /* __sparc */
297 };
298
299 static struct modldrv modldrv = {
300 &mod_driverops, /* module type - driver */
301 MRSAS_VERSION,
302 &mrsas_ops, /* driver ops */
303 };
304
305 static struct modlinkage modlinkage = {
306 MODREV_1, /* ml_rev - must be MODREV_1 */
307 &modldrv, /* ml_linkage */
308 NULL /* end of driver linkage */
309 };
310
311 static struct ddi_device_acc_attr endian_attr = {
312 DDI_DEVICE_ATTR_V1,
313 DDI_STRUCTURE_LE_ACC,
314 DDI_STRICTORDER_ACC,
315 DDI_DEFAULT_ACC
316 };
317
318 /* Use the LSI Fast Path for the 2208 (tbolt) commands. */
319 unsigned int enable_fp = 1;
320
321
322 /*
323 * ************************************************************************** *
324 * *
325 * common entry points - for loadable kernel modules *
326 * *
327 * ************************************************************************** *
328 */
329
330 /*
331 * _init - initialize a loadable module
332 * @void
333 *
334 * The driver should perform any one-time resource allocation or data
335 * initialization during driver loading in _init(). For example, the driver
336 * should initialize any mutexes global to the driver in this routine.
337 * The driver should not, however, use _init() to allocate or initialize
338 * anything that has to do with a particular instance of the device.
339 * Per-instance initialization must be done in attach().
340 */
341 int
342 _init(void)
343 {
344 int ret;
345
346 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
347
348 ret = ddi_soft_state_init(&mrsas_state,
349 sizeof (struct mrsas_instance), 0);
350
351 if (ret != DDI_SUCCESS) {
352 cmn_err(CE_WARN, "mr_sas: could not init state");
353 return (ret);
354 }
355
356 if ((ret = scsi_hba_init(&modlinkage)) != DDI_SUCCESS) {
357 cmn_err(CE_WARN, "mr_sas: could not init scsi hba");
358 ddi_soft_state_fini(&mrsas_state);
359 return (ret);
360 }
361
362 ret = mod_install(&modlinkage);
363
364 if (ret != DDI_SUCCESS) {
365 cmn_err(CE_WARN, "mr_sas: mod_install failed");
366 scsi_hba_fini(&modlinkage);
367 ddi_soft_state_fini(&mrsas_state);
368 }
369
370 return (ret);
371 }
372
373 /*
374 * _info - returns information about a loadable module.
375 * @void
376 *
377 * _info() is called to return module information. This is a typical entry
378 * point that does predefined role. It simply calls mod_info().
379 */
380 int
381 _info(struct modinfo *modinfop)
382 {
383 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
384
385 return (mod_info(&modlinkage, modinfop));
386 }
387
388 /*
389 * _fini - prepare a loadable module for unloading
390 * @void
391 *
392 * In _fini(), the driver should release any resources that were allocated in
393 * _init(). The driver must remove itself from the system module list.
394 */
395 int
396 _fini(void)
397 {
398 int ret;
399
400 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
401
402 if ((ret = mod_remove(&modlinkage)) != DDI_SUCCESS) {
403 con_log(CL_ANN1,
404 (CE_WARN, "_fini: mod_remove() failed, error 0x%X", ret));
405 return (ret);
406 }
407
408 scsi_hba_fini(&modlinkage);
409 con_log(CL_DLEVEL1, (CE_NOTE, "_fini: scsi_hba_fini() done."));
410
411 ddi_soft_state_fini(&mrsas_state);
412 con_log(CL_DLEVEL1, (CE_NOTE, "_fini: ddi_soft_state_fini() done."));
413
414 return (ret);
415 }
416
417
418 /*
419 * ************************************************************************** *
420 * *
421 * common entry points - for autoconfiguration *
422 * *
423 * ************************************************************************** *
424 */
425 /*
426 * attach - adds a device to the system as part of initialization
427 * @dip:
428 * @cmd:
429 *
430 * The kernel calls a driver's attach() entry point to attach an instance of
431 * a device (for MegaRAID, it is instance of a controller) or to resume
432 * operation for an instance of a device that has been suspended or has been
433 * shut down by the power management framework
434 * The attach() entry point typically includes the following types of
435 * processing:
436 * - allocate a soft-state structure for the device instance (for MegaRAID,
437 * controller instance)
438 * - initialize per-instance mutexes
439 * - initialize condition variables
440 * - register the device's interrupts (for MegaRAID, controller's interrupts)
441 * - map the registers and memory of the device instance (for MegaRAID,
442 * controller instance)
443 * - create minor device nodes for the device instance (for MegaRAID,
444 * controller instance)
445 * - report that the device instance (for MegaRAID, controller instance) has
446 * attached
447 */
448 static int
449 mrsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
450 {
451 int instance_no;
452 int nregs;
453 int i = 0;
454 uint8_t irq;
455 uint16_t vendor_id;
456 uint16_t device_id;
457 uint16_t subsysvid;
458 uint16_t subsysid;
459 uint16_t command;
460 off_t reglength = 0;
461 int intr_types = 0;
462 char *data;
463
464 scsi_hba_tran_t *tran;
465 ddi_dma_attr_t tran_dma_attr;
466 struct mrsas_instance *instance;
467
468 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
469
470 /* CONSTCOND */
471 ASSERT(NO_COMPETING_THREADS);
472
473 instance_no = ddi_get_instance(dip);
474
475 /*
476 * check to see whether this device is in a DMA-capable slot.
477 */
478 if (ddi_slaveonly(dip) == DDI_SUCCESS) {
479 cmn_err(CE_WARN,
480 "mr_sas%d: Device in slave-only slot, unused",
481 instance_no);
482 return (DDI_FAILURE);
483 }
484
485 switch (cmd) {
486 case DDI_ATTACH:
487 /* allocate the soft state for the instance */
488 if (ddi_soft_state_zalloc(mrsas_state, instance_no)
489 != DDI_SUCCESS) {
490 cmn_err(CE_WARN,
491 "mr_sas%d: Failed to allocate soft state",
492 instance_no);
493 return (DDI_FAILURE);
494 }
495
496 instance = (struct mrsas_instance *)ddi_get_soft_state
497 (mrsas_state, instance_no);
498
499 if (instance == NULL) {
500 cmn_err(CE_WARN,
501 "mr_sas%d: Bad soft state", instance_no);
502 ddi_soft_state_free(mrsas_state, instance_no);
503 return (DDI_FAILURE);
504 }
505
506 instance->unroll.softs = 1;
507
508 /* Setup the PCI configuration space handles */
509 if (pci_config_setup(dip, &instance->pci_handle) !=
510 DDI_SUCCESS) {
511 cmn_err(CE_WARN,
512 "mr_sas%d: pci config setup failed ",
513 instance_no);
514
515 ddi_soft_state_free(mrsas_state, instance_no);
516 return (DDI_FAILURE);
517 }
518
519 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) {
520 cmn_err(CE_WARN,
521 "mr_sas: failed to get registers.");
522
523 pci_config_teardown(&instance->pci_handle);
524 ddi_soft_state_free(mrsas_state, instance_no);
525 return (DDI_FAILURE);
526 }
527
528 vendor_id = pci_config_get16(instance->pci_handle,
529 PCI_CONF_VENID);
530 device_id = pci_config_get16(instance->pci_handle,
531 PCI_CONF_DEVID);
532
533 subsysvid = pci_config_get16(instance->pci_handle,
534 PCI_CONF_SUBVENID);
535 subsysid = pci_config_get16(instance->pci_handle,
536 PCI_CONF_SUBSYSID);
537
538 pci_config_put16(instance->pci_handle, PCI_CONF_COMM,
539 (pci_config_get16(instance->pci_handle,
540 PCI_CONF_COMM) | PCI_COMM_ME));
541 irq = pci_config_get8(instance->pci_handle,
542 PCI_CONF_ILINE);
543
544 con_log(CL_DLEVEL1, (CE_CONT, "mr_sas%d: "
545 "0x%x:0x%x 0x%x:0x%x, irq:%d drv-ver:%s",
546 instance_no, vendor_id, device_id, subsysvid,
547 subsysid, irq, MRSAS_VERSION));
548
549 /* enable bus-mastering */
550 command = pci_config_get16(instance->pci_handle,
551 PCI_CONF_COMM);
552
553 if (!(command & PCI_COMM_ME)) {
554 command |= PCI_COMM_ME;
555
556 pci_config_put16(instance->pci_handle,
557 PCI_CONF_COMM, command);
558
559 con_log(CL_ANN, (CE_CONT, "mr_sas%d: "
560 "enable bus-mastering", instance_no));
561 } else {
562 con_log(CL_DLEVEL1, (CE_CONT, "mr_sas%d: "
563 "bus-mastering already set", instance_no));
564 }
565
566 /* initialize function pointers */
567 switch (device_id) {
568 case PCI_DEVICE_ID_LSI_TBOLT:
569 case PCI_DEVICE_ID_LSI_INVADER:
570 con_log(CL_ANN, (CE_NOTE,
571 "mr_sas: 2208 T.B. device detected"));
572
573 instance->func_ptr =
574 &mrsas_function_template_fusion;
575 instance->tbolt = 1;
576 break;
577
578 case PCI_DEVICE_ID_LSI_2108VDE:
579 case PCI_DEVICE_ID_LSI_2108V:
580 con_log(CL_ANN, (CE_NOTE,
581 "mr_sas: 2108 Liberator device detected"));
582
583 instance->func_ptr =
584 &mrsas_function_template_ppc;
585 break;
586
587 default:
588 cmn_err(CE_WARN,
589 "mr_sas: Invalid device detected");
590
591 pci_config_teardown(&instance->pci_handle);
592 ddi_soft_state_free(mrsas_state, instance_no);
593 return (DDI_FAILURE);
594 }
595
596 instance->baseaddress = pci_config_get32(
597 instance->pci_handle, PCI_CONF_BASE0);
598 instance->baseaddress &= 0x0fffc;
599
600 instance->dip = dip;
601 instance->vendor_id = vendor_id;
602 instance->device_id = device_id;
603 instance->subsysvid = subsysvid;
604 instance->subsysid = subsysid;
605 instance->instance = instance_no;
606
607 /* Initialize FMA */
608 instance->fm_capabilities = ddi_prop_get_int(
609 DDI_DEV_T_ANY, instance->dip, DDI_PROP_DONTPASS,
610 "fm-capable", DDI_FM_EREPORT_CAPABLE |
611 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE
612 | DDI_FM_ERRCB_CAPABLE);
613
614 mrsas_fm_init(instance);
615
616 /* Setup register map */
617 if ((ddi_dev_regsize(instance->dip,
618 REGISTER_SET_IO_2108, ®length) != DDI_SUCCESS) ||
619 reglength < MINIMUM_MFI_MEM_SZ) {
620 goto fail_attach;
621 }
622 if (reglength > DEFAULT_MFI_MEM_SZ) {
623 reglength = DEFAULT_MFI_MEM_SZ;
624 con_log(CL_DLEVEL1, (CE_NOTE,
625 "mr_sas: register length to map is 0x%lx bytes",
626 reglength));
627 }
628 if (ddi_regs_map_setup(instance->dip,
629 REGISTER_SET_IO_2108, &instance->regmap, 0,
630 reglength, &endian_attr, &instance->regmap_handle)
631 != DDI_SUCCESS) {
632 cmn_err(CE_WARN,
633 "mr_sas: couldn't map control registers");
634 goto fail_attach;
635 }
636
637 instance->unroll.regs = 1;
638
639 /*
640 * Disable Interrupt Now.
641 * Setup Software interrupt
642 */
643 instance->func_ptr->disable_intr(instance);
644
645 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0,
646 "mrsas-enable-msi", &data) == DDI_SUCCESS) {
647 if (strncmp(data, "no", 3) == 0) {
648 msi_enable = 0;
649 con_log(CL_ANN1, (CE_WARN,
650 "msi_enable = %d disabled", msi_enable));
651 }
652 ddi_prop_free(data);
653 }
654
655 con_log(CL_DLEVEL1, (CE_NOTE, "msi_enable = %d", msi_enable));
656
657 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0,
658 "mrsas-enable-fp", &data) == DDI_SUCCESS) {
659 if (strncmp(data, "no", 3) == 0) {
660 enable_fp = 0;
661 cmn_err(CE_NOTE,
662 "enable_fp = %d, Fast-Path disabled.\n",
663 enable_fp);
664 }
665
666 ddi_prop_free(data);
667 }
668
669 con_log(CL_DLEVEL1, (CE_NOTE, "enable_fp = %d\n", enable_fp));
670
671 /* Check for all supported interrupt types */
672 if (ddi_intr_get_supported_types(
673 dip, &intr_types) != DDI_SUCCESS) {
674 cmn_err(CE_WARN,
675 "ddi_intr_get_supported_types() failed");
676 goto fail_attach;
677 }
678
679 con_log(CL_DLEVEL1, (CE_NOTE,
680 "ddi_intr_get_supported_types() ret: 0x%x", intr_types));
681
682 /* Initialize and Setup Interrupt handler */
683 if (msi_enable && (intr_types & DDI_INTR_TYPE_MSIX)) {
684 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_MSIX) !=
685 DDI_SUCCESS) {
686 cmn_err(CE_WARN,
687 "MSIX interrupt query failed");
688 goto fail_attach;
689 }
690 instance->intr_type = DDI_INTR_TYPE_MSIX;
691 } else if (msi_enable && (intr_types & DDI_INTR_TYPE_MSI)) {
692 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_MSI) !=
693 DDI_SUCCESS) {
694 cmn_err(CE_WARN,
695 "MSI interrupt query failed");
696 goto fail_attach;
697 }
698 instance->intr_type = DDI_INTR_TYPE_MSI;
699 } else if (intr_types & DDI_INTR_TYPE_FIXED) {
700 msi_enable = 0;
701 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_FIXED) !=
702 DDI_SUCCESS) {
703 cmn_err(CE_WARN,
704 "FIXED interrupt query failed");
705 goto fail_attach;
706 }
707 instance->intr_type = DDI_INTR_TYPE_FIXED;
708 } else {
709 cmn_err(CE_WARN, "Device cannot "
710 "suppport either FIXED or MSI/X "
711 "interrupts");
712 goto fail_attach;
713 }
714
715 instance->unroll.intr = 1;
716
717 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0,
718 "mrsas-enable-ctio", &data) == DDI_SUCCESS) {
719 if (strncmp(data, "no", 3) == 0) {
720 ctio_enable = 0;
721 con_log(CL_ANN1, (CE_WARN,
722 "ctio_enable = %d disabled", ctio_enable));
723 }
724 ddi_prop_free(data);
725 }
726
727 con_log(CL_DLEVEL1, (CE_WARN, "ctio_enable = %d", ctio_enable));
728
729 /* setup the mfi based low level driver */
730 if (mrsas_init_adapter(instance) != DDI_SUCCESS) {
731 cmn_err(CE_WARN, "mr_sas: "
732 "could not initialize the low level driver");
733
734 goto fail_attach;
735 }
736
737 /* Initialize all Mutex */
738 INIT_LIST_HEAD(&instance->completed_pool_list);
739 mutex_init(&instance->completed_pool_mtx, NULL,
740 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
741
742 mutex_init(&instance->sync_map_mtx, NULL,
743 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
744
745 mutex_init(&instance->app_cmd_pool_mtx, NULL,
746 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
747
748 mutex_init(&instance->config_dev_mtx, NULL,
749 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
750
751 mutex_init(&instance->cmd_pend_mtx, NULL,
752 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
753
754 mutex_init(&instance->ocr_flags_mtx, NULL,
755 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
756
757 mutex_init(&instance->int_cmd_mtx, NULL,
758 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
759 cv_init(&instance->int_cmd_cv, NULL, CV_DRIVER, NULL);
760
761 mutex_init(&instance->cmd_pool_mtx, NULL,
762 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
763
764 mutex_init(&instance->reg_write_mtx, NULL,
765 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
766
767 if (instance->tbolt) {
768 mutex_init(&instance->cmd_app_pool_mtx, NULL,
769 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
770
771 mutex_init(&instance->chip_mtx, NULL,
772 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
773
774 }
775
776 instance->unroll.mutexs = 1;
777
778 instance->timeout_id = (timeout_id_t)-1;
779
780 /* Register our soft-isr for highlevel interrupts. */
781 instance->isr_level = instance->intr_pri;
782 if (!(instance->tbolt)) {
783 if (instance->isr_level == HIGH_LEVEL_INTR) {
784 if (ddi_add_softintr(dip,
785 DDI_SOFTINT_HIGH,
786 &instance->soft_intr_id, NULL, NULL,
787 mrsas_softintr, (caddr_t)instance) !=
788 DDI_SUCCESS) {
789 cmn_err(CE_WARN,
790 "Software ISR did not register");
791
792 goto fail_attach;
793 }
794
795 instance->unroll.soft_isr = 1;
796
797 }
798 }
799
800 instance->softint_running = 0;
801
802 /* Allocate a transport structure */
803 tran = scsi_hba_tran_alloc(dip, SCSI_HBA_CANSLEEP);
804
805 if (tran == NULL) {
806 cmn_err(CE_WARN,
807 "scsi_hba_tran_alloc failed");
808 goto fail_attach;
809 }
810
811 instance->tran = tran;
812 instance->unroll.tran = 1;
813
814 tran->tran_hba_private = instance;
815 tran->tran_tgt_init = mrsas_tran_tgt_init;
816 tran->tran_tgt_probe = scsi_hba_probe;
817 tran->tran_tgt_free = mrsas_tran_tgt_free;
818 if (instance->tbolt) {
819 tran->tran_init_pkt =
820 mrsas_tbolt_tran_init_pkt;
821 tran->tran_start =
822 mrsas_tbolt_tran_start;
823 } else {
824 tran->tran_init_pkt = mrsas_tran_init_pkt;
825 tran->tran_start = mrsas_tran_start;
826 }
827 tran->tran_abort = mrsas_tran_abort;
828 tran->tran_reset = mrsas_tran_reset;
829 tran->tran_getcap = mrsas_tran_getcap;
830 tran->tran_setcap = mrsas_tran_setcap;
831 tran->tran_destroy_pkt = mrsas_tran_destroy_pkt;
832 tran->tran_dmafree = mrsas_tran_dmafree;
833 tran->tran_sync_pkt = mrsas_tran_sync_pkt;
834 tran->tran_quiesce = mrsas_tran_quiesce;
835 tran->tran_unquiesce = mrsas_tran_unquiesce;
836 tran->tran_bus_config = mrsas_tran_bus_config;
837
838 if (mrsas_relaxed_ordering)
839 mrsas_generic_dma_attr.dma_attr_flags |=
840 DDI_DMA_RELAXED_ORDERING;
841
842
843 tran_dma_attr = mrsas_generic_dma_attr;
844 tran_dma_attr.dma_attr_sgllen = instance->max_num_sge;
845
846 /* Attach this instance of the hba */
847 if (scsi_hba_attach_setup(dip, &tran_dma_attr, tran, 0)
848 != DDI_SUCCESS) {
849 cmn_err(CE_WARN,
850 "scsi_hba_attach failed");
851
852 goto fail_attach;
853 }
854 instance->unroll.tranSetup = 1;
855 con_log(CL_ANN1,
856 (CE_CONT, "scsi_hba_attach_setup() done."));
857
858 /* create devctl node for cfgadm command */
859 if (ddi_create_minor_node(dip, "devctl",
860 S_IFCHR, INST2DEVCTL(instance_no),
861 DDI_NT_SCSI_NEXUS, 0) == DDI_FAILURE) {
862 cmn_err(CE_WARN,
863 "mr_sas: failed to create devctl node.");
864
865 goto fail_attach;
866 }
867
868 instance->unroll.devctl = 1;
869
870 /* create scsi node for cfgadm command */
871 if (ddi_create_minor_node(dip, "scsi", S_IFCHR,
872 INST2SCSI(instance_no), DDI_NT_SCSI_ATTACHMENT_POINT, 0) ==
873 DDI_FAILURE) {
874 cmn_err(CE_WARN,
875 "mr_sas: failed to create scsi node.");
876
877 goto fail_attach;
878 }
879
880 instance->unroll.scsictl = 1;
881
882 (void) sprintf(instance->iocnode, "%d:lsirdctl",
883 instance_no);
884
885 /*
886 * Create a node for applications
887 * for issuing ioctl to the driver.
888 */
889 if (ddi_create_minor_node(dip, instance->iocnode,
890 S_IFCHR, INST2LSIRDCTL(instance_no), DDI_PSEUDO, 0) ==
891 DDI_FAILURE) {
892 cmn_err(CE_WARN,
893 "mr_sas: failed to create ioctl node.");
894
895 goto fail_attach;
896 }
897
898 instance->unroll.ioctl = 1;
899
900 /* Create a taskq to handle dr events */
901 if ((instance->taskq = ddi_taskq_create(dip,
902 "mrsas_dr_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
903 cmn_err(CE_WARN,
904 "mr_sas: failed to create taskq ");
905 instance->taskq = NULL;
906 goto fail_attach;
907 }
908 instance->unroll.taskq = 1;
909 con_log(CL_ANN1, (CE_CONT, "ddi_taskq_create() done."));
910
911 /* enable interrupt */
912 instance->func_ptr->enable_intr(instance);
913
914 /* initiate AEN */
915 if (start_mfi_aen(instance)) {
916 cmn_err(CE_WARN,
917 "mr_sas: failed to initiate AEN.");
918 goto fail_attach;
919 }
920 instance->unroll.aenPend = 1;
921 con_log(CL_ANN1,
922 (CE_CONT, "AEN started for instance %d.", instance_no));
923
924 /* Finally! We are on the air. */
925 ddi_report_dev(dip);
926
927 /* FMA handle checking. */
928 if (mrsas_check_acc_handle(instance->regmap_handle) !=
929 DDI_SUCCESS) {
930 goto fail_attach;
931 }
932 if (mrsas_check_acc_handle(instance->pci_handle) !=
933 DDI_SUCCESS) {
934 goto fail_attach;
935 }
936
937 instance->mr_ld_list =
938 kmem_zalloc(MRDRV_MAX_LD * sizeof (struct mrsas_ld),
939 KM_SLEEP);
940 instance->unroll.ldlist_buff = 1;
941
942 #ifdef PDSUPPORT
943 if (instance->tbolt) {
944 instance->mr_tbolt_pd_max = MRSAS_TBOLT_PD_TGT_MAX;
945 instance->mr_tbolt_pd_list =
946 kmem_zalloc(MRSAS_TBOLT_GET_PD_MAX(instance) *
947 sizeof (struct mrsas_tbolt_pd), KM_SLEEP);
948 ASSERT(instance->mr_tbolt_pd_list);
949 for (i = 0; i < instance->mr_tbolt_pd_max; i++) {
950 instance->mr_tbolt_pd_list[i].lun_type =
951 MRSAS_TBOLT_PD_LUN;
952 instance->mr_tbolt_pd_list[i].dev_id =
953 (uint8_t)i;
954 }
955
956 instance->unroll.pdlist_buff = 1;
957 }
958 #endif
959 break;
960 case DDI_PM_RESUME:
961 con_log(CL_ANN, (CE_NOTE, "mr_sas: DDI_PM_RESUME"));
962 break;
963 case DDI_RESUME:
964 con_log(CL_ANN, (CE_NOTE, "mr_sas: DDI_RESUME"));
965 break;
966 default:
967 con_log(CL_ANN,
968 (CE_WARN, "mr_sas: invalid attach cmd=%x", cmd));
969 return (DDI_FAILURE);
970 }
971
972
973 con_log(CL_DLEVEL1,
974 (CE_NOTE, "mrsas_attach() return SUCCESS instance_num %d",
975 instance_no));
976 return (DDI_SUCCESS);
977
978 fail_attach:
979
980 mrsas_undo_resources(dip, instance);
981
982 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE);
983 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
984
985 mrsas_fm_fini(instance);
986
987 pci_config_teardown(&instance->pci_handle);
988 ddi_soft_state_free(mrsas_state, instance_no);
989
990 con_log(CL_ANN, (CE_WARN, "mr_sas: return failure from mrsas_attach"));
991
992 cmn_err(CE_WARN, "mrsas_attach() return FAILURE instance_num %d",
993 instance_no);
994
995 return (DDI_FAILURE);
996 }
997
998 /*
999 * getinfo - gets device information
1000 * @dip:
1001 * @cmd:
1002 * @arg:
1003 * @resultp:
1004 *
1005 * The system calls getinfo() to obtain configuration information that only
1006 * the driver knows. The mapping of minor numbers to device instance is
1007 * entirely under the control of the driver. The system sometimes needs to ask
1008 * the driver which device a particular dev_t represents.
1009 * Given the device number return the devinfo pointer from the scsi_device
1010 * structure.
1011 */
1012 /*ARGSUSED*/
1013 static int
1014 mrsas_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **resultp)
1015 {
1016 int rval;
1017 int mrsas_minor = getminor((dev_t)arg);
1018
1019 struct mrsas_instance *instance;
1020
1021 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1022
1023 switch (cmd) {
1024 case DDI_INFO_DEVT2DEVINFO:
1025 instance = (struct mrsas_instance *)
1026 ddi_get_soft_state(mrsas_state,
1027 MINOR2INST(mrsas_minor));
1028
1029 if (instance == NULL) {
1030 *resultp = NULL;
1031 rval = DDI_FAILURE;
1032 } else {
1033 *resultp = instance->dip;
1034 rval = DDI_SUCCESS;
1035 }
1036 break;
1037 case DDI_INFO_DEVT2INSTANCE:
1038 *resultp = (void *)(intptr_t)
1039 (MINOR2INST(getminor((dev_t)arg)));
1040 rval = DDI_SUCCESS;
1041 break;
1042 default:
1043 *resultp = NULL;
1044 rval = DDI_FAILURE;
1045 }
1046
1047 return (rval);
1048 }
1049
1050 /*
1051 * detach - detaches a device from the system
1052 * @dip: pointer to the device's dev_info structure
1053 * @cmd: type of detach
1054 *
1055 * A driver's detach() entry point is called to detach an instance of a device
1056 * that is bound to the driver. The entry point is called with the instance of
1057 * the device node to be detached and with DDI_DETACH, which is specified as
1058 * the cmd argument to the entry point.
1059 * This routine is called during driver unload. We free all the allocated
1060 * resources and call the corresponding LLD so that it can also release all
1061 * its resources.
1062 */
1063 static int
1064 mrsas_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
1065 {
1066 int instance_no;
1067
1068 struct mrsas_instance *instance;
1069
1070 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1071
1072
1073 /* CONSTCOND */
1074 ASSERT(NO_COMPETING_THREADS);
1075
1076 instance_no = ddi_get_instance(dip);
1077
1078 instance = (struct mrsas_instance *)ddi_get_soft_state(mrsas_state,
1079 instance_no);
1080
1081 if (!instance) {
1082 cmn_err(CE_WARN,
1083 "mr_sas:%d could not get instance in detach",
1084 instance_no);
1085
1086 return (DDI_FAILURE);
1087 }
1088
1089 con_log(CL_ANN, (CE_NOTE,
1090 "mr_sas%d: detaching device 0x%4x:0x%4x:0x%4x:0x%4x",
1091 instance_no, instance->vendor_id, instance->device_id,
1092 instance->subsysvid, instance->subsysid));
1093
1094 switch (cmd) {
1095 case DDI_DETACH:
1096 con_log(CL_ANN, (CE_NOTE,
1097 "mrsas_detach: DDI_DETACH"));
1098
1099 mutex_enter(&instance->config_dev_mtx);
1100 if (instance->timeout_id != (timeout_id_t)-1) {
1101 mutex_exit(&instance->config_dev_mtx);
1102 (void) untimeout(instance->timeout_id);
1103 instance->timeout_id = (timeout_id_t)-1;
1104 mutex_enter(&instance->config_dev_mtx);
1105 instance->unroll.timer = 0;
1106 }
1107 mutex_exit(&instance->config_dev_mtx);
1108
1109 if (instance->unroll.tranSetup == 1) {
1110 if (scsi_hba_detach(dip) != DDI_SUCCESS) {
1111 cmn_err(CE_WARN,
1112 "mr_sas2%d: failed to detach",
1113 instance_no);
1114 return (DDI_FAILURE);
1115 }
1116 instance->unroll.tranSetup = 0;
1117 con_log(CL_ANN1,
1118 (CE_CONT, "scsi_hba_dettach() done."));
1119 }
1120
1121 flush_cache(instance);
1122
1123 mrsas_undo_resources(dip, instance);
1124
1125 mrsas_fm_fini(instance);
1126
1127 pci_config_teardown(&instance->pci_handle);
1128 ddi_soft_state_free(mrsas_state, instance_no);
1129 break;
1130
1131 case DDI_PM_SUSPEND:
1132 con_log(CL_ANN, (CE_NOTE,
1133 "mrsas_detach: DDI_PM_SUSPEND"));
1134
1135 break;
1136 case DDI_SUSPEND:
1137 con_log(CL_ANN, (CE_NOTE,
1138 "mrsas_detach: DDI_SUSPEND"));
1139
1140 break;
1141 default:
1142 con_log(CL_ANN, (CE_WARN,
1143 "invalid detach command:0x%x", cmd));
1144 return (DDI_FAILURE);
1145 }
1146
1147 return (DDI_SUCCESS);
1148 }
1149
1150
1151 static void
1152 mrsas_undo_resources(dev_info_t *dip, struct mrsas_instance *instance)
1153 {
1154 int instance_no;
1155
1156 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1157
1158
1159 instance_no = ddi_get_instance(dip);
1160
1161
1162 if (instance->unroll.ioctl == 1) {
1163 ddi_remove_minor_node(dip, instance->iocnode);
1164 instance->unroll.ioctl = 0;
1165 }
1166
1167 if (instance->unroll.scsictl == 1) {
1168 ddi_remove_minor_node(dip, "scsi");
1169 instance->unroll.scsictl = 0;
1170 }
1171
1172 if (instance->unroll.devctl == 1) {
1173 ddi_remove_minor_node(dip, "devctl");
1174 instance->unroll.devctl = 0;
1175 }
1176
1177 if (instance->unroll.tranSetup == 1) {
1178 if (scsi_hba_detach(dip) != DDI_SUCCESS) {
1179 cmn_err(CE_WARN,
1180 "mr_sas2%d: failed to detach", instance_no);
1181 return; /* DDI_FAILURE */
1182 }
1183 instance->unroll.tranSetup = 0;
1184 con_log(CL_ANN1, (CE_CONT, "scsi_hba_dettach() done."));
1185 }
1186
1187 if (instance->unroll.tran == 1) {
1188 scsi_hba_tran_free(instance->tran);
1189 instance->unroll.tran = 0;
1190 con_log(CL_ANN1, (CE_CONT, "scsi_hba_tran_free() done."));
1191 }
1192
1193 if (instance->unroll.syncCmd == 1) {
1194 if (instance->tbolt) {
1195 if (abort_syncmap_cmd(instance,
1196 instance->map_update_cmd)) {
1197 cmn_err(CE_WARN, "mrsas_detach: "
1198 "failed to abort previous syncmap command");
1199 }
1200
1201 instance->unroll.syncCmd = 0;
1202 con_log(CL_ANN1, (CE_CONT, "sync cmd aborted, done."));
1203 }
1204 }
1205
1206 if (instance->unroll.aenPend == 1) {
1207 if (abort_aen_cmd(instance, instance->aen_cmd))
1208 cmn_err(CE_WARN, "mrsas_detach: "
1209 "failed to abort prevous AEN command");
1210
1211 instance->unroll.aenPend = 0;
1212 con_log(CL_ANN1, (CE_CONT, "aen cmd aborted, done."));
1213 /* This means the controller is fully initialized and running */
1214 /* Shutdown should be a last command to controller. */
1215 /* shutdown_controller(); */
1216 }
1217
1218
1219 if (instance->unroll.timer == 1) {
1220 if (instance->timeout_id != (timeout_id_t)-1) {
1221 (void) untimeout(instance->timeout_id);
1222 instance->timeout_id = (timeout_id_t)-1;
1223
1224 instance->unroll.timer = 0;
1225 }
1226 }
1227
1228 instance->func_ptr->disable_intr(instance);
1229
1230
1231 if (instance->unroll.mutexs == 1) {
1232 mutex_destroy(&instance->cmd_pool_mtx);
1233 mutex_destroy(&instance->app_cmd_pool_mtx);
1234 mutex_destroy(&instance->cmd_pend_mtx);
1235 mutex_destroy(&instance->completed_pool_mtx);
1236 mutex_destroy(&instance->sync_map_mtx);
1237 mutex_destroy(&instance->int_cmd_mtx);
1238 cv_destroy(&instance->int_cmd_cv);
1239 mutex_destroy(&instance->config_dev_mtx);
1240 mutex_destroy(&instance->ocr_flags_mtx);
1241 mutex_destroy(&instance->reg_write_mtx);
1242
1243 if (instance->tbolt) {
1244 mutex_destroy(&instance->cmd_app_pool_mtx);
1245 mutex_destroy(&instance->chip_mtx);
1246 }
1247
1248 instance->unroll.mutexs = 0;
1249 con_log(CL_ANN1, (CE_CONT, "Destroy mutex & cv, done."));
1250 }
1251
1252
1253 if (instance->unroll.soft_isr == 1) {
1254 ddi_remove_softintr(instance->soft_intr_id);
1255 instance->unroll.soft_isr = 0;
1256 }
1257
1258 if (instance->unroll.intr == 1) {
1259 mrsas_rem_intrs(instance);
1260 instance->unroll.intr = 0;
1261 }
1262
1263
1264 if (instance->unroll.taskq == 1) {
1265 if (instance->taskq) {
1266 ddi_taskq_destroy(instance->taskq);
1267 instance->unroll.taskq = 0;
1268 }
1269
1270 }
1271
1272 /*
1273 * free dma memory allocated for
1274 * cmds/frames/queues/driver version etc
1275 */
1276 if (instance->unroll.verBuff == 1) {
1277 (void) mrsas_free_dma_obj(instance, instance->drv_ver_dma_obj);
1278 instance->unroll.verBuff = 0;
1279 }
1280
1281 if (instance->unroll.pdlist_buff == 1) {
1282 if (instance->mr_tbolt_pd_list != NULL) {
1283 kmem_free(instance->mr_tbolt_pd_list,
1284 MRSAS_TBOLT_GET_PD_MAX(instance) *
1285 sizeof (struct mrsas_tbolt_pd));
1286 }
1287
1288 instance->mr_tbolt_pd_list = NULL;
1289 instance->unroll.pdlist_buff = 0;
1290 }
1291
1292 if (instance->unroll.ldlist_buff == 1) {
1293 if (instance->mr_ld_list != NULL) {
1294 kmem_free(instance->mr_ld_list, MRDRV_MAX_LD
1295 * sizeof (struct mrsas_ld));
1296 }
1297
1298 instance->mr_ld_list = NULL;
1299 instance->unroll.ldlist_buff = 0;
1300 }
1301
1302 if (instance->tbolt) {
1303 if (instance->unroll.alloc_space_mpi2 == 1) {
1304 free_space_for_mpi2(instance);
1305 instance->unroll.alloc_space_mpi2 = 0;
1306 }
1307 } else {
1308 if (instance->unroll.alloc_space_mfi == 1) {
1309 free_space_for_mfi(instance);
1310 instance->unroll.alloc_space_mfi = 0;
1311 }
1312 }
1313
1314 if (instance->unroll.regs == 1) {
1315 ddi_regs_map_free(&instance->regmap_handle);
1316 instance->unroll.regs = 0;
1317 con_log(CL_ANN1, (CE_CONT, "ddi_regs_map_free() done."));
1318 }
1319 }
1320
1321
1322
1323 /*
1324 * ************************************************************************** *
1325 * *
1326 * common entry points - for character driver types *
1327 * *
1328 * ************************************************************************** *
1329 */
1330 /*
1331 * open - gets access to a device
1332 * @dev:
1333 * @openflags:
1334 * @otyp:
1335 * @credp:
1336 *
1337 * Access to a device by one or more application programs is controlled
1338 * through the open() and close() entry points. The primary function of
1339 * open() is to verify that the open request is allowed.
1340 */
1341 static int
1342 mrsas_open(dev_t *dev, int openflags, int otyp, cred_t *credp)
1343 {
1344 int rval = 0;
1345
1346 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1347
1348 /* Check root permissions */
1349 if (drv_priv(credp) != 0) {
1350 con_log(CL_ANN, (CE_WARN,
1351 "mr_sas: Non-root ioctl access denied!"));
1352 return (EPERM);
1353 }
1354
1355 /* Verify we are being opened as a character device */
1356 if (otyp != OTYP_CHR) {
1357 con_log(CL_ANN, (CE_WARN,
1358 "mr_sas: ioctl node must be a char node"));
1359 return (EINVAL);
1360 }
1361
1362 if (ddi_get_soft_state(mrsas_state, MINOR2INST(getminor(*dev)))
1363 == NULL) {
1364 return (ENXIO);
1365 }
1366
1367 if (scsi_hba_open) {
1368 rval = scsi_hba_open(dev, openflags, otyp, credp);
1369 }
1370
1371 return (rval);
1372 }
1373
1374 /*
1375 * close - gives up access to a device
1376 * @dev:
1377 * @openflags:
1378 * @otyp:
1379 * @credp:
1380 *
1381 * close() should perform any cleanup necessary to finish using the minor
1382 * device, and prepare the device (and driver) to be opened again.
1383 */
1384 static int
1385 mrsas_close(dev_t dev, int openflags, int otyp, cred_t *credp)
1386 {
1387 int rval = 0;
1388
1389 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1390
1391 /* no need for locks! */
1392
1393 if (scsi_hba_close) {
1394 rval = scsi_hba_close(dev, openflags, otyp, credp);
1395 }
1396
1397 return (rval);
1398 }
1399
1400 /*
1401 * ioctl - performs a range of I/O commands for character drivers
1402 * @dev:
1403 * @cmd:
1404 * @arg:
1405 * @mode:
1406 * @credp:
1407 * @rvalp:
1408 *
1409 * ioctl() routine must make sure that user data is copied into or out of the
1410 * kernel address space explicitly using copyin(), copyout(), ddi_copyin(),
1411 * and ddi_copyout(), as appropriate.
1412 * This is a wrapper routine to serialize access to the actual ioctl routine.
1413 * ioctl() should return 0 on success, or the appropriate error number. The
1414 * driver may also set the value returned to the calling process through rvalp.
1415 */
1416
1417 static int
1418 mrsas_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
1419 int *rvalp)
1420 {
1421 int rval = 0;
1422
1423 struct mrsas_instance *instance;
1424 struct mrsas_ioctl *ioctl;
1425 struct mrsas_aen aen;
1426 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1427
1428 instance = ddi_get_soft_state(mrsas_state, MINOR2INST(getminor(dev)));
1429
1430 if (instance == NULL) {
1431 /* invalid minor number */
1432 con_log(CL_ANN, (CE_WARN, "mr_sas: adapter not found."));
1433 return (ENXIO);
1434 }
1435
1436 ioctl = (struct mrsas_ioctl *)kmem_zalloc(sizeof (struct mrsas_ioctl),
1437 KM_SLEEP);
1438 ASSERT(ioctl);
1439
1440 switch ((uint_t)cmd) {
1441 case MRSAS_IOCTL_FIRMWARE:
1442 if (ddi_copyin((void *)arg, ioctl,
1443 sizeof (struct mrsas_ioctl), mode)) {
1444 con_log(CL_ANN, (CE_WARN, "mrsas_ioctl: "
1445 "ERROR IOCTL copyin"));
1446 kmem_free(ioctl, sizeof (struct mrsas_ioctl));
1447 return (EFAULT);
1448 }
1449
1450 if (ioctl->control_code == MRSAS_DRIVER_IOCTL_COMMON) {
1451 rval = handle_drv_ioctl(instance, ioctl, mode);
1452 } else {
1453 rval = handle_mfi_ioctl(instance, ioctl, mode);
1454 }
1455
1456 if (ddi_copyout((void *)ioctl, (void *)arg,
1457 (sizeof (struct mrsas_ioctl) - 1), mode)) {
1458 con_log(CL_ANN, (CE_WARN,
1459 "mrsas_ioctl: copy_to_user failed"));
1460 rval = 1;
1461 }
1462
1463 break;
1464 case MRSAS_IOCTL_AEN:
1465 if (ddi_copyin((void *) arg, &aen,
1466 sizeof (struct mrsas_aen), mode)) {
1467 con_log(CL_ANN, (CE_WARN,
1468 "mrsas_ioctl: ERROR AEN copyin"));
1469 kmem_free(ioctl, sizeof (struct mrsas_ioctl));
1470 return (EFAULT);
1471 }
1472
1473 rval = handle_mfi_aen(instance, &aen);
1474
1475 if (ddi_copyout((void *) &aen, (void *)arg,
1476 sizeof (struct mrsas_aen), mode)) {
1477 con_log(CL_ANN, (CE_WARN,
1478 "mrsas_ioctl: copy_to_user failed"));
1479 rval = 1;
1480 }
1481
1482 break;
1483 default:
1484 rval = scsi_hba_ioctl(dev, cmd, arg,
1485 mode, credp, rvalp);
1486
1487 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_ioctl: "
1488 "scsi_hba_ioctl called, ret = %x.", rval));
1489 }
1490
1491 kmem_free(ioctl, sizeof (struct mrsas_ioctl));
1492 return (rval);
1493 }
1494
1495 /*
1496 * ************************************************************************** *
1497 * *
1498 * common entry points - for block driver types *
1499 * *
1500 * ************************************************************************** *
1501 */
1502 #ifdef __sparc
1503 /*
1504 * reset - TBD
1505 * @dip:
1506 * @cmd:
1507 *
1508 * TBD
1509 */
1510 /*ARGSUSED*/
1511 static int
1512 mrsas_reset(dev_info_t *dip, ddi_reset_cmd_t cmd)
1513 {
1514 int instance_no;
1515
1516 struct mrsas_instance *instance;
1517
1518 instance_no = ddi_get_instance(dip);
1519 instance = (struct mrsas_instance *)ddi_get_soft_state
1520 (mrsas_state, instance_no);
1521
1522 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1523
1524 if (!instance) {
1525 con_log(CL_ANN, (CE_WARN, "mr_sas:%d could not get adapter "
1526 "in reset", instance_no));
1527 return (DDI_FAILURE);
1528 }
1529
1530 instance->func_ptr->disable_intr(instance);
1531
1532 con_log(CL_ANN1, (CE_CONT, "flushing cache for instance %d",
1533 instance_no));
1534
1535 flush_cache(instance);
1536
1537 return (DDI_SUCCESS);
1538 }
1539 #else /* __sparc */
1540 /*ARGSUSED*/
1541 static int
1542 mrsas_quiesce(dev_info_t *dip)
1543 {
1544 int instance_no;
1545
1546 struct mrsas_instance *instance;
1547
1548 instance_no = ddi_get_instance(dip);
1549 instance = (struct mrsas_instance *)ddi_get_soft_state
1550 (mrsas_state, instance_no);
1551
1552 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1553
1554 if (!instance) {
1555 con_log(CL_ANN1, (CE_WARN, "mr_sas:%d could not get adapter "
1556 "in quiesce", instance_no));
1557 return (DDI_FAILURE);
1558 }
1559 if (instance->deadadapter || instance->adapterresetinprogress) {
1560 con_log(CL_ANN1, (CE_WARN, "mr_sas:%d adapter is not in "
1561 "healthy state", instance_no));
1562 return (DDI_FAILURE);
1563 }
1564
1565 if (abort_aen_cmd(instance, instance->aen_cmd)) {
1566 con_log(CL_ANN1, (CE_WARN, "mrsas_quiesce: "
1567 "failed to abort prevous AEN command QUIESCE"));
1568 }
1569
1570 if (instance->tbolt) {
1571 if (abort_syncmap_cmd(instance,
1572 instance->map_update_cmd)) {
1573 cmn_err(CE_WARN,
1574 "mrsas_detach: failed to abort "
1575 "previous syncmap command");
1576 return (DDI_FAILURE);
1577 }
1578 }
1579
1580 instance->func_ptr->disable_intr(instance);
1581
1582 con_log(CL_ANN1, (CE_CONT, "flushing cache for instance %d",
1583 instance_no));
1584
1585 flush_cache(instance);
1586
1587 if (wait_for_outstanding(instance)) {
1588 con_log(CL_ANN1,
1589 (CE_CONT, "wait_for_outstanding: return FAIL.\n"));
1590 return (DDI_FAILURE);
1591 }
1592 return (DDI_SUCCESS);
1593 }
1594 #endif /* __sparc */
1595
1596 /*
1597 * ************************************************************************** *
1598 * *
1599 * entry points (SCSI HBA) *
1600 * *
1601 * ************************************************************************** *
1602 */
1603 /*
1604 * tran_tgt_init - initialize a target device instance
1605 * @hba_dip:
1606 * @tgt_dip:
1607 * @tran:
1608 * @sd:
1609 *
1610 * The tran_tgt_init() entry point enables the HBA to allocate and initialize
1611 * any per-target resources. tran_tgt_init() also enables the HBA to qualify
1612 * the device's address as valid and supportable for that particular HBA.
1613 * By returning DDI_FAILURE, the instance of the target driver for that device
1614 * is not probed or attached.
1615 */
1616 /*ARGSUSED*/
1617 static int
1618 mrsas_tran_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
1619 scsi_hba_tran_t *tran, struct scsi_device *sd)
1620 {
1621 struct mrsas_instance *instance;
1622 uint16_t tgt = sd->sd_address.a_target;
1623 uint8_t lun = sd->sd_address.a_lun;
1624 dev_info_t *child = NULL;
1625
1626 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init target %d lun %d",
1627 tgt, lun));
1628
1629 instance = ADDR2MR(&sd->sd_address);
1630
1631 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
1632 /*
1633 * If no persistent node exists, we don't allow .conf node
1634 * to be created.
1635 */
1636 if ((child = mrsas_find_child(instance, tgt, lun)) != NULL) {
1637 con_log(CL_DLEVEL2,
1638 (CE_NOTE, "mrsas_tgt_init find child ="
1639 " %p t = %d l = %d", (void *)child, tgt, lun));
1640 if (ndi_merge_node(tgt_dip, mrsas_name_node) !=
1641 DDI_SUCCESS)
1642 /* Create this .conf node */
1643 return (DDI_SUCCESS);
1644 }
1645 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init in ndi_per "
1646 "DDI_FAILURE t = %d l = %d", tgt, lun));
1647 return (DDI_FAILURE);
1648
1649 }
1650
1651 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init dev_dip %p tgt_dip %p",
1652 (void *)instance->mr_ld_list[tgt].dip, (void *)tgt_dip));
1653
1654 if (tgt < MRDRV_MAX_LD && lun == 0) {
1655 if (instance->mr_ld_list[tgt].dip == NULL &&
1656 strcmp(ddi_driver_name(sd->sd_dev), "sd") == 0) {
1657 mutex_enter(&instance->config_dev_mtx);
1658 instance->mr_ld_list[tgt].dip = tgt_dip;
1659 instance->mr_ld_list[tgt].lun_type = MRSAS_LD_LUN;
1660 instance->mr_ld_list[tgt].flag = MRDRV_TGT_VALID;
1661 mutex_exit(&instance->config_dev_mtx);
1662 }
1663 }
1664
1665 #ifdef PDSUPPORT
1666 else if (instance->tbolt) {
1667 if (instance->mr_tbolt_pd_list[tgt].dip == NULL) {
1668 mutex_enter(&instance->config_dev_mtx);
1669 instance->mr_tbolt_pd_list[tgt].dip = tgt_dip;
1670 instance->mr_tbolt_pd_list[tgt].flag =
1671 MRDRV_TGT_VALID;
1672 mutex_exit(&instance->config_dev_mtx);
1673 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_tgt_init:"
1674 "t%xl%x", tgt, lun));
1675 }
1676 }
1677 #endif
1678
1679 return (DDI_SUCCESS);
1680 }
1681
1682 /*ARGSUSED*/
1683 static void
1684 mrsas_tran_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
1685 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
1686 {
1687 struct mrsas_instance *instance;
1688 int tgt = sd->sd_address.a_target;
1689 int lun = sd->sd_address.a_lun;
1690
1691 instance = ADDR2MR(&sd->sd_address);
1692
1693 con_log(CL_DLEVEL2, (CE_NOTE, "tgt_free t = %d l = %d", tgt, lun));
1694
1695 if (tgt < MRDRV_MAX_LD && lun == 0) {
1696 if (instance->mr_ld_list[tgt].dip == tgt_dip) {
1697 mutex_enter(&instance->config_dev_mtx);
1698 instance->mr_ld_list[tgt].dip = NULL;
1699 mutex_exit(&instance->config_dev_mtx);
1700 }
1701 }
1702
1703 #ifdef PDSUPPORT
1704 else if (instance->tbolt) {
1705 mutex_enter(&instance->config_dev_mtx);
1706 instance->mr_tbolt_pd_list[tgt].dip = NULL;
1707 mutex_exit(&instance->config_dev_mtx);
1708 con_log(CL_ANN1, (CE_NOTE, "tgt_free: Setting dip = NULL"
1709 "for tgt:%x", tgt));
1710 }
1711 #endif
1712
1713 }
1714
1715 dev_info_t *
1716 mrsas_find_child(struct mrsas_instance *instance, uint16_t tgt, uint8_t lun)
1717 {
1718 dev_info_t *child = NULL;
1719 char addr[SCSI_MAXNAMELEN];
1720 char tmp[MAXNAMELEN];
1721
1722 (void) sprintf(addr, "%x,%x", tgt, lun);
1723 for (child = ddi_get_child(instance->dip); child;
1724 child = ddi_get_next_sibling(child)) {
1725
1726 if (ndi_dev_is_persistent_node(child) == 0) {
1727 continue;
1728 }
1729
1730 if (mrsas_name_node(child, tmp, MAXNAMELEN) !=
1731 DDI_SUCCESS) {
1732 continue;
1733 }
1734
1735 if (strcmp(addr, tmp) == 0) {
1736 break;
1737 }
1738 }
1739 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_find_child: return child = %p",
1740 (void *)child));
1741 return (child);
1742 }
1743
1744 /*
1745 * mrsas_name_node -
1746 * @dip:
1747 * @name:
1748 * @len:
1749 */
1750 static int
1751 mrsas_name_node(dev_info_t *dip, char *name, int len)
1752 {
1753 int tgt, lun;
1754
1755 tgt = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1756 DDI_PROP_DONTPASS, "target", -1);
1757 con_log(CL_DLEVEL2, (CE_NOTE,
1758 "mrsas_name_node: dip %p tgt %d", (void *)dip, tgt));
1759 if (tgt == -1) {
1760 return (DDI_FAILURE);
1761 }
1762 lun = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1763 "lun", -1);
1764 con_log(CL_DLEVEL2,
1765 (CE_NOTE, "mrsas_name_node: tgt %d lun %d", tgt, lun));
1766 if (lun == -1) {
1767 return (DDI_FAILURE);
1768 }
1769 (void) snprintf(name, len, "%x,%x", tgt, lun);
1770 return (DDI_SUCCESS);
1771 }
1772
1773 /*
1774 * tran_init_pkt - allocate & initialize a scsi_pkt structure
1775 * @ap:
1776 * @pkt:
1777 * @bp:
1778 * @cmdlen:
1779 * @statuslen:
1780 * @tgtlen:
1781 * @flags:
1782 * @callback:
1783 *
1784 * The tran_init_pkt() entry point allocates and initializes a scsi_pkt
1785 * structure and DMA resources for a target driver request. The
1786 * tran_init_pkt() entry point is called when the target driver calls the
1787 * SCSA function scsi_init_pkt(). Each call of the tran_init_pkt() entry point
1788 * is a request to perform one or more of three possible services:
1789 * - allocation and initialization of a scsi_pkt structure
1790 * - allocation of DMA resources for data transfer
1791 * - reallocation of DMA resources for the next portion of the data transfer
1792 */
1793 static struct scsi_pkt *
1794 mrsas_tran_init_pkt(struct scsi_address *ap, register struct scsi_pkt *pkt,
1795 struct buf *bp, int cmdlen, int statuslen, int tgtlen,
1796 int flags, int (*callback)(), caddr_t arg)
1797 {
1798 struct scsa_cmd *acmd;
1799 struct mrsas_instance *instance;
1800 struct scsi_pkt *new_pkt;
1801
1802 con_log(CL_DLEVEL1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1803
1804 instance = ADDR2MR(ap);
1805
1806 /* step #1 : pkt allocation */
1807 if (pkt == NULL) {
1808 pkt = scsi_hba_pkt_alloc(instance->dip, ap, cmdlen, statuslen,
1809 tgtlen, sizeof (struct scsa_cmd), callback, arg);
1810 if (pkt == NULL) {
1811 return (NULL);
1812 }
1813
1814 acmd = PKT2CMD(pkt);
1815
1816 /*
1817 * Initialize the new pkt - we redundantly initialize
1818 * all the fields for illustrative purposes.
1819 */
1820 acmd->cmd_pkt = pkt;
1821 acmd->cmd_flags = 0;
1822 acmd->cmd_scblen = statuslen;
1823 acmd->cmd_cdblen = cmdlen;
1824 acmd->cmd_dmahandle = NULL;
1825 acmd->cmd_ncookies = 0;
1826 acmd->cmd_cookie = 0;
1827 acmd->cmd_cookiecnt = 0;
1828 acmd->cmd_nwin = 0;
1829
1830 pkt->pkt_address = *ap;
1831 pkt->pkt_comp = (void (*)())NULL;
1832 pkt->pkt_flags = 0;
1833 pkt->pkt_time = 0;
1834 pkt->pkt_resid = 0;
1835 pkt->pkt_state = 0;
1836 pkt->pkt_statistics = 0;
1837 pkt->pkt_reason = 0;
1838 new_pkt = pkt;
1839 } else {
1840 acmd = PKT2CMD(pkt);
1841 new_pkt = NULL;
1842 }
1843
1844 /* step #2 : dma allocation/move */
1845 if (bp && bp->b_bcount != 0) {
1846 if (acmd->cmd_dmahandle == NULL) {
1847 if (mrsas_dma_alloc(instance, pkt, bp, flags,
1848 callback) == DDI_FAILURE) {
1849 if (new_pkt) {
1850 scsi_hba_pkt_free(ap, new_pkt);
1851 }
1852 return ((struct scsi_pkt *)NULL);
1853 }
1854 } else {
1855 if (mrsas_dma_move(instance, pkt, bp) == DDI_FAILURE) {
1856 return ((struct scsi_pkt *)NULL);
1857 }
1858 }
1859 }
1860
1861 return (pkt);
1862 }
1863
1864 /*
1865 * tran_start - transport a SCSI command to the addressed target
1866 * @ap:
1867 * @pkt:
1868 *
1869 * The tran_start() entry point for a SCSI HBA driver is called to transport a
1870 * SCSI command to the addressed target. The SCSI command is described
1871 * entirely within the scsi_pkt structure, which the target driver allocated
1872 * through the HBA driver's tran_init_pkt() entry point. If the command
1873 * involves a data transfer, DMA resources must also have been allocated for
1874 * the scsi_pkt structure.
1875 *
1876 * Return Values :
1877 * TRAN_BUSY - request queue is full, no more free scbs
1878 * TRAN_ACCEPT - pkt has been submitted to the instance
1879 */
1880 static int
1881 mrsas_tran_start(struct scsi_address *ap, register struct scsi_pkt *pkt)
1882 {
1883 uchar_t cmd_done = 0;
1884
1885 struct mrsas_instance *instance = ADDR2MR(ap);
1886 struct mrsas_cmd *cmd;
1887
1888 con_log(CL_DLEVEL1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1889 if (instance->deadadapter == 1) {
1890 con_log(CL_ANN1, (CE_WARN,
1891 "mrsas_tran_start: return TRAN_FATAL_ERROR "
1892 "for IO, as the HBA doesnt take any more IOs"));
1893 if (pkt) {
1894 pkt->pkt_reason = CMD_DEV_GONE;
1895 pkt->pkt_statistics = STAT_DISCON;
1896 }
1897 return (TRAN_FATAL_ERROR);
1898 }
1899
1900 if (instance->adapterresetinprogress) {
1901 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_start: Reset flag set, "
1902 "returning mfi_pkt and setting TRAN_BUSY\n"));
1903 return (TRAN_BUSY);
1904 }
1905
1906 con_log(CL_ANN1, (CE_CONT, "chkpnt:%s:%d:SCSI CDB[0]=0x%x time:%x",
1907 __func__, __LINE__, pkt->pkt_cdbp[0], pkt->pkt_time));
1908
1909 pkt->pkt_reason = CMD_CMPLT;
1910 *pkt->pkt_scbp = STATUS_GOOD; /* clear arq scsi_status */
1911
1912 cmd = build_cmd(instance, ap, pkt, &cmd_done);
1913
1914 /*
1915 * Check if the command is already completed by the mrsas_build_cmd()
1916 * routine. In which case the busy_flag would be clear and scb will be
1917 * NULL and appropriate reason provided in pkt_reason field
1918 */
1919 if (cmd_done) {
1920 pkt->pkt_reason = CMD_CMPLT;
1921 pkt->pkt_scbp[0] = STATUS_GOOD;
1922 pkt->pkt_state |= STATE_GOT_BUS | STATE_GOT_TARGET
1923 | STATE_SENT_CMD;
1924 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) && pkt->pkt_comp) {
1925 (*pkt->pkt_comp)(pkt);
1926 }
1927
1928 return (TRAN_ACCEPT);
1929 }
1930
1931 if (cmd == NULL) {
1932 return (TRAN_BUSY);
1933 }
1934
1935 if ((pkt->pkt_flags & FLAG_NOINTR) == 0) {
1936 if (instance->fw_outstanding > instance->max_fw_cmds) {
1937 con_log(CL_ANN, (CE_CONT, "mr_sas:Firmware busy"));
1938 DTRACE_PROBE2(start_tran_err,
1939 uint16_t, instance->fw_outstanding,
1940 uint16_t, instance->max_fw_cmds);
1941 return_mfi_pkt(instance, cmd);
1942 return (TRAN_BUSY);
1943 }
1944
1945 /* Synchronize the Cmd frame for the controller */
1946 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 0, 0,
1947 DDI_DMA_SYNC_FORDEV);
1948 con_log(CL_ANN, (CE_CONT, "issue_cmd_ppc: SCSI CDB[0]=0x%x"
1949 "cmd->index:%x\n", pkt->pkt_cdbp[0], cmd->index));
1950 instance->func_ptr->issue_cmd(cmd, instance);
1951
1952 } else {
1953 struct mrsas_header *hdr = &cmd->frame->hdr;
1954
1955 instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd);
1956
1957 pkt->pkt_reason = CMD_CMPLT;
1958 pkt->pkt_statistics = 0;
1959 pkt->pkt_state |= STATE_XFERRED_DATA | STATE_GOT_STATUS;
1960
1961 switch (ddi_get8(cmd->frame_dma_obj.acc_handle,
1962 &hdr->cmd_status)) {
1963 case MFI_STAT_OK:
1964 pkt->pkt_scbp[0] = STATUS_GOOD;
1965 break;
1966
1967 case MFI_STAT_SCSI_DONE_WITH_ERROR:
1968 con_log(CL_ANN, (CE_CONT,
1969 "mrsas_tran_start: scsi done with error"));
1970 pkt->pkt_reason = CMD_CMPLT;
1971 pkt->pkt_statistics = 0;
1972
1973 ((struct scsi_status *)pkt->pkt_scbp)->sts_chk = 1;
1974 break;
1975
1976 case MFI_STAT_DEVICE_NOT_FOUND:
1977 con_log(CL_ANN, (CE_CONT,
1978 "mrsas_tran_start: device not found error"));
1979 pkt->pkt_reason = CMD_DEV_GONE;
1980 pkt->pkt_statistics = STAT_DISCON;
1981 break;
1982
1983 default:
1984 ((struct scsi_status *)pkt->pkt_scbp)->sts_busy = 1;
1985 }
1986
1987 (void) mrsas_common_check(instance, cmd);
1988 DTRACE_PROBE2(start_nointr_done, uint8_t, hdr->cmd,
1989 uint8_t, hdr->cmd_status);
1990 return_mfi_pkt(instance, cmd);
1991
1992 if (pkt->pkt_comp) {
1993 (*pkt->pkt_comp)(pkt);
1994 }
1995
1996 }
1997
1998 return (TRAN_ACCEPT);
1999 }
2000
2001 /*
2002 * tran_abort - Abort any commands that are currently in transport
2003 * @ap:
2004 * @pkt:
2005 *
2006 * The tran_abort() entry point for a SCSI HBA driver is called to abort any
2007 * commands that are currently in transport for a particular target. This entry
2008 * point is called when a target driver calls scsi_abort(). The tran_abort()
2009 * entry point should attempt to abort the command denoted by the pkt
2010 * parameter. If the pkt parameter is NULL, tran_abort() should attempt to
2011 * abort all outstanding commands in the transport layer for the particular
2012 * target or logical unit.
2013 */
2014 /*ARGSUSED*/
2015 static int
2016 mrsas_tran_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
2017 {
2018 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2019
2020 /* abort command not supported by H/W */
2021
2022 return (DDI_FAILURE);
2023 }
2024
2025 /*
2026 * tran_reset - reset either the SCSI bus or target
2027 * @ap:
2028 * @level:
2029 *
2030 * The tran_reset() entry point for a SCSI HBA driver is called to reset either
2031 * the SCSI bus or a particular SCSI target device. This entry point is called
2032 * when a target driver calls scsi_reset(). The tran_reset() entry point must
2033 * reset the SCSI bus if level is RESET_ALL. If level is RESET_TARGET, just the
2034 * particular target or logical unit must be reset.
2035 */
2036 /*ARGSUSED*/
2037 static int
2038 mrsas_tran_reset(struct scsi_address *ap, int level)
2039 {
2040 struct mrsas_instance *instance = ADDR2MR(ap);
2041
2042 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2043
2044 if (wait_for_outstanding(instance)) {
2045 con_log(CL_ANN1,
2046 (CE_CONT, "wait_for_outstanding: return FAIL.\n"));
2047 return (DDI_FAILURE);
2048 } else {
2049 return (DDI_SUCCESS);
2050 }
2051 }
2052
2053 /*
2054 * tran_getcap - get one of a set of SCSA-defined capabilities
2055 * @ap:
2056 * @cap:
2057 * @whom:
2058 *
2059 * The target driver can request the current setting of the capability for a
2060 * particular target by setting the whom parameter to nonzero. A whom value of
2061 * zero indicates a request for the current setting of the general capability
2062 * for the SCSI bus or for adapter hardware. The tran_getcap() should return -1
2063 * for undefined capabilities or the current value of the requested capability.
2064 */
2065 /*ARGSUSED*/
2066 static int
2067 mrsas_tran_getcap(struct scsi_address *ap, char *cap, int whom)
2068 {
2069 int rval = 0;
2070
2071 struct mrsas_instance *instance = ADDR2MR(ap);
2072
2073 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2074
2075 /* we do allow inquiring about capabilities for other targets */
2076 if (cap == NULL) {
2077 return (-1);
2078 }
2079
2080 switch (scsi_hba_lookup_capstr(cap)) {
2081 case SCSI_CAP_DMA_MAX:
2082 if (instance->tbolt) {
2083 /* Limit to 256k max transfer */
2084 rval = mrsas_tbolt_max_cap_maxxfer;
2085 } else {
2086 /* Limit to 16MB max transfer */
2087 rval = mrsas_max_cap_maxxfer;
2088 }
2089 break;
2090 case SCSI_CAP_MSG_OUT:
2091 rval = 1;
2092 break;
2093 case SCSI_CAP_DISCONNECT:
2094 rval = 0;
2095 break;
2096 case SCSI_CAP_SYNCHRONOUS:
2097 rval = 0;
2098 break;
2099 case SCSI_CAP_WIDE_XFER:
2100 rval = 1;
2101 break;
2102 case SCSI_CAP_TAGGED_QING:
2103 rval = 1;
2104 break;
2105 case SCSI_CAP_UNTAGGED_QING:
2106 rval = 1;
2107 break;
2108 case SCSI_CAP_PARITY:
2109 rval = 1;
2110 break;
2111 case SCSI_CAP_INITIATOR_ID:
2112 rval = instance->init_id;
2113 break;
2114 case SCSI_CAP_ARQ:
2115 rval = 1;
2116 break;
2117 case SCSI_CAP_LINKED_CMDS:
2118 rval = 0;
2119 break;
2120 case SCSI_CAP_RESET_NOTIFICATION:
2121 rval = 1;
2122 break;
2123 case SCSI_CAP_GEOMETRY:
2124 rval = -1;
2125
2126 break;
2127 default:
2128 con_log(CL_DLEVEL2, (CE_NOTE, "Default cap coming 0x%x",
2129 scsi_hba_lookup_capstr(cap)));
2130 rval = -1;
2131 break;
2132 }
2133
2134 return (rval);
2135 }
2136
2137 /*
2138 * tran_setcap - set one of a set of SCSA-defined capabilities
2139 * @ap:
2140 * @cap:
2141 * @value:
2142 * @whom:
2143 *
2144 * The target driver might request that the new value be set for a particular
2145 * target by setting the whom parameter to nonzero. A whom value of zero
2146 * means that request is to set the new value for the SCSI bus or for adapter
2147 * hardware in general.
2148 * The tran_setcap() should return the following values as appropriate:
2149 * - -1 for undefined capabilities
2150 * - 0 if the HBA driver cannot set the capability to the requested value
2151 * - 1 if the HBA driver is able to set the capability to the requested value
2152 */
2153 /*ARGSUSED*/
2154 static int
2155 mrsas_tran_setcap(struct scsi_address *ap, char *cap, int value, int whom)
2156 {
2157 int rval = 1;
2158
2159 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2160
2161 /* We don't allow setting capabilities for other targets */
2162 if (cap == NULL || whom == 0) {
2163 return (-1);
2164 }
2165
2166 switch (scsi_hba_lookup_capstr(cap)) {
2167 case SCSI_CAP_DMA_MAX:
2168 case SCSI_CAP_MSG_OUT:
2169 case SCSI_CAP_PARITY:
2170 case SCSI_CAP_LINKED_CMDS:
2171 case SCSI_CAP_RESET_NOTIFICATION:
2172 case SCSI_CAP_DISCONNECT:
2173 case SCSI_CAP_SYNCHRONOUS:
2174 case SCSI_CAP_UNTAGGED_QING:
2175 case SCSI_CAP_WIDE_XFER:
2176 case SCSI_CAP_INITIATOR_ID:
2177 case SCSI_CAP_ARQ:
2178 /*
2179 * None of these are settable via
2180 * the capability interface.
2181 */
2182 break;
2183 case SCSI_CAP_TAGGED_QING:
2184 rval = 1;
2185 break;
2186 case SCSI_CAP_SECTOR_SIZE:
2187 rval = 1;
2188 break;
2189
2190 case SCSI_CAP_TOTAL_SECTORS:
2191 rval = 1;
2192 break;
2193 default:
2194 rval = -1;
2195 break;
2196 }
2197
2198 return (rval);
2199 }
2200
2201 /*
2202 * tran_destroy_pkt - deallocate scsi_pkt structure
2203 * @ap:
2204 * @pkt:
2205 *
2206 * The tran_destroy_pkt() entry point is the HBA driver function that
2207 * deallocates scsi_pkt structures. The tran_destroy_pkt() entry point is
2208 * called when the target driver calls scsi_destroy_pkt(). The
2209 * tran_destroy_pkt() entry point must free any DMA resources that have been
2210 * allocated for the packet. An implicit DMA synchronization occurs if the
2211 * DMA resources are freed and any cached data remains after the completion
2212 * of the transfer.
2213 */
2214 static void
2215 mrsas_tran_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
2216 {
2217 struct scsa_cmd *acmd = PKT2CMD(pkt);
2218
2219 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2220
2221 if (acmd->cmd_flags & CFLAG_DMAVALID) {
2222 acmd->cmd_flags &= ~CFLAG_DMAVALID;
2223
2224 (void) ddi_dma_unbind_handle(acmd->cmd_dmahandle);
2225
2226 ddi_dma_free_handle(&acmd->cmd_dmahandle);
2227
2228 acmd->cmd_dmahandle = NULL;
2229 }
2230
2231 /* free the pkt */
2232 scsi_hba_pkt_free(ap, pkt);
2233 }
2234
2235 /*
2236 * tran_dmafree - deallocates DMA resources
2237 * @ap:
2238 * @pkt:
2239 *
2240 * The tran_dmafree() entry point deallocates DMAQ resources that have been
2241 * allocated for a scsi_pkt structure. The tran_dmafree() entry point is
2242 * called when the target driver calls scsi_dmafree(). The tran_dmafree() must
2243 * free only DMA resources allocated for a scsi_pkt structure, not the
2244 * scsi_pkt itself. When DMA resources are freed, a DMA synchronization is
2245 * implicitly performed.
2246 */
2247 /*ARGSUSED*/
2248 static void
2249 mrsas_tran_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
2250 {
2251 register struct scsa_cmd *acmd = PKT2CMD(pkt);
2252
2253 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2254
2255 if (acmd->cmd_flags & CFLAG_DMAVALID) {
2256 acmd->cmd_flags &= ~CFLAG_DMAVALID;
2257
2258 (void) ddi_dma_unbind_handle(acmd->cmd_dmahandle);
2259
2260 ddi_dma_free_handle(&acmd->cmd_dmahandle);
2261
2262 acmd->cmd_dmahandle = NULL;
2263 }
2264 }
2265
2266 /*
2267 * tran_sync_pkt - synchronize the DMA object allocated
2268 * @ap:
2269 * @pkt:
2270 *
2271 * The tran_sync_pkt() entry point synchronizes the DMA object allocated for
2272 * the scsi_pkt structure before or after a DMA transfer. The tran_sync_pkt()
2273 * entry point is called when the target driver calls scsi_sync_pkt(). If the
2274 * data transfer direction is a DMA read from device to memory, tran_sync_pkt()
2275 * must synchronize the CPU's view of the data. If the data transfer direction
2276 * is a DMA write from memory to device, tran_sync_pkt() must synchronize the
2277 * device's view of the data.
2278 */
2279 /*ARGSUSED*/
2280 static void
2281 mrsas_tran_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
2282 {
2283 register struct scsa_cmd *acmd = PKT2CMD(pkt);
2284
2285 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2286
2287 if (acmd->cmd_flags & CFLAG_DMAVALID) {
2288 (void) ddi_dma_sync(acmd->cmd_dmahandle, acmd->cmd_dma_offset,
2289 acmd->cmd_dma_len, (acmd->cmd_flags & CFLAG_DMASEND) ?
2290 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
2291 }
2292 }
2293
2294 /*ARGSUSED*/
2295 static int
2296 mrsas_tran_quiesce(dev_info_t *dip)
2297 {
2298 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2299
2300 return (1);
2301 }
2302
2303 /*ARGSUSED*/
2304 static int
2305 mrsas_tran_unquiesce(dev_info_t *dip)
2306 {
2307 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2308
2309 return (1);
2310 }
2311
2312
2313 /*
2314 * mrsas_isr(caddr_t)
2315 *
2316 * The Interrupt Service Routine
2317 *
2318 * Collect status for all completed commands and do callback
2319 *
2320 */
2321 static uint_t
2322 mrsas_isr(struct mrsas_instance *instance)
2323 {
2324 int need_softintr;
2325 uint32_t producer;
2326 uint32_t consumer;
2327 uint32_t context;
2328 int retval;
2329
2330 struct mrsas_cmd *cmd;
2331 struct mrsas_header *hdr;
2332 struct scsi_pkt *pkt;
2333
2334 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2335 ASSERT(instance);
2336 if (instance->tbolt) {
2337 mutex_enter(&instance->chip_mtx);
2338 if ((instance->intr_type == DDI_INTR_TYPE_FIXED) &&
2339 !(instance->func_ptr->intr_ack(instance))) {
2340 mutex_exit(&instance->chip_mtx);
2341 return (DDI_INTR_UNCLAIMED);
2342 }
2343 retval = mr_sas_tbolt_process_outstanding_cmd(instance);
2344 mutex_exit(&instance->chip_mtx);
2345 return (retval);
2346 } else {
2347 if ((instance->intr_type == DDI_INTR_TYPE_FIXED) &&
2348 !instance->func_ptr->intr_ack(instance)) {
2349 return (DDI_INTR_UNCLAIMED);
2350 }
2351 }
2352
2353 (void) ddi_dma_sync(instance->mfi_internal_dma_obj.dma_handle,
2354 0, 0, DDI_DMA_SYNC_FORCPU);
2355
2356 if (mrsas_check_dma_handle(instance->mfi_internal_dma_obj.dma_handle)
2357 != DDI_SUCCESS) {
2358 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE);
2359 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
2360 con_log(CL_ANN1, (CE_WARN,
2361 "mr_sas_isr(): FMA check, returning DDI_INTR_UNCLAIMED"));
2362 return (DDI_INTR_CLAIMED);
2363 }
2364 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2365
2366 #ifdef OCRDEBUG
2367 if (debug_consecutive_timeout_after_ocr_g == 1) {
2368 con_log(CL_ANN1, (CE_NOTE,
2369 "simulating consecutive timeout after ocr"));
2370 return (DDI_INTR_CLAIMED);
2371 }
2372 #endif
2373
2374 mutex_enter(&instance->completed_pool_mtx);
2375 mutex_enter(&instance->cmd_pend_mtx);
2376
2377 producer = ddi_get32(instance->mfi_internal_dma_obj.acc_handle,
2378 instance->producer);
2379 consumer = ddi_get32(instance->mfi_internal_dma_obj.acc_handle,
2380 instance->consumer);
2381
2382 con_log(CL_ANN, (CE_CONT, " producer %x consumer %x ",
2383 producer, consumer));
2384 if (producer == consumer) {
2385 con_log(CL_ANN, (CE_WARN, "producer == consumer case"));
2386 DTRACE_PROBE2(isr_pc_err, uint32_t, producer,
2387 uint32_t, consumer);
2388 mutex_exit(&instance->cmd_pend_mtx);
2389 mutex_exit(&instance->completed_pool_mtx);
2390 return (DDI_INTR_CLAIMED);
2391 }
2392
2393 while (consumer != producer) {
2394 context = ddi_get32(instance->mfi_internal_dma_obj.acc_handle,
2395 &instance->reply_queue[consumer]);
2396 cmd = instance->cmd_list[context];
2397
2398 if (cmd->sync_cmd == MRSAS_TRUE) {
2399 hdr = (struct mrsas_header *)&cmd->frame->hdr;
2400 if (hdr) {
2401 mlist_del_init(&cmd->list);
2402 }
2403 } else {
2404 pkt = cmd->pkt;
2405 if (pkt) {
2406 mlist_del_init(&cmd->list);
2407 }
2408 }
2409
2410 mlist_add_tail(&cmd->list, &instance->completed_pool_list);
2411
2412 consumer++;
2413 if (consumer == (instance->max_fw_cmds + 1)) {
2414 consumer = 0;
2415 }
2416 }
2417 ddi_put32(instance->mfi_internal_dma_obj.acc_handle,
2418 instance->consumer, consumer);
2419 mutex_exit(&instance->cmd_pend_mtx);
2420 mutex_exit(&instance->completed_pool_mtx);
2421
2422 (void) ddi_dma_sync(instance->mfi_internal_dma_obj.dma_handle,
2423 0, 0, DDI_DMA_SYNC_FORDEV);
2424
2425 if (instance->softint_running) {
2426 need_softintr = 0;
2427 } else {
2428 need_softintr = 1;
2429 }
2430
2431 if (instance->isr_level == HIGH_LEVEL_INTR) {
2432 if (need_softintr) {
2433 ddi_trigger_softintr(instance->soft_intr_id);
2434 }
2435 } else {
2436 /*
2437 * Not a high-level interrupt, therefore call the soft level
2438 * interrupt explicitly
2439 */
2440 (void) mrsas_softintr(instance);
2441 }
2442
2443 return (DDI_INTR_CLAIMED);
2444 }
2445
2446
2447 /*
2448 * ************************************************************************** *
2449 * *
2450 * libraries *
2451 * *
2452 * ************************************************************************** *
2453 */
2454 /*
2455 * get_mfi_pkt : Get a command from the free pool
2456 * After successful allocation, the caller of this routine
2457 * must clear the frame buffer (memset to zero) before
2458 * using the packet further.
2459 *
2460 * ***** Note *****
2461 * After clearing the frame buffer the context id of the
2462 * frame buffer SHOULD be restored back.
2463 */
2464 static struct mrsas_cmd *
2465 get_mfi_pkt(struct mrsas_instance *instance)
2466 {
2467 mlist_t *head = &instance->cmd_pool_list;
2468 struct mrsas_cmd *cmd = NULL;
2469
2470 mutex_enter(&instance->cmd_pool_mtx);
2471
2472 if (!mlist_empty(head)) {
2473 cmd = mlist_entry(head->next, struct mrsas_cmd, list);
2474 mlist_del_init(head->next);
2475 }
2476 if (cmd != NULL) {
2477 cmd->pkt = NULL;
2478 cmd->retry_count_for_ocr = 0;
2479 cmd->drv_pkt_time = 0;
2480
2481 }
2482 mutex_exit(&instance->cmd_pool_mtx);
2483
2484 return (cmd);
2485 }
2486
2487 static struct mrsas_cmd *
2488 get_mfi_app_pkt(struct mrsas_instance *instance)
2489 {
2490 mlist_t *head = &instance->app_cmd_pool_list;
2491 struct mrsas_cmd *cmd = NULL;
2492
2493 mutex_enter(&instance->app_cmd_pool_mtx);
2494
2495 if (!mlist_empty(head)) {
2496 cmd = mlist_entry(head->next, struct mrsas_cmd, list);
2497 mlist_del_init(head->next);
2498 }
2499 if (cmd != NULL) {
2500 cmd->pkt = NULL;
2501 cmd->retry_count_for_ocr = 0;
2502 cmd->drv_pkt_time = 0;
2503 }
2504
2505 mutex_exit(&instance->app_cmd_pool_mtx);
2506
2507 return (cmd);
2508 }
2509 /*
2510 * return_mfi_pkt : Return a cmd to free command pool
2511 */
2512 static void
2513 return_mfi_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
2514 {
2515 mutex_enter(&instance->cmd_pool_mtx);
2516 /* use mlist_add_tail for debug assistance */
2517 mlist_add_tail(&cmd->list, &instance->cmd_pool_list);
2518
2519 mutex_exit(&instance->cmd_pool_mtx);
2520 }
2521
2522 static void
2523 return_mfi_app_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
2524 {
2525 mutex_enter(&instance->app_cmd_pool_mtx);
2526
2527 mlist_add(&cmd->list, &instance->app_cmd_pool_list);
2528
2529 mutex_exit(&instance->app_cmd_pool_mtx);
2530 }
2531 void
2532 push_pending_mfi_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
2533 {
2534 struct scsi_pkt *pkt;
2535 struct mrsas_header *hdr;
2536 con_log(CL_DLEVEL2, (CE_NOTE, "push_pending_pkt(): Called\n"));
2537 mutex_enter(&instance->cmd_pend_mtx);
2538 mlist_del_init(&cmd->list);
2539 mlist_add_tail(&cmd->list, &instance->cmd_pend_list);
2540 if (cmd->sync_cmd == MRSAS_TRUE) {
2541 hdr = (struct mrsas_header *)&cmd->frame->hdr;
2542 if (hdr) {
2543 con_log(CL_ANN1, (CE_CONT,
2544 "push_pending_mfi_pkt: "
2545 "cmd %p index %x "
2546 "time %llx",
2547 (void *)cmd, cmd->index,
2548 gethrtime()));
2549 /* Wait for specified interval */
2550 cmd->drv_pkt_time = ddi_get16(
2551 cmd->frame_dma_obj.acc_handle, &hdr->timeout);
2552 if (cmd->drv_pkt_time < debug_timeout_g)
2553 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
2554 con_log(CL_ANN1, (CE_CONT,
2555 "push_pending_pkt(): "
2556 "Called IO Timeout Value %x\n",
2557 cmd->drv_pkt_time));
2558 }
2559 if (hdr && instance->timeout_id == (timeout_id_t)-1) {
2560 instance->timeout_id = timeout(io_timeout_checker,
2561 (void *) instance, drv_usectohz(MRSAS_1_SECOND));
2562 }
2563 } else {
2564 pkt = cmd->pkt;
2565 if (pkt) {
2566 con_log(CL_ANN1, (CE_CONT,
2567 "push_pending_mfi_pkt: "
2568 "cmd %p index %x pkt %p, "
2569 "time %llx",
2570 (void *)cmd, cmd->index, (void *)pkt,
2571 gethrtime()));
2572 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
2573 }
2574 if (pkt && instance->timeout_id == (timeout_id_t)-1) {
2575 instance->timeout_id = timeout(io_timeout_checker,
2576 (void *) instance, drv_usectohz(MRSAS_1_SECOND));
2577 }
2578 }
2579
2580 mutex_exit(&instance->cmd_pend_mtx);
2581
2582 }
2583
2584 int
2585 mrsas_print_pending_cmds(struct mrsas_instance *instance)
2586 {
2587 mlist_t *head = &instance->cmd_pend_list;
2588 mlist_t *tmp = head;
2589 struct mrsas_cmd *cmd = NULL;
2590 struct mrsas_header *hdr;
2591 unsigned int flag = 1;
2592 struct scsi_pkt *pkt;
2593 int saved_level;
2594 int cmd_count = 0;
2595
2596 saved_level = debug_level_g;
2597 debug_level_g = CL_ANN1;
2598
2599 cmn_err(CE_NOTE, "mrsas_print_pending_cmds(): Called\n");
2600
2601 while (flag) {
2602 mutex_enter(&instance->cmd_pend_mtx);
2603 tmp = tmp->next;
2604 if (tmp == head) {
2605 mutex_exit(&instance->cmd_pend_mtx);
2606 flag = 0;
2607 con_log(CL_ANN1, (CE_CONT, "mrsas_print_pending_cmds():"
2608 " NO MORE CMDS PENDING....\n"));
2609 break;
2610 } else {
2611 cmd = mlist_entry(tmp, struct mrsas_cmd, list);
2612 mutex_exit(&instance->cmd_pend_mtx);
2613 if (cmd) {
2614 if (cmd->sync_cmd == MRSAS_TRUE) {
2615 hdr = (struct mrsas_header *)
2616 &cmd->frame->hdr;
2617 if (hdr) {
2618 con_log(CL_ANN1, (CE_CONT,
2619 "print: cmd %p index 0x%x "
2620 "drv_pkt_time 0x%x (NO-PKT)"
2621 " hdr %p\n", (void *)cmd,
2622 cmd->index,
2623 cmd->drv_pkt_time,
2624 (void *)hdr));
2625 }
2626 } else {
2627 pkt = cmd->pkt;
2628 if (pkt) {
2629 con_log(CL_ANN1, (CE_CONT,
2630 "print: cmd %p index 0x%x "
2631 "drv_pkt_time 0x%x pkt %p \n",
2632 (void *)cmd, cmd->index,
2633 cmd->drv_pkt_time, (void *)pkt));
2634 }
2635 }
2636
2637 if (++cmd_count == 1) {
2638 mrsas_print_cmd_details(instance, cmd,
2639 0xDD);
2640 } else {
2641 mrsas_print_cmd_details(instance, cmd,
2642 1);
2643 }
2644
2645 }
2646 }
2647 }
2648 con_log(CL_ANN1, (CE_CONT, "mrsas_print_pending_cmds(): Done\n"));
2649
2650
2651 debug_level_g = saved_level;
2652
2653 return (DDI_SUCCESS);
2654 }
2655
2656
2657 int
2658 mrsas_complete_pending_cmds(struct mrsas_instance *instance)
2659 {
2660
2661 struct mrsas_cmd *cmd = NULL;
2662 struct scsi_pkt *pkt;
2663 struct mrsas_header *hdr;
2664
2665 struct mlist_head *pos, *next;
2666
2667 con_log(CL_ANN1, (CE_NOTE,
2668 "mrsas_complete_pending_cmds(): Called"));
2669
2670 mutex_enter(&instance->cmd_pend_mtx);
2671 mlist_for_each_safe(pos, next, &instance->cmd_pend_list) {
2672 cmd = mlist_entry(pos, struct mrsas_cmd, list);
2673 if (cmd) {
2674 pkt = cmd->pkt;
2675 if (pkt) { /* for IO */
2676 if (((pkt->pkt_flags & FLAG_NOINTR)
2677 == 0) && pkt->pkt_comp) {
2678 pkt->pkt_reason
2679 = CMD_DEV_GONE;
2680 pkt->pkt_statistics
2681 = STAT_DISCON;
2682 con_log(CL_ANN1, (CE_CONT,
2683 "fail and posting to scsa "
2684 "cmd %p index %x"
2685 " pkt %p "
2686 "time : %llx",
2687 (void *)cmd, cmd->index,
2688 (void *)pkt, gethrtime()));
2689 (*pkt->pkt_comp)(pkt);
2690 }
2691 } else { /* for DCMDS */
2692 if (cmd->sync_cmd == MRSAS_TRUE) {
2693 hdr = (struct mrsas_header *)&cmd->frame->hdr;
2694 con_log(CL_ANN1, (CE_CONT,
2695 "posting invalid status to application "
2696 "cmd %p index %x"
2697 " hdr %p "
2698 "time : %llx",
2699 (void *)cmd, cmd->index,
2700 (void *)hdr, gethrtime()));
2701 hdr->cmd_status = MFI_STAT_INVALID_STATUS;
2702 complete_cmd_in_sync_mode(instance, cmd);
2703 }
2704 }
2705 mlist_del_init(&cmd->list);
2706 } else {
2707 con_log(CL_ANN1, (CE_CONT,
2708 "mrsas_complete_pending_cmds:"
2709 "NULL command\n"));
2710 }
2711 con_log(CL_ANN1, (CE_CONT,
2712 "mrsas_complete_pending_cmds:"
2713 "looping for more commands\n"));
2714 }
2715 mutex_exit(&instance->cmd_pend_mtx);
2716
2717 con_log(CL_ANN1, (CE_CONT, "mrsas_complete_pending_cmds(): DONE\n"));
2718 return (DDI_SUCCESS);
2719 }
2720
2721 void
2722 mrsas_print_cmd_details(struct mrsas_instance *instance, struct mrsas_cmd *cmd,
2723 int detail)
2724 {
2725 struct scsi_pkt *pkt = cmd->pkt;
2726 Mpi2RaidSCSIIORequest_t *scsi_io = cmd->scsi_io_request;
2727 int i;
2728 int saved_level;
2729 ddi_acc_handle_t acc_handle =
2730 instance->mpi2_frame_pool_dma_obj.acc_handle;
2731
2732 if (detail == 0xDD) {
2733 saved_level = debug_level_g;
2734 debug_level_g = CL_ANN1;
2735 }
2736
2737
2738 if (instance->tbolt) {
2739 con_log(CL_ANN1, (CE_CONT, "print_cmd_details: cmd %p "
2740 "cmd->index 0x%x SMID 0x%x timer 0x%x sec\n",
2741 (void *)cmd, cmd->index, cmd->SMID, cmd->drv_pkt_time));
2742 } else {
2743 con_log(CL_ANN1, (CE_CONT, "print_cmd_details: cmd %p "
2744 "cmd->index 0x%x timer 0x%x sec\n",
2745 (void *)cmd, cmd->index, cmd->drv_pkt_time));
2746 }
2747
2748 if (pkt) {
2749 con_log(CL_ANN1, (CE_CONT, "scsi_pkt CDB[0]=0x%x",
2750 pkt->pkt_cdbp[0]));
2751 } else {
2752 con_log(CL_ANN1, (CE_CONT, "NO-PKT"));
2753 }
2754
2755 if ((detail == 0xDD) && instance->tbolt) {
2756 con_log(CL_ANN1, (CE_CONT, "RAID_SCSI_IO_REQUEST\n"));
2757 con_log(CL_ANN1, (CE_CONT, "DevHandle=0x%X Function=0x%X "
2758 "IoFlags=0x%X SGLFlags=0x%X DataLength=0x%X\n",
2759 ddi_get16(acc_handle, &scsi_io->DevHandle),
2760 ddi_get8(acc_handle, &scsi_io->Function),
2761 ddi_get16(acc_handle, &scsi_io->IoFlags),
2762 ddi_get16(acc_handle, &scsi_io->SGLFlags),
2763 ddi_get32(acc_handle, &scsi_io->DataLength)));
2764
2765 for (i = 0; i < 32; i++) {
2766 con_log(CL_ANN1, (CE_CONT, "CDB[%d]=0x%x ", i,
2767 ddi_get8(acc_handle, &scsi_io->CDB.CDB32[i])));
2768 }
2769
2770 con_log(CL_ANN1, (CE_CONT, "RAID-CONTEXT\n"));
2771 con_log(CL_ANN1, (CE_CONT, "status=0x%X extStatus=0x%X "
2772 "ldTargetId=0x%X timeoutValue=0x%X regLockFlags=0x%X "
2773 "RAIDFlags=0x%X regLockRowLBA=0x%" PRIu64
2774 " regLockLength=0x%X spanArm=0x%X\n",
2775 ddi_get8(acc_handle, &scsi_io->RaidContext.status),
2776 ddi_get8(acc_handle, &scsi_io->RaidContext.extStatus),
2777 ddi_get16(acc_handle, &scsi_io->RaidContext.ldTargetId),
2778 ddi_get16(acc_handle, &scsi_io->RaidContext.timeoutValue),
2779 ddi_get8(acc_handle, &scsi_io->RaidContext.regLockFlags),
2780 ddi_get8(acc_handle, &scsi_io->RaidContext.RAIDFlags),
2781 ddi_get64(acc_handle, &scsi_io->RaidContext.regLockRowLBA),
2782 ddi_get32(acc_handle, &scsi_io->RaidContext.regLockLength),
2783 ddi_get8(acc_handle, &scsi_io->RaidContext.spanArm)));
2784 }
2785
2786 if (detail == 0xDD) {
2787 debug_level_g = saved_level;
2788 }
2789 }
2790
2791
2792 int
2793 mrsas_issue_pending_cmds(struct mrsas_instance *instance)
2794 {
2795 mlist_t *head = &instance->cmd_pend_list;
2796 mlist_t *tmp = head->next;
2797 struct mrsas_cmd *cmd = NULL;
2798 struct scsi_pkt *pkt;
2799
2800 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_pending_cmds(): Called"));
2801 while (tmp != head) {
2802 mutex_enter(&instance->cmd_pend_mtx);
2803 cmd = mlist_entry(tmp, struct mrsas_cmd, list);
2804 tmp = tmp->next;
2805 mutex_exit(&instance->cmd_pend_mtx);
2806 if (cmd) {
2807 con_log(CL_ANN1, (CE_CONT,
2808 "mrsas_issue_pending_cmds(): "
2809 "Got a cmd: cmd %p index 0x%x drv_pkt_time 0x%x ",
2810 (void *)cmd, cmd->index, cmd->drv_pkt_time));
2811
2812 /* Reset command timeout value */
2813 if (cmd->drv_pkt_time < debug_timeout_g)
2814 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
2815
2816 cmd->retry_count_for_ocr++;
2817
2818 cmn_err(CE_CONT, "cmd retry count = %d\n",
2819 cmd->retry_count_for_ocr);
2820
2821 if (cmd->retry_count_for_ocr > IO_RETRY_COUNT) {
2822 cmn_err(CE_WARN, "mrsas_issue_pending_cmds(): "
2823 "cmd->retry_count exceeded limit >%d\n",
2824 IO_RETRY_COUNT);
2825 mrsas_print_cmd_details(instance, cmd, 0xDD);
2826
2827 cmn_err(CE_WARN,
2828 "mrsas_issue_pending_cmds():"
2829 "Calling KILL Adapter\n");
2830 if (instance->tbolt)
2831 mrsas_tbolt_kill_adapter(instance);
2832 else
2833 (void) mrsas_kill_adapter(instance);
2834 return (DDI_FAILURE);
2835 }
2836
2837 pkt = cmd->pkt;
2838 if (pkt) {
2839 con_log(CL_ANN1, (CE_CONT,
2840 "PENDING PKT-CMD ISSUE: cmd %p index %x "
2841 "pkt %p time %llx",
2842 (void *)cmd, cmd->index,
2843 (void *)pkt,
2844 gethrtime()));
2845
2846 } else {
2847 cmn_err(CE_CONT,
2848 "mrsas_issue_pending_cmds(): NO-PKT, "
2849 "cmd %p index 0x%x drv_pkt_time 0x%x ",
2850 (void *)cmd, cmd->index, cmd->drv_pkt_time);
2851 }
2852
2853
2854 if (cmd->sync_cmd == MRSAS_TRUE) {
2855 cmn_err(CE_CONT, "mrsas_issue_pending_cmds(): "
2856 "SYNC_CMD == TRUE \n");
2857 instance->func_ptr->issue_cmd_in_sync_mode(
2858 instance, cmd);
2859 } else {
2860 instance->func_ptr->issue_cmd(cmd, instance);
2861 }
2862 } else {
2863 con_log(CL_ANN1, (CE_CONT,
2864 "mrsas_issue_pending_cmds: NULL command\n"));
2865 }
2866 con_log(CL_ANN1, (CE_CONT,
2867 "mrsas_issue_pending_cmds:"
2868 "looping for more commands"));
2869 }
2870 con_log(CL_ANN1, (CE_CONT, "mrsas_issue_pending_cmds(): DONE\n"));
2871 return (DDI_SUCCESS);
2872 }
2873
2874
2875
2876 /*
2877 * destroy_mfi_frame_pool
2878 */
2879 void
2880 destroy_mfi_frame_pool(struct mrsas_instance *instance)
2881 {
2882 int i;
2883 uint32_t max_cmd = instance->max_fw_cmds;
2884
2885 struct mrsas_cmd *cmd;
2886
2887 /* return all frames to pool */
2888
2889 for (i = 0; i < max_cmd; i++) {
2890
2891 cmd = instance->cmd_list[i];
2892
2893 if (cmd->frame_dma_obj_status == DMA_OBJ_ALLOCATED)
2894 (void) mrsas_free_dma_obj(instance, cmd->frame_dma_obj);
2895
2896 cmd->frame_dma_obj_status = DMA_OBJ_FREED;
2897 }
2898
2899 }
2900
2901 /*
2902 * create_mfi_frame_pool
2903 */
2904 int
2905 create_mfi_frame_pool(struct mrsas_instance *instance)
2906 {
2907 int i = 0;
2908 int cookie_cnt;
2909 uint16_t max_cmd;
2910 uint16_t sge_sz;
2911 uint32_t sgl_sz;
2912 uint32_t tot_frame_size;
2913 struct mrsas_cmd *cmd;
2914 int retval = DDI_SUCCESS;
2915
2916 max_cmd = instance->max_fw_cmds;
2917 sge_sz = sizeof (struct mrsas_sge_ieee);
2918 /* calculated the number of 64byte frames required for SGL */
2919 sgl_sz = sge_sz * instance->max_num_sge;
2920 tot_frame_size = sgl_sz + MRMFI_FRAME_SIZE + SENSE_LENGTH;
2921
2922 con_log(CL_DLEVEL3, (CE_NOTE, "create_mfi_frame_pool: "
2923 "sgl_sz %x tot_frame_size %x", sgl_sz, tot_frame_size));
2924
2925 while (i < max_cmd) {
2926 cmd = instance->cmd_list[i];
2927
2928 cmd->frame_dma_obj.size = tot_frame_size;
2929 cmd->frame_dma_obj.dma_attr = mrsas_generic_dma_attr;
2930 cmd->frame_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
2931 cmd->frame_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
2932 cmd->frame_dma_obj.dma_attr.dma_attr_sgllen = 1;
2933 cmd->frame_dma_obj.dma_attr.dma_attr_align = 64;
2934
2935 cookie_cnt = mrsas_alloc_dma_obj(instance, &cmd->frame_dma_obj,
2936 (uchar_t)DDI_STRUCTURE_LE_ACC);
2937
2938 if (cookie_cnt == -1 || cookie_cnt > 1) {
2939 cmn_err(CE_WARN,
2940 "create_mfi_frame_pool: could not alloc.");
2941 retval = DDI_FAILURE;
2942 goto mrsas_undo_frame_pool;
2943 }
2944
2945 bzero(cmd->frame_dma_obj.buffer, tot_frame_size);
2946
2947 cmd->frame_dma_obj_status = DMA_OBJ_ALLOCATED;
2948 cmd->frame = (union mrsas_frame *)cmd->frame_dma_obj.buffer;
2949 cmd->frame_phys_addr =
2950 cmd->frame_dma_obj.dma_cookie[0].dmac_address;
2951
2952 cmd->sense = (uint8_t *)(((unsigned long)
2953 cmd->frame_dma_obj.buffer) +
2954 tot_frame_size - SENSE_LENGTH);
2955 cmd->sense_phys_addr =
2956 cmd->frame_dma_obj.dma_cookie[0].dmac_address +
2957 tot_frame_size - SENSE_LENGTH;
2958
2959 if (!cmd->frame || !cmd->sense) {
2960 cmn_err(CE_WARN,
2961 "mr_sas: pci_pool_alloc failed");
2962 retval = ENOMEM;
2963 goto mrsas_undo_frame_pool;
2964 }
2965
2966 ddi_put32(cmd->frame_dma_obj.acc_handle,
2967 &cmd->frame->io.context, cmd->index);
2968 i++;
2969
2970 con_log(CL_DLEVEL3, (CE_NOTE, "[%x]-%x",
2971 cmd->index, cmd->frame_phys_addr));
2972 }
2973
2974 return (DDI_SUCCESS);
2975
2976 mrsas_undo_frame_pool:
2977 if (i > 0)
2978 destroy_mfi_frame_pool(instance);
2979
2980 return (retval);
2981 }
2982
2983 /*
2984 * free_additional_dma_buffer
2985 */
2986 static void
2987 free_additional_dma_buffer(struct mrsas_instance *instance)
2988 {
2989 if (instance->mfi_internal_dma_obj.status == DMA_OBJ_ALLOCATED) {
2990 (void) mrsas_free_dma_obj(instance,
2991 instance->mfi_internal_dma_obj);
2992 instance->mfi_internal_dma_obj.status = DMA_OBJ_FREED;
2993 }
2994
2995 if (instance->mfi_evt_detail_obj.status == DMA_OBJ_ALLOCATED) {
2996 (void) mrsas_free_dma_obj(instance,
2997 instance->mfi_evt_detail_obj);
2998 instance->mfi_evt_detail_obj.status = DMA_OBJ_FREED;
2999 }
3000 }
3001
3002 /*
3003 * alloc_additional_dma_buffer
3004 */
3005 static int
3006 alloc_additional_dma_buffer(struct mrsas_instance *instance)
3007 {
3008 uint32_t reply_q_sz;
3009 uint32_t internal_buf_size = PAGESIZE*2;
3010
3011 /* max cmds plus 1 + producer & consumer */
3012 reply_q_sz = sizeof (uint32_t) * (instance->max_fw_cmds + 1 + 2);
3013
3014 instance->mfi_internal_dma_obj.size = internal_buf_size;
3015 instance->mfi_internal_dma_obj.dma_attr = mrsas_generic_dma_attr;
3016 instance->mfi_internal_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
3017 instance->mfi_internal_dma_obj.dma_attr.dma_attr_count_max =
3018 0xFFFFFFFFU;
3019 instance->mfi_internal_dma_obj.dma_attr.dma_attr_sgllen = 1;
3020
3021 if (mrsas_alloc_dma_obj(instance, &instance->mfi_internal_dma_obj,
3022 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
3023 cmn_err(CE_WARN,
3024 "mr_sas: could not alloc reply queue");
3025 return (DDI_FAILURE);
3026 }
3027
3028 bzero(instance->mfi_internal_dma_obj.buffer, internal_buf_size);
3029
3030 instance->mfi_internal_dma_obj.status |= DMA_OBJ_ALLOCATED;
3031
3032 instance->producer = (uint32_t *)((unsigned long)
3033 instance->mfi_internal_dma_obj.buffer);
3034 instance->consumer = (uint32_t *)((unsigned long)
3035 instance->mfi_internal_dma_obj.buffer + 4);
3036 instance->reply_queue = (uint32_t *)((unsigned long)
3037 instance->mfi_internal_dma_obj.buffer + 8);
3038 instance->internal_buf = (caddr_t)(((unsigned long)
3039 instance->mfi_internal_dma_obj.buffer) + reply_q_sz + 8);
3040 instance->internal_buf_dmac_add =
3041 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address +
3042 (reply_q_sz + 8);
3043 instance->internal_buf_size = internal_buf_size -
3044 (reply_q_sz + 8);
3045
3046 /* allocate evt_detail */
3047 instance->mfi_evt_detail_obj.size = sizeof (struct mrsas_evt_detail);
3048 instance->mfi_evt_detail_obj.dma_attr = mrsas_generic_dma_attr;
3049 instance->mfi_evt_detail_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
3050 instance->mfi_evt_detail_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
3051 instance->mfi_evt_detail_obj.dma_attr.dma_attr_sgllen = 1;
3052 instance->mfi_evt_detail_obj.dma_attr.dma_attr_align = 1;
3053
3054 if (mrsas_alloc_dma_obj(instance, &instance->mfi_evt_detail_obj,
3055 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
3056 cmn_err(CE_WARN, "alloc_additional_dma_buffer: "
3057 "could not allocate data transfer buffer.");
3058 goto mrsas_undo_internal_buff;
3059 }
3060
3061 bzero(instance->mfi_evt_detail_obj.buffer,
3062 sizeof (struct mrsas_evt_detail));
3063
3064 instance->mfi_evt_detail_obj.status |= DMA_OBJ_ALLOCATED;
3065
3066 return (DDI_SUCCESS);
3067
3068 mrsas_undo_internal_buff:
3069 if (instance->mfi_internal_dma_obj.status == DMA_OBJ_ALLOCATED) {
3070 (void) mrsas_free_dma_obj(instance,
3071 instance->mfi_internal_dma_obj);
3072 instance->mfi_internal_dma_obj.status = DMA_OBJ_FREED;
3073 }
3074
3075 return (DDI_FAILURE);
3076 }
3077
3078
3079 void
3080 mrsas_free_cmd_pool(struct mrsas_instance *instance)
3081 {
3082 int i;
3083 uint32_t max_cmd;
3084 size_t sz;
3085
3086 /* already freed */
3087 if (instance->cmd_list == NULL) {
3088 return;
3089 }
3090
3091 max_cmd = instance->max_fw_cmds;
3092
3093 /* size of cmd_list array */
3094 sz = sizeof (struct mrsas_cmd *) * max_cmd;
3095
3096 /* First free each cmd */
3097 for (i = 0; i < max_cmd; i++) {
3098 if (instance->cmd_list[i] != NULL) {
3099 kmem_free(instance->cmd_list[i],
3100 sizeof (struct mrsas_cmd));
3101 }
3102
3103 instance->cmd_list[i] = NULL;
3104 }
3105
3106 /* Now, free cmd_list array */
3107 if (instance->cmd_list != NULL)
3108 kmem_free(instance->cmd_list, sz);
3109
3110 instance->cmd_list = NULL;
3111
3112 INIT_LIST_HEAD(&instance->cmd_pool_list);
3113 INIT_LIST_HEAD(&instance->cmd_pend_list);
3114 if (instance->tbolt) {
3115 INIT_LIST_HEAD(&instance->cmd_app_pool_list);
3116 } else {
3117 INIT_LIST_HEAD(&instance->app_cmd_pool_list);
3118 }
3119
3120 }
3121
3122
3123 /*
3124 * mrsas_alloc_cmd_pool
3125 */
3126 int
3127 mrsas_alloc_cmd_pool(struct mrsas_instance *instance)
3128 {
3129 int i;
3130 int count;
3131 uint32_t max_cmd;
3132 uint32_t reserve_cmd;
3133 size_t sz;
3134
3135 struct mrsas_cmd *cmd;
3136
3137 max_cmd = instance->max_fw_cmds;
3138 con_log(CL_ANN1, (CE_NOTE, "mrsas_alloc_cmd_pool: "
3139 "max_cmd %x", max_cmd));
3140
3141
3142 sz = sizeof (struct mrsas_cmd *) * max_cmd;
3143
3144 /*
3145 * instance->cmd_list is an array of struct mrsas_cmd pointers.
3146 * Allocate the dynamic array first and then allocate individual
3147 * commands.
3148 */
3149 instance->cmd_list = kmem_zalloc(sz, KM_SLEEP);
3150 ASSERT(instance->cmd_list);
3151
3152 /* create a frame pool and assign one frame to each cmd */
3153 for (count = 0; count < max_cmd; count++) {
3154 instance->cmd_list[count] =
3155 kmem_zalloc(sizeof (struct mrsas_cmd), KM_SLEEP);
3156 ASSERT(instance->cmd_list[count]);
3157 }
3158
3159 /* add all the commands to command pool */
3160
3161 INIT_LIST_HEAD(&instance->cmd_pool_list);
3162 INIT_LIST_HEAD(&instance->cmd_pend_list);
3163 INIT_LIST_HEAD(&instance->app_cmd_pool_list);
3164
3165 reserve_cmd = MRSAS_APP_RESERVED_CMDS;
3166
3167 for (i = 0; i < reserve_cmd; i++) {
3168 cmd = instance->cmd_list[i];
3169 cmd->index = i;
3170 mlist_add_tail(&cmd->list, &instance->app_cmd_pool_list);
3171 }
3172
3173
3174 for (i = reserve_cmd; i < max_cmd; i++) {
3175 cmd = instance->cmd_list[i];
3176 cmd->index = i;
3177 mlist_add_tail(&cmd->list, &instance->cmd_pool_list);
3178 }
3179
3180 return (DDI_SUCCESS);
3181
3182 mrsas_undo_cmds:
3183 if (count > 0) {
3184 /* free each cmd */
3185 for (i = 0; i < count; i++) {
3186 if (instance->cmd_list[i] != NULL) {
3187 kmem_free(instance->cmd_list[i],
3188 sizeof (struct mrsas_cmd));
3189 }
3190 instance->cmd_list[i] = NULL;
3191 }
3192 }
3193
3194 mrsas_undo_cmd_list:
3195 if (instance->cmd_list != NULL)
3196 kmem_free(instance->cmd_list, sz);
3197 instance->cmd_list = NULL;
3198
3199 return (DDI_FAILURE);
3200 }
3201
3202
3203 /*
3204 * free_space_for_mfi
3205 */
3206 static void
3207 free_space_for_mfi(struct mrsas_instance *instance)
3208 {
3209
3210 /* already freed */
3211 if (instance->cmd_list == NULL) {
3212 return;
3213 }
3214
3215 /* Free additional dma buffer */
3216 free_additional_dma_buffer(instance);
3217
3218 /* Free the MFI frame pool */
3219 destroy_mfi_frame_pool(instance);
3220
3221 /* Free all the commands in the cmd_list */
3222 /* Free the cmd_list buffer itself */
3223 mrsas_free_cmd_pool(instance);
3224 }
3225
3226 /*
3227 * alloc_space_for_mfi
3228 */
3229 static int
3230 alloc_space_for_mfi(struct mrsas_instance *instance)
3231 {
3232 /* Allocate command pool (memory for cmd_list & individual commands) */
3233 if (mrsas_alloc_cmd_pool(instance)) {
3234 cmn_err(CE_WARN, "error creating cmd pool");
3235 return (DDI_FAILURE);
3236 }
3237
3238 /* Allocate MFI Frame pool */
3239 if (create_mfi_frame_pool(instance)) {
3240 cmn_err(CE_WARN, "error creating frame DMA pool");
3241 goto mfi_undo_cmd_pool;
3242 }
3243
3244 /* Allocate additional DMA buffer */
3245 if (alloc_additional_dma_buffer(instance)) {
3246 cmn_err(CE_WARN, "error creating frame DMA pool");
3247 goto mfi_undo_frame_pool;
3248 }
3249
3250 return (DDI_SUCCESS);
3251
3252 mfi_undo_frame_pool:
3253 destroy_mfi_frame_pool(instance);
3254
3255 mfi_undo_cmd_pool:
3256 mrsas_free_cmd_pool(instance);
3257
3258 return (DDI_FAILURE);
3259 }
3260
3261
3262
3263 /*
3264 * get_ctrl_info
3265 */
3266 static int
3267 get_ctrl_info(struct mrsas_instance *instance,
3268 struct mrsas_ctrl_info *ctrl_info)
3269 {
3270 int ret = 0;
3271
3272 struct mrsas_cmd *cmd;
3273 struct mrsas_dcmd_frame *dcmd;
3274 struct mrsas_ctrl_info *ci;
3275
3276 if (instance->tbolt) {
3277 cmd = get_raid_msg_mfi_pkt(instance);
3278 } else {
3279 cmd = get_mfi_pkt(instance);
3280 }
3281
3282 if (!cmd) {
3283 con_log(CL_ANN, (CE_WARN,
3284 "Failed to get a cmd for ctrl info"));
3285 DTRACE_PROBE2(info_mfi_err, uint16_t, instance->fw_outstanding,
3286 uint16_t, instance->max_fw_cmds);
3287 return (DDI_FAILURE);
3288 }
3289
3290 /* Clear the frame buffer and assign back the context id */
3291 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3292 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3293 cmd->index);
3294
3295 dcmd = &cmd->frame->dcmd;
3296
3297 ci = (struct mrsas_ctrl_info *)instance->internal_buf;
3298
3299 if (!ci) {
3300 cmn_err(CE_WARN,
3301 "Failed to alloc mem for ctrl info");
3302 return_mfi_pkt(instance, cmd);
3303 return (DDI_FAILURE);
3304 }
3305
3306 (void) memset(ci, 0, sizeof (struct mrsas_ctrl_info));
3307
3308 /* for( i = 0; i < DCMD_MBOX_SZ; i++ ) dcmd->mbox.b[i] = 0; */
3309 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ);
3310
3311 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD);
3312 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status,
3313 MFI_CMD_STATUS_POLL_MODE);
3314 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1);
3315 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags,
3316 MFI_FRAME_DIR_READ);
3317 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0);
3318 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len,
3319 sizeof (struct mrsas_ctrl_info));
3320 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode,
3321 MR_DCMD_CTRL_GET_INFO);
3322 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr,
3323 instance->internal_buf_dmac_add);
3324 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length,
3325 sizeof (struct mrsas_ctrl_info));
3326
3327 cmd->frame_count = 1;
3328
3329 if (instance->tbolt) {
3330 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
3331 }
3332
3333 if (!instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
3334 ret = 0;
3335
3336 ctrl_info->max_request_size = ddi_get32(
3337 cmd->frame_dma_obj.acc_handle, &ci->max_request_size);
3338
3339 ctrl_info->ld_present_count = ddi_get16(
3340 cmd->frame_dma_obj.acc_handle, &ci->ld_present_count);
3341
3342 ctrl_info->properties.on_off_properties = ddi_get32(
3343 cmd->frame_dma_obj.acc_handle,
3344 &ci->properties.on_off_properties);
3345 ddi_rep_get8(cmd->frame_dma_obj.acc_handle,
3346 (uint8_t *)(ctrl_info->product_name),
3347 (uint8_t *)(ci->product_name), 80 * sizeof (char),
3348 DDI_DEV_AUTOINCR);
3349 /* should get more members of ci with ddi_get when needed */
3350 } else {
3351 cmn_err(CE_WARN, "get_ctrl_info: Ctrl info failed");
3352 ret = -1;
3353 }
3354
3355 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) {
3356 ret = -1;
3357 }
3358 if (instance->tbolt) {
3359 return_raid_msg_mfi_pkt(instance, cmd);
3360 } else {
3361 return_mfi_pkt(instance, cmd);
3362 }
3363
3364 return (ret);
3365 }
3366
3367 /*
3368 * abort_aen_cmd
3369 */
3370 static int
3371 abort_aen_cmd(struct mrsas_instance *instance,
3372 struct mrsas_cmd *cmd_to_abort)
3373 {
3374 int ret = 0;
3375
3376 struct mrsas_cmd *cmd;
3377 struct mrsas_abort_frame *abort_fr;
3378
3379 con_log(CL_ANN1, (CE_NOTE, "chkpnt: abort_aen:%d", __LINE__));
3380
3381 if (instance->tbolt) {
3382 cmd = get_raid_msg_mfi_pkt(instance);
3383 } else {
3384 cmd = get_mfi_pkt(instance);
3385 }
3386
3387 if (!cmd) {
3388 con_log(CL_ANN1, (CE_WARN,
3389 "abort_aen_cmd():Failed to get a cmd for abort_aen_cmd"));
3390 DTRACE_PROBE2(abort_mfi_err, uint16_t, instance->fw_outstanding,
3391 uint16_t, instance->max_fw_cmds);
3392 return (DDI_FAILURE);
3393 }
3394
3395 /* Clear the frame buffer and assign back the context id */
3396 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3397 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3398 cmd->index);
3399
3400 abort_fr = &cmd->frame->abort;
3401
3402 /* prepare and issue the abort frame */
3403 ddi_put8(cmd->frame_dma_obj.acc_handle,
3404 &abort_fr->cmd, MFI_CMD_OP_ABORT);
3405 ddi_put8(cmd->frame_dma_obj.acc_handle, &abort_fr->cmd_status,
3406 MFI_CMD_STATUS_SYNC_MODE);
3407 ddi_put16(cmd->frame_dma_obj.acc_handle, &abort_fr->flags, 0);
3408 ddi_put32(cmd->frame_dma_obj.acc_handle, &abort_fr->abort_context,
3409 cmd_to_abort->index);
3410 ddi_put32(cmd->frame_dma_obj.acc_handle,
3411 &abort_fr->abort_mfi_phys_addr_lo, cmd_to_abort->frame_phys_addr);
3412 ddi_put32(cmd->frame_dma_obj.acc_handle,
3413 &abort_fr->abort_mfi_phys_addr_hi, 0);
3414
3415 instance->aen_cmd->abort_aen = 1;
3416
3417 cmd->frame_count = 1;
3418
3419 if (instance->tbolt) {
3420 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
3421 }
3422
3423 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
3424 con_log(CL_ANN1, (CE_WARN,
3425 "abort_aen_cmd: issue_cmd_in_poll_mode failed"));
3426 ret = -1;
3427 } else {
3428 ret = 0;
3429 }
3430
3431 instance->aen_cmd->abort_aen = 1;
3432 instance->aen_cmd = 0;
3433
3434 if (instance->tbolt) {
3435 return_raid_msg_mfi_pkt(instance, cmd);
3436 } else {
3437 return_mfi_pkt(instance, cmd);
3438 }
3439
3440 atomic_add_16(&instance->fw_outstanding, (-1));
3441
3442 return (ret);
3443 }
3444
3445
3446 static int
3447 mrsas_build_init_cmd(struct mrsas_instance *instance,
3448 struct mrsas_cmd **cmd_ptr)
3449 {
3450 struct mrsas_cmd *cmd;
3451 struct mrsas_init_frame *init_frame;
3452 struct mrsas_init_queue_info *initq_info;
3453 struct mrsas_drv_ver drv_ver_info;
3454
3455
3456 /*
3457 * Prepare a init frame. Note the init frame points to queue info
3458 * structure. Each frame has SGL allocated after first 64 bytes. For
3459 * this frame - since we don't need any SGL - we use SGL's space as
3460 * queue info structure
3461 */
3462 cmd = *cmd_ptr;
3463
3464
3465 /* Clear the frame buffer and assign back the context id */
3466 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3467 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3468 cmd->index);
3469
3470 init_frame = (struct mrsas_init_frame *)cmd->frame;
3471 initq_info = (struct mrsas_init_queue_info *)
3472 ((unsigned long)init_frame + 64);
3473
3474 (void) memset(init_frame, 0, MRMFI_FRAME_SIZE);
3475 (void) memset(initq_info, 0, sizeof (struct mrsas_init_queue_info));
3476
3477 ddi_put32(cmd->frame_dma_obj.acc_handle, &initq_info->init_flags, 0);
3478
3479 ddi_put32(cmd->frame_dma_obj.acc_handle,
3480 &initq_info->reply_queue_entries, instance->max_fw_cmds + 1);
3481
3482 ddi_put32(cmd->frame_dma_obj.acc_handle,
3483 &initq_info->producer_index_phys_addr_hi, 0);
3484 ddi_put32(cmd->frame_dma_obj.acc_handle,
3485 &initq_info->producer_index_phys_addr_lo,
3486 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address);
3487
3488 ddi_put32(cmd->frame_dma_obj.acc_handle,
3489 &initq_info->consumer_index_phys_addr_hi, 0);
3490 ddi_put32(cmd->frame_dma_obj.acc_handle,
3491 &initq_info->consumer_index_phys_addr_lo,
3492 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 4);
3493
3494 ddi_put32(cmd->frame_dma_obj.acc_handle,
3495 &initq_info->reply_queue_start_phys_addr_hi, 0);
3496 ddi_put32(cmd->frame_dma_obj.acc_handle,
3497 &initq_info->reply_queue_start_phys_addr_lo,
3498 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 8);
3499
3500 ddi_put8(cmd->frame_dma_obj.acc_handle,
3501 &init_frame->cmd, MFI_CMD_OP_INIT);
3502 ddi_put8(cmd->frame_dma_obj.acc_handle, &init_frame->cmd_status,
3503 MFI_CMD_STATUS_POLL_MODE);
3504 ddi_put16(cmd->frame_dma_obj.acc_handle, &init_frame->flags, 0);
3505 ddi_put32(cmd->frame_dma_obj.acc_handle,
3506 &init_frame->queue_info_new_phys_addr_lo,
3507 cmd->frame_phys_addr + 64);
3508 ddi_put32(cmd->frame_dma_obj.acc_handle,
3509 &init_frame->queue_info_new_phys_addr_hi, 0);
3510
3511
3512 /* fill driver version information */
3513 fill_up_drv_ver(&drv_ver_info);
3514
3515 /* allocate the driver version data transfer buffer */
3516 instance->drv_ver_dma_obj.size = sizeof (drv_ver_info.drv_ver);
3517 instance->drv_ver_dma_obj.dma_attr = mrsas_generic_dma_attr;
3518 instance->drv_ver_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
3519 instance->drv_ver_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
3520 instance->drv_ver_dma_obj.dma_attr.dma_attr_sgllen = 1;
3521 instance->drv_ver_dma_obj.dma_attr.dma_attr_align = 1;
3522
3523 if (mrsas_alloc_dma_obj(instance, &instance->drv_ver_dma_obj,
3524 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
3525 con_log(CL_ANN, (CE_WARN,
3526 "init_mfi : Could not allocate driver version buffer."));
3527 return (DDI_FAILURE);
3528 }
3529 /* copy driver version to dma buffer */
3530 (void) memset(instance->drv_ver_dma_obj.buffer, 0,
3531 sizeof (drv_ver_info.drv_ver));
3532 ddi_rep_put8(cmd->frame_dma_obj.acc_handle,
3533 (uint8_t *)drv_ver_info.drv_ver,
3534 (uint8_t *)instance->drv_ver_dma_obj.buffer,
3535 sizeof (drv_ver_info.drv_ver), DDI_DEV_AUTOINCR);
3536
3537
3538 /* copy driver version physical address to init frame */
3539 ddi_put64(cmd->frame_dma_obj.acc_handle, &init_frame->driverversion,
3540 instance->drv_ver_dma_obj.dma_cookie[0].dmac_address);
3541
3542 ddi_put32(cmd->frame_dma_obj.acc_handle, &init_frame->data_xfer_len,
3543 sizeof (struct mrsas_init_queue_info));
3544
3545 cmd->frame_count = 1;
3546
3547 *cmd_ptr = cmd;
3548
3549 return (DDI_SUCCESS);
3550 }
3551
3552
3553 /*
3554 * mrsas_init_adapter_ppc - Initialize MFI interface adapter.
3555 */
3556 int
3557 mrsas_init_adapter_ppc(struct mrsas_instance *instance)
3558 {
3559 struct mrsas_cmd *cmd;
3560
3561 /*
3562 * allocate memory for mfi adapter(cmd pool, individual commands, mfi
3563 * frames etc
3564 */
3565 if (alloc_space_for_mfi(instance) != DDI_SUCCESS) {
3566 con_log(CL_ANN, (CE_NOTE,
3567 "Error, failed to allocate memory for MFI adapter"));
3568 return (DDI_FAILURE);
3569 }
3570
3571 /* Build INIT command */
3572 cmd = get_mfi_pkt(instance);
3573
3574 if (mrsas_build_init_cmd(instance, &cmd) != DDI_SUCCESS) {
3575 con_log(CL_ANN,
3576 (CE_NOTE, "Error, failed to build INIT command"));
3577
3578 goto fail_undo_alloc_mfi_space;
3579 }
3580
3581 /*
3582 * Disable interrupt before sending init frame ( see linux driver code)
3583 * send INIT MFI frame in polled mode
3584 */
3585 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
3586 con_log(CL_ANN, (CE_WARN, "failed to init firmware"));
3587 goto fail_fw_init;
3588 }
3589
3590 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS)
3591 goto fail_fw_init;
3592 return_mfi_pkt(instance, cmd);
3593
3594 if (ctio_enable &&
3595 (instance->func_ptr->read_fw_status_reg(instance) & 0x04000000)) {
3596 con_log(CL_ANN, (CE_NOTE, "mr_sas: IEEE SGL's supported"));
3597 instance->flag_ieee = 1;
3598 } else {
3599 instance->flag_ieee = 0;
3600 }
3601
3602 instance->unroll.alloc_space_mfi = 1;
3603 instance->unroll.verBuff = 1;
3604
3605 return (DDI_SUCCESS);
3606
3607
3608 fail_fw_init:
3609 (void) mrsas_free_dma_obj(instance, instance->drv_ver_dma_obj);
3610
3611 fail_undo_alloc_mfi_space:
3612 return_mfi_pkt(instance, cmd);
3613 free_space_for_mfi(instance);
3614
3615 return (DDI_FAILURE);
3616
3617 }
3618
3619 /*
3620 * mrsas_init_adapter - Initialize adapter.
3621 */
3622 int
3623 mrsas_init_adapter(struct mrsas_instance *instance)
3624 {
3625 struct mrsas_ctrl_info ctrl_info;
3626
3627
3628 /* we expect the FW state to be READY */
3629 if (mfi_state_transition_to_ready(instance)) {
3630 con_log(CL_ANN, (CE_WARN, "mr_sas: F/W is not ready"));
3631 return (DDI_FAILURE);
3632 }
3633
3634 /* get various operational parameters from status register */
3635 instance->max_num_sge =
3636 (instance->func_ptr->read_fw_status_reg(instance) &
3637 0xFF0000) >> 0x10;
3638 instance->max_num_sge =
3639 (instance->max_num_sge > MRSAS_MAX_SGE_CNT) ?
3640 MRSAS_MAX_SGE_CNT : instance->max_num_sge;
3641
3642 /*
3643 * Reduce the max supported cmds by 1. This is to ensure that the
3644 * reply_q_sz (1 more than the max cmd that driver may send)
3645 * does not exceed max cmds that the FW can support
3646 */
3647 instance->max_fw_cmds =
3648 instance->func_ptr->read_fw_status_reg(instance) & 0xFFFF;
3649 instance->max_fw_cmds = instance->max_fw_cmds - 1;
3650
3651
3652
3653 /* Initialize adapter */
3654 if (instance->func_ptr->init_adapter(instance) != DDI_SUCCESS) {
3655 con_log(CL_ANN,
3656 (CE_WARN, "mr_sas: could not initialize adapter"));
3657 return (DDI_FAILURE);
3658 }
3659
3660 /* gather misc FW related information */
3661 instance->disable_online_ctrl_reset = 0;
3662
3663 if (!get_ctrl_info(instance, &ctrl_info)) {
3664 instance->max_sectors_per_req = ctrl_info.max_request_size;
3665 con_log(CL_ANN1, (CE_NOTE,
3666 "product name %s ld present %d",
3667 ctrl_info.product_name, ctrl_info.ld_present_count));
3668 } else {
3669 instance->max_sectors_per_req = instance->max_num_sge *
3670 PAGESIZE / 512;
3671 }
3672
3673 if (ctrl_info.properties.on_off_properties & DISABLE_OCR_PROP_FLAG)
3674 instance->disable_online_ctrl_reset = 1;
3675
3676 return (DDI_SUCCESS);
3677
3678 }
3679
3680
3681
3682 static int
3683 mrsas_issue_init_mfi(struct mrsas_instance *instance)
3684 {
3685 struct mrsas_cmd *cmd;
3686 struct mrsas_init_frame *init_frame;
3687 struct mrsas_init_queue_info *initq_info;
3688
3689 /*
3690 * Prepare a init frame. Note the init frame points to queue info
3691 * structure. Each frame has SGL allocated after first 64 bytes. For
3692 * this frame - since we don't need any SGL - we use SGL's space as
3693 * queue info structure
3694 */
3695 con_log(CL_ANN1, (CE_NOTE,
3696 "mrsas_issue_init_mfi: entry\n"));
3697 cmd = get_mfi_app_pkt(instance);
3698
3699 if (!cmd) {
3700 con_log(CL_ANN1, (CE_WARN,
3701 "mrsas_issue_init_mfi: get_pkt failed\n"));
3702 return (DDI_FAILURE);
3703 }
3704
3705 /* Clear the frame buffer and assign back the context id */
3706 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3707 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3708 cmd->index);
3709
3710 init_frame = (struct mrsas_init_frame *)cmd->frame;
3711 initq_info = (struct mrsas_init_queue_info *)
3712 ((unsigned long)init_frame + 64);
3713
3714 (void) memset(init_frame, 0, MRMFI_FRAME_SIZE);
3715 (void) memset(initq_info, 0, sizeof (struct mrsas_init_queue_info));
3716
3717 ddi_put32(cmd->frame_dma_obj.acc_handle, &initq_info->init_flags, 0);
3718
3719 ddi_put32(cmd->frame_dma_obj.acc_handle,
3720 &initq_info->reply_queue_entries, instance->max_fw_cmds + 1);
3721 ddi_put32(cmd->frame_dma_obj.acc_handle,
3722 &initq_info->producer_index_phys_addr_hi, 0);
3723 ddi_put32(cmd->frame_dma_obj.acc_handle,
3724 &initq_info->producer_index_phys_addr_lo,
3725 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address);
3726 ddi_put32(cmd->frame_dma_obj.acc_handle,
3727 &initq_info->consumer_index_phys_addr_hi, 0);
3728 ddi_put32(cmd->frame_dma_obj.acc_handle,
3729 &initq_info->consumer_index_phys_addr_lo,
3730 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 4);
3731
3732 ddi_put32(cmd->frame_dma_obj.acc_handle,
3733 &initq_info->reply_queue_start_phys_addr_hi, 0);
3734 ddi_put32(cmd->frame_dma_obj.acc_handle,
3735 &initq_info->reply_queue_start_phys_addr_lo,
3736 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 8);
3737
3738 ddi_put8(cmd->frame_dma_obj.acc_handle,
3739 &init_frame->cmd, MFI_CMD_OP_INIT);
3740 ddi_put8(cmd->frame_dma_obj.acc_handle, &init_frame->cmd_status,
3741 MFI_CMD_STATUS_POLL_MODE);
3742 ddi_put16(cmd->frame_dma_obj.acc_handle, &init_frame->flags, 0);
3743 ddi_put32(cmd->frame_dma_obj.acc_handle,
3744 &init_frame->queue_info_new_phys_addr_lo,
3745 cmd->frame_phys_addr + 64);
3746 ddi_put32(cmd->frame_dma_obj.acc_handle,
3747 &init_frame->queue_info_new_phys_addr_hi, 0);
3748
3749 ddi_put32(cmd->frame_dma_obj.acc_handle, &init_frame->data_xfer_len,
3750 sizeof (struct mrsas_init_queue_info));
3751
3752 cmd->frame_count = 1;
3753
3754 /* issue the init frame in polled mode */
3755 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
3756 con_log(CL_ANN1, (CE_WARN,
3757 "mrsas_issue_init_mfi():failed to "
3758 "init firmware"));
3759 return_mfi_app_pkt(instance, cmd);
3760 return (DDI_FAILURE);
3761 }
3762
3763 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) {
3764 return_mfi_pkt(instance, cmd);
3765 return (DDI_FAILURE);
3766 }
3767
3768 return_mfi_app_pkt(instance, cmd);
3769 con_log(CL_ANN1, (CE_CONT, "mrsas_issue_init_mfi: Done"));
3770
3771 return (DDI_SUCCESS);
3772 }
3773 /*
3774 * mfi_state_transition_to_ready : Move the FW to READY state
3775 *
3776 * @reg_set : MFI register set
3777 */
3778 int
3779 mfi_state_transition_to_ready(struct mrsas_instance *instance)
3780 {
3781 int i;
3782 uint8_t max_wait;
3783 uint32_t fw_ctrl = 0;
3784 uint32_t fw_state;
3785 uint32_t cur_state;
3786 uint32_t cur_abs_reg_val;
3787 uint32_t prev_abs_reg_val;
3788 uint32_t status;
3789
3790 cur_abs_reg_val =
3791 instance->func_ptr->read_fw_status_reg(instance);
3792 fw_state =
3793 cur_abs_reg_val & MFI_STATE_MASK;
3794 con_log(CL_ANN1, (CE_CONT,
3795 "mfi_state_transition_to_ready:FW state = 0x%x", fw_state));
3796
3797 while (fw_state != MFI_STATE_READY) {
3798 con_log(CL_ANN, (CE_CONT,
3799 "mfi_state_transition_to_ready:FW state%x", fw_state));
3800
3801 switch (fw_state) {
3802 case MFI_STATE_FAULT:
3803 con_log(CL_ANN, (CE_NOTE,
3804 "mr_sas: FW in FAULT state!!"));
3805
3806 return (ENODEV);
3807 case MFI_STATE_WAIT_HANDSHAKE:
3808 /* set the CLR bit in IMR0 */
3809 con_log(CL_ANN1, (CE_NOTE,
3810 "mr_sas: FW waiting for HANDSHAKE"));
3811 /*
3812 * PCI_Hot Plug: MFI F/W requires
3813 * (MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG)
3814 * to be set
3815 */
3816 /* WR_IB_MSG_0(MFI_INIT_CLEAR_HANDSHAKE, instance); */
3817 if (!instance->tbolt) {
3818 WR_IB_DOORBELL(MFI_INIT_CLEAR_HANDSHAKE |
3819 MFI_INIT_HOTPLUG, instance);
3820 } else {
3821 WR_RESERVED0_REGISTER(MFI_INIT_CLEAR_HANDSHAKE |
3822 MFI_INIT_HOTPLUG, instance);
3823 }
3824 max_wait = (instance->tbolt == 1) ? 180 : 2;
3825 cur_state = MFI_STATE_WAIT_HANDSHAKE;
3826 break;
3827 case MFI_STATE_BOOT_MESSAGE_PENDING:
3828 /* set the CLR bit in IMR0 */
3829 con_log(CL_ANN1, (CE_NOTE,
3830 "mr_sas: FW state boot message pending"));
3831 /*
3832 * PCI_Hot Plug: MFI F/W requires
3833 * (MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG)
3834 * to be set
3835 */
3836 if (!instance->tbolt) {
3837 WR_IB_DOORBELL(MFI_INIT_HOTPLUG, instance);
3838 } else {
3839 WR_RESERVED0_REGISTER(MFI_INIT_HOTPLUG,
3840 instance);
3841 }
3842 max_wait = (instance->tbolt == 1) ? 180 : 10;
3843 cur_state = MFI_STATE_BOOT_MESSAGE_PENDING;
3844 break;
3845 case MFI_STATE_OPERATIONAL:
3846 /* bring it to READY state; assuming max wait 2 secs */
3847 instance->func_ptr->disable_intr(instance);
3848 con_log(CL_ANN1, (CE_NOTE,
3849 "mr_sas: FW in OPERATIONAL state"));
3850 /*
3851 * PCI_Hot Plug: MFI F/W requires
3852 * (MFI_INIT_READY | MFI_INIT_MFIMODE | MFI_INIT_ABORT)
3853 * to be set
3854 */
3855 /* WR_IB_DOORBELL(MFI_INIT_READY, instance); */
3856 if (!instance->tbolt) {
3857 WR_IB_DOORBELL(MFI_RESET_FLAGS, instance);
3858 } else {
3859 WR_RESERVED0_REGISTER(MFI_RESET_FLAGS,
3860 instance);
3861
3862 for (i = 0; i < (10 * 1000); i++) {
3863 status =
3864 RD_RESERVED0_REGISTER(instance);
3865 if (status & 1) {
3866 delay(1 *
3867 drv_usectohz(MILLISEC));
3868 } else {
3869 break;
3870 }
3871 }
3872
3873 }
3874 max_wait = (instance->tbolt == 1) ? 180 : 10;
3875 cur_state = MFI_STATE_OPERATIONAL;
3876 break;
3877 case MFI_STATE_UNDEFINED:
3878 /* this state should not last for more than 2 seconds */
3879 con_log(CL_ANN1, (CE_NOTE, "FW state undefined"));
3880
3881 max_wait = (instance->tbolt == 1) ? 180 : 2;
3882 cur_state = MFI_STATE_UNDEFINED;
3883 break;
3884 case MFI_STATE_BB_INIT:
3885 max_wait = (instance->tbolt == 1) ? 180 : 2;
3886 cur_state = MFI_STATE_BB_INIT;
3887 break;
3888 case MFI_STATE_FW_INIT:
3889 max_wait = (instance->tbolt == 1) ? 180 : 2;
3890 cur_state = MFI_STATE_FW_INIT;
3891 break;
3892 case MFI_STATE_FW_INIT_2:
3893 max_wait = 180;
3894 cur_state = MFI_STATE_FW_INIT_2;
3895 break;
3896 case MFI_STATE_DEVICE_SCAN:
3897 max_wait = 180;
3898 cur_state = MFI_STATE_DEVICE_SCAN;
3899 prev_abs_reg_val = cur_abs_reg_val;
3900 con_log(CL_NONE, (CE_NOTE,
3901 "Device scan in progress ...\n"));
3902 break;
3903 case MFI_STATE_FLUSH_CACHE:
3904 max_wait = 180;
3905 cur_state = MFI_STATE_FLUSH_CACHE;
3906 break;
3907 default:
3908 con_log(CL_ANN1, (CE_NOTE,
3909 "mr_sas: Unknown state 0x%x", fw_state));
3910 return (ENODEV);
3911 }
3912
3913 /* the cur_state should not last for more than max_wait secs */
3914 for (i = 0; i < (max_wait * MILLISEC); i++) {
3915 /* fw_state = RD_OB_MSG_0(instance) & MFI_STATE_MASK; */
3916 cur_abs_reg_val =
3917 instance->func_ptr->read_fw_status_reg(instance);
3918 fw_state = cur_abs_reg_val & MFI_STATE_MASK;
3919
3920 if (fw_state == cur_state) {
3921 delay(1 * drv_usectohz(MILLISEC));
3922 } else {
3923 break;
3924 }
3925 }
3926 if (fw_state == MFI_STATE_DEVICE_SCAN) {
3927 if (prev_abs_reg_val != cur_abs_reg_val) {
3928 continue;
3929 }
3930 }
3931
3932 /* return error if fw_state hasn't changed after max_wait */
3933 if (fw_state == cur_state) {
3934 con_log(CL_ANN1, (CE_WARN,
3935 "FW state hasn't changed in %d secs", max_wait));
3936 return (ENODEV);
3937 }
3938 };
3939
3940 if (!instance->tbolt) {
3941 fw_ctrl = RD_IB_DOORBELL(instance);
3942 con_log(CL_ANN1, (CE_CONT,
3943 "mfi_state_transition_to_ready:FW ctrl = 0x%x", fw_ctrl));
3944
3945 /*
3946 * Write 0xF to the doorbell register to do the following.
3947 * - Abort all outstanding commands (bit 0).
3948 * - Transition from OPERATIONAL to READY state (bit 1).
3949 * - Discard (possible) low MFA posted in 64-bit mode (bit-2).
3950 * - Set to release FW to continue running (i.e. BIOS handshake
3951 * (bit 3).
3952 */
3953 WR_IB_DOORBELL(0xF, instance);
3954 }
3955
3956 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) {
3957 return (EIO);
3958 }
3959
3960 return (DDI_SUCCESS);
3961 }
3962
3963 /*
3964 * get_seq_num
3965 */
3966 static int
3967 get_seq_num(struct mrsas_instance *instance,
3968 struct mrsas_evt_log_info *eli)
3969 {
3970 int ret = DDI_SUCCESS;
3971
3972 dma_obj_t dcmd_dma_obj;
3973 struct mrsas_cmd *cmd;
3974 struct mrsas_dcmd_frame *dcmd;
3975 struct mrsas_evt_log_info *eli_tmp;
3976 if (instance->tbolt) {
3977 cmd = get_raid_msg_mfi_pkt(instance);
3978 } else {
3979 cmd = get_mfi_pkt(instance);
3980 }
3981
3982 if (!cmd) {
3983 cmn_err(CE_WARN, "mr_sas: failed to get a cmd");
3984 DTRACE_PROBE2(seq_num_mfi_err, uint16_t,
3985 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
3986 return (ENOMEM);
3987 }
3988
3989 /* Clear the frame buffer and assign back the context id */
3990 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3991 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3992 cmd->index);
3993
3994 dcmd = &cmd->frame->dcmd;
3995
3996 /* allocate the data transfer buffer */
3997 dcmd_dma_obj.size = sizeof (struct mrsas_evt_log_info);
3998 dcmd_dma_obj.dma_attr = mrsas_generic_dma_attr;
3999 dcmd_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
4000 dcmd_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
4001 dcmd_dma_obj.dma_attr.dma_attr_sgllen = 1;
4002 dcmd_dma_obj.dma_attr.dma_attr_align = 1;
4003
4004 if (mrsas_alloc_dma_obj(instance, &dcmd_dma_obj,
4005 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
4006 cmn_err(CE_WARN,
4007 "get_seq_num: could not allocate data transfer buffer.");
4008 return (DDI_FAILURE);
4009 }
4010
4011 (void) memset(dcmd_dma_obj.buffer, 0,
4012 sizeof (struct mrsas_evt_log_info));
4013
4014 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ);
4015
4016 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD);
4017 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0);
4018 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1);
4019 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags,
4020 MFI_FRAME_DIR_READ);
4021 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0);
4022 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len,
4023 sizeof (struct mrsas_evt_log_info));
4024 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode,
4025 MR_DCMD_CTRL_EVENT_GET_INFO);
4026 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length,
4027 sizeof (struct mrsas_evt_log_info));
4028 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr,
4029 dcmd_dma_obj.dma_cookie[0].dmac_address);
4030
4031 cmd->sync_cmd = MRSAS_TRUE;
4032 cmd->frame_count = 1;
4033
4034 if (instance->tbolt) {
4035 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
4036 }
4037
4038 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
4039 cmn_err(CE_WARN, "get_seq_num: "
4040 "failed to issue MRSAS_DCMD_CTRL_EVENT_GET_INFO");
4041 ret = DDI_FAILURE;
4042 } else {
4043 eli_tmp = (struct mrsas_evt_log_info *)dcmd_dma_obj.buffer;
4044 eli->newest_seq_num = ddi_get32(cmd->frame_dma_obj.acc_handle,
4045 &eli_tmp->newest_seq_num);
4046 ret = DDI_SUCCESS;
4047 }
4048
4049 if (mrsas_free_dma_obj(instance, dcmd_dma_obj) != DDI_SUCCESS)
4050 ret = DDI_FAILURE;
4051
4052 if (instance->tbolt) {
4053 return_raid_msg_mfi_pkt(instance, cmd);
4054 } else {
4055 return_mfi_pkt(instance, cmd);
4056 }
4057
4058 return (ret);
4059 }
4060
4061 /*
4062 * start_mfi_aen
4063 */
4064 static int
4065 start_mfi_aen(struct mrsas_instance *instance)
4066 {
4067 int ret = 0;
4068
4069 struct mrsas_evt_log_info eli;
4070 union mrsas_evt_class_locale class_locale;
4071
4072 /* get the latest sequence number from FW */
4073 (void) memset(&eli, 0, sizeof (struct mrsas_evt_log_info));
4074
4075 if (get_seq_num(instance, &eli)) {
4076 cmn_err(CE_WARN, "start_mfi_aen: failed to get seq num");
4077 return (-1);
4078 }
4079
4080 /* register AEN with FW for latest sequence number plus 1 */
4081 class_locale.members.reserved = 0;
4082 class_locale.members.locale = LE_16(MR_EVT_LOCALE_ALL);
4083 class_locale.members.class = MR_EVT_CLASS_INFO;
4084 class_locale.word = LE_32(class_locale.word);
4085 ret = register_mfi_aen(instance, eli.newest_seq_num + 1,
4086 class_locale.word);
4087
4088 if (ret) {
4089 cmn_err(CE_WARN, "start_mfi_aen: aen registration failed");
4090 return (-1);
4091 }
4092
4093
4094 return (ret);
4095 }
4096
4097 /*
4098 * flush_cache
4099 */
4100 static void
4101 flush_cache(struct mrsas_instance *instance)
4102 {
4103 struct mrsas_cmd *cmd = NULL;
4104 struct mrsas_dcmd_frame *dcmd;
4105 if (instance->tbolt) {
4106 cmd = get_raid_msg_mfi_pkt(instance);
4107 } else {
4108 cmd = get_mfi_pkt(instance);
4109 }
4110
4111 if (!cmd) {
4112 con_log(CL_ANN1, (CE_WARN,
4113 "flush_cache():Failed to get a cmd for flush_cache"));
4114 DTRACE_PROBE2(flush_cache_err, uint16_t,
4115 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
4116 return;
4117 }
4118
4119 /* Clear the frame buffer and assign back the context id */
4120 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
4121 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
4122 cmd->index);
4123
4124 dcmd = &cmd->frame->dcmd;
4125
4126 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ);
4127
4128 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD);
4129 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0x0);
4130 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 0);
4131 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags,
4132 MFI_FRAME_DIR_NONE);
4133 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0);
4134 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 0);
4135 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode,
4136 MR_DCMD_CTRL_CACHE_FLUSH);
4137 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.b[0],
4138 MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE);
4139
4140 cmd->frame_count = 1;
4141
4142 if (instance->tbolt) {
4143 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
4144 }
4145
4146 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
4147 con_log(CL_ANN1, (CE_WARN,
4148 "flush_cache: failed to issue MFI_DCMD_CTRL_CACHE_FLUSH"));
4149 }
4150 con_log(CL_ANN1, (CE_CONT, "flush_cache done"));
4151 if (instance->tbolt) {
4152 return_raid_msg_mfi_pkt(instance, cmd);
4153 } else {
4154 return_mfi_pkt(instance, cmd);
4155 }
4156
4157 }
4158
4159 /*
4160 * service_mfi_aen- Completes an AEN command
4161 * @instance: Adapter soft state
4162 * @cmd: Command to be completed
4163 *
4164 */
4165 void
4166 service_mfi_aen(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
4167 {
4168 uint32_t seq_num;
4169 struct mrsas_evt_detail *evt_detail =
4170 (struct mrsas_evt_detail *)instance->mfi_evt_detail_obj.buffer;
4171 int rval = 0;
4172 int tgt = 0;
4173 uint8_t dtype;
4174 #ifdef PDSUPPORT
4175 mrsas_pd_address_t *pd_addr;
4176 #endif
4177 ddi_acc_handle_t acc_handle;
4178
4179 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
4180
4181 acc_handle = cmd->frame_dma_obj.acc_handle;
4182 cmd->cmd_status = ddi_get8(acc_handle, &cmd->frame->io.cmd_status);
4183 if (cmd->cmd_status == ENODATA) {
4184 cmd->cmd_status = 0;
4185 }
4186
4187 /*
4188 * log the MFI AEN event to the sysevent queue so that
4189 * application will get noticed
4190 */
4191 if (ddi_log_sysevent(instance->dip, DDI_VENDOR_LSI, "LSIMEGA", "SAS",
4192 NULL, NULL, DDI_NOSLEEP) != DDI_SUCCESS) {
4193 int instance_no = ddi_get_instance(instance->dip);
4194 con_log(CL_ANN, (CE_WARN,
4195 "mr_sas%d: Failed to log AEN event", instance_no));
4196 }
4197 /*
4198 * Check for any ld devices that has changed state. i.e. online
4199 * or offline.
4200 */
4201 con_log(CL_ANN1, (CE_CONT,
4202 "AEN: code = %x class = %x locale = %x args = %x",
4203 ddi_get32(acc_handle, &evt_detail->code),
4204 evt_detail->cl.members.class,
4205 ddi_get16(acc_handle, &evt_detail->cl.members.locale),
4206 ddi_get8(acc_handle, &evt_detail->arg_type)));
4207
4208 switch (ddi_get32(acc_handle, &evt_detail->code)) {
4209 case MR_EVT_CFG_CLEARED: {
4210 for (tgt = 0; tgt < MRDRV_MAX_LD; tgt++) {
4211 if (instance->mr_ld_list[tgt].dip != NULL) {
4212 mutex_enter(&instance->config_dev_mtx);
4213 instance->mr_ld_list[tgt].flag =
4214 (uint8_t)~MRDRV_TGT_VALID;
4215 mutex_exit(&instance->config_dev_mtx);
4216 rval = mrsas_service_evt(instance, tgt, 0,
4217 MRSAS_EVT_UNCONFIG_TGT, NULL);
4218 con_log(CL_ANN1, (CE_WARN,
4219 "mr_sas: CFG CLEARED AEN rval = %d "
4220 "tgt id = %d", rval, tgt));
4221 }
4222 }
4223 break;
4224 }
4225
4226 case MR_EVT_LD_DELETED: {
4227 tgt = ddi_get16(acc_handle, &evt_detail->args.ld.target_id);
4228 mutex_enter(&instance->config_dev_mtx);
4229 instance->mr_ld_list[tgt].flag = (uint8_t)~MRDRV_TGT_VALID;
4230 mutex_exit(&instance->config_dev_mtx);
4231 rval = mrsas_service_evt(instance,
4232 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 0,
4233 MRSAS_EVT_UNCONFIG_TGT, NULL);
4234 con_log(CL_ANN1, (CE_WARN, "mr_sas: LD DELETED AEN rval = %d "
4235 "tgt id = %d index = %d", rval,
4236 ddi_get16(acc_handle, &evt_detail->args.ld.target_id),
4237 ddi_get8(acc_handle, &evt_detail->args.ld.ld_index)));
4238 break;
4239 } /* End of MR_EVT_LD_DELETED */
4240
4241 case MR_EVT_LD_CREATED: {
4242 rval = mrsas_service_evt(instance,
4243 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 0,
4244 MRSAS_EVT_CONFIG_TGT, NULL);
4245 con_log(CL_ANN1, (CE_WARN, "mr_sas: LD CREATED AEN rval = %d "
4246 "tgt id = %d index = %d", rval,
4247 ddi_get16(acc_handle, &evt_detail->args.ld.target_id),
4248 ddi_get8(acc_handle, &evt_detail->args.ld.ld_index)));
4249 break;
4250 } /* End of MR_EVT_LD_CREATED */
4251
4252 #ifdef PDSUPPORT
4253 case MR_EVT_PD_REMOVED_EXT: {
4254 if (instance->tbolt) {
4255 pd_addr = &evt_detail->args.pd_addr;
4256 dtype = pd_addr->scsi_dev_type;
4257 con_log(CL_DLEVEL1, (CE_NOTE,
4258 " MR_EVT_PD_REMOVED_EXT: dtype = %x,"
4259 " arg_type = %d ", dtype, evt_detail->arg_type));
4260 tgt = ddi_get16(acc_handle,
4261 &evt_detail->args.pd.device_id);
4262 mutex_enter(&instance->config_dev_mtx);
4263 instance->mr_tbolt_pd_list[tgt].flag =
4264 (uint8_t)~MRDRV_TGT_VALID;
4265 mutex_exit(&instance->config_dev_mtx);
4266 rval = mrsas_service_evt(instance, ddi_get16(
4267 acc_handle, &evt_detail->args.pd.device_id),
4268 1, MRSAS_EVT_UNCONFIG_TGT, NULL);
4269 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_REMOVED:"
4270 "rval = %d tgt id = %d ", rval,
4271 ddi_get16(acc_handle,
4272 &evt_detail->args.pd.device_id)));
4273 }
4274 break;
4275 } /* End of MR_EVT_PD_REMOVED_EXT */
4276
4277 case MR_EVT_PD_INSERTED_EXT: {
4278 if (instance->tbolt) {
4279 rval = mrsas_service_evt(instance,
4280 ddi_get16(acc_handle,
4281 &evt_detail->args.pd.device_id),
4282 1, MRSAS_EVT_CONFIG_TGT, NULL);
4283 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_INSERTEDi_EXT:"
4284 "rval = %d tgt id = %d ", rval,
4285 ddi_get16(acc_handle,
4286 &evt_detail->args.pd.device_id)));
4287 }
4288 break;
4289 } /* End of MR_EVT_PD_INSERTED_EXT */
4290
4291 case MR_EVT_PD_STATE_CHANGE: {
4292 if (instance->tbolt) {
4293 tgt = ddi_get16(acc_handle,
4294 &evt_detail->args.pd.device_id);
4295 if ((evt_detail->args.pd_state.prevState ==
4296 PD_SYSTEM) &&
4297 (evt_detail->args.pd_state.newState != PD_SYSTEM)) {
4298 mutex_enter(&instance->config_dev_mtx);
4299 instance->mr_tbolt_pd_list[tgt].flag =
4300 (uint8_t)~MRDRV_TGT_VALID;
4301 mutex_exit(&instance->config_dev_mtx);
4302 rval = mrsas_service_evt(instance,
4303 ddi_get16(acc_handle,
4304 &evt_detail->args.pd.device_id),
4305 1, MRSAS_EVT_UNCONFIG_TGT, NULL);
4306 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_REMOVED:"
4307 "rval = %d tgt id = %d ", rval,
4308 ddi_get16(acc_handle,
4309 &evt_detail->args.pd.device_id)));
4310 break;
4311 }
4312 if ((evt_detail->args.pd_state.prevState
4313 == UNCONFIGURED_GOOD) &&
4314 (evt_detail->args.pd_state.newState == PD_SYSTEM)) {
4315 rval = mrsas_service_evt(instance,
4316 ddi_get16(acc_handle,
4317 &evt_detail->args.pd.device_id),
4318 1, MRSAS_EVT_CONFIG_TGT, NULL);
4319 con_log(CL_ANN1, (CE_WARN,
4320 "mr_sas: PD_INSERTED: rval = %d "
4321 " tgt id = %d ", rval,
4322 ddi_get16(acc_handle,
4323 &evt_detail->args.pd.device_id)));
4324 break;
4325 }
4326 }
4327 break;
4328 }
4329 #endif
4330
4331 } /* End of Main Switch */
4332
4333 /* get copy of seq_num and class/locale for re-registration */
4334 seq_num = ddi_get32(acc_handle, &evt_detail->seq_num);
4335 seq_num++;
4336 (void) memset(instance->mfi_evt_detail_obj.buffer, 0,
4337 sizeof (struct mrsas_evt_detail));
4338
4339 ddi_put8(acc_handle, &cmd->frame->dcmd.cmd_status, 0x0);
4340 ddi_put32(acc_handle, &cmd->frame->dcmd.mbox.w[0], seq_num);
4341
4342 instance->aen_seq_num = seq_num;
4343
4344 cmd->frame_count = 1;
4345
4346 cmd->retry_count_for_ocr = 0;
4347 cmd->drv_pkt_time = 0;
4348
4349 /* Issue the aen registration frame */
4350 instance->func_ptr->issue_cmd(cmd, instance);
4351 }
4352
4353 /*
4354 * complete_cmd_in_sync_mode - Completes an internal command
4355 * @instance: Adapter soft state
4356 * @cmd: Command to be completed
4357 *
4358 * The issue_cmd_in_sync_mode() function waits for a command to complete
4359 * after it issues a command. This function wakes up that waiting routine by
4360 * calling wake_up() on the wait queue.
4361 */
4362 static void
4363 complete_cmd_in_sync_mode(struct mrsas_instance *instance,
4364 struct mrsas_cmd *cmd)
4365 {
4366 cmd->cmd_status = ddi_get8(cmd->frame_dma_obj.acc_handle,
4367 &cmd->frame->io.cmd_status);
4368
4369 cmd->sync_cmd = MRSAS_FALSE;
4370
4371 con_log(CL_ANN1, (CE_NOTE, "complete_cmd_in_sync_mode called %p \n",
4372 (void *)cmd));
4373
4374 mutex_enter(&instance->int_cmd_mtx);
4375 if (cmd->cmd_status == ENODATA) {
4376 cmd->cmd_status = 0;
4377 }
4378 cv_broadcast(&instance->int_cmd_cv);
4379 mutex_exit(&instance->int_cmd_mtx);
4380
4381 }
4382
4383 /*
4384 * Call this function inside mrsas_softintr.
4385 * mrsas_initiate_ocr_if_fw_is_faulty - Initiates OCR if FW status is faulty
4386 * @instance: Adapter soft state
4387 */
4388
4389 static uint32_t
4390 mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *instance)
4391 {
4392 uint32_t cur_abs_reg_val;
4393 uint32_t fw_state;
4394
4395 cur_abs_reg_val = instance->func_ptr->read_fw_status_reg(instance);
4396 fw_state = cur_abs_reg_val & MFI_STATE_MASK;
4397 if (fw_state == MFI_STATE_FAULT) {
4398 if (instance->disable_online_ctrl_reset == 1) {
4399 cmn_err(CE_WARN,
4400 "mrsas_initiate_ocr_if_fw_is_faulty: "
4401 "FW in Fault state, detected in ISR: "
4402 "FW doesn't support ocr ");
4403
4404 return (ADAPTER_RESET_NOT_REQUIRED);
4405 } else {
4406 con_log(CL_ANN, (CE_NOTE,
4407 "mrsas_initiate_ocr_if_fw_is_faulty: FW in Fault "
4408 "state, detected in ISR: FW supports ocr "));
4409
4410 return (ADAPTER_RESET_REQUIRED);
4411 }
4412 }
4413
4414 return (ADAPTER_RESET_NOT_REQUIRED);
4415 }
4416
4417 /*
4418 * mrsas_softintr - The Software ISR
4419 * @param arg : HBA soft state
4420 *
4421 * called from high-level interrupt if hi-level interrupt are not there,
4422 * otherwise triggered as a soft interrupt
4423 */
4424 static uint_t
4425 mrsas_softintr(struct mrsas_instance *instance)
4426 {
4427 struct scsi_pkt *pkt;
4428 struct scsa_cmd *acmd;
4429 struct mrsas_cmd *cmd;
4430 struct mlist_head *pos, *next;
4431 mlist_t process_list;
4432 struct mrsas_header *hdr;
4433 struct scsi_arq_status *arqstat;
4434
4435 con_log(CL_ANN1, (CE_NOTE, "mrsas_softintr() called."));
4436
4437 ASSERT(instance);
4438
4439 mutex_enter(&instance->completed_pool_mtx);
4440
4441 if (mlist_empty(&instance->completed_pool_list)) {
4442 mutex_exit(&instance->completed_pool_mtx);
4443 return (DDI_INTR_CLAIMED);
4444 }
4445
4446 instance->softint_running = 1;
4447
4448 INIT_LIST_HEAD(&process_list);
4449 mlist_splice(&instance->completed_pool_list, &process_list);
4450 INIT_LIST_HEAD(&instance->completed_pool_list);
4451
4452 mutex_exit(&instance->completed_pool_mtx);
4453
4454 /* perform all callbacks first, before releasing the SCBs */
4455 mlist_for_each_safe(pos, next, &process_list) {
4456 cmd = mlist_entry(pos, struct mrsas_cmd, list);
4457
4458 /* syncronize the Cmd frame for the controller */
4459 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle,
4460 0, 0, DDI_DMA_SYNC_FORCPU);
4461
4462 if (mrsas_check_dma_handle(cmd->frame_dma_obj.dma_handle) !=
4463 DDI_SUCCESS) {
4464 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE);
4465 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
4466 con_log(CL_ANN1, (CE_WARN,
4467 "mrsas_softintr: "
4468 "FMA check reports DMA handle failure"));
4469 return (DDI_INTR_CLAIMED);
4470 }
4471
4472 hdr = &cmd->frame->hdr;
4473
4474 /* remove the internal command from the process list */
4475 mlist_del_init(&cmd->list);
4476
4477 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, &hdr->cmd)) {
4478 case MFI_CMD_OP_PD_SCSI:
4479 case MFI_CMD_OP_LD_SCSI:
4480 case MFI_CMD_OP_LD_READ:
4481 case MFI_CMD_OP_LD_WRITE:
4482 /*
4483 * MFI_CMD_OP_PD_SCSI and MFI_CMD_OP_LD_SCSI
4484 * could have been issued either through an
4485 * IO path or an IOCTL path. If it was via IOCTL,
4486 * we will send it to internal completion.
4487 */
4488 if (cmd->sync_cmd == MRSAS_TRUE) {
4489 complete_cmd_in_sync_mode(instance, cmd);
4490 break;
4491 }
4492
4493 /* regular commands */
4494 acmd = cmd->cmd;
4495 pkt = CMD2PKT(acmd);
4496
4497 if (acmd->cmd_flags & CFLAG_DMAVALID) {
4498 if (acmd->cmd_flags & CFLAG_CONSISTENT) {
4499 (void) ddi_dma_sync(acmd->cmd_dmahandle,
4500 acmd->cmd_dma_offset,
4501 acmd->cmd_dma_len,
4502 DDI_DMA_SYNC_FORCPU);
4503 }
4504 }
4505
4506 pkt->pkt_reason = CMD_CMPLT;
4507 pkt->pkt_statistics = 0;
4508 pkt->pkt_state = STATE_GOT_BUS
4509 | STATE_GOT_TARGET | STATE_SENT_CMD
4510 | STATE_XFERRED_DATA | STATE_GOT_STATUS;
4511
4512 con_log(CL_ANN, (CE_CONT,
4513 "CDB[0] = %x completed for %s: size %lx context %x",
4514 pkt->pkt_cdbp[0], ((acmd->islogical) ? "LD" : "PD"),
4515 acmd->cmd_dmacount, hdr->context));
4516 DTRACE_PROBE3(softintr_cdb, uint8_t, pkt->pkt_cdbp[0],
4517 uint_t, acmd->cmd_cdblen, ulong_t,
4518 acmd->cmd_dmacount);
4519
4520 if (pkt->pkt_cdbp[0] == SCMD_INQUIRY) {
4521 struct scsi_inquiry *inq;
4522
4523 if (acmd->cmd_dmacount != 0) {
4524 bp_mapin(acmd->cmd_buf);
4525 inq = (struct scsi_inquiry *)
4526 acmd->cmd_buf->b_un.b_addr;
4527
4528 /* don't expose physical drives to OS */
4529 if (acmd->islogical &&
4530 (hdr->cmd_status == MFI_STAT_OK)) {
4531 display_scsi_inquiry(
4532 (caddr_t)inq);
4533 } else if ((hdr->cmd_status ==
4534 MFI_STAT_OK) && inq->inq_dtype ==
4535 DTYPE_DIRECT) {
4536
4537 display_scsi_inquiry(
4538 (caddr_t)inq);
4539
4540 /* for physical disk */
4541 hdr->cmd_status =
4542 MFI_STAT_DEVICE_NOT_FOUND;
4543 }
4544 }
4545 }
4546
4547 DTRACE_PROBE2(softintr_done, uint8_t, hdr->cmd,
4548 uint8_t, hdr->cmd_status);
4549
4550 switch (hdr->cmd_status) {
4551 case MFI_STAT_OK:
4552 pkt->pkt_scbp[0] = STATUS_GOOD;
4553 break;
4554 case MFI_STAT_LD_CC_IN_PROGRESS:
4555 case MFI_STAT_LD_RECON_IN_PROGRESS:
4556 pkt->pkt_scbp[0] = STATUS_GOOD;
4557 break;
4558 case MFI_STAT_LD_INIT_IN_PROGRESS:
4559 con_log(CL_ANN,
4560 (CE_WARN, "Initialization in Progress"));
4561 pkt->pkt_reason = CMD_TRAN_ERR;
4562
4563 break;
4564 case MFI_STAT_SCSI_DONE_WITH_ERROR:
4565 con_log(CL_ANN, (CE_CONT, "scsi_done error"));
4566
4567 pkt->pkt_reason = CMD_CMPLT;
4568 ((struct scsi_status *)
4569 pkt->pkt_scbp)->sts_chk = 1;
4570
4571 if (pkt->pkt_cdbp[0] == SCMD_TEST_UNIT_READY) {
4572 con_log(CL_ANN,
4573 (CE_WARN, "TEST_UNIT_READY fail"));
4574 } else {
4575 pkt->pkt_state |= STATE_ARQ_DONE;
4576 arqstat = (void *)(pkt->pkt_scbp);
4577 arqstat->sts_rqpkt_reason = CMD_CMPLT;
4578 arqstat->sts_rqpkt_resid = 0;
4579 arqstat->sts_rqpkt_state |=
4580 STATE_GOT_BUS | STATE_GOT_TARGET
4581 | STATE_SENT_CMD
4582 | STATE_XFERRED_DATA;
4583 *(uint8_t *)&arqstat->sts_rqpkt_status =
4584 STATUS_GOOD;
4585 ddi_rep_get8(
4586 cmd->frame_dma_obj.acc_handle,
4587 (uint8_t *)
4588 &(arqstat->sts_sensedata),
4589 cmd->sense,
4590 sizeof (struct scsi_extended_sense),
4591 DDI_DEV_AUTOINCR);
4592 }
4593 break;
4594 case MFI_STAT_LD_OFFLINE:
4595 case MFI_STAT_DEVICE_NOT_FOUND:
4596 con_log(CL_ANN, (CE_CONT,
4597 "mrsas_softintr:device not found error"));
4598 pkt->pkt_reason = CMD_DEV_GONE;
4599 pkt->pkt_statistics = STAT_DISCON;
4600 break;
4601 case MFI_STAT_LD_LBA_OUT_OF_RANGE:
4602 pkt->pkt_state |= STATE_ARQ_DONE;
4603 pkt->pkt_reason = CMD_CMPLT;
4604 ((struct scsi_status *)
4605 pkt->pkt_scbp)->sts_chk = 1;
4606
4607 arqstat = (void *)(pkt->pkt_scbp);
4608 arqstat->sts_rqpkt_reason = CMD_CMPLT;
4609 arqstat->sts_rqpkt_resid = 0;
4610 arqstat->sts_rqpkt_state |= STATE_GOT_BUS
4611 | STATE_GOT_TARGET | STATE_SENT_CMD
4612 | STATE_XFERRED_DATA;
4613 *(uint8_t *)&arqstat->sts_rqpkt_status =
4614 STATUS_GOOD;
4615
4616 arqstat->sts_sensedata.es_valid = 1;
4617 arqstat->sts_sensedata.es_key =
4618 KEY_ILLEGAL_REQUEST;
4619 arqstat->sts_sensedata.es_class =
4620 CLASS_EXTENDED_SENSE;
4621
4622 /*
4623 * LOGICAL BLOCK ADDRESS OUT OF RANGE:
4624 * ASC: 0x21h; ASCQ: 0x00h;
4625 */
4626 arqstat->sts_sensedata.es_add_code = 0x21;
4627 arqstat->sts_sensedata.es_qual_code = 0x00;
4628
4629 break;
4630
4631 default:
4632 con_log(CL_ANN, (CE_CONT, "Unknown status!"));
4633 pkt->pkt_reason = CMD_TRAN_ERR;
4634
4635 break;
4636 }
4637
4638 atomic_add_16(&instance->fw_outstanding, (-1));
4639
4640 (void) mrsas_common_check(instance, cmd);
4641
4642 if (acmd->cmd_dmahandle) {
4643 if (mrsas_check_dma_handle(
4644 acmd->cmd_dmahandle) != DDI_SUCCESS) {
4645 ddi_fm_service_impact(instance->dip,
4646 DDI_SERVICE_UNAFFECTED);
4647 pkt->pkt_reason = CMD_TRAN_ERR;
4648 pkt->pkt_statistics = 0;
4649 }
4650 }
4651
4652 /* Call the callback routine */
4653 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) &&
4654 pkt->pkt_comp) {
4655
4656 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_softintr: "
4657 "posting to scsa cmd %p index %x pkt %p "
4658 "time %llx", (void *)cmd, cmd->index,
4659 (void *)pkt, gethrtime()));
4660 (*pkt->pkt_comp)(pkt);
4661
4662 }
4663
4664 return_mfi_pkt(instance, cmd);
4665 break;
4666
4667 case MFI_CMD_OP_SMP:
4668 case MFI_CMD_OP_STP:
4669 complete_cmd_in_sync_mode(instance, cmd);
4670 break;
4671
4672 case MFI_CMD_OP_DCMD:
4673 /* see if got an event notification */
4674 if (ddi_get32(cmd->frame_dma_obj.acc_handle,
4675 &cmd->frame->dcmd.opcode) ==
4676 MR_DCMD_CTRL_EVENT_WAIT) {
4677 if ((instance->aen_cmd == cmd) &&
4678 (instance->aen_cmd->abort_aen)) {
4679 con_log(CL_ANN, (CE_WARN,
4680 "mrsas_softintr: "
4681 "aborted_aen returned"));
4682 } else {
4683 atomic_add_16(&instance->fw_outstanding,
4684 (-1));
4685 service_mfi_aen(instance, cmd);
4686 }
4687 } else {
4688 complete_cmd_in_sync_mode(instance, cmd);
4689 }
4690
4691 break;
4692
4693 case MFI_CMD_OP_ABORT:
4694 con_log(CL_ANN, (CE_NOTE, "MFI_CMD_OP_ABORT complete"));
4695 /*
4696 * MFI_CMD_OP_ABORT successfully completed
4697 * in the synchronous mode
4698 */
4699 complete_cmd_in_sync_mode(instance, cmd);
4700 break;
4701
4702 default:
4703 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE);
4704 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
4705
4706 if (cmd->pkt != NULL) {
4707 pkt = cmd->pkt;
4708 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) &&
4709 pkt->pkt_comp) {
4710
4711 con_log(CL_ANN1, (CE_CONT, "posting to "
4712 "scsa cmd %p index %x pkt %p"
4713 "time %llx, default ", (void *)cmd,
4714 cmd->index, (void *)pkt,
4715 gethrtime()));
4716
4717 (*pkt->pkt_comp)(pkt);
4718
4719 }
4720 }
4721 con_log(CL_ANN, (CE_WARN, "Cmd type unknown !"));
4722 break;
4723 }
4724 }
4725
4726 instance->softint_running = 0;
4727
4728 return (DDI_INTR_CLAIMED);
4729 }
4730
4731 /*
4732 * mrsas_alloc_dma_obj
4733 *
4734 * Allocate the memory and other resources for an dma object.
4735 */
4736 int
4737 mrsas_alloc_dma_obj(struct mrsas_instance *instance, dma_obj_t *obj,
4738 uchar_t endian_flags)
4739 {
4740 int i;
4741 size_t alen = 0;
4742 uint_t cookie_cnt;
4743 struct ddi_device_acc_attr tmp_endian_attr;
4744
4745 tmp_endian_attr = endian_attr;
4746 tmp_endian_attr.devacc_attr_endian_flags = endian_flags;
4747 tmp_endian_attr.devacc_attr_access = DDI_DEFAULT_ACC;
4748
4749 i = ddi_dma_alloc_handle(instance->dip, &obj->dma_attr,
4750 DDI_DMA_SLEEP, NULL, &obj->dma_handle);
4751 if (i != DDI_SUCCESS) {
4752
4753 switch (i) {
4754 case DDI_DMA_BADATTR :
4755 con_log(CL_ANN, (CE_WARN,
4756 "Failed ddi_dma_alloc_handle- Bad attribute"));
4757 break;
4758 case DDI_DMA_NORESOURCES :
4759 con_log(CL_ANN, (CE_WARN,
4760 "Failed ddi_dma_alloc_handle- No Resources"));
4761 break;
4762 default :
4763 con_log(CL_ANN, (CE_WARN,
4764 "Failed ddi_dma_alloc_handle: "
4765 "unknown status %d", i));
4766 break;
4767 }
4768
4769 return (-1);
4770 }
4771
4772 if ((ddi_dma_mem_alloc(obj->dma_handle, obj->size, &tmp_endian_attr,
4773 DDI_DMA_RDWR | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL,
4774 &obj->buffer, &alen, &obj->acc_handle) != DDI_SUCCESS) ||
4775 alen < obj->size) {
4776
4777 ddi_dma_free_handle(&obj->dma_handle);
4778
4779 con_log(CL_ANN, (CE_WARN, "Failed : ddi_dma_mem_alloc"));
4780
4781 return (-1);
4782 }
4783
4784 if (ddi_dma_addr_bind_handle(obj->dma_handle, NULL, obj->buffer,
4785 obj->size, DDI_DMA_RDWR | DDI_DMA_STREAMING, DDI_DMA_SLEEP,
4786 NULL, &obj->dma_cookie[0], &cookie_cnt) != DDI_SUCCESS) {
4787
4788 ddi_dma_mem_free(&obj->acc_handle);
4789 ddi_dma_free_handle(&obj->dma_handle);
4790
4791 con_log(CL_ANN, (CE_WARN, "Failed : ddi_dma_addr_bind_handle"));
4792
4793 return (-1);
4794 }
4795
4796 if (mrsas_check_dma_handle(obj->dma_handle) != DDI_SUCCESS) {
4797 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
4798 return (-1);
4799 }
4800
4801 if (mrsas_check_acc_handle(obj->acc_handle) != DDI_SUCCESS) {
4802 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
4803 return (-1);
4804 }
4805
4806 return (cookie_cnt);
4807 }
4808
4809 /*
4810 * mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t)
4811 *
4812 * De-allocate the memory and other resources for an dma object, which must
4813 * have been alloated by a previous call to mrsas_alloc_dma_obj()
4814 */
4815 int
4816 mrsas_free_dma_obj(struct mrsas_instance *instance, dma_obj_t obj)
4817 {
4818
4819 if ((obj.dma_handle == NULL) || (obj.acc_handle == NULL)) {
4820 return (DDI_SUCCESS);
4821 }
4822
4823 /*
4824 * NOTE: These check-handle functions fail if *_handle == NULL, but
4825 * this function succeeds because of the previous check.
4826 */
4827 if (mrsas_check_dma_handle(obj.dma_handle) != DDI_SUCCESS) {
4828 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
4829 return (DDI_FAILURE);
4830 }
4831
4832 if (mrsas_check_acc_handle(obj.acc_handle) != DDI_SUCCESS) {
4833 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
4834 return (DDI_FAILURE);
4835 }
4836
4837 (void) ddi_dma_unbind_handle(obj.dma_handle);
4838 ddi_dma_mem_free(&obj.acc_handle);
4839 ddi_dma_free_handle(&obj.dma_handle);
4840 obj.acc_handle = NULL;
4841 return (DDI_SUCCESS);
4842 }
4843
4844 /*
4845 * mrsas_dma_alloc(instance_t *, struct scsi_pkt *, struct buf *,
4846 * int, int (*)())
4847 *
4848 * Allocate dma resources for a new scsi command
4849 */
4850 int
4851 mrsas_dma_alloc(struct mrsas_instance *instance, struct scsi_pkt *pkt,
4852 struct buf *bp, int flags, int (*callback)())
4853 {
4854 int dma_flags;
4855 int (*cb)(caddr_t);
4856 int i;
4857
4858 ddi_dma_attr_t tmp_dma_attr = mrsas_generic_dma_attr;
4859 struct scsa_cmd *acmd = PKT2CMD(pkt);
4860
4861 acmd->cmd_buf = bp;
4862
4863 if (bp->b_flags & B_READ) {
4864 acmd->cmd_flags &= ~CFLAG_DMASEND;
4865 dma_flags = DDI_DMA_READ;
4866 } else {
4867 acmd->cmd_flags |= CFLAG_DMASEND;
4868 dma_flags = DDI_DMA_WRITE;
4869 }
4870
4871 if (flags & PKT_CONSISTENT) {
4872 acmd->cmd_flags |= CFLAG_CONSISTENT;
4873 dma_flags |= DDI_DMA_CONSISTENT;
4874 }
4875
4876 if (flags & PKT_DMA_PARTIAL) {
4877 dma_flags |= DDI_DMA_PARTIAL;
4878 }
4879
4880 dma_flags |= DDI_DMA_REDZONE;
4881
4882 cb = (callback == NULL_FUNC) ? DDI_DMA_DONTWAIT : DDI_DMA_SLEEP;
4883
4884 tmp_dma_attr.dma_attr_sgllen = instance->max_num_sge;
4885 tmp_dma_attr.dma_attr_addr_hi = 0xffffffffffffffffull;
4886 if (instance->tbolt) {
4887 /* OCR-RESET FIX */
4888 tmp_dma_attr.dma_attr_count_max =
4889 (U64)mrsas_tbolt_max_cap_maxxfer; /* limit to 256K */
4890 tmp_dma_attr.dma_attr_maxxfer =
4891 (U64)mrsas_tbolt_max_cap_maxxfer; /* limit to 256K */
4892 }
4893
4894 if ((i = ddi_dma_alloc_handle(instance->dip, &tmp_dma_attr,
4895 cb, 0, &acmd->cmd_dmahandle)) != DDI_SUCCESS) {
4896 switch (i) {
4897 case DDI_DMA_BADATTR:
4898 bioerror(bp, EFAULT);
4899 return (DDI_FAILURE);
4900
4901 case DDI_DMA_NORESOURCES:
4902 bioerror(bp, 0);
4903 return (DDI_FAILURE);
4904
4905 default:
4906 con_log(CL_ANN, (CE_PANIC, "ddi_dma_alloc_handle: "
4907 "impossible result (0x%x)", i));
4908 bioerror(bp, EFAULT);
4909 return (DDI_FAILURE);
4910 }
4911 }
4912
4913 i = ddi_dma_buf_bind_handle(acmd->cmd_dmahandle, bp, dma_flags,
4914 cb, 0, &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies);
4915
4916 switch (i) {
4917 case DDI_DMA_PARTIAL_MAP:
4918 if ((dma_flags & DDI_DMA_PARTIAL) == 0) {
4919 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle: "
4920 "DDI_DMA_PARTIAL_MAP impossible"));
4921 goto no_dma_cookies;
4922 }
4923
4924 if (ddi_dma_numwin(acmd->cmd_dmahandle, &acmd->cmd_nwin) ==
4925 DDI_FAILURE) {
4926 con_log(CL_ANN, (CE_PANIC, "ddi_dma_numwin failed"));
4927 goto no_dma_cookies;
4928 }
4929
4930 if (ddi_dma_getwin(acmd->cmd_dmahandle, acmd->cmd_curwin,
4931 &acmd->cmd_dma_offset, &acmd->cmd_dma_len,
4932 &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies) ==
4933 DDI_FAILURE) {
4934
4935 con_log(CL_ANN, (CE_PANIC, "ddi_dma_getwin failed"));
4936 goto no_dma_cookies;
4937 }
4938
4939 goto get_dma_cookies;
4940 case DDI_DMA_MAPPED:
4941 acmd->cmd_nwin = 1;
4942 acmd->cmd_dma_len = 0;
4943 acmd->cmd_dma_offset = 0;
4944
4945 get_dma_cookies:
4946 i = 0;
4947 acmd->cmd_dmacount = 0;
4948 for (;;) {
4949 acmd->cmd_dmacount +=
4950 acmd->cmd_dmacookies[i++].dmac_size;
4951
4952 if (i == instance->max_num_sge ||
4953 i == acmd->cmd_ncookies)
4954 break;
4955
4956 ddi_dma_nextcookie(acmd->cmd_dmahandle,
4957 &acmd->cmd_dmacookies[i]);
4958 }
4959
4960 acmd->cmd_cookie = i;
4961 acmd->cmd_cookiecnt = i;
4962
4963 acmd->cmd_flags |= CFLAG_DMAVALID;
4964
4965 if (bp->b_bcount >= acmd->cmd_dmacount) {
4966 pkt->pkt_resid = bp->b_bcount - acmd->cmd_dmacount;
4967 } else {
4968 pkt->pkt_resid = 0;
4969 }
4970
4971 return (DDI_SUCCESS);
4972 case DDI_DMA_NORESOURCES:
4973 bioerror(bp, 0);
4974 break;
4975 case DDI_DMA_NOMAPPING:
4976 bioerror(bp, EFAULT);
4977 break;
4978 case DDI_DMA_TOOBIG:
4979 bioerror(bp, EINVAL);
4980 break;
4981 case DDI_DMA_INUSE:
4982 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle:"
4983 " DDI_DMA_INUSE impossible"));
4984 break;
4985 default:
4986 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle: "
4987 "impossible result (0x%x)", i));
4988 break;
4989 }
4990
4991 no_dma_cookies:
4992 ddi_dma_free_handle(&acmd->cmd_dmahandle);
4993 acmd->cmd_dmahandle = NULL;
4994 acmd->cmd_flags &= ~CFLAG_DMAVALID;
4995 return (DDI_FAILURE);
4996 }
4997
4998 /*
4999 * mrsas_dma_move(struct mrsas_instance *, struct scsi_pkt *, struct buf *)
5000 *
5001 * move dma resources to next dma window
5002 *
5003 */
5004 int
5005 mrsas_dma_move(struct mrsas_instance *instance, struct scsi_pkt *pkt,
5006 struct buf *bp)
5007 {
5008 int i = 0;
5009
5010 struct scsa_cmd *acmd = PKT2CMD(pkt);
5011
5012 /*
5013 * If there are no more cookies remaining in this window,
5014 * must move to the next window first.
5015 */
5016 if (acmd->cmd_cookie == acmd->cmd_ncookies) {
5017 if (acmd->cmd_curwin == acmd->cmd_nwin && acmd->cmd_nwin == 1) {
5018 return (DDI_SUCCESS);
5019 }
5020
5021 /* at last window, cannot move */
5022 if (++acmd->cmd_curwin >= acmd->cmd_nwin) {
5023 return (DDI_FAILURE);
5024 }
5025
5026 if (ddi_dma_getwin(acmd->cmd_dmahandle, acmd->cmd_curwin,
5027 &acmd->cmd_dma_offset, &acmd->cmd_dma_len,
5028 &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies) ==
5029 DDI_FAILURE) {
5030 return (DDI_FAILURE);
5031 }
5032
5033 acmd->cmd_cookie = 0;
5034 } else {
5035 /* still more cookies in this window - get the next one */
5036 ddi_dma_nextcookie(acmd->cmd_dmahandle,
5037 &acmd->cmd_dmacookies[0]);
5038 }
5039
5040 /* get remaining cookies in this window, up to our maximum */
5041 for (;;) {
5042 acmd->cmd_dmacount += acmd->cmd_dmacookies[i++].dmac_size;
5043 acmd->cmd_cookie++;
5044
5045 if (i == instance->max_num_sge ||
5046 acmd->cmd_cookie == acmd->cmd_ncookies) {
5047 break;
5048 }
5049
5050 ddi_dma_nextcookie(acmd->cmd_dmahandle,
5051 &acmd->cmd_dmacookies[i]);
5052 }
5053
5054 acmd->cmd_cookiecnt = i;
5055
5056 if (bp->b_bcount >= acmd->cmd_dmacount) {
5057 pkt->pkt_resid = bp->b_bcount - acmd->cmd_dmacount;
5058 } else {
5059 pkt->pkt_resid = 0;
5060 }
5061
5062 return (DDI_SUCCESS);
5063 }
5064
5065 /*
5066 * build_cmd
5067 */
5068 static struct mrsas_cmd *
5069 build_cmd(struct mrsas_instance *instance, struct scsi_address *ap,
5070 struct scsi_pkt *pkt, uchar_t *cmd_done)
5071 {
5072 uint16_t flags = 0;
5073 uint32_t i;
5074 uint32_t context;
5075 uint32_t sge_bytes;
5076 uint32_t tmp_data_xfer_len;
5077 ddi_acc_handle_t acc_handle;
5078 struct mrsas_cmd *cmd;
5079 struct mrsas_sge64 *mfi_sgl;
5080 struct mrsas_sge_ieee *mfi_sgl_ieee;
5081 struct scsa_cmd *acmd = PKT2CMD(pkt);
5082 struct mrsas_pthru_frame *pthru;
5083 struct mrsas_io_frame *ldio;
5084
5085 /* find out if this is logical or physical drive command. */
5086 acmd->islogical = MRDRV_IS_LOGICAL(ap);
5087 acmd->device_id = MAP_DEVICE_ID(instance, ap);
5088 *cmd_done = 0;
5089
5090 /* get the command packet */
5091 if (!(cmd = get_mfi_pkt(instance))) {
5092 DTRACE_PROBE2(build_cmd_mfi_err, uint16_t,
5093 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
5094 return (NULL);
5095 }
5096
5097 acc_handle = cmd->frame_dma_obj.acc_handle;
5098
5099 /* Clear the frame buffer and assign back the context id */
5100 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
5101 ddi_put32(acc_handle, &cmd->frame->hdr.context, cmd->index);
5102
5103 cmd->pkt = pkt;
5104 cmd->cmd = acmd;
5105 DTRACE_PROBE3(build_cmds, uint8_t, pkt->pkt_cdbp[0],
5106 ulong_t, acmd->cmd_dmacount, ulong_t, acmd->cmd_dma_len);
5107
5108 /* lets get the command directions */
5109 if (acmd->cmd_flags & CFLAG_DMASEND) {
5110 flags = MFI_FRAME_DIR_WRITE;
5111
5112 if (acmd->cmd_flags & CFLAG_CONSISTENT) {
5113 (void) ddi_dma_sync(acmd->cmd_dmahandle,
5114 acmd->cmd_dma_offset, acmd->cmd_dma_len,
5115 DDI_DMA_SYNC_FORDEV);
5116 }
5117 } else if (acmd->cmd_flags & ~CFLAG_DMASEND) {
5118 flags = MFI_FRAME_DIR_READ;
5119
5120 if (acmd->cmd_flags & CFLAG_CONSISTENT) {
5121 (void) ddi_dma_sync(acmd->cmd_dmahandle,
5122 acmd->cmd_dma_offset, acmd->cmd_dma_len,
5123 DDI_DMA_SYNC_FORCPU);
5124 }
5125 } else {
5126 flags = MFI_FRAME_DIR_NONE;
5127 }
5128
5129 if (instance->flag_ieee) {
5130 flags |= MFI_FRAME_IEEE;
5131 }
5132 flags |= MFI_FRAME_SGL64;
5133
5134 switch (pkt->pkt_cdbp[0]) {
5135
5136 /*
5137 * case SCMD_SYNCHRONIZE_CACHE:
5138 * flush_cache(instance);
5139 * return_mfi_pkt(instance, cmd);
5140 * *cmd_done = 1;
5141 *
5142 * return (NULL);
5143 */
5144
5145 case SCMD_READ:
5146 case SCMD_WRITE:
5147 case SCMD_READ_G1:
5148 case SCMD_WRITE_G1:
5149 case SCMD_READ_G4:
5150 case SCMD_WRITE_G4:
5151 case SCMD_READ_G5:
5152 case SCMD_WRITE_G5:
5153 if (acmd->islogical) {
5154 ldio = (struct mrsas_io_frame *)cmd->frame;
5155
5156 /*
5157 * preare the Logical IO frame:
5158 * 2nd bit is zero for all read cmds
5159 */
5160 ddi_put8(acc_handle, &ldio->cmd,
5161 (pkt->pkt_cdbp[0] & 0x02) ? MFI_CMD_OP_LD_WRITE
5162 : MFI_CMD_OP_LD_READ);
5163 ddi_put8(acc_handle, &ldio->cmd_status, 0x0);
5164 ddi_put8(acc_handle, &ldio->scsi_status, 0x0);
5165 ddi_put8(acc_handle, &ldio->target_id, acmd->device_id);
5166 ddi_put16(acc_handle, &ldio->timeout, 0);
5167 ddi_put8(acc_handle, &ldio->reserved_0, 0);
5168 ddi_put16(acc_handle, &ldio->pad_0, 0);
5169 ddi_put16(acc_handle, &ldio->flags, flags);
5170
5171 /* Initialize sense Information */
5172 bzero(cmd->sense, SENSE_LENGTH);
5173 ddi_put8(acc_handle, &ldio->sense_len, SENSE_LENGTH);
5174 ddi_put32(acc_handle, &ldio->sense_buf_phys_addr_hi, 0);
5175 ddi_put32(acc_handle, &ldio->sense_buf_phys_addr_lo,
5176 cmd->sense_phys_addr);
5177 ddi_put32(acc_handle, &ldio->start_lba_hi, 0);
5178 ddi_put8(acc_handle, &ldio->access_byte,
5179 (acmd->cmd_cdblen != 6) ? pkt->pkt_cdbp[1] : 0);
5180 ddi_put8(acc_handle, &ldio->sge_count,
5181 acmd->cmd_cookiecnt);
5182 if (instance->flag_ieee) {
5183 mfi_sgl_ieee =
5184 (struct mrsas_sge_ieee *)&ldio->sgl;
5185 } else {
5186 mfi_sgl = (struct mrsas_sge64 *)&ldio->sgl;
5187 }
5188
5189 context = ddi_get32(acc_handle, &ldio->context);
5190
5191 if (acmd->cmd_cdblen == CDB_GROUP0) {
5192 /* 6-byte cdb */
5193 ddi_put32(acc_handle, &ldio->lba_count, (
5194 (uint16_t)(pkt->pkt_cdbp[4])));
5195
5196 ddi_put32(acc_handle, &ldio->start_lba_lo, (
5197 ((uint32_t)(pkt->pkt_cdbp[3])) |
5198 ((uint32_t)(pkt->pkt_cdbp[2]) << 8) |
5199 ((uint32_t)((pkt->pkt_cdbp[1]) & 0x1F)
5200 << 16)));
5201 } else if (acmd->cmd_cdblen == CDB_GROUP1) {
5202 /* 10-byte cdb */
5203 ddi_put32(acc_handle, &ldio->lba_count, (
5204 ((uint16_t)(pkt->pkt_cdbp[8])) |
5205 ((uint16_t)(pkt->pkt_cdbp[7]) << 8)));
5206
5207 ddi_put32(acc_handle, &ldio->start_lba_lo, (
5208 ((uint32_t)(pkt->pkt_cdbp[5])) |
5209 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) |
5210 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) |
5211 ((uint32_t)(pkt->pkt_cdbp[2]) << 24)));
5212 } else if (acmd->cmd_cdblen == CDB_GROUP5) {
5213 /* 12-byte cdb */
5214 ddi_put32(acc_handle, &ldio->lba_count, (
5215 ((uint32_t)(pkt->pkt_cdbp[9])) |
5216 ((uint32_t)(pkt->pkt_cdbp[8]) << 8) |
5217 ((uint32_t)(pkt->pkt_cdbp[7]) << 16) |
5218 ((uint32_t)(pkt->pkt_cdbp[6]) << 24)));
5219
5220 ddi_put32(acc_handle, &ldio->start_lba_lo, (
5221 ((uint32_t)(pkt->pkt_cdbp[5])) |
5222 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) |
5223 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) |
5224 ((uint32_t)(pkt->pkt_cdbp[2]) << 24)));
5225 } else if (acmd->cmd_cdblen == CDB_GROUP4) {
5226 /* 16-byte cdb */
5227 ddi_put32(acc_handle, &ldio->lba_count, (
5228 ((uint32_t)(pkt->pkt_cdbp[13])) |
5229 ((uint32_t)(pkt->pkt_cdbp[12]) << 8) |
5230 ((uint32_t)(pkt->pkt_cdbp[11]) << 16) |
5231 ((uint32_t)(pkt->pkt_cdbp[10]) << 24)));
5232
5233 ddi_put32(acc_handle, &ldio->start_lba_lo, (
5234 ((uint32_t)(pkt->pkt_cdbp[9])) |
5235 ((uint32_t)(pkt->pkt_cdbp[8]) << 8) |
5236 ((uint32_t)(pkt->pkt_cdbp[7]) << 16) |
5237 ((uint32_t)(pkt->pkt_cdbp[6]) << 24)));
5238
5239 ddi_put32(acc_handle, &ldio->start_lba_hi, (
5240 ((uint32_t)(pkt->pkt_cdbp[5])) |
5241 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) |
5242 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) |
5243 ((uint32_t)(pkt->pkt_cdbp[2]) << 24)));
5244 }
5245
5246 break;
5247 }
5248 /* fall through For all non-rd/wr cmds */
5249 default:
5250
5251 switch (pkt->pkt_cdbp[0]) {
5252 case SCMD_MODE_SENSE:
5253 case SCMD_MODE_SENSE_G1: {
5254 union scsi_cdb *cdbp;
5255 uint16_t page_code;
5256
5257 cdbp = (void *)pkt->pkt_cdbp;
5258 page_code = (uint16_t)cdbp->cdb_un.sg.scsi[0];
5259 switch (page_code) {
5260 case 0x3:
5261 case 0x4:
5262 (void) mrsas_mode_sense_build(pkt);
5263 return_mfi_pkt(instance, cmd);
5264 *cmd_done = 1;
5265 return (NULL);
5266 }
5267 break;
5268 }
5269 default:
5270 break;
5271 }
5272
5273 pthru = (struct mrsas_pthru_frame *)cmd->frame;
5274
5275 /* prepare the DCDB frame */
5276 ddi_put8(acc_handle, &pthru->cmd, (acmd->islogical) ?
5277 MFI_CMD_OP_LD_SCSI : MFI_CMD_OP_PD_SCSI);
5278 ddi_put8(acc_handle, &pthru->cmd_status, 0x0);
5279 ddi_put8(acc_handle, &pthru->scsi_status, 0x0);
5280 ddi_put8(acc_handle, &pthru->target_id, acmd->device_id);
5281 ddi_put8(acc_handle, &pthru->lun, 0);
5282 ddi_put8(acc_handle, &pthru->cdb_len, acmd->cmd_cdblen);
5283 ddi_put16(acc_handle, &pthru->timeout, 0);
5284 ddi_put16(acc_handle, &pthru->flags, flags);
5285 tmp_data_xfer_len = 0;
5286 for (i = 0; i < acmd->cmd_cookiecnt; i++) {
5287 tmp_data_xfer_len += acmd->cmd_dmacookies[i].dmac_size;
5288 }
5289 ddi_put32(acc_handle, &pthru->data_xfer_len,
5290 tmp_data_xfer_len);
5291 ddi_put8(acc_handle, &pthru->sge_count, acmd->cmd_cookiecnt);
5292 if (instance->flag_ieee) {
5293 mfi_sgl_ieee = (struct mrsas_sge_ieee *)&pthru->sgl;
5294 } else {
5295 mfi_sgl = (struct mrsas_sge64 *)&pthru->sgl;
5296 }
5297
5298 bzero(cmd->sense, SENSE_LENGTH);
5299 ddi_put8(acc_handle, &pthru->sense_len, SENSE_LENGTH);
5300 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_hi, 0);
5301 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_lo,
5302 cmd->sense_phys_addr);
5303
5304 context = ddi_get32(acc_handle, &pthru->context);
5305 ddi_rep_put8(acc_handle, (uint8_t *)pkt->pkt_cdbp,
5306 (uint8_t *)pthru->cdb, acmd->cmd_cdblen, DDI_DEV_AUTOINCR);
5307
5308 break;
5309 }
5310 #ifdef lint
5311 context = context;
5312 #endif
5313 /* prepare the scatter-gather list for the firmware */
5314 if (instance->flag_ieee) {
5315 for (i = 0; i < acmd->cmd_cookiecnt; i++, mfi_sgl_ieee++) {
5316 ddi_put64(acc_handle, &mfi_sgl_ieee->phys_addr,
5317 acmd->cmd_dmacookies[i].dmac_laddress);
5318 ddi_put32(acc_handle, &mfi_sgl_ieee->length,
5319 acmd->cmd_dmacookies[i].dmac_size);
5320 }
5321 sge_bytes = sizeof (struct mrsas_sge_ieee)*acmd->cmd_cookiecnt;
5322 } else {
5323 for (i = 0; i < acmd->cmd_cookiecnt; i++, mfi_sgl++) {
5324 ddi_put64(acc_handle, &mfi_sgl->phys_addr,
5325 acmd->cmd_dmacookies[i].dmac_laddress);
5326 ddi_put32(acc_handle, &mfi_sgl->length,
5327 acmd->cmd_dmacookies[i].dmac_size);
5328 }
5329 sge_bytes = sizeof (struct mrsas_sge64)*acmd->cmd_cookiecnt;
5330 }
5331
5332 cmd->frame_count = (sge_bytes / MRMFI_FRAME_SIZE) +
5333 ((sge_bytes % MRMFI_FRAME_SIZE) ? 1 : 0) + 1;
5334
5335 if (cmd->frame_count >= 8) {
5336 cmd->frame_count = 8;
5337 }
5338
5339 return (cmd);
5340 }
5341
5342 /*
5343 * wait_for_outstanding - Wait for all outstanding cmds
5344 * @instance: Adapter soft state
5345 *
5346 * This function waits for upto MRDRV_RESET_WAIT_TIME seconds for FW to
5347 * complete all its outstanding commands. Returns error if one or more IOs
5348 * are pending after this time period.
5349 */
5350 static int
5351 wait_for_outstanding(struct mrsas_instance *instance)
5352 {
5353 int i;
5354 uint32_t wait_time = 90;
5355
5356 for (i = 0; i < wait_time; i++) {
5357 if (!instance->fw_outstanding) {
5358 break;
5359 }
5360
5361 drv_usecwait(MILLISEC); /* wait for 1000 usecs */;
5362 }
5363
5364 if (instance->fw_outstanding) {
5365 return (1);
5366 }
5367
5368 return (0);
5369 }
5370
5371 /*
5372 * issue_mfi_pthru
5373 */
5374 static int
5375 issue_mfi_pthru(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
5376 struct mrsas_cmd *cmd, int mode)
5377 {
5378 void *ubuf;
5379 uint32_t kphys_addr = 0;
5380 uint32_t xferlen = 0;
5381 uint32_t new_xfer_length = 0;
5382 uint_t model;
5383 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle;
5384 dma_obj_t pthru_dma_obj;
5385 struct mrsas_pthru_frame *kpthru;
5386 struct mrsas_pthru_frame *pthru;
5387 int i;
5388 pthru = &cmd->frame->pthru;
5389 kpthru = (struct mrsas_pthru_frame *)&ioctl->frame[0];
5390
5391 if (instance->adapterresetinprogress) {
5392 con_log(CL_ANN1, (CE_WARN, "issue_mfi_pthru: Reset flag set, "
5393 "returning mfi_pkt and setting TRAN_BUSY\n"));
5394 return (DDI_FAILURE);
5395 }
5396 model = ddi_model_convert_from(mode & FMODELS);
5397 if (model == DDI_MODEL_ILP32) {
5398 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP32"));
5399
5400 xferlen = kpthru->sgl.sge32[0].length;
5401
5402 ubuf = (void *)(ulong_t)kpthru->sgl.sge32[0].phys_addr;
5403 } else {
5404 #ifdef _ILP32
5405 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP32"));
5406 xferlen = kpthru->sgl.sge32[0].length;
5407 ubuf = (void *)(ulong_t)kpthru->sgl.sge32[0].phys_addr;
5408 #else
5409 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP64"));
5410 xferlen = kpthru->sgl.sge64[0].length;
5411 ubuf = (void *)(ulong_t)kpthru->sgl.sge64[0].phys_addr;
5412 #endif
5413 }
5414
5415 if (xferlen) {
5416 /* means IOCTL requires DMA */
5417 /* allocate the data transfer buffer */
5418 /* pthru_dma_obj.size = xferlen; */
5419 MRSAS_GET_BOUNDARY_ALIGNED_LEN(xferlen, new_xfer_length,
5420 PAGESIZE);
5421 pthru_dma_obj.size = new_xfer_length;
5422 pthru_dma_obj.dma_attr = mrsas_generic_dma_attr;
5423 pthru_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5424 pthru_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5425 pthru_dma_obj.dma_attr.dma_attr_sgllen = 1;
5426 pthru_dma_obj.dma_attr.dma_attr_align = 1;
5427
5428 /* allocate kernel buffer for DMA */
5429 if (mrsas_alloc_dma_obj(instance, &pthru_dma_obj,
5430 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5431 con_log(CL_ANN, (CE_WARN, "issue_mfi_pthru: "
5432 "could not allocate data transfer buffer."));
5433 return (DDI_FAILURE);
5434 }
5435 (void) memset(pthru_dma_obj.buffer, 0, xferlen);
5436
5437 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5438 if (kpthru->flags & MFI_FRAME_DIR_WRITE) {
5439 for (i = 0; i < xferlen; i++) {
5440 if (ddi_copyin((uint8_t *)ubuf+i,
5441 (uint8_t *)pthru_dma_obj.buffer+i,
5442 1, mode)) {
5443 con_log(CL_ANN, (CE_WARN,
5444 "issue_mfi_pthru : "
5445 "copy from user space failed"));
5446 return (DDI_FAILURE);
5447 }
5448 }
5449 }
5450
5451 kphys_addr = pthru_dma_obj.dma_cookie[0].dmac_address;
5452 }
5453
5454 ddi_put8(acc_handle, &pthru->cmd, kpthru->cmd);
5455 ddi_put8(acc_handle, &pthru->sense_len, SENSE_LENGTH);
5456 ddi_put8(acc_handle, &pthru->cmd_status, 0);
5457 ddi_put8(acc_handle, &pthru->scsi_status, 0);
5458 ddi_put8(acc_handle, &pthru->target_id, kpthru->target_id);
5459 ddi_put8(acc_handle, &pthru->lun, kpthru->lun);
5460 ddi_put8(acc_handle, &pthru->cdb_len, kpthru->cdb_len);
5461 ddi_put8(acc_handle, &pthru->sge_count, kpthru->sge_count);
5462 ddi_put16(acc_handle, &pthru->timeout, kpthru->timeout);
5463 ddi_put32(acc_handle, &pthru->data_xfer_len, kpthru->data_xfer_len);
5464
5465 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_hi, 0);
5466 pthru->sense_buf_phys_addr_lo = cmd->sense_phys_addr;
5467 /* ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_lo, 0); */
5468
5469 ddi_rep_put8(acc_handle, (uint8_t *)kpthru->cdb, (uint8_t *)pthru->cdb,
5470 pthru->cdb_len, DDI_DEV_AUTOINCR);
5471
5472 ddi_put16(acc_handle, &pthru->flags, kpthru->flags & ~MFI_FRAME_SGL64);
5473 ddi_put32(acc_handle, &pthru->sgl.sge32[0].length, xferlen);
5474 ddi_put32(acc_handle, &pthru->sgl.sge32[0].phys_addr, kphys_addr);
5475
5476 cmd->sync_cmd = MRSAS_TRUE;
5477 cmd->frame_count = 1;
5478
5479 if (instance->tbolt) {
5480 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
5481 }
5482
5483 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
5484 con_log(CL_ANN, (CE_WARN,
5485 "issue_mfi_pthru: fw_ioctl failed"));
5486 } else {
5487 if (xferlen && kpthru->flags & MFI_FRAME_DIR_READ) {
5488 for (i = 0; i < xferlen; i++) {
5489 if (ddi_copyout(
5490 (uint8_t *)pthru_dma_obj.buffer+i,
5491 (uint8_t *)ubuf+i, 1, mode)) {
5492 con_log(CL_ANN, (CE_WARN,
5493 "issue_mfi_pthru : "
5494 "copy to user space failed"));
5495 return (DDI_FAILURE);
5496 }
5497 }
5498 }
5499 }
5500
5501 kpthru->cmd_status = ddi_get8(acc_handle, &pthru->cmd_status);
5502 kpthru->scsi_status = ddi_get8(acc_handle, &pthru->scsi_status);
5503
5504 con_log(CL_ANN, (CE_CONT, "issue_mfi_pthru: cmd_status %x, "
5505 "scsi_status %x", kpthru->cmd_status, kpthru->scsi_status));
5506 DTRACE_PROBE3(issue_pthru, uint8_t, kpthru->cmd, uint8_t,
5507 kpthru->cmd_status, uint8_t, kpthru->scsi_status);
5508
5509 if (kpthru->sense_len) {
5510 uint_t sense_len = SENSE_LENGTH;
5511 void *sense_ubuf =
5512 (void *)(ulong_t)kpthru->sense_buf_phys_addr_lo;
5513 if (kpthru->sense_len <= SENSE_LENGTH) {
5514 sense_len = kpthru->sense_len;
5515 }
5516
5517 for (i = 0; i < sense_len; i++) {
5518 if (ddi_copyout(
5519 (uint8_t *)cmd->sense+i,
5520 (uint8_t *)sense_ubuf+i, 1, mode)) {
5521 con_log(CL_ANN, (CE_WARN,
5522 "issue_mfi_pthru : "
5523 "copy to user space failed"));
5524 }
5525 con_log(CL_DLEVEL1, (CE_WARN,
5526 "Copying Sense info sense_buff[%d] = 0x%X",
5527 i, *((uint8_t *)cmd->sense + i)));
5528 }
5529 }
5530 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 0, 0,
5531 DDI_DMA_SYNC_FORDEV);
5532
5533 if (xferlen) {
5534 /* free kernel buffer */
5535 if (mrsas_free_dma_obj(instance, pthru_dma_obj) != DDI_SUCCESS)
5536 return (DDI_FAILURE);
5537 }
5538
5539 return (DDI_SUCCESS);
5540 }
5541
5542 /*
5543 * issue_mfi_dcmd
5544 */
5545 static int
5546 issue_mfi_dcmd(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
5547 struct mrsas_cmd *cmd, int mode)
5548 {
5549 void *ubuf;
5550 uint32_t kphys_addr = 0;
5551 uint32_t xferlen = 0;
5552 uint32_t new_xfer_length = 0;
5553 uint32_t model;
5554 dma_obj_t dcmd_dma_obj;
5555 struct mrsas_dcmd_frame *kdcmd;
5556 struct mrsas_dcmd_frame *dcmd;
5557 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle;
5558 int i;
5559 dcmd = &cmd->frame->dcmd;
5560 kdcmd = (struct mrsas_dcmd_frame *)&ioctl->frame[0];
5561
5562 if (instance->adapterresetinprogress) {
5563 con_log(CL_ANN1, (CE_NOTE, "Reset flag set, "
5564 "returning mfi_pkt and setting TRAN_BUSY"));
5565 return (DDI_FAILURE);
5566 }
5567 model = ddi_model_convert_from(mode & FMODELS);
5568 if (model == DDI_MODEL_ILP32) {
5569 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_ILP32"));
5570
5571 xferlen = kdcmd->sgl.sge32[0].length;
5572
5573 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr;
5574 } else {
5575 #ifdef _ILP32
5576 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_ILP32"));
5577 xferlen = kdcmd->sgl.sge32[0].length;
5578 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr;
5579 #else
5580 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_LP64"));
5581 xferlen = kdcmd->sgl.sge64[0].length;
5582 ubuf = (void *)(ulong_t)kdcmd->sgl.sge64[0].phys_addr;
5583 #endif
5584 }
5585 if (xferlen) {
5586 /* means IOCTL requires DMA */
5587 /* allocate the data transfer buffer */
5588 /* dcmd_dma_obj.size = xferlen; */
5589 MRSAS_GET_BOUNDARY_ALIGNED_LEN(xferlen, new_xfer_length,
5590 PAGESIZE);
5591 dcmd_dma_obj.size = new_xfer_length;
5592 dcmd_dma_obj.dma_attr = mrsas_generic_dma_attr;
5593 dcmd_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5594 dcmd_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5595 dcmd_dma_obj.dma_attr.dma_attr_sgllen = 1;
5596 dcmd_dma_obj.dma_attr.dma_attr_align = 1;
5597
5598 /* allocate kernel buffer for DMA */
5599 if (mrsas_alloc_dma_obj(instance, &dcmd_dma_obj,
5600 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5601 con_log(CL_ANN,
5602 (CE_WARN, "issue_mfi_dcmd: could not "
5603 "allocate data transfer buffer."));
5604 return (DDI_FAILURE);
5605 }
5606 (void) memset(dcmd_dma_obj.buffer, 0, xferlen);
5607
5608 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5609 if (kdcmd->flags & MFI_FRAME_DIR_WRITE) {
5610 for (i = 0; i < xferlen; i++) {
5611 if (ddi_copyin((uint8_t *)ubuf + i,
5612 (uint8_t *)dcmd_dma_obj.buffer + i,
5613 1, mode)) {
5614 con_log(CL_ANN, (CE_WARN,
5615 "issue_mfi_dcmd : "
5616 "copy from user space failed"));
5617 return (DDI_FAILURE);
5618 }
5619 }
5620 }
5621
5622 kphys_addr = dcmd_dma_obj.dma_cookie[0].dmac_address;
5623 }
5624
5625 ddi_put8(acc_handle, &dcmd->cmd, kdcmd->cmd);
5626 ddi_put8(acc_handle, &dcmd->cmd_status, 0);
5627 ddi_put8(acc_handle, &dcmd->sge_count, kdcmd->sge_count);
5628 ddi_put16(acc_handle, &dcmd->timeout, kdcmd->timeout);
5629 ddi_put32(acc_handle, &dcmd->data_xfer_len, kdcmd->data_xfer_len);
5630 ddi_put32(acc_handle, &dcmd->opcode, kdcmd->opcode);
5631
5632 ddi_rep_put8(acc_handle, (uint8_t *)kdcmd->mbox.b,
5633 (uint8_t *)dcmd->mbox.b, DCMD_MBOX_SZ, DDI_DEV_AUTOINCR);
5634
5635 ddi_put16(acc_handle, &dcmd->flags, kdcmd->flags & ~MFI_FRAME_SGL64);
5636 ddi_put32(acc_handle, &dcmd->sgl.sge32[0].length, xferlen);
5637 ddi_put32(acc_handle, &dcmd->sgl.sge32[0].phys_addr, kphys_addr);
5638
5639 cmd->sync_cmd = MRSAS_TRUE;
5640 cmd->frame_count = 1;
5641
5642 if (instance->tbolt) {
5643 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
5644 }
5645
5646 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
5647 con_log(CL_ANN, (CE_WARN, "issue_mfi_dcmd: fw_ioctl failed"));
5648 } else {
5649 if (xferlen && (kdcmd->flags & MFI_FRAME_DIR_READ)) {
5650 for (i = 0; i < xferlen; i++) {
5651 if (ddi_copyout(
5652 (uint8_t *)dcmd_dma_obj.buffer + i,
5653 (uint8_t *)ubuf + i,
5654 1, mode)) {
5655 con_log(CL_ANN, (CE_WARN,
5656 "issue_mfi_dcmd : "
5657 "copy to user space failed"));
5658 return (DDI_FAILURE);
5659 }
5660 }
5661 }
5662 }
5663
5664 kdcmd->cmd_status = ddi_get8(acc_handle, &dcmd->cmd_status);
5665 con_log(CL_ANN,
5666 (CE_CONT, "issue_mfi_dcmd: cmd_status %x", kdcmd->cmd_status));
5667 DTRACE_PROBE3(issue_dcmd, uint32_t, kdcmd->opcode, uint8_t,
5668 kdcmd->cmd, uint8_t, kdcmd->cmd_status);
5669
5670 if (xferlen) {
5671 /* free kernel buffer */
5672 if (mrsas_free_dma_obj(instance, dcmd_dma_obj) != DDI_SUCCESS)
5673 return (DDI_FAILURE);
5674 }
5675
5676 return (DDI_SUCCESS);
5677 }
5678
5679 /*
5680 * issue_mfi_smp
5681 */
5682 static int
5683 issue_mfi_smp(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
5684 struct mrsas_cmd *cmd, int mode)
5685 {
5686 void *request_ubuf;
5687 void *response_ubuf;
5688 uint32_t request_xferlen = 0;
5689 uint32_t response_xferlen = 0;
5690 uint32_t new_xfer_length1 = 0;
5691 uint32_t new_xfer_length2 = 0;
5692 uint_t model;
5693 dma_obj_t request_dma_obj;
5694 dma_obj_t response_dma_obj;
5695 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle;
5696 struct mrsas_smp_frame *ksmp;
5697 struct mrsas_smp_frame *smp;
5698 struct mrsas_sge32 *sge32;
5699 #ifndef _ILP32
5700 struct mrsas_sge64 *sge64;
5701 #endif
5702 int i;
5703 uint64_t tmp_sas_addr;
5704
5705 smp = &cmd->frame->smp;
5706 ksmp = (struct mrsas_smp_frame *)&ioctl->frame[0];
5707
5708 if (instance->adapterresetinprogress) {
5709 con_log(CL_ANN1, (CE_WARN, "Reset flag set, "
5710 "returning mfi_pkt and setting TRAN_BUSY\n"));
5711 return (DDI_FAILURE);
5712 }
5713 model = ddi_model_convert_from(mode & FMODELS);
5714 if (model == DDI_MODEL_ILP32) {
5715 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_ILP32"));
5716
5717 sge32 = &ksmp->sgl[0].sge32[0];
5718 response_xferlen = sge32[0].length;
5719 request_xferlen = sge32[1].length;
5720 con_log(CL_ANN, (CE_CONT, "issue_mfi_smp: "
5721 "response_xferlen = %x, request_xferlen = %x",
5722 response_xferlen, request_xferlen));
5723
5724 response_ubuf = (void *)(ulong_t)sge32[0].phys_addr;
5725 request_ubuf = (void *)(ulong_t)sge32[1].phys_addr;
5726 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: "
5727 "response_ubuf = %p, request_ubuf = %p",
5728 response_ubuf, request_ubuf));
5729 } else {
5730 #ifdef _ILP32
5731 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_ILP32"));
5732
5733 sge32 = &ksmp->sgl[0].sge32[0];
5734 response_xferlen = sge32[0].length;
5735 request_xferlen = sge32[1].length;
5736 con_log(CL_ANN, (CE_CONT, "issue_mfi_smp: "
5737 "response_xferlen = %x, request_xferlen = %x",
5738 response_xferlen, request_xferlen));
5739
5740 response_ubuf = (void *)(ulong_t)sge32[0].phys_addr;
5741 request_ubuf = (void *)(ulong_t)sge32[1].phys_addr;
5742 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: "
5743 "response_ubuf = %p, request_ubuf = %p",
5744 response_ubuf, request_ubuf));
5745 #else
5746 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_LP64"));
5747
5748 sge64 = &ksmp->sgl[0].sge64[0];
5749 response_xferlen = sge64[0].length;
5750 request_xferlen = sge64[1].length;
5751
5752 response_ubuf = (void *)(ulong_t)sge64[0].phys_addr;
5753 request_ubuf = (void *)(ulong_t)sge64[1].phys_addr;
5754 #endif
5755 }
5756 if (request_xferlen) {
5757 /* means IOCTL requires DMA */
5758 /* allocate the data transfer buffer */
5759 /* request_dma_obj.size = request_xferlen; */
5760 MRSAS_GET_BOUNDARY_ALIGNED_LEN(request_xferlen,
5761 new_xfer_length1, PAGESIZE);
5762 request_dma_obj.size = new_xfer_length1;
5763 request_dma_obj.dma_attr = mrsas_generic_dma_attr;
5764 request_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5765 request_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5766 request_dma_obj.dma_attr.dma_attr_sgllen = 1;
5767 request_dma_obj.dma_attr.dma_attr_align = 1;
5768
5769 /* allocate kernel buffer for DMA */
5770 if (mrsas_alloc_dma_obj(instance, &request_dma_obj,
5771 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5772 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: "
5773 "could not allocate data transfer buffer."));
5774 return (DDI_FAILURE);
5775 }
5776 (void) memset(request_dma_obj.buffer, 0, request_xferlen);
5777
5778 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5779 for (i = 0; i < request_xferlen; i++) {
5780 if (ddi_copyin((uint8_t *)request_ubuf + i,
5781 (uint8_t *)request_dma_obj.buffer + i,
5782 1, mode)) {
5783 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: "
5784 "copy from user space failed"));
5785 return (DDI_FAILURE);
5786 }
5787 }
5788 }
5789
5790 if (response_xferlen) {
5791 /* means IOCTL requires DMA */
5792 /* allocate the data transfer buffer */
5793 /* response_dma_obj.size = response_xferlen; */
5794 MRSAS_GET_BOUNDARY_ALIGNED_LEN(response_xferlen,
5795 new_xfer_length2, PAGESIZE);
5796 response_dma_obj.size = new_xfer_length2;
5797 response_dma_obj.dma_attr = mrsas_generic_dma_attr;
5798 response_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5799 response_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5800 response_dma_obj.dma_attr.dma_attr_sgllen = 1;
5801 response_dma_obj.dma_attr.dma_attr_align = 1;
5802
5803 /* allocate kernel buffer for DMA */
5804 if (mrsas_alloc_dma_obj(instance, &response_dma_obj,
5805 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5806 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: "
5807 "could not allocate data transfer buffer."));
5808 return (DDI_FAILURE);
5809 }
5810 (void) memset(response_dma_obj.buffer, 0, response_xferlen);
5811
5812 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5813 for (i = 0; i < response_xferlen; i++) {
5814 if (ddi_copyin((uint8_t *)response_ubuf + i,
5815 (uint8_t *)response_dma_obj.buffer + i,
5816 1, mode)) {
5817 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: "
5818 "copy from user space failed"));
5819 return (DDI_FAILURE);
5820 }
5821 }
5822 }
5823
5824 ddi_put8(acc_handle, &smp->cmd, ksmp->cmd);
5825 ddi_put8(acc_handle, &smp->cmd_status, 0);
5826 ddi_put8(acc_handle, &smp->connection_status, 0);
5827 ddi_put8(acc_handle, &smp->sge_count, ksmp->sge_count);
5828 /* smp->context = ksmp->context; */
5829 ddi_put16(acc_handle, &smp->timeout, ksmp->timeout);
5830 ddi_put32(acc_handle, &smp->data_xfer_len, ksmp->data_xfer_len);
5831
5832 bcopy((void *)&ksmp->sas_addr, (void *)&tmp_sas_addr,
5833 sizeof (uint64_t));
5834 ddi_put64(acc_handle, &smp->sas_addr, tmp_sas_addr);
5835
5836 ddi_put16(acc_handle, &smp->flags, ksmp->flags & ~MFI_FRAME_SGL64);
5837
5838 model = ddi_model_convert_from(mode & FMODELS);
5839 if (model == DDI_MODEL_ILP32) {
5840 con_log(CL_ANN1, (CE_CONT,
5841 "issue_mfi_smp: DDI_MODEL_ILP32"));
5842
5843 sge32 = &smp->sgl[0].sge32[0];
5844 ddi_put32(acc_handle, &sge32[0].length, response_xferlen);
5845 ddi_put32(acc_handle, &sge32[0].phys_addr,
5846 response_dma_obj.dma_cookie[0].dmac_address);
5847 ddi_put32(acc_handle, &sge32[1].length, request_xferlen);
5848 ddi_put32(acc_handle, &sge32[1].phys_addr,
5849 request_dma_obj.dma_cookie[0].dmac_address);
5850 } else {
5851 #ifdef _ILP32
5852 con_log(CL_ANN1, (CE_CONT,
5853 "issue_mfi_smp: DDI_MODEL_ILP32"));
5854 sge32 = &smp->sgl[0].sge32[0];
5855 ddi_put32(acc_handle, &sge32[0].length, response_xferlen);
5856 ddi_put32(acc_handle, &sge32[0].phys_addr,
5857 response_dma_obj.dma_cookie[0].dmac_address);
5858 ddi_put32(acc_handle, &sge32[1].length, request_xferlen);
5859 ddi_put32(acc_handle, &sge32[1].phys_addr,
5860 request_dma_obj.dma_cookie[0].dmac_address);
5861 #else
5862 con_log(CL_ANN1, (CE_CONT,
5863 "issue_mfi_smp: DDI_MODEL_LP64"));
5864 sge64 = &smp->sgl[0].sge64[0];
5865 ddi_put32(acc_handle, &sge64[0].length, response_xferlen);
5866 ddi_put64(acc_handle, &sge64[0].phys_addr,
5867 response_dma_obj.dma_cookie[0].dmac_address);
5868 ddi_put32(acc_handle, &sge64[1].length, request_xferlen);
5869 ddi_put64(acc_handle, &sge64[1].phys_addr,
5870 request_dma_obj.dma_cookie[0].dmac_address);
5871 #endif
5872 }
5873 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp : "
5874 "smp->response_xferlen = %d, smp->request_xferlen = %d "
5875 "smp->data_xfer_len = %d", ddi_get32(acc_handle, &sge32[0].length),
5876 ddi_get32(acc_handle, &sge32[1].length),
5877 ddi_get32(acc_handle, &smp->data_xfer_len)));
5878
5879 cmd->sync_cmd = MRSAS_TRUE;
5880 cmd->frame_count = 1;
5881
5882 if (instance->tbolt) {
5883 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
5884 }
5885
5886 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
5887 con_log(CL_ANN, (CE_WARN,
5888 "issue_mfi_smp: fw_ioctl failed"));
5889 } else {
5890 con_log(CL_ANN1, (CE_CONT,
5891 "issue_mfi_smp: copy to user space"));
5892
5893 if (request_xferlen) {
5894 for (i = 0; i < request_xferlen; i++) {
5895 if (ddi_copyout(
5896 (uint8_t *)request_dma_obj.buffer +
5897 i, (uint8_t *)request_ubuf + i,
5898 1, mode)) {
5899 con_log(CL_ANN, (CE_WARN,
5900 "issue_mfi_smp : copy to user space"
5901 " failed"));
5902 return (DDI_FAILURE);
5903 }
5904 }
5905 }
5906
5907 if (response_xferlen) {
5908 for (i = 0; i < response_xferlen; i++) {
5909 if (ddi_copyout(
5910 (uint8_t *)response_dma_obj.buffer
5911 + i, (uint8_t *)response_ubuf
5912 + i, 1, mode)) {
5913 con_log(CL_ANN, (CE_WARN,
5914 "issue_mfi_smp : copy to "
5915 "user space failed"));
5916 return (DDI_FAILURE);
5917 }
5918 }
5919 }
5920 }
5921
5922 ksmp->cmd_status = ddi_get8(acc_handle, &smp->cmd_status);
5923 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_smp: smp->cmd_status = %d",
5924 ksmp->cmd_status));
5925 DTRACE_PROBE2(issue_smp, uint8_t, ksmp->cmd, uint8_t, ksmp->cmd_status);
5926
5927 if (request_xferlen) {
5928 /* free kernel buffer */
5929 if (mrsas_free_dma_obj(instance, request_dma_obj) !=
5930 DDI_SUCCESS)
5931 return (DDI_FAILURE);
5932 }
5933
5934 if (response_xferlen) {
5935 /* free kernel buffer */
5936 if (mrsas_free_dma_obj(instance, response_dma_obj) !=
5937 DDI_SUCCESS)
5938 return (DDI_FAILURE);
5939 }
5940
5941 return (DDI_SUCCESS);
5942 }
5943
5944 /*
5945 * issue_mfi_stp
5946 */
5947 static int
5948 issue_mfi_stp(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
5949 struct mrsas_cmd *cmd, int mode)
5950 {
5951 void *fis_ubuf;
5952 void *data_ubuf;
5953 uint32_t fis_xferlen = 0;
5954 uint32_t new_xfer_length1 = 0;
5955 uint32_t new_xfer_length2 = 0;
5956 uint32_t data_xferlen = 0;
5957 uint_t model;
5958 dma_obj_t fis_dma_obj;
5959 dma_obj_t data_dma_obj;
5960 struct mrsas_stp_frame *kstp;
5961 struct mrsas_stp_frame *stp;
5962 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle;
5963 int i;
5964
5965 stp = &cmd->frame->stp;
5966 kstp = (struct mrsas_stp_frame *)&ioctl->frame[0];
5967
5968 if (instance->adapterresetinprogress) {
5969 con_log(CL_ANN1, (CE_WARN, "Reset flag set, "
5970 "returning mfi_pkt and setting TRAN_BUSY\n"));
5971 return (DDI_FAILURE);
5972 }
5973 model = ddi_model_convert_from(mode & FMODELS);
5974 if (model == DDI_MODEL_ILP32) {
5975 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_ILP32"));
5976
5977 fis_xferlen = kstp->sgl.sge32[0].length;
5978 data_xferlen = kstp->sgl.sge32[1].length;
5979
5980 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge32[0].phys_addr;
5981 data_ubuf = (void *)(ulong_t)kstp->sgl.sge32[1].phys_addr;
5982 } else {
5983 #ifdef _ILP32
5984 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_ILP32"));
5985
5986 fis_xferlen = kstp->sgl.sge32[0].length;
5987 data_xferlen = kstp->sgl.sge32[1].length;
5988
5989 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge32[0].phys_addr;
5990 data_ubuf = (void *)(ulong_t)kstp->sgl.sge32[1].phys_addr;
5991 #else
5992 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_LP64"));
5993
5994 fis_xferlen = kstp->sgl.sge64[0].length;
5995 data_xferlen = kstp->sgl.sge64[1].length;
5996
5997 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge64[0].phys_addr;
5998 data_ubuf = (void *)(ulong_t)kstp->sgl.sge64[1].phys_addr;
5999 #endif
6000 }
6001
6002
6003 if (fis_xferlen) {
6004 con_log(CL_ANN, (CE_CONT, "issue_mfi_stp: "
6005 "fis_ubuf = %p fis_xferlen = %x", fis_ubuf, fis_xferlen));
6006
6007 /* means IOCTL requires DMA */
6008 /* allocate the data transfer buffer */
6009 /* fis_dma_obj.size = fis_xferlen; */
6010 MRSAS_GET_BOUNDARY_ALIGNED_LEN(fis_xferlen,
6011 new_xfer_length1, PAGESIZE);
6012 fis_dma_obj.size = new_xfer_length1;
6013 fis_dma_obj.dma_attr = mrsas_generic_dma_attr;
6014 fis_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
6015 fis_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
6016 fis_dma_obj.dma_attr.dma_attr_sgllen = 1;
6017 fis_dma_obj.dma_attr.dma_attr_align = 1;
6018
6019 /* allocate kernel buffer for DMA */
6020 if (mrsas_alloc_dma_obj(instance, &fis_dma_obj,
6021 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
6022 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp : "
6023 "could not allocate data transfer buffer."));
6024 return (DDI_FAILURE);
6025 }
6026 (void) memset(fis_dma_obj.buffer, 0, fis_xferlen);
6027
6028 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
6029 for (i = 0; i < fis_xferlen; i++) {
6030 if (ddi_copyin((uint8_t *)fis_ubuf + i,
6031 (uint8_t *)fis_dma_obj.buffer + i, 1, mode)) {
6032 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: "
6033 "copy from user space failed"));
6034 return (DDI_FAILURE);
6035 }
6036 }
6037 }
6038
6039 if (data_xferlen) {
6040 con_log(CL_ANN, (CE_CONT, "issue_mfi_stp: data_ubuf = %p "
6041 "data_xferlen = %x", data_ubuf, data_xferlen));
6042
6043 /* means IOCTL requires DMA */
6044 /* allocate the data transfer buffer */
6045 /* data_dma_obj.size = data_xferlen; */
6046 MRSAS_GET_BOUNDARY_ALIGNED_LEN(data_xferlen, new_xfer_length2,
6047 PAGESIZE);
6048 data_dma_obj.size = new_xfer_length2;
6049 data_dma_obj.dma_attr = mrsas_generic_dma_attr;
6050 data_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
6051 data_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
6052 data_dma_obj.dma_attr.dma_attr_sgllen = 1;
6053 data_dma_obj.dma_attr.dma_attr_align = 1;
6054
6055 /* allocate kernel buffer for DMA */
6056 if (mrsas_alloc_dma_obj(instance, &data_dma_obj,
6057 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
6058 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: "
6059 "could not allocate data transfer buffer."));
6060 return (DDI_FAILURE);
6061 }
6062 (void) memset(data_dma_obj.buffer, 0, data_xferlen);
6063
6064 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
6065 for (i = 0; i < data_xferlen; i++) {
6066 if (ddi_copyin((uint8_t *)data_ubuf + i,
6067 (uint8_t *)data_dma_obj.buffer + i, 1, mode)) {
6068 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: "
6069 "copy from user space failed"));
6070 return (DDI_FAILURE);
6071 }
6072 }
6073 }
6074
6075 ddi_put8(acc_handle, &stp->cmd, kstp->cmd);
6076 ddi_put8(acc_handle, &stp->cmd_status, 0);
6077 ddi_put8(acc_handle, &stp->connection_status, 0);
6078 ddi_put8(acc_handle, &stp->target_id, kstp->target_id);
6079 ddi_put8(acc_handle, &stp->sge_count, kstp->sge_count);
6080
6081 ddi_put16(acc_handle, &stp->timeout, kstp->timeout);
6082 ddi_put32(acc_handle, &stp->data_xfer_len, kstp->data_xfer_len);
6083
6084 ddi_rep_put8(acc_handle, (uint8_t *)kstp->fis, (uint8_t *)stp->fis, 10,
6085 DDI_DEV_AUTOINCR);
6086
6087 ddi_put16(acc_handle, &stp->flags, kstp->flags & ~MFI_FRAME_SGL64);
6088 ddi_put32(acc_handle, &stp->stp_flags, kstp->stp_flags);
6089 ddi_put32(acc_handle, &stp->sgl.sge32[0].length, fis_xferlen);
6090 ddi_put32(acc_handle, &stp->sgl.sge32[0].phys_addr,
6091 fis_dma_obj.dma_cookie[0].dmac_address);
6092 ddi_put32(acc_handle, &stp->sgl.sge32[1].length, data_xferlen);
6093 ddi_put32(acc_handle, &stp->sgl.sge32[1].phys_addr,
6094 data_dma_obj.dma_cookie[0].dmac_address);
6095
6096 cmd->sync_cmd = MRSAS_TRUE;
6097 cmd->frame_count = 1;
6098
6099 if (instance->tbolt) {
6100 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
6101 }
6102
6103 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
6104 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: fw_ioctl failed"));
6105 } else {
6106
6107 if (fis_xferlen) {
6108 for (i = 0; i < fis_xferlen; i++) {
6109 if (ddi_copyout(
6110 (uint8_t *)fis_dma_obj.buffer + i,
6111 (uint8_t *)fis_ubuf + i, 1, mode)) {
6112 con_log(CL_ANN, (CE_WARN,
6113 "issue_mfi_stp : copy to "
6114 "user space failed"));
6115 return (DDI_FAILURE);
6116 }
6117 }
6118 }
6119 }
6120 if (data_xferlen) {
6121 for (i = 0; i < data_xferlen; i++) {
6122 if (ddi_copyout(
6123 (uint8_t *)data_dma_obj.buffer + i,
6124 (uint8_t *)data_ubuf + i, 1, mode)) {
6125 con_log(CL_ANN, (CE_WARN,
6126 "issue_mfi_stp : copy to"
6127 " user space failed"));
6128 return (DDI_FAILURE);
6129 }
6130 }
6131 }
6132
6133 kstp->cmd_status = ddi_get8(acc_handle, &stp->cmd_status);
6134 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_stp: stp->cmd_status = %d",
6135 kstp->cmd_status));
6136 DTRACE_PROBE2(issue_stp, uint8_t, kstp->cmd, uint8_t, kstp->cmd_status);
6137
6138 if (fis_xferlen) {
6139 /* free kernel buffer */
6140 if (mrsas_free_dma_obj(instance, fis_dma_obj) != DDI_SUCCESS)
6141 return (DDI_FAILURE);
6142 }
6143
6144 if (data_xferlen) {
6145 /* free kernel buffer */
6146 if (mrsas_free_dma_obj(instance, data_dma_obj) != DDI_SUCCESS)
6147 return (DDI_FAILURE);
6148 }
6149
6150 return (DDI_SUCCESS);
6151 }
6152
6153 /*
6154 * fill_up_drv_ver
6155 */
6156 void
6157 fill_up_drv_ver(struct mrsas_drv_ver *dv)
6158 {
6159 (void) memset(dv, 0, sizeof (struct mrsas_drv_ver));
6160
6161 (void) memcpy(dv->signature, "$LSI LOGIC$", strlen("$LSI LOGIC$"));
6162 (void) memcpy(dv->os_name, "Solaris", strlen("Solaris"));
6163 (void) memcpy(dv->drv_name, "mr_sas", strlen("mr_sas"));
6164 (void) memcpy(dv->drv_ver, MRSAS_VERSION, strlen(MRSAS_VERSION));
6165 (void) memcpy(dv->drv_rel_date, MRSAS_RELDATE,
6166 strlen(MRSAS_RELDATE));
6167
6168 }
6169
6170 /*
6171 * handle_drv_ioctl
6172 */
6173 static int
6174 handle_drv_ioctl(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
6175 int mode)
6176 {
6177 int i;
6178 int rval = DDI_SUCCESS;
6179 int *props = NULL;
6180 void *ubuf;
6181
6182 uint8_t *pci_conf_buf;
6183 uint32_t xferlen;
6184 uint32_t num_props;
6185 uint_t model;
6186 struct mrsas_dcmd_frame *kdcmd;
6187 struct mrsas_drv_ver dv;
6188 struct mrsas_pci_information pi;
6189
6190 kdcmd = (struct mrsas_dcmd_frame *)&ioctl->frame[0];
6191
6192 model = ddi_model_convert_from(mode & FMODELS);
6193 if (model == DDI_MODEL_ILP32) {
6194 con_log(CL_ANN1, (CE_CONT,
6195 "handle_drv_ioctl: DDI_MODEL_ILP32"));
6196
6197 xferlen = kdcmd->sgl.sge32[0].length;
6198
6199 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr;
6200 } else {
6201 #ifdef _ILP32
6202 con_log(CL_ANN1, (CE_CONT,
6203 "handle_drv_ioctl: DDI_MODEL_ILP32"));
6204 xferlen = kdcmd->sgl.sge32[0].length;
6205 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr;
6206 #else
6207 con_log(CL_ANN1, (CE_CONT,
6208 "handle_drv_ioctl: DDI_MODEL_LP64"));
6209 xferlen = kdcmd->sgl.sge64[0].length;
6210 ubuf = (void *)(ulong_t)kdcmd->sgl.sge64[0].phys_addr;
6211 #endif
6212 }
6213 con_log(CL_ANN1, (CE_CONT, "handle_drv_ioctl: "
6214 "dataBuf=%p size=%d bytes", ubuf, xferlen));
6215
6216 switch (kdcmd->opcode) {
6217 case MRSAS_DRIVER_IOCTL_DRIVER_VERSION:
6218 con_log(CL_ANN1, (CE_CONT, "handle_drv_ioctl: "
6219 "MRSAS_DRIVER_IOCTL_DRIVER_VERSION"));
6220
6221 fill_up_drv_ver(&dv);
6222
6223 if (ddi_copyout(&dv, ubuf, xferlen, mode)) {
6224 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: "
6225 "MRSAS_DRIVER_IOCTL_DRIVER_VERSION : "
6226 "copy to user space failed"));
6227 kdcmd->cmd_status = 1;
6228 rval = 1;
6229 } else {
6230 kdcmd->cmd_status = 0;
6231 }
6232 break;
6233 case MRSAS_DRIVER_IOCTL_PCI_INFORMATION:
6234 con_log(CL_ANN1, (CE_NOTE, "handle_drv_ioctl: "
6235 "MRSAS_DRIVER_IOCTL_PCI_INFORMAITON"));
6236
6237 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, instance->dip,
6238 0, "reg", &props, &num_props)) {
6239 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: "
6240 "MRSAS_DRIVER_IOCTL_PCI_INFORMATION : "
6241 "ddi_prop_look_int_array failed"));
6242 rval = DDI_FAILURE;
6243 } else {
6244
6245 pi.busNumber = (props[0] >> 16) & 0xFF;
6246 pi.deviceNumber = (props[0] >> 11) & 0x1f;
6247 pi.functionNumber = (props[0] >> 8) & 0x7;
6248 ddi_prop_free((void *)props);
6249 }
6250
6251 pci_conf_buf = (uint8_t *)&pi.pciHeaderInfo;
6252
6253 for (i = 0; i < (sizeof (struct mrsas_pci_information) -
6254 offsetof(struct mrsas_pci_information, pciHeaderInfo));
6255 i++) {
6256 pci_conf_buf[i] =
6257 pci_config_get8(instance->pci_handle, i);
6258 }
6259
6260 if (ddi_copyout(&pi, ubuf, xferlen, mode)) {
6261 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: "
6262 "MRSAS_DRIVER_IOCTL_PCI_INFORMATION : "
6263 "copy to user space failed"));
6264 kdcmd->cmd_status = 1;
6265 rval = 1;
6266 } else {
6267 kdcmd->cmd_status = 0;
6268 }
6269 break;
6270 default:
6271 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: "
6272 "invalid driver specific IOCTL opcode = 0x%x",
6273 kdcmd->opcode));
6274 kdcmd->cmd_status = 1;
6275 rval = DDI_FAILURE;
6276 break;
6277 }
6278
6279 return (rval);
6280 }
6281
6282 /*
6283 * handle_mfi_ioctl
6284 */
6285 static int
6286 handle_mfi_ioctl(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
6287 int mode)
6288 {
6289 int rval = DDI_SUCCESS;
6290
6291 struct mrsas_header *hdr;
6292 struct mrsas_cmd *cmd;
6293
6294 if (instance->tbolt) {
6295 cmd = get_raid_msg_mfi_pkt(instance);
6296 } else {
6297 cmd = get_mfi_pkt(instance);
6298 }
6299 if (!cmd) {
6300 con_log(CL_ANN, (CE_WARN, "mr_sas: "
6301 "failed to get a cmd packet"));
6302 DTRACE_PROBE2(mfi_ioctl_err, uint16_t,
6303 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
6304 return (DDI_FAILURE);
6305 }
6306
6307 /* Clear the frame buffer and assign back the context id */
6308 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
6309 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
6310 cmd->index);
6311
6312 hdr = (struct mrsas_header *)&ioctl->frame[0];
6313
6314 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, &hdr->cmd)) {
6315 case MFI_CMD_OP_DCMD:
6316 rval = issue_mfi_dcmd(instance, ioctl, cmd, mode);
6317 break;
6318 case MFI_CMD_OP_SMP:
6319 rval = issue_mfi_smp(instance, ioctl, cmd, mode);
6320 break;
6321 case MFI_CMD_OP_STP:
6322 rval = issue_mfi_stp(instance, ioctl, cmd, mode);
6323 break;
6324 case MFI_CMD_OP_LD_SCSI:
6325 case MFI_CMD_OP_PD_SCSI:
6326 rval = issue_mfi_pthru(instance, ioctl, cmd, mode);
6327 break;
6328 default:
6329 con_log(CL_ANN, (CE_WARN, "handle_mfi_ioctl: "
6330 "invalid mfi ioctl hdr->cmd = %d", hdr->cmd));
6331 rval = DDI_FAILURE;
6332 break;
6333 }
6334
6335 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS)
6336 rval = DDI_FAILURE;
6337
6338 if (instance->tbolt) {
6339 return_raid_msg_mfi_pkt(instance, cmd);
6340 } else {
6341 return_mfi_pkt(instance, cmd);
6342 }
6343
6344 return (rval);
6345 }
6346
6347 /*
6348 * AEN
6349 */
6350 static int
6351 handle_mfi_aen(struct mrsas_instance *instance, struct mrsas_aen *aen)
6352 {
6353 int rval = 0;
6354
6355 rval = register_mfi_aen(instance, instance->aen_seq_num,
6356 aen->class_locale_word);
6357
6358 aen->cmd_status = (uint8_t)rval;
6359
6360 return (rval);
6361 }
6362
6363 static int
6364 register_mfi_aen(struct mrsas_instance *instance, uint32_t seq_num,
6365 uint32_t class_locale_word)
6366 {
6367 int ret_val;
6368
6369 struct mrsas_cmd *cmd, *aen_cmd;
6370 struct mrsas_dcmd_frame *dcmd;
6371 union mrsas_evt_class_locale curr_aen;
6372 union mrsas_evt_class_locale prev_aen;
6373
6374 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
6375 /*
6376 * If there an AEN pending already (aen_cmd), check if the
6377 * class_locale of that pending AEN is inclusive of the new
6378 * AEN request we currently have. If it is, then we don't have
6379 * to do anything. In other words, whichever events the current
6380 * AEN request is subscribing to, have already been subscribed
6381 * to.
6382 *
6383 * If the old_cmd is _not_ inclusive, then we have to abort
6384 * that command, form a class_locale that is superset of both
6385 * old and current and re-issue to the FW
6386 */
6387
6388 curr_aen.word = LE_32(class_locale_word);
6389 curr_aen.members.locale = LE_16(curr_aen.members.locale);
6390 aen_cmd = instance->aen_cmd;
6391 if (aen_cmd) {
6392 prev_aen.word = ddi_get32(aen_cmd->frame_dma_obj.acc_handle,
6393 &aen_cmd->frame->dcmd.mbox.w[1]);
6394 prev_aen.word = LE_32(prev_aen.word);
6395 prev_aen.members.locale = LE_16(prev_aen.members.locale);
6396 /*
6397 * A class whose enum value is smaller is inclusive of all
6398 * higher values. If a PROGRESS (= -1) was previously
6399 * registered, then a new registration requests for higher
6400 * classes need not be sent to FW. They are automatically
6401 * included.
6402 *
6403 * Locale numbers don't have such hierarchy. They are bitmap
6404 * values
6405 */
6406 if ((prev_aen.members.class <= curr_aen.members.class) &&
6407 !((prev_aen.members.locale & curr_aen.members.locale) ^
6408 curr_aen.members.locale)) {
6409 /*
6410 * Previously issued event registration includes
6411 * current request. Nothing to do.
6412 */
6413
6414 return (0);
6415 } else {
6416 curr_aen.members.locale |= prev_aen.members.locale;
6417
6418 if (prev_aen.members.class < curr_aen.members.class)
6419 curr_aen.members.class = prev_aen.members.class;
6420
6421 ret_val = abort_aen_cmd(instance, aen_cmd);
6422
6423 if (ret_val) {
6424 con_log(CL_ANN, (CE_WARN, "register_mfi_aen: "
6425 "failed to abort prevous AEN command"));
6426
6427 return (ret_val);
6428 }
6429 }
6430 } else {
6431 curr_aen.word = LE_32(class_locale_word);
6432 curr_aen.members.locale = LE_16(curr_aen.members.locale);
6433 }
6434
6435 if (instance->tbolt) {
6436 cmd = get_raid_msg_mfi_pkt(instance);
6437 } else {
6438 cmd = get_mfi_pkt(instance);
6439 }
6440
6441 if (!cmd) {
6442 DTRACE_PROBE2(mfi_aen_err, uint16_t, instance->fw_outstanding,
6443 uint16_t, instance->max_fw_cmds);
6444 return (ENOMEM);
6445 }
6446
6447 /* Clear the frame buffer and assign back the context id */
6448 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
6449 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
6450 cmd->index);
6451
6452 dcmd = &cmd->frame->dcmd;
6453
6454 /* for(i = 0; i < DCMD_MBOX_SZ; i++) dcmd->mbox.b[i] = 0; */
6455 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ);
6456
6457 (void) memset(instance->mfi_evt_detail_obj.buffer, 0,
6458 sizeof (struct mrsas_evt_detail));
6459
6460 /* Prepare DCMD for aen registration */
6461 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD);
6462 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0x0);
6463 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1);
6464 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags,
6465 MFI_FRAME_DIR_READ);
6466 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0);
6467 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len,
6468 sizeof (struct mrsas_evt_detail));
6469 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode,
6470 MR_DCMD_CTRL_EVENT_WAIT);
6471 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.w[0], seq_num);
6472 curr_aen.members.locale = LE_16(curr_aen.members.locale);
6473 curr_aen.word = LE_32(curr_aen.word);
6474 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.w[1],
6475 curr_aen.word);
6476 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr,
6477 instance->mfi_evt_detail_obj.dma_cookie[0].dmac_address);
6478 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length,
6479 sizeof (struct mrsas_evt_detail));
6480
6481 instance->aen_seq_num = seq_num;
6482
6483
6484 /*
6485 * Store reference to the cmd used to register for AEN. When an
6486 * application wants us to register for AEN, we have to abort this
6487 * cmd and re-register with a new EVENT LOCALE supplied by that app
6488 */
6489 instance->aen_cmd = cmd;
6490
6491 cmd->frame_count = 1;
6492
6493 /* Issue the aen registration frame */
6494 /* atomic_add_16 (&instance->fw_outstanding, 1); */
6495 if (instance->tbolt) {
6496 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
6497 }
6498 instance->func_ptr->issue_cmd(cmd, instance);
6499
6500 return (0);
6501 }
6502
6503 void
6504 display_scsi_inquiry(caddr_t scsi_inq)
6505 {
6506 #define MAX_SCSI_DEVICE_CODE 14
6507 int i;
6508 char inquiry_buf[256] = {0};
6509 int len;
6510 const char *const scsi_device_types[] = {
6511 "Direct-Access ",
6512 "Sequential-Access",
6513 "Printer ",
6514 "Processor ",
6515 "WORM ",
6516 "CD-ROM ",
6517 "Scanner ",
6518 "Optical Device ",
6519 "Medium Changer ",
6520 "Communications ",
6521 "Unknown ",
6522 "Unknown ",
6523 "Unknown ",
6524 "Enclosure ",
6525 };
6526
6527 len = 0;
6528
6529 len += snprintf(inquiry_buf + len, 265 - len, " Vendor: ");
6530 for (i = 8; i < 16; i++) {
6531 len += snprintf(inquiry_buf + len, 265 - len, "%c",
6532 scsi_inq[i]);
6533 }
6534
6535 len += snprintf(inquiry_buf + len, 265 - len, " Model: ");
6536
6537 for (i = 16; i < 32; i++) {
6538 len += snprintf(inquiry_buf + len, 265 - len, "%c",
6539 scsi_inq[i]);
6540 }
6541
6542 len += snprintf(inquiry_buf + len, 265 - len, " Rev: ");
6543
6544 for (i = 32; i < 36; i++) {
6545 len += snprintf(inquiry_buf + len, 265 - len, "%c",
6546 scsi_inq[i]);
6547 }
6548
6549 len += snprintf(inquiry_buf + len, 265 - len, "\n");
6550
6551
6552 i = scsi_inq[0] & 0x1f;
6553
6554
6555 len += snprintf(inquiry_buf + len, 265 - len, " Type: %s ",
6556 i < MAX_SCSI_DEVICE_CODE ? scsi_device_types[i] :
6557 "Unknown ");
6558
6559
6560 len += snprintf(inquiry_buf + len, 265 - len,
6561 " ANSI SCSI revision: %02x", scsi_inq[2] & 0x07);
6562
6563 if ((scsi_inq[2] & 0x07) == 1 && (scsi_inq[3] & 0x0f) == 1) {
6564 len += snprintf(inquiry_buf + len, 265 - len, " CCS\n");
6565 } else {
6566 len += snprintf(inquiry_buf + len, 265 - len, "\n");
6567 }
6568
6569 con_log(CL_DLEVEL2, (CE_CONT, inquiry_buf));
6570 }
6571
6572 static void
6573 io_timeout_checker(void *arg)
6574 {
6575 struct scsi_pkt *pkt;
6576 struct mrsas_instance *instance = arg;
6577 struct mrsas_cmd *cmd = NULL;
6578 struct mrsas_header *hdr;
6579 int time = 0;
6580 int counter = 0;
6581 struct mlist_head *pos, *next;
6582 mlist_t process_list;
6583
6584 if (instance->adapterresetinprogress == 1) {
6585 con_log(CL_ANN, (CE_NOTE, "io_timeout_checker:"
6586 " reset in progress"));
6587
6588 instance->timeout_id = timeout(io_timeout_checker,
6589 (void *) instance, drv_usectohz(MRSAS_1_SECOND));
6590 return;
6591 }
6592
6593 /* See if this check needs to be in the beginning or last in ISR */
6594 if (mrsas_initiate_ocr_if_fw_is_faulty(instance) == 1) {
6595 cmn_err(CE_WARN, "io_timeout_checker: "
6596 "FW Fault, calling reset adapter");
6597 cmn_err(CE_CONT, "io_timeout_checker: "
6598 "fw_outstanding 0x%X max_fw_cmds 0x%X",
6599 instance->fw_outstanding, instance->max_fw_cmds);
6600 if (instance->adapterresetinprogress == 0) {
6601 instance->adapterresetinprogress = 1;
6602 if (instance->tbolt)
6603 (void) mrsas_tbolt_reset_ppc(instance);
6604 else
6605 (void) mrsas_reset_ppc(instance);
6606 instance->adapterresetinprogress = 0;
6607 }
6608 instance->timeout_id = timeout(io_timeout_checker,
6609 (void *) instance, drv_usectohz(MRSAS_1_SECOND));
6610 return;
6611 }
6612
6613 INIT_LIST_HEAD(&process_list);
6614
6615 mutex_enter(&instance->cmd_pend_mtx);
6616 mlist_for_each_safe(pos, next, &instance->cmd_pend_list) {
6617 cmd = mlist_entry(pos, struct mrsas_cmd, list);
6618
6619 if (cmd == NULL) {
6620 continue;
6621 }
6622
6623 if (cmd->sync_cmd == MRSAS_TRUE) {
6624 hdr = (struct mrsas_header *)&cmd->frame->hdr;
6625 if (hdr == NULL) {
6626 continue;
6627 }
6628 time = --cmd->drv_pkt_time;
6629 } else {
6630 pkt = cmd->pkt;
6631 if (pkt == NULL) {
6632 continue;
6633 }
6634 time = --cmd->drv_pkt_time;
6635 }
6636 if (time <= 0) {
6637 cmn_err(CE_WARN, "%llx: "
6638 "io_timeout_checker: TIMING OUT: pkt: %p, "
6639 "cmd %p fw_outstanding 0x%X max_fw_cmds 0x%X\n",
6640 gethrtime(), (void *)pkt, (void *)cmd,
6641 instance->fw_outstanding, instance->max_fw_cmds);
6642
6643 counter++;
6644 break;
6645 }
6646 }
6647 mutex_exit(&instance->cmd_pend_mtx);
6648
6649 if (counter) {
6650 if (instance->disable_online_ctrl_reset == 1) {
6651 cmn_err(CE_WARN, "mr_sas %d: %s(): OCR is NOT "
6652 "supported by Firmware, KILL adapter!!!",
6653 instance->instance, __func__);
6654
6655 if (instance->tbolt)
6656 mrsas_tbolt_kill_adapter(instance);
6657 else
6658 (void) mrsas_kill_adapter(instance);
6659
6660 return;
6661 } else {
6662 if (cmd->retry_count_for_ocr <= IO_RETRY_COUNT) {
6663 if (instance->adapterresetinprogress == 0) {
6664 if (instance->tbolt) {
6665 (void) mrsas_tbolt_reset_ppc(
6666 instance);
6667 } else {
6668 (void) mrsas_reset_ppc(
6669 instance);
6670 }
6671 }
6672 } else {
6673 cmn_err(CE_WARN,
6674 "io_timeout_checker: "
6675 "cmd %p cmd->index %d "
6676 "timed out even after 3 resets: "
6677 "so KILL adapter", (void *)cmd, cmd->index);
6678
6679 mrsas_print_cmd_details(instance, cmd, 0xDD);
6680
6681 if (instance->tbolt)
6682 mrsas_tbolt_kill_adapter(instance);
6683 else
6684 (void) mrsas_kill_adapter(instance);
6685 return;
6686 }
6687 }
6688 }
6689 con_log(CL_ANN, (CE_NOTE, "mrsas: "
6690 "schedule next timeout check: "
6691 "do timeout \n"));
6692 instance->timeout_id =
6693 timeout(io_timeout_checker, (void *)instance,
6694 drv_usectohz(MRSAS_1_SECOND));
6695 }
6696
6697 static uint32_t
6698 read_fw_status_reg_ppc(struct mrsas_instance *instance)
6699 {
6700 return ((uint32_t)RD_OB_SCRATCH_PAD_0(instance));
6701 }
6702
6703 static void
6704 issue_cmd_ppc(struct mrsas_cmd *cmd, struct mrsas_instance *instance)
6705 {
6706 struct scsi_pkt *pkt;
6707 atomic_add_16(&instance->fw_outstanding, 1);
6708
6709 pkt = cmd->pkt;
6710 if (pkt) {
6711 con_log(CL_DLEVEL1, (CE_NOTE, "%llx : issue_cmd_ppc:"
6712 "ISSUED CMD TO FW : called : cmd:"
6713 ": %p instance : %p pkt : %p pkt_time : %x\n",
6714 gethrtime(), (void *)cmd, (void *)instance,
6715 (void *)pkt, cmd->drv_pkt_time));
6716 if (instance->adapterresetinprogress) {
6717 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
6718 con_log(CL_ANN1, (CE_NOTE, "Reset the scsi_pkt timer"));
6719 } else {
6720 push_pending_mfi_pkt(instance, cmd);
6721 }
6722
6723 } else {
6724 con_log(CL_DLEVEL1, (CE_NOTE, "%llx : issue_cmd_ppc:"
6725 "ISSUED CMD TO FW : called : cmd : %p, instance: %p"
6726 "(NO PKT)\n", gethrtime(), (void *)cmd, (void *)instance));
6727 }
6728
6729 mutex_enter(&instance->reg_write_mtx);
6730 /* Issue the command to the FW */
6731 WR_IB_QPORT((cmd->frame_phys_addr) |
6732 (((cmd->frame_count - 1) << 1) | 1), instance);
6733 mutex_exit(&instance->reg_write_mtx);
6734
6735 }
6736
6737 /*
6738 * issue_cmd_in_sync_mode
6739 */
6740 static int
6741 issue_cmd_in_sync_mode_ppc(struct mrsas_instance *instance,
6742 struct mrsas_cmd *cmd)
6743 {
6744 int i;
6745 uint32_t msecs = MFI_POLL_TIMEOUT_SECS * (10 * MILLISEC);
6746 struct mrsas_header *hdr = &cmd->frame->hdr;
6747
6748 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_sync_mode_ppc: called"));
6749
6750 if (instance->adapterresetinprogress) {
6751 cmd->drv_pkt_time = ddi_get16(
6752 cmd->frame_dma_obj.acc_handle, &hdr->timeout);
6753 if (cmd->drv_pkt_time < debug_timeout_g)
6754 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
6755
6756 con_log(CL_ANN1, (CE_NOTE, "sync_mode_ppc: "
6757 "issue and return in reset case\n"));
6758 WR_IB_QPORT((cmd->frame_phys_addr) |
6759 (((cmd->frame_count - 1) << 1) | 1), instance);
6760
6761 return (DDI_SUCCESS);
6762 } else {
6763 con_log(CL_ANN1, (CE_NOTE, "sync_mode_ppc: pushing the pkt\n"));
6764 push_pending_mfi_pkt(instance, cmd);
6765 }
6766
6767 cmd->cmd_status = ENODATA;
6768
6769 mutex_enter(&instance->reg_write_mtx);
6770 /* Issue the command to the FW */
6771 WR_IB_QPORT((cmd->frame_phys_addr) |
6772 (((cmd->frame_count - 1) << 1) | 1), instance);
6773 mutex_exit(&instance->reg_write_mtx);
6774
6775 mutex_enter(&instance->int_cmd_mtx);
6776 for (i = 0; i < msecs && (cmd->cmd_status == ENODATA); i++) {
6777 cv_wait(&instance->int_cmd_cv, &instance->int_cmd_mtx);
6778 }
6779 mutex_exit(&instance->int_cmd_mtx);
6780
6781 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_sync_mode_ppc: done"));
6782
6783 if (i < (msecs -1)) {
6784 return (DDI_SUCCESS);
6785 } else {
6786 return (DDI_FAILURE);
6787 }
6788 }
6789
6790 /*
6791 * issue_cmd_in_poll_mode
6792 */
6793 static int
6794 issue_cmd_in_poll_mode_ppc(struct mrsas_instance *instance,
6795 struct mrsas_cmd *cmd)
6796 {
6797 int i;
6798 uint16_t flags;
6799 uint32_t msecs = MFI_POLL_TIMEOUT_SECS * MILLISEC;
6800 struct mrsas_header *frame_hdr;
6801
6802 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_poll_mode_ppc: called"));
6803
6804 frame_hdr = (struct mrsas_header *)cmd->frame;
6805 ddi_put8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status,
6806 MFI_CMD_STATUS_POLL_MODE);
6807 flags = ddi_get16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags);
6808 flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
6809
6810 ddi_put16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags, flags);
6811
6812 /* issue the frame using inbound queue port */
6813 WR_IB_QPORT((cmd->frame_phys_addr) |
6814 (((cmd->frame_count - 1) << 1) | 1), instance);
6815
6816 /* wait for cmd_status to change from 0xFF */
6817 for (i = 0; i < msecs && (
6818 ddi_get8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status)
6819 == MFI_CMD_STATUS_POLL_MODE); i++) {
6820 drv_usecwait(MILLISEC); /* wait for 1000 usecs */
6821 }
6822
6823 if (ddi_get8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status)
6824 == MFI_CMD_STATUS_POLL_MODE) {
6825 con_log(CL_ANN, (CE_NOTE, "issue_cmd_in_poll_mode: "
6826 "cmd polling timed out"));
6827 return (DDI_FAILURE);
6828 }
6829
6830 return (DDI_SUCCESS);
6831 }
6832
6833 static void
6834 enable_intr_ppc(struct mrsas_instance *instance)
6835 {
6836 uint32_t mask;
6837
6838 con_log(CL_ANN1, (CE_NOTE, "enable_intr_ppc: called"));
6839
6840 /* WR_OB_DOORBELL_CLEAR(0xFFFFFFFF, instance); */
6841 WR_OB_DOORBELL_CLEAR(OB_DOORBELL_CLEAR_MASK, instance);
6842
6843 /* WR_OB_INTR_MASK(~0x80000000, instance); */
6844 WR_OB_INTR_MASK(~(MFI_REPLY_2108_MESSAGE_INTR_MASK), instance);
6845
6846 /* dummy read to force PCI flush */
6847 mask = RD_OB_INTR_MASK(instance);
6848
6849 con_log(CL_ANN1, (CE_NOTE, "enable_intr_ppc: "
6850 "outbound_intr_mask = 0x%x", mask));
6851 }
6852
6853 static void
6854 disable_intr_ppc(struct mrsas_instance *instance)
6855 {
6856 uint32_t mask;
6857
6858 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: called"));
6859
6860 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: before : "
6861 "outbound_intr_mask = 0x%x", RD_OB_INTR_MASK(instance)));
6862
6863 /* WR_OB_INTR_MASK(0xFFFFFFFF, instance); */
6864 WR_OB_INTR_MASK(OB_INTR_MASK, instance);
6865
6866 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: after : "
6867 "outbound_intr_mask = 0x%x", RD_OB_INTR_MASK(instance)));
6868
6869 /* dummy read to force PCI flush */
6870 mask = RD_OB_INTR_MASK(instance);
6871 #ifdef lint
6872 mask = mask;
6873 #endif
6874 }
6875
6876 static int
6877 intr_ack_ppc(struct mrsas_instance *instance)
6878 {
6879 uint32_t status;
6880 int ret = DDI_INTR_CLAIMED;
6881
6882 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: called"));
6883
6884 /* check if it is our interrupt */
6885 status = RD_OB_INTR_STATUS(instance);
6886
6887 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: status = 0x%x", status));
6888
6889 if (!(status & MFI_REPLY_2108_MESSAGE_INTR)) {
6890 ret = DDI_INTR_UNCLAIMED;
6891 }
6892
6893 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) {
6894 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
6895 ret = DDI_INTR_UNCLAIMED;
6896 }
6897
6898 if (ret == DDI_INTR_UNCLAIMED) {
6899 return (ret);
6900 }
6901 /* clear the interrupt by writing back the same value */
6902 WR_OB_DOORBELL_CLEAR(status, instance);
6903
6904 /* dummy READ */
6905 status = RD_OB_INTR_STATUS(instance);
6906
6907 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: interrupt cleared"));
6908
6909 return (ret);
6910 }
6911
6912 /*
6913 * Marks HBA as bad. This will be called either when an
6914 * IO packet times out even after 3 FW resets
6915 * or FW is found to be fault even after 3 continuous resets.
6916 */
6917
6918 static int
6919 mrsas_kill_adapter(struct mrsas_instance *instance)
6920 {
6921 if (instance->deadadapter == 1)
6922 return (DDI_FAILURE);
6923
6924 con_log(CL_ANN1, (CE_NOTE, "mrsas_kill_adapter: "
6925 "Writing to doorbell with MFI_STOP_ADP "));
6926 mutex_enter(&instance->ocr_flags_mtx);
6927 instance->deadadapter = 1;
6928 mutex_exit(&instance->ocr_flags_mtx);
6929 instance->func_ptr->disable_intr(instance);
6930 WR_IB_DOORBELL(MFI_STOP_ADP, instance);
6931 (void) mrsas_complete_pending_cmds(instance);
6932 return (DDI_SUCCESS);
6933 }
6934
6935
6936 static int
6937 mrsas_reset_ppc(struct mrsas_instance *instance)
6938 {
6939 uint32_t status;
6940 uint32_t retry = 0;
6941 uint32_t cur_abs_reg_val;
6942 uint32_t fw_state;
6943
6944 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
6945
6946 if (instance->deadadapter == 1) {
6947 cmn_err(CE_WARN, "mrsas_reset_ppc: "
6948 "no more resets as HBA has been marked dead ");
6949 return (DDI_FAILURE);
6950 }
6951 mutex_enter(&instance->ocr_flags_mtx);
6952 instance->adapterresetinprogress = 1;
6953 mutex_exit(&instance->ocr_flags_mtx);
6954 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: adpterresetinprogress "
6955 "flag set, time %llx", gethrtime()));
6956
6957 instance->func_ptr->disable_intr(instance);
6958 retry_reset:
6959 WR_IB_WRITE_SEQ(0, instance);
6960 WR_IB_WRITE_SEQ(4, instance);
6961 WR_IB_WRITE_SEQ(0xb, instance);
6962 WR_IB_WRITE_SEQ(2, instance);
6963 WR_IB_WRITE_SEQ(7, instance);
6964 WR_IB_WRITE_SEQ(0xd, instance);
6965 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: magic number written "
6966 "to write sequence register\n"));
6967 delay(100 * drv_usectohz(MILLISEC));
6968 status = RD_OB_DRWE(instance);
6969
6970 while (!(status & DIAG_WRITE_ENABLE)) {
6971 delay(100 * drv_usectohz(MILLISEC));
6972 status = RD_OB_DRWE(instance);
6973 if (retry++ == 100) {
6974 cmn_err(CE_WARN, "mrsas_reset_ppc: DRWE bit "
6975 "check retry count %d", retry);
6976 return (DDI_FAILURE);
6977 }
6978 }
6979 WR_IB_DRWE(status | DIAG_RESET_ADAPTER, instance);
6980 delay(100 * drv_usectohz(MILLISEC));
6981 status = RD_OB_DRWE(instance);
6982 while (status & DIAG_RESET_ADAPTER) {
6983 delay(100 * drv_usectohz(MILLISEC));
6984 status = RD_OB_DRWE(instance);
6985 if (retry++ == 100) {
6986 cmn_err(CE_WARN, "mrsas_reset_ppc: "
6987 "RESET FAILED. KILL adapter called.");
6988
6989 (void) mrsas_kill_adapter(instance);
6990 return (DDI_FAILURE);
6991 }
6992 }
6993 con_log(CL_ANN, (CE_NOTE, "mrsas_reset_ppc: Adapter reset complete"));
6994 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
6995 "Calling mfi_state_transition_to_ready"));
6996
6997 /* Mark HBA as bad, if FW is fault after 3 continuous resets */
6998 if (mfi_state_transition_to_ready(instance) ||
6999 debug_fw_faults_after_ocr_g == 1) {
7000 cur_abs_reg_val =
7001 instance->func_ptr->read_fw_status_reg(instance);
7002 fw_state = cur_abs_reg_val & MFI_STATE_MASK;
7003
7004 #ifdef OCRDEBUG
7005 con_log(CL_ANN1, (CE_NOTE,
7006 "mrsas_reset_ppc :before fake: FW is not ready "
7007 "FW state = 0x%x", fw_state));
7008 if (debug_fw_faults_after_ocr_g == 1)
7009 fw_state = MFI_STATE_FAULT;
7010 #endif
7011
7012 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc : FW is not ready "
7013 "FW state = 0x%x", fw_state));
7014
7015 if (fw_state == MFI_STATE_FAULT) {
7016 /* increment the count */
7017 instance->fw_fault_count_after_ocr++;
7018 if (instance->fw_fault_count_after_ocr
7019 < MAX_FW_RESET_COUNT) {
7020 cmn_err(CE_WARN, "mrsas_reset_ppc: "
7021 "FW is in fault after OCR count %d "
7022 "Retry Reset",
7023 instance->fw_fault_count_after_ocr);
7024 goto retry_reset;
7025
7026 } else {
7027 cmn_err(CE_WARN, "mrsas_reset_ppc: "
7028 "Max Reset Count exceeded >%d"
7029 "Mark HBA as bad, KILL adapter",
7030 MAX_FW_RESET_COUNT);
7031
7032 (void) mrsas_kill_adapter(instance);
7033 return (DDI_FAILURE);
7034 }
7035 }
7036 }
7037 /* reset the counter as FW is up after OCR */
7038 instance->fw_fault_count_after_ocr = 0;
7039
7040
7041 ddi_put32(instance->mfi_internal_dma_obj.acc_handle,
7042 instance->producer, 0);
7043
7044 ddi_put32(instance->mfi_internal_dma_obj.acc_handle,
7045 instance->consumer, 0);
7046
7047 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7048 " after resetting produconsumer chck indexs:"
7049 "producer %x consumer %x", *instance->producer,
7050 *instance->consumer));
7051
7052 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7053 "Calling mrsas_issue_init_mfi"));
7054 (void) mrsas_issue_init_mfi(instance);
7055 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7056 "mrsas_issue_init_mfi Done"));
7057
7058 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7059 "Calling mrsas_print_pending_cmd\n"));
7060 (void) mrsas_print_pending_cmds(instance);
7061 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7062 "mrsas_print_pending_cmd done\n"));
7063
7064 instance->func_ptr->enable_intr(instance);
7065 instance->fw_outstanding = 0;
7066
7067 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7068 "Calling mrsas_issue_pending_cmds"));
7069 (void) mrsas_issue_pending_cmds(instance);
7070 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7071 "issue_pending_cmds done.\n"));
7072
7073 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7074 "Calling aen registration"));
7075
7076
7077 instance->aen_cmd->retry_count_for_ocr = 0;
7078 instance->aen_cmd->drv_pkt_time = 0;
7079
7080 instance->func_ptr->issue_cmd(instance->aen_cmd, instance);
7081 con_log(CL_ANN1, (CE_NOTE, "Unsetting adpresetinprogress flag.\n"));
7082
7083 mutex_enter(&instance->ocr_flags_mtx);
7084 instance->adapterresetinprogress = 0;
7085 mutex_exit(&instance->ocr_flags_mtx);
7086 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7087 "adpterresetinprogress flag unset"));
7088
7089 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc done\n"));
7090 return (DDI_SUCCESS);
7091 }
7092
7093 /*
7094 * FMA functions.
7095 */
7096 int
7097 mrsas_common_check(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
7098 {
7099 int ret = DDI_SUCCESS;
7100
7101 if (cmd != NULL &&
7102 mrsas_check_dma_handle(cmd->frame_dma_obj.dma_handle) !=
7103 DDI_SUCCESS) {
7104 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
7105 if (cmd->pkt != NULL) {
7106 cmd->pkt->pkt_reason = CMD_TRAN_ERR;
7107 cmd->pkt->pkt_statistics = 0;
7108 }
7109 ret = DDI_FAILURE;
7110 }
7111 if (mrsas_check_dma_handle(instance->mfi_internal_dma_obj.dma_handle)
7112 != DDI_SUCCESS) {
7113 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
7114 if (cmd != NULL && cmd->pkt != NULL) {
7115 cmd->pkt->pkt_reason = CMD_TRAN_ERR;
7116 cmd->pkt->pkt_statistics = 0;
7117 }
7118 ret = DDI_FAILURE;
7119 }
7120 if (mrsas_check_dma_handle(instance->mfi_evt_detail_obj.dma_handle) !=
7121 DDI_SUCCESS) {
7122 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
7123 if (cmd != NULL && cmd->pkt != NULL) {
7124 cmd->pkt->pkt_reason = CMD_TRAN_ERR;
7125 cmd->pkt->pkt_statistics = 0;
7126 }
7127 ret = DDI_FAILURE;
7128 }
7129 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) {
7130 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
7131
7132 ddi_fm_acc_err_clear(instance->regmap_handle, DDI_FME_VER0);
7133
7134 if (cmd != NULL && cmd->pkt != NULL) {
7135 cmd->pkt->pkt_reason = CMD_TRAN_ERR;
7136 cmd->pkt->pkt_statistics = 0;
7137 }
7138 ret = DDI_FAILURE;
7139 }
7140
7141 return (ret);
7142 }
7143
7144 /*ARGSUSED*/
7145 static int
7146 mrsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
7147 {
7148 /*
7149 * as the driver can always deal with an error in any dma or
7150 * access handle, we can just return the fme_status value.
7151 */
7152 pci_ereport_post(dip, err, NULL);
7153 return (err->fme_status);
7154 }
7155
7156 static void
7157 mrsas_fm_init(struct mrsas_instance *instance)
7158 {
7159 /* Need to change iblock to priority for new MSI intr */
7160 ddi_iblock_cookie_t fm_ibc;
7161
7162 /* Only register with IO Fault Services if we have some capability */
7163 if (instance->fm_capabilities) {
7164 /* Adjust access and dma attributes for FMA */
7165 endian_attr.devacc_attr_access = DDI_FLAGERR_ACC;
7166 mrsas_generic_dma_attr.dma_attr_flags = DDI_DMA_FLAGERR;
7167
7168 /*
7169 * Register capabilities with IO Fault Services.
7170 * fm_capabilities will be updated to indicate
7171 * capabilities actually supported (not requested.)
7172 */
7173
7174 ddi_fm_init(instance->dip, &instance->fm_capabilities, &fm_ibc);
7175
7176 /*
7177 * Initialize pci ereport capabilities if ereport
7178 * capable (should always be.)
7179 */
7180
7181 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities) ||
7182 DDI_FM_ERRCB_CAP(instance->fm_capabilities)) {
7183 pci_ereport_setup(instance->dip);
7184 }
7185
7186 /*
7187 * Register error callback if error callback capable.
7188 */
7189 if (DDI_FM_ERRCB_CAP(instance->fm_capabilities)) {
7190 ddi_fm_handler_register(instance->dip,
7191 mrsas_fm_error_cb, (void*) instance);
7192 }
7193 } else {
7194 endian_attr.devacc_attr_access = DDI_DEFAULT_ACC;
7195 mrsas_generic_dma_attr.dma_attr_flags = 0;
7196 }
7197 }
7198
7199 static void
7200 mrsas_fm_fini(struct mrsas_instance *instance)
7201 {
7202 /* Only unregister FMA capabilities if registered */
7203 if (instance->fm_capabilities) {
7204 /*
7205 * Un-register error callback if error callback capable.
7206 */
7207 if (DDI_FM_ERRCB_CAP(instance->fm_capabilities)) {
7208 ddi_fm_handler_unregister(instance->dip);
7209 }
7210
7211 /*
7212 * Release any resources allocated by pci_ereport_setup()
7213 */
7214 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities) ||
7215 DDI_FM_ERRCB_CAP(instance->fm_capabilities)) {
7216 pci_ereport_teardown(instance->dip);
7217 }
7218
7219 /* Unregister from IO Fault Services */
7220 ddi_fm_fini(instance->dip);
7221
7222 /* Adjust access and dma attributes for FMA */
7223 endian_attr.devacc_attr_access = DDI_DEFAULT_ACC;
7224 mrsas_generic_dma_attr.dma_attr_flags = 0;
7225 }
7226 }
7227
7228 int
7229 mrsas_check_acc_handle(ddi_acc_handle_t handle)
7230 {
7231 ddi_fm_error_t de;
7232
7233 if (handle == NULL) {
7234 return (DDI_FAILURE);
7235 }
7236
7237 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
7238
7239 return (de.fme_status);
7240 }
7241
7242 int
7243 mrsas_check_dma_handle(ddi_dma_handle_t handle)
7244 {
7245 ddi_fm_error_t de;
7246
7247 if (handle == NULL) {
7248 return (DDI_FAILURE);
7249 }
7250
7251 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
7252
7253 return (de.fme_status);
7254 }
7255
7256 void
7257 mrsas_fm_ereport(struct mrsas_instance *instance, char *detail)
7258 {
7259 uint64_t ena;
7260 char buf[FM_MAX_CLASS];
7261
7262 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
7263 ena = fm_ena_generate(0, FM_ENA_FMT1);
7264 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities)) {
7265 ddi_fm_ereport_post(instance->dip, buf, ena, DDI_NOSLEEP,
7266 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERSION, NULL);
7267 }
7268 }
7269
7270 static int
7271 mrsas_add_intrs(struct mrsas_instance *instance, int intr_type)
7272 {
7273
7274 dev_info_t *dip = instance->dip;
7275 int avail, actual, count;
7276 int i, flag, ret;
7277
7278 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: intr_type = %x",
7279 intr_type));
7280
7281 /* Get number of interrupts */
7282 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
7283 if ((ret != DDI_SUCCESS) || (count == 0)) {
7284 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_nintrs() failed:"
7285 "ret %d count %d", ret, count));
7286
7287 return (DDI_FAILURE);
7288 }
7289
7290 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: count = %d ", count));
7291
7292 /* Get number of available interrupts */
7293 ret = ddi_intr_get_navail(dip, intr_type, &avail);
7294 if ((ret != DDI_SUCCESS) || (avail == 0)) {
7295 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_navail() failed:"
7296 "ret %d avail %d", ret, avail));
7297
7298 return (DDI_FAILURE);
7299 }
7300 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: avail = %d ", avail));
7301
7302 /* Only one interrupt routine. So limit the count to 1 */
7303 if (count > 1) {
7304 count = 1;
7305 }
7306
7307 /*
7308 * Allocate an array of interrupt handlers. Currently we support
7309 * only one interrupt. The framework can be extended later.
7310 */
7311 instance->intr_htable_size = count * sizeof (ddi_intr_handle_t);
7312 instance->intr_htable = kmem_zalloc(instance->intr_htable_size,
7313 KM_SLEEP);
7314 ASSERT(instance->intr_htable);
7315
7316 flag = ((intr_type == DDI_INTR_TYPE_MSI) ||
7317 (intr_type == DDI_INTR_TYPE_MSIX)) ?
7318 DDI_INTR_ALLOC_STRICT : DDI_INTR_ALLOC_NORMAL;
7319
7320 /* Allocate interrupt */
7321 ret = ddi_intr_alloc(dip, instance->intr_htable, intr_type, 0,
7322 count, &actual, flag);
7323
7324 if ((ret != DDI_SUCCESS) || (actual == 0)) {
7325 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: "
7326 "avail = %d", avail));
7327 goto mrsas_free_htable;
7328 }
7329
7330 if (actual < count) {
7331 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: "
7332 "Requested = %d Received = %d", count, actual));
7333 }
7334 instance->intr_cnt = actual;
7335
7336 /*
7337 * Get the priority of the interrupt allocated.
7338 */
7339 if ((ret = ddi_intr_get_pri(instance->intr_htable[0],
7340 &instance->intr_pri)) != DDI_SUCCESS) {
7341 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: "
7342 "get priority call failed"));
7343 goto mrsas_free_handles;
7344 }
7345
7346 /*
7347 * Test for high level mutex. we don't support them.
7348 */
7349 if (instance->intr_pri >= ddi_intr_get_hilevel_pri()) {
7350 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: "
7351 "High level interrupts not supported."));
7352 goto mrsas_free_handles;
7353 }
7354
7355 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: intr_pri = 0x%x ",
7356 instance->intr_pri));
7357
7358 /* Call ddi_intr_add_handler() */
7359 for (i = 0; i < actual; i++) {
7360 ret = ddi_intr_add_handler(instance->intr_htable[i],
7361 (ddi_intr_handler_t *)mrsas_isr, (caddr_t)instance,
7362 (caddr_t)(uintptr_t)i);
7363
7364 if (ret != DDI_SUCCESS) {
7365 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs:"
7366 "failed %d", ret));
7367 goto mrsas_free_handles;
7368 }
7369
7370 }
7371
7372 con_log(CL_DLEVEL1, (CE_NOTE, " ddi_intr_add_handler done"));
7373
7374 if ((ret = ddi_intr_get_cap(instance->intr_htable[0],
7375 &instance->intr_cap)) != DDI_SUCCESS) {
7376 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_cap() failed %d",
7377 ret));
7378 goto mrsas_free_handlers;
7379 }
7380
7381 if (instance->intr_cap & DDI_INTR_FLAG_BLOCK) {
7382 con_log(CL_ANN, (CE_WARN, "Calling ddi_intr_block _enable"));
7383
7384 (void) ddi_intr_block_enable(instance->intr_htable,
7385 instance->intr_cnt);
7386 } else {
7387 con_log(CL_ANN, (CE_NOTE, " calling ddi_intr_enable"));
7388
7389 for (i = 0; i < instance->intr_cnt; i++) {
7390 (void) ddi_intr_enable(instance->intr_htable[i]);
7391 con_log(CL_ANN, (CE_NOTE, "ddi intr enable returns "
7392 "%d", i));
7393 }
7394 }
7395
7396 return (DDI_SUCCESS);
7397
7398 mrsas_free_handlers:
7399 for (i = 0; i < actual; i++)
7400 (void) ddi_intr_remove_handler(instance->intr_htable[i]);
7401
7402 mrsas_free_handles:
7403 for (i = 0; i < actual; i++)
7404 (void) ddi_intr_free(instance->intr_htable[i]);
7405
7406 mrsas_free_htable:
7407 if (instance->intr_htable != NULL)
7408 kmem_free(instance->intr_htable, instance->intr_htable_size);
7409
7410 instance->intr_htable = NULL;
7411 instance->intr_htable_size = 0;
7412
7413 return (DDI_FAILURE);
7414
7415 }
7416
7417
7418 static void
7419 mrsas_rem_intrs(struct mrsas_instance *instance)
7420 {
7421 int i;
7422
7423 con_log(CL_ANN, (CE_NOTE, "mrsas_rem_intrs called"));
7424
7425 /* Disable all interrupts first */
7426 if (instance->intr_cap & DDI_INTR_FLAG_BLOCK) {
7427 (void) ddi_intr_block_disable(instance->intr_htable,
7428 instance->intr_cnt);
7429 } else {
7430 for (i = 0; i < instance->intr_cnt; i++) {
7431 (void) ddi_intr_disable(instance->intr_htable[i]);
7432 }
7433 }
7434
7435 /* Remove all the handlers */
7436
7437 for (i = 0; i < instance->intr_cnt; i++) {
7438 (void) ddi_intr_remove_handler(instance->intr_htable[i]);
7439 (void) ddi_intr_free(instance->intr_htable[i]);
7440 }
7441
7442 if (instance->intr_htable != NULL)
7443 kmem_free(instance->intr_htable, instance->intr_htable_size);
7444
7445 instance->intr_htable = NULL;
7446 instance->intr_htable_size = 0;
7447
7448 }
7449
7450 static int
7451 mrsas_tran_bus_config(dev_info_t *parent, uint_t flags,
7452 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
7453 {
7454 struct mrsas_instance *instance;
7455 int config;
7456 int rval = NDI_SUCCESS;
7457
7458 char *ptr = NULL;
7459 int tgt, lun;
7460
7461 con_log(CL_ANN1, (CE_NOTE, "Bus config called for op = %x", op));
7462
7463 if ((instance = ddi_get_soft_state(mrsas_state,
7464 ddi_get_instance(parent))) == NULL) {
7465 return (NDI_FAILURE);
7466 }
7467
7468 /* Hold nexus during bus_config */
7469 ndi_devi_enter(parent, &config);
7470 switch (op) {
7471 case BUS_CONFIG_ONE: {
7472
7473 /* parse wwid/target name out of name given */
7474 if ((ptr = strchr((char *)arg, '@')) == NULL) {
7475 rval = NDI_FAILURE;
7476 break;
7477 }
7478 ptr++;
7479
7480 if (mrsas_parse_devname(arg, &tgt, &lun) != 0) {
7481 rval = NDI_FAILURE;
7482 break;
7483 }
7484
7485 if (lun == 0) {
7486 rval = mrsas_config_ld(instance, tgt, lun, childp);
7487 #ifdef PDSUPPORT
7488 } else if (instance->tbolt == 1 && lun != 0) {
7489 rval = mrsas_tbolt_config_pd(instance,
7490 tgt, lun, childp);
7491 #endif
7492 } else {
7493 rval = NDI_FAILURE;
7494 }
7495
7496 break;
7497 }
7498 case BUS_CONFIG_DRIVER:
7499 case BUS_CONFIG_ALL: {
7500
7501 rval = mrsas_config_all_devices(instance);
7502
7503 rval = NDI_SUCCESS;
7504 break;
7505 }
7506 }
7507
7508 if (rval == NDI_SUCCESS) {
7509 rval = ndi_busop_bus_config(parent, flags, op, arg, childp, 0);
7510
7511 }
7512 ndi_devi_exit(parent, config);
7513
7514 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_bus_config: rval = %x",
7515 rval));
7516 return (rval);
7517 }
7518
7519 static int
7520 mrsas_config_all_devices(struct mrsas_instance *instance)
7521 {
7522 int rval, tgt;
7523
7524 for (tgt = 0; tgt < MRDRV_MAX_LD; tgt++) {
7525 (void) mrsas_config_ld(instance, tgt, 0, NULL);
7526
7527 }
7528
7529 #ifdef PDSUPPORT
7530 /* Config PD devices connected to the card */
7531 if (instance->tbolt) {
7532 for (tgt = 0; tgt < instance->mr_tbolt_pd_max; tgt++) {
7533 (void) mrsas_tbolt_config_pd(instance, tgt, 1, NULL);
7534 }
7535 }
7536 #endif
7537
7538 rval = NDI_SUCCESS;
7539 return (rval);
7540 }
7541
7542 static int
7543 mrsas_parse_devname(char *devnm, int *tgt, int *lun)
7544 {
7545 char devbuf[SCSI_MAXNAMELEN];
7546 char *addr;
7547 char *p, *tp, *lp;
7548 long num;
7549
7550 /* Parse dev name and address */
7551 (void) strcpy(devbuf, devnm);
7552 addr = "";
7553 for (p = devbuf; *p != '\0'; p++) {
7554 if (*p == '@') {
7555 addr = p + 1;
7556 *p = '\0';
7557 } else if (*p == ':') {
7558 *p = '\0';
7559 break;
7560 }
7561 }
7562
7563 /* Parse target and lun */
7564 for (p = tp = addr, lp = NULL; *p != '\0'; p++) {
7565 if (*p == ',') {
7566 lp = p + 1;
7567 *p = '\0';
7568 break;
7569 }
7570 }
7571 if (tgt && tp) {
7572 if (ddi_strtol(tp, NULL, 0x10, &num)) {
7573 return (DDI_FAILURE); /* Can declare this as constant */
7574 }
7575 *tgt = (int)num;
7576 }
7577 if (lun && lp) {
7578 if (ddi_strtol(lp, NULL, 0x10, &num)) {
7579 return (DDI_FAILURE);
7580 }
7581 *lun = (int)num;
7582 }
7583 return (DDI_SUCCESS); /* Success case */
7584 }
7585
7586 static int
7587 mrsas_config_ld(struct mrsas_instance *instance, uint16_t tgt,
7588 uint8_t lun, dev_info_t **ldip)
7589 {
7590 struct scsi_device *sd;
7591 dev_info_t *child;
7592 int rval;
7593
7594 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_config_ld: t = %d l = %d",
7595 tgt, lun));
7596
7597 if ((child = mrsas_find_child(instance, tgt, lun)) != NULL) {
7598 if (ldip) {
7599 *ldip = child;
7600 }
7601 if (instance->mr_ld_list[tgt].flag != MRDRV_TGT_VALID) {
7602 rval = mrsas_service_evt(instance, tgt, 0,
7603 MRSAS_EVT_UNCONFIG_TGT, NULL);
7604 con_log(CL_ANN1, (CE_WARN,
7605 "mr_sas: DELETING STALE ENTRY rval = %d "
7606 "tgt id = %d ", rval, tgt));
7607 return (NDI_FAILURE);
7608 }
7609 return (NDI_SUCCESS);
7610 }
7611
7612 sd = kmem_zalloc(sizeof (struct scsi_device), KM_SLEEP);
7613 sd->sd_address.a_hba_tran = instance->tran;
7614 sd->sd_address.a_target = (uint16_t)tgt;
7615 sd->sd_address.a_lun = (uint8_t)lun;
7616
7617 if (scsi_hba_probe(sd, NULL) == SCSIPROBE_EXISTS)
7618 rval = mrsas_config_scsi_device(instance, sd, ldip);
7619 else
7620 rval = NDI_FAILURE;
7621
7622 /* sd_unprobe is blank now. Free buffer manually */
7623 if (sd->sd_inq) {
7624 kmem_free(sd->sd_inq, SUN_INQSIZE);
7625 sd->sd_inq = (struct scsi_inquiry *)NULL;
7626 }
7627
7628 kmem_free(sd, sizeof (struct scsi_device));
7629 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_config_ld: return rval = %d",
7630 rval));
7631 return (rval);
7632 }
7633
7634 int
7635 mrsas_config_scsi_device(struct mrsas_instance *instance,
7636 struct scsi_device *sd, dev_info_t **dipp)
7637 {
7638 char *nodename = NULL;
7639 char **compatible = NULL;
7640 int ncompatible = 0;
7641 char *childname;
7642 dev_info_t *ldip = NULL;
7643 int tgt = sd->sd_address.a_target;
7644 int lun = sd->sd_address.a_lun;
7645 int dtype = sd->sd_inq->inq_dtype & DTYPE_MASK;
7646 int rval;
7647
7648 con_log(CL_DLEVEL1, (CE_NOTE, "mr_sas: scsi_device t%dL%d", tgt, lun));
7649 scsi_hba_nodename_compatible_get(sd->sd_inq, NULL, dtype,
7650 NULL, &nodename, &compatible, &ncompatible);
7651
7652 if (nodename == NULL) {
7653 con_log(CL_ANN1, (CE_WARN, "mr_sas: Found no compatible driver "
7654 "for t%dL%d", tgt, lun));
7655 rval = NDI_FAILURE;
7656 goto finish;
7657 }
7658
7659 childname = (dtype == DTYPE_DIRECT) ? "sd" : nodename;
7660 con_log(CL_DLEVEL1, (CE_NOTE,
7661 "mr_sas: Childname = %2s nodename = %s", childname, nodename));
7662
7663 /* Create a dev node */
7664 rval = ndi_devi_alloc(instance->dip, childname, DEVI_SID_NODEID, &ldip);
7665 con_log(CL_DLEVEL1, (CE_NOTE,
7666 "mr_sas_config_scsi_device: ndi_devi_alloc rval = %x", rval));
7667 if (rval == NDI_SUCCESS) {
7668 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "target", tgt) !=
7669 DDI_PROP_SUCCESS) {
7670 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create "
7671 "property for t%dl%d target", tgt, lun));
7672 rval = NDI_FAILURE;
7673 goto finish;
7674 }
7675 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "lun", lun) !=
7676 DDI_PROP_SUCCESS) {
7677 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create "
7678 "property for t%dl%d lun", tgt, lun));
7679 rval = NDI_FAILURE;
7680 goto finish;
7681 }
7682
7683 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, ldip,
7684 "compatible", compatible, ncompatible) !=
7685 DDI_PROP_SUCCESS) {
7686 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create "
7687 "property for t%dl%d compatible", tgt, lun));
7688 rval = NDI_FAILURE;
7689 goto finish;
7690 }
7691
7692 rval = ndi_devi_online(ldip, NDI_ONLINE_ATTACH);
7693 if (rval != NDI_SUCCESS) {
7694 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to online "
7695 "t%dl%d", tgt, lun));
7696 ndi_prop_remove_all(ldip);
7697 (void) ndi_devi_free(ldip);
7698 } else {
7699 con_log(CL_ANN1, (CE_CONT, "mr_sas: online Done :"
7700 "0 t%dl%d", tgt, lun));
7701 }
7702
7703 }
7704 finish:
7705 if (dipp) {
7706 *dipp = ldip;
7707 }
7708
7709 con_log(CL_DLEVEL1, (CE_NOTE,
7710 "mr_sas: config_scsi_device rval = %d t%dL%d",
7711 rval, tgt, lun));
7712 scsi_hba_nodename_compatible_free(nodename, compatible);
7713 return (rval);
7714 }
7715
7716 /*ARGSUSED*/
7717 int
7718 mrsas_service_evt(struct mrsas_instance *instance, int tgt, int lun, int event,
7719 uint64_t wwn)
7720 {
7721 struct mrsas_eventinfo *mrevt = NULL;
7722
7723 con_log(CL_ANN1, (CE_NOTE,
7724 "mrsas_service_evt called for t%dl%d event = %d",
7725 tgt, lun, event));
7726
7727 if ((instance->taskq == NULL) || (mrevt =
7728 kmem_zalloc(sizeof (struct mrsas_eventinfo), KM_NOSLEEP)) == NULL) {
7729 return (ENOMEM);
7730 }
7731
7732 mrevt->instance = instance;
7733 mrevt->tgt = tgt;
7734 mrevt->lun = lun;
7735 mrevt->event = event;
7736 mrevt->wwn = wwn;
7737
7738 if ((ddi_taskq_dispatch(instance->taskq,
7739 (void (*)(void *))mrsas_issue_evt_taskq, mrevt, DDI_NOSLEEP)) !=
7740 DDI_SUCCESS) {
7741 con_log(CL_ANN1, (CE_NOTE,
7742 "mr_sas: Event task failed for t%dl%d event = %d",
7743 tgt, lun, event));
7744 kmem_free(mrevt, sizeof (struct mrsas_eventinfo));
7745 return (DDI_FAILURE);
7746 }
7747 DTRACE_PROBE3(service_evt, int, tgt, int, lun, int, event);
7748 return (DDI_SUCCESS);
7749 }
7750
7751 static void
7752 mrsas_issue_evt_taskq(struct mrsas_eventinfo *mrevt)
7753 {
7754 struct mrsas_instance *instance = mrevt->instance;
7755 dev_info_t *dip, *pdip;
7756 int circ1 = 0;
7757 char *devname;
7758
7759 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_evt_taskq: called for"
7760 " tgt %d lun %d event %d",
7761 mrevt->tgt, mrevt->lun, mrevt->event));
7762
7763 if (mrevt->tgt < MRDRV_MAX_LD && mrevt->lun == 0) {
7764 mutex_enter(&instance->config_dev_mtx);
7765 dip = instance->mr_ld_list[mrevt->tgt].dip;
7766 mutex_exit(&instance->config_dev_mtx);
7767 #ifdef PDSUPPORT
7768 } else {
7769 mutex_enter(&instance->config_dev_mtx);
7770 dip = instance->mr_tbolt_pd_list[mrevt->tgt].dip;
7771 mutex_exit(&instance->config_dev_mtx);
7772 #endif
7773 }
7774
7775
7776 ndi_devi_enter(instance->dip, &circ1);
7777 switch (mrevt->event) {
7778 case MRSAS_EVT_CONFIG_TGT:
7779 if (dip == NULL) {
7780
7781 if (mrevt->lun == 0) {
7782 (void) mrsas_config_ld(instance, mrevt->tgt,
7783 0, NULL);
7784 #ifdef PDSUPPORT
7785 } else if (instance->tbolt) {
7786 (void) mrsas_tbolt_config_pd(instance,
7787 mrevt->tgt,
7788 1, NULL);
7789 #endif
7790 }
7791 con_log(CL_ANN1, (CE_NOTE,
7792 "mr_sas: EVT_CONFIG_TGT called:"
7793 " for tgt %d lun %d event %d",
7794 mrevt->tgt, mrevt->lun, mrevt->event));
7795
7796 } else {
7797 con_log(CL_ANN1, (CE_NOTE,
7798 "mr_sas: EVT_CONFIG_TGT dip != NULL:"
7799 " for tgt %d lun %d event %d",
7800 mrevt->tgt, mrevt->lun, mrevt->event));
7801 }
7802 break;
7803 case MRSAS_EVT_UNCONFIG_TGT:
7804 if (dip) {
7805 if (i_ddi_devi_attached(dip)) {
7806
7807 pdip = ddi_get_parent(dip);
7808
7809 devname = kmem_zalloc(MAXNAMELEN + 1, KM_SLEEP);
7810 (void) ddi_deviname(dip, devname);
7811
7812 (void) devfs_clean(pdip, devname + 1,
7813 DV_CLEAN_FORCE);
7814 kmem_free(devname, MAXNAMELEN + 1);
7815 }
7816 (void) ndi_devi_offline(dip, NDI_DEVI_REMOVE);
7817 con_log(CL_ANN1, (CE_NOTE,
7818 "mr_sas: EVT_UNCONFIG_TGT called:"
7819 " for tgt %d lun %d event %d",
7820 mrevt->tgt, mrevt->lun, mrevt->event));
7821 } else {
7822 con_log(CL_ANN1, (CE_NOTE,
7823 "mr_sas: EVT_UNCONFIG_TGT dip == NULL:"
7824 " for tgt %d lun %d event %d",
7825 mrevt->tgt, mrevt->lun, mrevt->event));
7826 }
7827 break;
7828 }
7829 kmem_free(mrevt, sizeof (struct mrsas_eventinfo));
7830 ndi_devi_exit(instance->dip, circ1);
7831 }
7832
7833
7834 int
7835 mrsas_mode_sense_build(struct scsi_pkt *pkt)
7836 {
7837 union scsi_cdb *cdbp;
7838 uint16_t page_code;
7839 struct scsa_cmd *acmd;
7840 struct buf *bp;
7841 struct mode_header *modehdrp;
7842
7843 cdbp = (void *)pkt->pkt_cdbp;
7844 page_code = cdbp->cdb_un.sg.scsi[0];
7845 acmd = PKT2CMD(pkt);
7846 bp = acmd->cmd_buf;
7847 if ((!bp) && bp->b_un.b_addr && bp->b_bcount && acmd->cmd_dmacount) {
7848 con_log(CL_ANN1, (CE_WARN, "Failing MODESENSE Command"));
7849 /* ADD pkt statistics as Command failed. */
7850 return (NULL);
7851 }
7852
7853 bp_mapin(bp);
7854 bzero(bp->b_un.b_addr, bp->b_bcount);
7855
7856 switch (page_code) {
7857 case 0x3: {
7858 struct mode_format *page3p = NULL;
7859 modehdrp = (struct mode_header *)(bp->b_un.b_addr);
7860 modehdrp->bdesc_length = MODE_BLK_DESC_LENGTH;
7861
7862 page3p = (void *)((caddr_t)modehdrp +
7863 MODE_HEADER_LENGTH + MODE_BLK_DESC_LENGTH);
7864 page3p->mode_page.code = 0x3;
7865 page3p->mode_page.length =
7866 (uchar_t)(sizeof (struct mode_format));
7867 page3p->data_bytes_sect = 512;
7868 page3p->sect_track = 63;
7869 break;
7870 }
7871 case 0x4: {
7872 struct mode_geometry *page4p = NULL;
7873 modehdrp = (struct mode_header *)(bp->b_un.b_addr);
7874 modehdrp->bdesc_length = MODE_BLK_DESC_LENGTH;
7875
7876 page4p = (void *)((caddr_t)modehdrp +
7877 MODE_HEADER_LENGTH + MODE_BLK_DESC_LENGTH);
7878 page4p->mode_page.code = 0x4;
7879 page4p->mode_page.length =
7880 (uchar_t)(sizeof (struct mode_geometry));
7881 page4p->heads = 255;
7882 page4p->rpm = 10000;
7883 break;
7884 }
7885 default:
7886 break;
7887 }
7888 return (NULL);
7889 }