1 /******************************************************************************
   2 
   3   Copyright (c) 2001-2013, Intel Corporation 
   4   All rights reserved.
   5   
   6   Redistribution and use in source and binary forms, with or without 
   7   modification, are permitted provided that the following conditions are met:
   8   
   9    1. Redistributions of source code must retain the above copyright notice, 
  10       this list of conditions and the following disclaimer.
  11   
  12    2. Redistributions in binary form must reproduce the above copyright 
  13       notice, this list of conditions and the following disclaimer in the 
  14       documentation and/or other materials provided with the distribution.
  15   
  16    3. Neither the name of the Intel Corporation nor the names of its 
  17       contributors may be used to endorse or promote products derived from 
  18       this software without specific prior written permission.
  19   
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31 
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34 
  35 #ifndef _IXGBE_PHY_H_
  36 #define _IXGBE_PHY_H_
  37 
  38 #include "ixgbe_type.h"
  39 #define IXGBE_I2C_EEPROM_DEV_ADDR       0xA0
  40 #define IXGBE_I2C_EEPROM_DEV_ADDR2      0xA2
  41 #define IXGBE_I2C_EEPROM_BANK_LEN       0xFF
  42 
  43 /* EEPROM byte offsets */
  44 #define IXGBE_SFF_IDENTIFIER            0x0
  45 #define IXGBE_SFF_IDENTIFIER_SFP        0x3
  46 #define IXGBE_SFF_VENDOR_OUI_BYTE0      0x25
  47 #define IXGBE_SFF_VENDOR_OUI_BYTE1      0x26
  48 #define IXGBE_SFF_VENDOR_OUI_BYTE2      0x27
  49 #define IXGBE_SFF_1GBE_COMP_CODES       0x6
  50 #define IXGBE_SFF_10GBE_COMP_CODES      0x3
  51 #define IXGBE_SFF_CABLE_TECHNOLOGY      0x8
  52 #define IXGBE_SFF_CABLE_SPEC_COMP       0x3C
  53 #define IXGBE_SFF_SFF_8472_SWAP         0x5C
  54 #define IXGBE_SFF_SFF_8472_COMP         0x5E
  55 #define IXGBE_SFF_SFF_8472_OSCB         0x6E
  56 #define IXGBE_SFF_SFF_8472_ESCB         0x76
  57 
  58 /* Bitmasks */
  59 #define IXGBE_SFF_DA_PASSIVE_CABLE      0x4
  60 #define IXGBE_SFF_DA_ACTIVE_CABLE       0x8
  61 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING       0x4
  62 #define IXGBE_SFF_1GBASESX_CAPABLE      0x1
  63 #define IXGBE_SFF_1GBASELX_CAPABLE      0x2
  64 #define IXGBE_SFF_1GBASET_CAPABLE       0x8
  65 #define IXGBE_SFF_10GBASESR_CAPABLE     0x10
  66 #define IXGBE_SFF_10GBASELR_CAPABLE     0x20
  67 #define IXGBE_SFF_SOFT_RS_SELECT_MASK   0x8
  68 #define IXGBE_SFF_SOFT_RS_SELECT_10G    0x8
  69 #define IXGBE_SFF_SOFT_RS_SELECT_1G     0x0
  70 #define IXGBE_I2C_EEPROM_READ_MASK      0x100
  71 #define IXGBE_I2C_EEPROM_STATUS_MASK    0x3
  72 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION    0x0
  73 #define IXGBE_I2C_EEPROM_STATUS_PASS    0x1
  74 #define IXGBE_I2C_EEPROM_STATUS_FAIL    0x2
  75 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS     0x3
  76 
  77 /* Flow control defines */
  78 #define IXGBE_TAF_SYM_PAUSE             0x400
  79 #define IXGBE_TAF_ASM_PAUSE             0x800
  80 
  81 /* Bit-shift macros */
  82 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT        24
  83 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT        16
  84 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT        8
  85 
  86 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
  87 #define IXGBE_SFF_VENDOR_OUI_TYCO       0x00407600
  88 #define IXGBE_SFF_VENDOR_OUI_FTL        0x00906500
  89 #define IXGBE_SFF_VENDOR_OUI_AVAGO      0x00176A00
  90 #define IXGBE_SFF_VENDOR_OUI_INTEL      0x001B2100
  91 
  92 /* I2C SDA and SCL timing parameters for standard mode */
  93 #define IXGBE_I2C_T_HD_STA      4
  94 #define IXGBE_I2C_T_LOW         5
  95 #define IXGBE_I2C_T_HIGH        4
  96 #define IXGBE_I2C_T_SU_STA      5
  97 #define IXGBE_I2C_T_HD_DATA     5
  98 #define IXGBE_I2C_T_SU_DATA     1
  99 #define IXGBE_I2C_T_RISE        1
 100 #define IXGBE_I2C_T_FALL        1
 101 #define IXGBE_I2C_T_SU_STO      4
 102 #define IXGBE_I2C_T_BUF         5
 103 
 104 #define IXGBE_TN_LASI_STATUS_REG        0x9005
 105 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
 106 
 107 /* SFP+ SFF-8472 Compliance */
 108 #define IXGBE_SFF_SFF_8472_UNSUP        0x00
 109 #define IXGBE_SFF_SFF_8472_REV_9_3      0x01
 110 #define IXGBE_SFF_SFF_8472_REV_9_5      0x02
 111 #define IXGBE_SFF_SFF_8472_REV_10_2     0x03
 112 #define IXGBE_SFF_SFF_8472_REV_10_4     0x04
 113 #define IXGBE_SFF_SFF_8472_REV_11_0     0x05
 114 
 115 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
 116 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
 117 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
 118 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
 119 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
 120 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
 121 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 122                                u32 device_type, u16 *phy_data);
 123 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 124                                 u32 device_type, u16 phy_data);
 125 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
 126 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 127                                        ixgbe_link_speed speed,
 128                                        bool autoneg_wait_to_complete);
 129 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 130                                                ixgbe_link_speed *speed,
 131                                                bool *autoneg);
 132 
 133 /* PHY specific */
 134 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
 135                              ixgbe_link_speed *speed,
 136                              bool *link_up);
 137 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
 138 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 139                                        u16 *firmware_version);
 140 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 141                                            u16 *firmware_version);
 142 
 143 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
 144 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
 145 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
 146 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
 147                                         u16 *list_offset,
 148                                         u16 *data_offset);
 149 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
 150 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 151                                 u8 dev_addr, u8 *data);
 152 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 153                                  u8 dev_addr, u8 data);
 154 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 155                                   u8 *eeprom_data);
 156 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 157                                    u8 eeprom_data);
 158 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
 159 #endif /* _IXGBE_PHY_H_ */