Import some changes from FreeBSD (details later, this is quick-n-dirty for now).

*** 1,8 ****
  /******************************************************************************
  
!   Copyright (c) 2001-2012, Intel Corporation 
    All rights reserved.
    
    Redistribution and use in source and binary forms, with or without 
    modification, are permitted provided that the following conditions are met:
    
--- 1,8 ----
  /******************************************************************************
  
!   Copyright (c) 2001-2013, Intel Corporation 
    All rights reserved.
    
    Redistribution and use in source and binary forms, with or without 
    modification, are permitted provided that the following conditions are met:
    
*** 35,44 ****
--- 35,46 ----
  #ifndef _IXGBE_PHY_H_
  #define _IXGBE_PHY_H_
  
  #include "ixgbe_type.h"
  #define IXGBE_I2C_EEPROM_DEV_ADDR       0xA0
+ #define IXGBE_I2C_EEPROM_DEV_ADDR2      0xA2
+ #define IXGBE_I2C_EEPROM_BANK_LEN       0xFF
  
  /* EEPROM byte offsets */
  #define IXGBE_SFF_IDENTIFIER            0x0
  #define IXGBE_SFF_IDENTIFIER_SFP        0x3
  #define IXGBE_SFF_VENDOR_OUI_BYTE0      0x25
*** 46,55 ****
--- 48,61 ----
  #define IXGBE_SFF_VENDOR_OUI_BYTE2      0x27
  #define IXGBE_SFF_1GBE_COMP_CODES       0x6
  #define IXGBE_SFF_10GBE_COMP_CODES      0x3
  #define IXGBE_SFF_CABLE_TECHNOLOGY      0x8
  #define IXGBE_SFF_CABLE_SPEC_COMP       0x3C
+ #define IXGBE_SFF_SFF_8472_SWAP         0x5C
+ #define IXGBE_SFF_SFF_8472_COMP         0x5E
+ #define IXGBE_SFF_SFF_8472_OSCB         0x6E
+ #define IXGBE_SFF_SFF_8472_ESCB         0x76
  
  /* Bitmasks */
  #define IXGBE_SFF_DA_PASSIVE_CABLE      0x4
  #define IXGBE_SFF_DA_ACTIVE_CABLE       0x8
  #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING       0x4
*** 56,65 ****
--- 62,74 ----
  #define IXGBE_SFF_1GBASESX_CAPABLE      0x1
  #define IXGBE_SFF_1GBASELX_CAPABLE      0x2
  #define IXGBE_SFF_1GBASET_CAPABLE       0x8
  #define IXGBE_SFF_10GBASESR_CAPABLE     0x10
  #define IXGBE_SFF_10GBASELR_CAPABLE     0x20
+ #define IXGBE_SFF_SOFT_RS_SELECT_MASK   0x8
+ #define IXGBE_SFF_SOFT_RS_SELECT_10G    0x8
+ #define IXGBE_SFF_SOFT_RS_SELECT_1G     0x0
  #define IXGBE_I2C_EEPROM_READ_MASK      0x100
  #define IXGBE_I2C_EEPROM_STATUS_MASK    0x3
  #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION    0x0
  #define IXGBE_I2C_EEPROM_STATUS_PASS    0x1
  #define IXGBE_I2C_EEPROM_STATUS_FAIL    0x2
*** 93,102 ****
--- 102,119 ----
  #define IXGBE_I2C_T_BUF         5
  
  #define IXGBE_TN_LASI_STATUS_REG        0x9005
  #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
  
+ /* SFP+ SFF-8472 Compliance */
+ #define IXGBE_SFF_SFF_8472_UNSUP        0x00
+ #define IXGBE_SFF_SFF_8472_REV_9_3      0x01
+ #define IXGBE_SFF_SFF_8472_REV_9_5      0x02
+ #define IXGBE_SFF_SFF_8472_REV_10_2     0x03
+ #define IXGBE_SFF_SFF_8472_REV_10_4     0x04
+ #define IXGBE_SFF_SFF_8472_REV_11_0     0x05
+ 
  s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
  bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
  enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
*** 106,116 ****
  s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                                  u32 device_type, u16 phy_data);
  s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
  s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
                                         ixgbe_link_speed speed,
-                                        bool autoneg,
                                         bool autoneg_wait_to_complete);
  s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
                                                 ixgbe_link_speed *speed,
                                                 bool *autoneg);
  
--- 123,132 ----