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Import some changes from FreeBSD (details later, this is quick-n-dirty for now).
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--- old/usr/src/uts/common/io/ixgbe/ixgbe_phy.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_phy.c
1 1 /******************************************************************************
2 2
3 - Copyright (c) 2001-2012, Intel Corporation
3 + Copyright (c) 2001-2013, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34 34
35 35 #include "ixgbe_api.h"
36 36 #include "ixgbe_common.h"
37 37 #include "ixgbe_phy.h"
38 38
39 39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
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40 40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
50 +static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
51 + u8 *sff8472_data);
50 52
51 53 /**
52 54 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
53 55 * @hw: pointer to the hardware structure
54 56 *
55 57 * Initialize the function pointers.
56 58 **/
57 59 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
58 60 {
59 61 struct ixgbe_phy_info *phy = &hw->phy;
60 62
61 63 DEBUGFUNC("ixgbe_init_phy_ops_generic");
62 64
63 65 /* PHY */
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64 66 phy->ops.identify = &ixgbe_identify_phy_generic;
65 67 phy->ops.reset = &ixgbe_reset_phy_generic;
66 68 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
67 69 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
68 70 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
69 71 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
70 72 phy->ops.check_link = NULL;
71 73 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
72 74 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
73 75 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
76 + phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
74 77 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
75 78 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
76 79 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
77 80 phy->ops.identify_sfp = &ixgbe_identify_module_generic;
78 81 phy->sfp_type = ixgbe_sfp_type_unknown;
79 82 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
80 83 return IXGBE_SUCCESS;
81 84 }
82 85
83 86 /**
84 87 * ixgbe_identify_phy_generic - Get physical layer module
85 88 * @hw: pointer to hardware structure
86 89 *
87 90 * Determines the physical layer module found on the current adapter.
88 91 **/
89 92 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
90 93 {
91 94 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
92 95 u32 phy_addr;
93 96 u16 ext_ability = 0;
94 97
95 98 DEBUGFUNC("ixgbe_identify_phy_generic");
96 99
97 100 if (hw->phy.type == ixgbe_phy_unknown) {
98 101 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
99 102 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
100 103 hw->phy.addr = phy_addr;
101 104 (void) ixgbe_get_phy_id(hw);
102 105 hw->phy.type =
103 106 ixgbe_get_phy_type_from_id(hw->phy.id);
104 107
105 108 if (hw->phy.type == ixgbe_phy_unknown) {
106 109 hw->phy.ops.read_reg(hw,
107 110 IXGBE_MDIO_PHY_EXT_ABILITY,
108 111 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
109 112 &ext_ability);
110 113 if (ext_ability &
111 114 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
112 115 IXGBE_MDIO_PHY_1000BASET_ABILITY))
113 116 hw->phy.type =
114 117 ixgbe_phy_cu_unknown;
115 118 else
116 119 hw->phy.type =
117 120 ixgbe_phy_generic;
118 121 }
119 122
120 123 status = IXGBE_SUCCESS;
121 124 break;
122 125 }
123 126 }
124 127 /* clear value if nothing found */
125 128 if (status != IXGBE_SUCCESS)
126 129 hw->phy.addr = 0;
127 130 } else {
128 131 status = IXGBE_SUCCESS;
129 132 }
130 133
131 134 return status;
132 135 }
133 136
134 137 /**
135 138 * ixgbe_validate_phy_addr - Determines phy address is valid
136 139 * @hw: pointer to hardware structure
137 140 *
138 141 **/
139 142 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
140 143 {
141 144 u16 phy_id = 0;
142 145 bool valid = FALSE;
143 146
144 147 DEBUGFUNC("ixgbe_validate_phy_addr");
145 148
146 149 hw->phy.addr = phy_addr;
147 150 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
148 151 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
149 152
150 153 if (phy_id != 0xFFFF && phy_id != 0x0)
151 154 valid = TRUE;
152 155
153 156 return valid;
154 157 }
155 158
156 159 /**
157 160 * ixgbe_get_phy_id - Get the phy type
158 161 * @hw: pointer to hardware structure
159 162 *
160 163 **/
161 164 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
162 165 {
163 166 u32 status;
164 167 u16 phy_id_high = 0;
165 168 u16 phy_id_low = 0;
166 169
167 170 DEBUGFUNC("ixgbe_get_phy_id");
168 171
169 172 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
170 173 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
171 174 &phy_id_high);
172 175
173 176 if (status == IXGBE_SUCCESS) {
174 177 hw->phy.id = (u32)(phy_id_high << 16);
175 178 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
176 179 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
177 180 &phy_id_low);
178 181 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
179 182 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
180 183 }
181 184 return status;
182 185 }
183 186
184 187 /**
185 188 * ixgbe_get_phy_type_from_id - Get the phy type
186 189 * @hw: pointer to hardware structure
187 190 *
188 191 **/
189 192 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
190 193 {
191 194 enum ixgbe_phy_type phy_type;
192 195
193 196 DEBUGFUNC("ixgbe_get_phy_type_from_id");
194 197
195 198 switch (phy_id) {
196 199 case TN1010_PHY_ID:
197 200 phy_type = ixgbe_phy_tn;
198 201 break;
199 202 case X540_PHY_ID:
200 203 phy_type = ixgbe_phy_aq;
201 204 break;
202 205 case QT2022_PHY_ID:
203 206 phy_type = ixgbe_phy_qt;
204 207 break;
205 208 case ATH_PHY_ID:
206 209 phy_type = ixgbe_phy_nl;
207 210 break;
208 211 default:
209 212 phy_type = ixgbe_phy_unknown;
210 213 break;
211 214 }
212 215
213 216 DEBUGOUT1("phy type found is %d\n", phy_type);
214 217 return phy_type;
215 218 }
216 219
217 220 /**
218 221 * ixgbe_reset_phy_generic - Performs a PHY reset
219 222 * @hw: pointer to hardware structure
220 223 **/
221 224 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
222 225 {
223 226 u32 i;
224 227 u16 ctrl = 0;
225 228 s32 status = IXGBE_SUCCESS;
226 229
227 230 DEBUGFUNC("ixgbe_reset_phy_generic");
228 231
229 232 if (hw->phy.type == ixgbe_phy_unknown)
230 233 status = ixgbe_identify_phy_generic(hw);
231 234
232 235 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
233 236 goto out;
234 237
235 238 /* Don't reset PHY if it's shut down due to overtemp. */
236 239 if (!hw->phy.reset_if_overtemp &&
237 240 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
238 241 goto out;
239 242
240 243 /*
241 244 * Perform soft PHY reset to the PHY_XS.
242 245 * This will cause a soft reset to the PHY
243 246 */
244 247 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
245 248 IXGBE_MDIO_PHY_XS_DEV_TYPE,
246 249 IXGBE_MDIO_PHY_XS_RESET);
247 250
248 251 /*
249 252 * Poll for reset bit to self-clear indicating reset is complete.
250 253 * Some PHYs could take up to 3 seconds to complete and need about
251 254 * 1.7 usec delay after the reset is complete.
252 255 */
253 256 for (i = 0; i < 30; i++) {
254 257 msec_delay(100);
255 258 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
256 259 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
257 260 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
258 261 usec_delay(2);
259 262 break;
260 263 }
261 264 }
262 265
263 266 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
264 267 status = IXGBE_ERR_RESET_FAILED;
265 268 DEBUGOUT("PHY reset polling failed to complete.\n");
266 269 }
267 270
268 271 out:
269 272 return status;
270 273 }
271 274
272 275 /**
273 276 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
274 277 * @hw: pointer to hardware structure
275 278 * @reg_addr: 32 bit address of PHY register to read
276 279 * @phy_data: Pointer to read data from PHY register
277 280 **/
278 281 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
279 282 u32 device_type, u16 *phy_data)
280 283 {
281 284 u32 command;
282 285 u32 i;
283 286 u32 data;
284 287 s32 status = IXGBE_SUCCESS;
285 288 u16 gssr;
286 289
287 290 DEBUGFUNC("ixgbe_read_phy_reg_generic");
288 291
289 292 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
290 293 gssr = IXGBE_GSSR_PHY1_SM;
291 294 else
292 295 gssr = IXGBE_GSSR_PHY0_SM;
293 296
294 297 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
295 298 status = IXGBE_ERR_SWFW_SYNC;
296 299
297 300 if (status == IXGBE_SUCCESS) {
298 301 /* Setup and write the address cycle command */
299 302 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
300 303 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
301 304 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
302 305 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
303 306
304 307 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
305 308
306 309 /*
307 310 * Check every 10 usec to see if the address cycle completed.
308 311 * The MDI Command bit will clear when the operation is
309 312 * complete
310 313 */
311 314 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
312 315 usec_delay(10);
313 316
314 317 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
315 318
316 319 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
317 320 break;
318 321 }
319 322
320 323 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
321 324 DEBUGOUT("PHY address command did not complete.\n");
322 325 status = IXGBE_ERR_PHY;
323 326 }
324 327
325 328 if (status == IXGBE_SUCCESS) {
326 329 /*
327 330 * Address cycle complete, setup and write the read
328 331 * command
329 332 */
330 333 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
331 334 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
332 335 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
333 336 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
334 337
335 338 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
336 339
337 340 /*
338 341 * Check every 10 usec to see if the address cycle
339 342 * completed. The MDI Command bit will clear when the
340 343 * operation is complete
341 344 */
342 345 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
343 346 usec_delay(10);
344 347
345 348 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
346 349
347 350 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
348 351 break;
349 352 }
350 353
351 354 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
352 355 DEBUGOUT("PHY read command didn't complete\n");
353 356 status = IXGBE_ERR_PHY;
354 357 } else {
355 358 /*
356 359 * Read operation is complete. Get the data
357 360 * from MSRWD
358 361 */
359 362 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
360 363 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
361 364 *phy_data = (u16)(data);
362 365 }
363 366 }
364 367
365 368 hw->mac.ops.release_swfw_sync(hw, gssr);
366 369 }
367 370
368 371 return status;
369 372 }
370 373
371 374 /**
372 375 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
373 376 * @hw: pointer to hardware structure
374 377 * @reg_addr: 32 bit PHY register to write
375 378 * @device_type: 5 bit device type
376 379 * @phy_data: Data to write to the PHY register
377 380 **/
378 381 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
379 382 u32 device_type, u16 phy_data)
380 383 {
381 384 u32 command;
382 385 u32 i;
383 386 s32 status = IXGBE_SUCCESS;
384 387 u16 gssr;
385 388
386 389 DEBUGFUNC("ixgbe_write_phy_reg_generic");
387 390
388 391 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
389 392 gssr = IXGBE_GSSR_PHY1_SM;
390 393 else
391 394 gssr = IXGBE_GSSR_PHY0_SM;
392 395
393 396 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
394 397 status = IXGBE_ERR_SWFW_SYNC;
395 398
396 399 if (status == IXGBE_SUCCESS) {
397 400 /* Put the data in the MDI single read and write data register*/
398 401 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
399 402
400 403 /* Setup and write the address cycle command */
401 404 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
402 405 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
403 406 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
404 407 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
405 408
406 409 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
407 410
408 411 /*
409 412 * Check every 10 usec to see if the address cycle completed.
410 413 * The MDI Command bit will clear when the operation is
411 414 * complete
412 415 */
413 416 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
414 417 usec_delay(10);
415 418
416 419 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
417 420
418 421 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
419 422 break;
420 423 }
421 424
422 425 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
423 426 DEBUGOUT("PHY address cmd didn't complete\n");
424 427 status = IXGBE_ERR_PHY;
425 428 }
426 429
427 430 if (status == IXGBE_SUCCESS) {
428 431 /*
429 432 * Address cycle complete, setup and write the write
430 433 * command
431 434 */
432 435 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
433 436 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
434 437 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
435 438 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
436 439
437 440 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
438 441
439 442 /*
440 443 * Check every 10 usec to see if the address cycle
441 444 * completed. The MDI Command bit will clear when the
442 445 * operation is complete
443 446 */
444 447 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
445 448 usec_delay(10);
446 449
447 450 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
448 451
449 452 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
450 453 break;
451 454 }
452 455
453 456 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
454 457 DEBUGOUT("PHY address cmd didn't complete\n");
455 458 status = IXGBE_ERR_PHY;
456 459 }
457 460 }
458 461
459 462 hw->mac.ops.release_swfw_sync(hw, gssr);
460 463 }
461 464
462 465 return status;
463 466 }
464 467
465 468 /**
466 469 * ixgbe_setup_phy_link_generic - Set and restart autoneg
467 470 * @hw: pointer to hardware structure
468 471 *
469 472 * Restart autonegotiation and PHY and waits for completion.
470 473 **/
471 474 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
472 475 {
473 476 s32 status;
474 477 u32 time_out;
475 478 u32 max_time_out = 10;
476 479 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
477 480 bool autoneg = FALSE;
478 481 ixgbe_link_speed speed;
479 482
480 483 DEBUGFUNC("ixgbe_setup_phy_link_generic");
481 484
482 485 status =
483 486 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
484 487 if (status != IXGBE_SUCCESS)
485 488 return status;
486 489
487 490 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
488 491 /* Set or unset auto-negotiation 10G advertisement */
489 492 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
490 493 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
491 494 &autoneg_reg);
492 495
493 496 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
494 497 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
495 498 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
496 499
497 500 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
498 501 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
499 502 autoneg_reg);
500 503 }
501 504
502 505 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
503 506 /* Set or unset auto-negotiation 1G advertisement */
504 507 hw->phy.ops.read_reg(hw,
505 508 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
506 509 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
507 510 &autoneg_reg);
508 511
509 512 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
510 513 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
511 514 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
512 515
513 516 hw->phy.ops.write_reg(hw,
514 517 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
515 518 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
516 519 autoneg_reg);
517 520 }
518 521
519 522 if (speed & IXGBE_LINK_SPEED_100_FULL) {
520 523 /* Set or unset auto-negotiation 100M advertisement */
521 524 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
522 525 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
523 526 &autoneg_reg);
524 527
525 528 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
526 529 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
527 530 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
528 531 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
529 532
530 533 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
531 534 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
532 535 autoneg_reg);
533 536 }
534 537
535 538 /* Restart PHY autonegotiation and wait for completion */
536 539 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
537 540 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
538 541
539 542 autoneg_reg |= IXGBE_MII_RESTART;
540 543
541 544 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
542 545 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
543 546
544 547 /* Wait for autonegotiation to finish */
545 548 for (time_out = 0; time_out < max_time_out; time_out++) {
546 549 usec_delay(10);
547 550 /* Restart PHY autonegotiation and wait for completion */
548 551 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
549 552 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
550 553 &autoneg_reg);
551 554
552 555 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
553 556 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
554 557 break;
555 558 }
556 559
557 560 if (time_out == max_time_out) {
558 561 status = IXGBE_ERR_LINK_SETUP;
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559 562 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
560 563 }
561 564
562 565 return status;
563 566 }
564 567
565 568 /**
566 569 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
567 570 * @hw: pointer to hardware structure
568 571 * @speed: new link speed
569 - * @autoneg: TRUE if autonegotiation enabled
570 572 **/
571 573 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
572 574 ixgbe_link_speed speed,
573 - bool autoneg,
574 575 bool autoneg_wait_to_complete)
575 576 {
576 - UNREFERENCED_2PARAMETER(autoneg, autoneg_wait_to_complete);
577 + UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
577 578
578 579 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
579 580
580 581 /*
581 582 * Clear autoneg_advertised and set new values based on input link
582 583 * speed.
583 584 */
584 585 hw->phy.autoneg_advertised = 0;
585 586
586 587 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
587 588 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
588 589
589 590 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
590 591 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
591 592
592 593 if (speed & IXGBE_LINK_SPEED_100_FULL)
593 594 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
594 595
595 596 /* Setup link based on the new speed settings */
596 597 hw->phy.ops.setup_link(hw);
597 598
598 599 return IXGBE_SUCCESS;
599 600 }
600 601
601 602 /**
602 603 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
603 604 * @hw: pointer to hardware structure
604 605 * @speed: pointer to link speed
605 606 * @autoneg: boolean auto-negotiation value
606 607 *
607 608 * Determines the link capabilities by reading the AUTOC register.
608 609 **/
609 610 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
610 611 ixgbe_link_speed *speed,
611 612 bool *autoneg)
612 613 {
613 614 s32 status = IXGBE_ERR_LINK_SETUP;
614 615 u16 speed_ability;
615 616
616 617 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
617 618
618 619 *speed = 0;
619 620 *autoneg = TRUE;
620 621
621 622 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
622 623 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
623 624 &speed_ability);
624 625
625 626 if (status == IXGBE_SUCCESS) {
626 627 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
627 628 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
628 629 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
629 630 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
630 631 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
631 632 *speed |= IXGBE_LINK_SPEED_100_FULL;
632 633 }
633 634
634 635 return status;
635 636 }
636 637
637 638 /**
638 639 * ixgbe_check_phy_link_tnx - Determine link and speed status
639 640 * @hw: pointer to hardware structure
640 641 *
641 642 * Reads the VS1 register to determine if link is up and the current speed for
642 643 * the PHY.
643 644 **/
644 645 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
645 646 bool *link_up)
646 647 {
647 648 s32 status = IXGBE_SUCCESS;
648 649 u32 time_out;
649 650 u32 max_time_out = 10;
650 651 u16 phy_link = 0;
651 652 u16 phy_speed = 0;
652 653 u16 phy_data = 0;
653 654
654 655 DEBUGFUNC("ixgbe_check_phy_link_tnx");
655 656
656 657 /* Initialize speed and link to default case */
657 658 *link_up = FALSE;
658 659 *speed = IXGBE_LINK_SPEED_10GB_FULL;
659 660
660 661 /*
661 662 * Check current speed and link status of the PHY register.
662 663 * This is a vendor specific register and may have to
663 664 * be changed for other copper PHYs.
664 665 */
665 666 for (time_out = 0; time_out < max_time_out; time_out++) {
666 667 usec_delay(10);
667 668 status = hw->phy.ops.read_reg(hw,
668 669 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
669 670 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
670 671 &phy_data);
671 672 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
672 673 phy_speed = phy_data &
673 674 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
674 675 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
675 676 *link_up = TRUE;
676 677 if (phy_speed ==
677 678 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
678 679 *speed = IXGBE_LINK_SPEED_1GB_FULL;
679 680 break;
680 681 }
681 682 }
682 683
683 684 return status;
684 685 }
685 686
686 687 /**
687 688 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
688 689 * @hw: pointer to hardware structure
689 690 *
690 691 * Restart autonegotiation and PHY and waits for completion.
691 692 **/
692 693 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
693 694 {
694 695 s32 status;
695 696 u32 time_out;
696 697 u32 max_time_out = 10;
697 698 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
698 699 bool autoneg = FALSE;
699 700 ixgbe_link_speed speed;
700 701
701 702 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
702 703
703 704 status =
704 705 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
705 706 if (status != IXGBE_SUCCESS)
706 707 return status;
707 708
708 709 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
709 710 /* Set or unset auto-negotiation 10G advertisement */
710 711 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
711 712 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
712 713 &autoneg_reg);
713 714
714 715 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
715 716 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
716 717 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
717 718
718 719 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
719 720 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
720 721 autoneg_reg);
721 722 }
722 723
723 724 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
724 725 /* Set or unset auto-negotiation 1G advertisement */
725 726 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
726 727 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
727 728 &autoneg_reg);
728 729
729 730 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
730 731 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
731 732 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
732 733
733 734 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
734 735 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
735 736 autoneg_reg);
736 737 }
737 738
738 739 if (speed & IXGBE_LINK_SPEED_100_FULL) {
739 740 /* Set or unset auto-negotiation 100M advertisement */
740 741 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
741 742 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
742 743 &autoneg_reg);
743 744
744 745 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
745 746 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
746 747 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
747 748
748 749 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
749 750 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
750 751 autoneg_reg);
751 752 }
752 753
753 754 /* Restart PHY autonegotiation and wait for completion */
754 755 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
755 756 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
756 757
757 758 autoneg_reg |= IXGBE_MII_RESTART;
758 759
759 760 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
760 761 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
761 762
762 763 /* Wait for autonegotiation to finish */
763 764 for (time_out = 0; time_out < max_time_out; time_out++) {
764 765 usec_delay(10);
765 766 /* Restart PHY autonegotiation and wait for completion */
766 767 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
767 768 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
768 769 &autoneg_reg);
769 770
770 771 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
771 772 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
772 773 break;
773 774 }
774 775
775 776 if (time_out == max_time_out) {
776 777 status = IXGBE_ERR_LINK_SETUP;
777 778 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
778 779 }
779 780
780 781 return status;
781 782 }
782 783
783 784 /**
784 785 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
785 786 * @hw: pointer to hardware structure
786 787 * @firmware_version: pointer to the PHY Firmware Version
787 788 **/
788 789 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
789 790 u16 *firmware_version)
790 791 {
791 792 s32 status = IXGBE_SUCCESS;
792 793
793 794 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
794 795
795 796 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
796 797 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
797 798 firmware_version);
798 799
799 800 return status;
800 801 }
801 802
802 803 /**
803 804 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
804 805 * @hw: pointer to hardware structure
805 806 * @firmware_version: pointer to the PHY Firmware Version
806 807 **/
807 808 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
808 809 u16 *firmware_version)
809 810 {
810 811 s32 status = IXGBE_SUCCESS;
811 812
812 813 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
813 814
814 815 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
815 816 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
816 817 firmware_version);
817 818
818 819 return status;
819 820 }
820 821
821 822 /**
822 823 * ixgbe_reset_phy_nl - Performs a PHY reset
823 824 * @hw: pointer to hardware structure
824 825 **/
825 826 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
826 827 {
827 828 u16 phy_offset, control, eword, edata, block_crc;
828 829 bool end_data = FALSE;
829 830 u16 list_offset, data_offset;
830 831 u16 phy_data = 0;
831 832 s32 ret_val = IXGBE_SUCCESS;
832 833 u32 i;
833 834
834 835 DEBUGFUNC("ixgbe_reset_phy_nl");
835 836
836 837 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
837 838 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
838 839
839 840 /* reset the PHY and poll for completion */
840 841 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
841 842 IXGBE_MDIO_PHY_XS_DEV_TYPE,
842 843 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
843 844
844 845 for (i = 0; i < 100; i++) {
845 846 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
846 847 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
847 848 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
848 849 break;
849 850 msec_delay(10);
850 851 }
851 852
852 853 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
853 854 DEBUGOUT("PHY reset did not complete.\n");
854 855 ret_val = IXGBE_ERR_PHY;
855 856 goto out;
856 857 }
857 858
858 859 /* Get init offsets */
859 860 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
860 861 &data_offset);
861 862 if (ret_val != IXGBE_SUCCESS)
862 863 goto out;
863 864
864 865 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
865 866 data_offset++;
866 867 while (!end_data) {
867 868 /*
868 869 * Read control word from PHY init contents offset
869 870 */
870 871 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
871 872 control = (eword & IXGBE_CONTROL_MASK_NL) >>
872 873 IXGBE_CONTROL_SHIFT_NL;
873 874 edata = eword & IXGBE_DATA_MASK_NL;
874 875 switch (control) {
875 876 case IXGBE_DELAY_NL:
876 877 data_offset++;
877 878 DEBUGOUT1("DELAY: %d MS\n", edata);
878 879 msec_delay(edata);
879 880 break;
880 881 case IXGBE_DATA_NL:
881 882 DEBUGOUT("DATA:\n");
882 883 data_offset++;
883 884 hw->eeprom.ops.read(hw, data_offset++,
884 885 &phy_offset);
885 886 for (i = 0; i < edata; i++) {
886 887 hw->eeprom.ops.read(hw, data_offset, &eword);
887 888 hw->phy.ops.write_reg(hw, phy_offset,
888 889 IXGBE_TWINAX_DEV, eword);
889 890 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
890 891 phy_offset);
891 892 data_offset++;
892 893 phy_offset++;
893 894 }
894 895 break;
895 896 case IXGBE_CONTROL_NL:
896 897 data_offset++;
897 898 DEBUGOUT("CONTROL:\n");
898 899 if (edata == IXGBE_CONTROL_EOL_NL) {
899 900 DEBUGOUT("EOL\n");
900 901 end_data = TRUE;
901 902 } else if (edata == IXGBE_CONTROL_SOL_NL) {
902 903 DEBUGOUT("SOL\n");
903 904 } else {
904 905 DEBUGOUT("Bad control value\n");
905 906 ret_val = IXGBE_ERR_PHY;
906 907 goto out;
907 908 }
908 909 break;
909 910 default:
910 911 DEBUGOUT("Bad control type\n");
911 912 ret_val = IXGBE_ERR_PHY;
912 913 goto out;
913 914 }
914 915 }
915 916
916 917 out:
917 918 return ret_val;
918 919 }
919 920
920 921 /**
921 922 * ixgbe_identify_module_generic - Identifies module type
922 923 * @hw: pointer to hardware structure
923 924 *
924 925 * Determines HW type and calls appropriate function.
925 926 **/
926 927 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
927 928 {
928 929 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
929 930
930 931 DEBUGFUNC("ixgbe_identify_module_generic");
931 932
932 933 switch (hw->mac.ops.get_media_type(hw)) {
933 934 case ixgbe_media_type_fiber:
934 935 status = ixgbe_identify_sfp_module_generic(hw);
935 936 break;
936 937
937 938
938 939 default:
939 940 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
940 941 status = IXGBE_ERR_SFP_NOT_PRESENT;
941 942 break;
942 943 }
943 944
944 945 return status;
945 946 }
946 947
947 948 /**
948 949 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
949 950 * @hw: pointer to hardware structure
950 951 *
951 952 * Searches for and identifies the SFP module and assigns appropriate PHY type.
952 953 **/
953 954 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
954 955 {
955 956 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
956 957 u32 vendor_oui = 0;
957 958 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
958 959 u8 identifier = 0;
959 960 u8 comp_codes_1g = 0;
960 961 u8 comp_codes_10g = 0;
961 962 u8 oui_bytes[3] = {0, 0, 0};
962 963 u8 cable_tech = 0;
963 964 u8 cable_spec = 0;
964 965 u16 enforce_sfp = 0;
965 966
966 967 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
967 968
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968 969 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
969 970 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
970 971 status = IXGBE_ERR_SFP_NOT_PRESENT;
971 972 goto out;
972 973 }
973 974
974 975 status = hw->phy.ops.read_i2c_eeprom(hw,
975 976 IXGBE_SFF_IDENTIFIER,
976 977 &identifier);
977 978
978 - if (status == IXGBE_ERR_SWFW_SYNC ||
979 - status == IXGBE_ERR_I2C ||
980 - status == IXGBE_ERR_SFP_NOT_PRESENT)
979 + if (status != IXGBE_SUCCESS)
981 980 goto err_read_i2c_eeprom;
982 981
983 982 /* LAN ID is needed for sfp_type determination */
984 983 hw->mac.ops.set_lan_id(hw);
985 984
986 985 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
987 986 hw->phy.type = ixgbe_phy_sfp_unsupported;
988 987 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
989 988 } else {
990 989 status = hw->phy.ops.read_i2c_eeprom(hw,
991 990 IXGBE_SFF_1GBE_COMP_CODES,
992 991 &comp_codes_1g);
993 992
994 - if (status == IXGBE_ERR_SWFW_SYNC ||
995 - status == IXGBE_ERR_I2C ||
996 - status == IXGBE_ERR_SFP_NOT_PRESENT)
993 + if (status != IXGBE_SUCCESS)
997 994 goto err_read_i2c_eeprom;
998 995
999 996 status = hw->phy.ops.read_i2c_eeprom(hw,
1000 997 IXGBE_SFF_10GBE_COMP_CODES,
1001 998 &comp_codes_10g);
1002 999
1003 - if (status == IXGBE_ERR_SWFW_SYNC ||
1004 - status == IXGBE_ERR_I2C ||
1005 - status == IXGBE_ERR_SFP_NOT_PRESENT)
1000 + if (status != IXGBE_SUCCESS)
1006 1001 goto err_read_i2c_eeprom;
1007 1002 status = hw->phy.ops.read_i2c_eeprom(hw,
1008 1003 IXGBE_SFF_CABLE_TECHNOLOGY,
1009 1004 &cable_tech);
1010 1005
1011 - if (status == IXGBE_ERR_SWFW_SYNC ||
1012 - status == IXGBE_ERR_I2C ||
1013 - status == IXGBE_ERR_SFP_NOT_PRESENT)
1006 + if (status != IXGBE_SUCCESS)
1014 1007 goto err_read_i2c_eeprom;
1015 1008
1016 1009 /* ID Module
1017 1010 * =========
1018 1011 * 0 SFP_DA_CU
1019 1012 * 1 SFP_SR
1020 1013 * 2 SFP_LR
1021 1014 * 3 SFP_DA_CORE0 - 82599-specific
1022 1015 * 4 SFP_DA_CORE1 - 82599-specific
1023 1016 * 5 SFP_SR/LR_CORE0 - 82599-specific
1024 1017 * 6 SFP_SR/LR_CORE1 - 82599-specific
1025 1018 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1026 1019 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1027 1020 * 9 SFP_1g_cu_CORE0 - 82599-specific
1028 1021 * 10 SFP_1g_cu_CORE1 - 82599-specific
1029 1022 * 11 SFP_1g_sx_CORE0 - 82599-specific
1030 1023 * 12 SFP_1g_sx_CORE1 - 82599-specific
1031 1024 */
1032 1025 if (hw->mac.type == ixgbe_mac_82598EB) {
1033 1026 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1034 1027 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1035 1028 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1036 1029 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1037 1030 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1038 1031 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1039 1032 else
1040 1033 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1041 1034 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1042 1035 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1043 1036 if (hw->bus.lan_id == 0)
1044 1037 hw->phy.sfp_type =
1045 1038 ixgbe_sfp_type_da_cu_core0;
1046 1039 else
1047 1040 hw->phy.sfp_type =
1048 1041 ixgbe_sfp_type_da_cu_core1;
1049 1042 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1050 1043 hw->phy.ops.read_i2c_eeprom(
1051 1044 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1052 1045 &cable_spec);
1053 1046 if (cable_spec &
1054 1047 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1055 1048 if (hw->bus.lan_id == 0)
1056 1049 hw->phy.sfp_type =
1057 1050 ixgbe_sfp_type_da_act_lmt_core0;
1058 1051 else
1059 1052 hw->phy.sfp_type =
1060 1053 ixgbe_sfp_type_da_act_lmt_core1;
1061 1054 } else {
1062 1055 hw->phy.sfp_type =
1063 1056 ixgbe_sfp_type_unknown;
1064 1057 }
1065 1058 } else if (comp_codes_10g &
1066 1059 (IXGBE_SFF_10GBASESR_CAPABLE |
1067 1060 IXGBE_SFF_10GBASELR_CAPABLE)) {
1068 1061 if (hw->bus.lan_id == 0)
1069 1062 hw->phy.sfp_type =
1070 1063 ixgbe_sfp_type_srlr_core0;
1071 1064 else
1072 1065 hw->phy.sfp_type =
1073 1066 ixgbe_sfp_type_srlr_core1;
1074 1067 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1075 1068 if (hw->bus.lan_id == 0)
1076 1069 hw->phy.sfp_type =
1077 1070 ixgbe_sfp_type_1g_cu_core0;
1078 1071 else
1079 1072 hw->phy.sfp_type =
1080 1073 ixgbe_sfp_type_1g_cu_core1;
1081 1074 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1082 1075 if (hw->bus.lan_id == 0)
1083 1076 hw->phy.sfp_type =
1084 1077 ixgbe_sfp_type_1g_sx_core0;
1085 1078 else
1086 1079 hw->phy.sfp_type =
1087 1080 ixgbe_sfp_type_1g_sx_core1;
1088 1081 } else {
1089 1082 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1090 1083 }
1091 1084 }
1092 1085
1093 1086 if (hw->phy.sfp_type != stored_sfp_type)
1094 1087 hw->phy.sfp_setup_needed = TRUE;
1095 1088
1096 1089 /* Determine if the SFP+ PHY is dual speed or not. */
1097 1090 hw->phy.multispeed_fiber = FALSE;
1098 1091 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1099 1092 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1100 1093 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
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1101 1094 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1102 1095 hw->phy.multispeed_fiber = TRUE;
1103 1096
1104 1097 /* Determine PHY vendor */
1105 1098 if (hw->phy.type != ixgbe_phy_nl) {
1106 1099 hw->phy.id = identifier;
1107 1100 status = hw->phy.ops.read_i2c_eeprom(hw,
1108 1101 IXGBE_SFF_VENDOR_OUI_BYTE0,
1109 1102 &oui_bytes[0]);
1110 1103
1111 - if (status == IXGBE_ERR_SWFW_SYNC ||
1112 - status == IXGBE_ERR_I2C ||
1113 - status == IXGBE_ERR_SFP_NOT_PRESENT)
1104 + if (status != IXGBE_SUCCESS)
1114 1105 goto err_read_i2c_eeprom;
1115 1106
1116 1107 status = hw->phy.ops.read_i2c_eeprom(hw,
1117 1108 IXGBE_SFF_VENDOR_OUI_BYTE1,
1118 1109 &oui_bytes[1]);
1119 1110
1120 - if (status == IXGBE_ERR_SWFW_SYNC ||
1121 - status == IXGBE_ERR_I2C ||
1122 - status == IXGBE_ERR_SFP_NOT_PRESENT)
1111 + if (status != IXGBE_SUCCESS)
1123 1112 goto err_read_i2c_eeprom;
1124 1113
1125 1114 status = hw->phy.ops.read_i2c_eeprom(hw,
1126 1115 IXGBE_SFF_VENDOR_OUI_BYTE2,
1127 1116 &oui_bytes[2]);
1128 1117
1129 - if (status == IXGBE_ERR_SWFW_SYNC ||
1130 - status == IXGBE_ERR_I2C ||
1131 - status == IXGBE_ERR_SFP_NOT_PRESENT)
1118 + if (status != IXGBE_SUCCESS)
1132 1119 goto err_read_i2c_eeprom;
1133 1120
1134 1121 vendor_oui =
1135 1122 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1136 1123 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1137 1124 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1138 1125
1139 1126 switch (vendor_oui) {
1140 1127 case IXGBE_SFF_VENDOR_OUI_TYCO:
1141 1128 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1142 1129 hw->phy.type =
1143 1130 ixgbe_phy_sfp_passive_tyco;
1144 1131 break;
1145 1132 case IXGBE_SFF_VENDOR_OUI_FTL:
1146 1133 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1147 1134 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1148 1135 else
1149 1136 hw->phy.type = ixgbe_phy_sfp_ftl;
1150 1137 break;
1151 1138 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1152 1139 hw->phy.type = ixgbe_phy_sfp_avago;
1153 1140 break;
1154 1141 case IXGBE_SFF_VENDOR_OUI_INTEL:
1155 1142 hw->phy.type = ixgbe_phy_sfp_intel;
1156 1143 break;
1157 1144 default:
1158 1145 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1159 1146 hw->phy.type =
1160 1147 ixgbe_phy_sfp_passive_unknown;
1161 1148 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1162 1149 hw->phy.type =
1163 1150 ixgbe_phy_sfp_active_unknown;
1164 1151 else
1165 1152 hw->phy.type = ixgbe_phy_sfp_unknown;
1166 1153 break;
1167 1154 }
1168 1155 }
1169 1156
1170 1157 /* Allow any DA cable vendor */
1171 1158 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1172 1159 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1173 1160 status = IXGBE_SUCCESS;
1174 1161 goto out;
1175 1162 }
1176 1163
1177 1164 /* Verify supported 1G SFP modules */
1178 1165 if (comp_codes_10g == 0 &&
1179 1166 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1180 1167 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1181 1168 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1182 1169 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1183 1170 hw->phy.type = ixgbe_phy_sfp_unsupported;
1184 1171 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1185 1172 goto out;
1186 1173 }
1187 1174
1188 1175 /* Anything else 82598-based is supported */
1189 1176 if (hw->mac.type == ixgbe_mac_82598EB) {
1190 1177 status = IXGBE_SUCCESS;
1191 1178 goto out;
1192 1179 }
1193 1180
1194 1181 (void) ixgbe_get_device_caps(hw, &enforce_sfp);
1195 1182 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1196 1183 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1197 1184 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1198 1185 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
1199 1186 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1200 1187 /* Make sure we're a supported PHY type */
1201 1188 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1202 1189 status = IXGBE_SUCCESS;
1203 1190 } else {
1204 1191 if (hw->allow_unsupported_sfp == TRUE) {
1205 1192 EWARN(hw, "WARNING: Intel (R) Network "
1206 1193 "Connections are quality tested "
1207 1194 "using Intel (R) Ethernet Optics."
1208 1195 " Using untested modules is not "
1209 1196 "supported and may cause unstable"
1210 1197 " operation or damage to the "
1211 1198 "module or the adapter. Intel "
1212 1199 "Corporation is not responsible "
1213 1200 "for any harm caused by using "
1214 1201 "untested modules.\n", status);
1215 1202 status = IXGBE_SUCCESS;
1216 1203 } else {
1217 1204 EWARN(hw, "SFP+ module not supported\n",
1218 1205 status);
1219 1206 hw->phy.type =
1220 1207 ixgbe_phy_sfp_unsupported;
1221 1208 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1222 1209 }
1223 1210 }
1224 1211 } else {
1225 1212 status = IXGBE_SUCCESS;
1226 1213 }
1227 1214 }
1228 1215
1229 1216 out:
1230 1217 return status;
1231 1218
1232 1219 err_read_i2c_eeprom:
1233 1220 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1234 1221 if (hw->phy.type != ixgbe_phy_nl) {
1235 1222 hw->phy.id = 0;
1236 1223 hw->phy.type = ixgbe_phy_unknown;
1237 1224 }
1238 1225 return IXGBE_ERR_SFP_NOT_PRESENT;
1239 1226 }
1240 1227
1241 1228
1242 1229
1243 1230 /**
1244 1231 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1245 1232 * @hw: pointer to hardware structure
1246 1233 * @list_offset: offset to the SFP ID list
1247 1234 * @data_offset: offset to the SFP data block
1248 1235 *
1249 1236 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1250 1237 * so it returns the offsets to the phy init sequence block.
1251 1238 **/
1252 1239 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1253 1240 u16 *list_offset,
1254 1241 u16 *data_offset)
1255 1242 {
1256 1243 u16 sfp_id;
1257 1244 u16 sfp_type = hw->phy.sfp_type;
1258 1245
1259 1246 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1260 1247
1261 1248 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1262 1249 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1263 1250
1264 1251 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1265 1252 return IXGBE_ERR_SFP_NOT_PRESENT;
1266 1253
1267 1254 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1268 1255 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1269 1256 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1270 1257
1271 1258 /*
1272 1259 * Limiting active cables and 1G Phys must be initialized as
1273 1260 * SR modules
1274 1261 */
1275 1262 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1276 1263 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1277 1264 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1278 1265 sfp_type = ixgbe_sfp_type_srlr_core0;
1279 1266 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1280 1267 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1281 1268 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1282 1269 sfp_type = ixgbe_sfp_type_srlr_core1;
1283 1270
1284 1271 /* Read offset to PHY init contents */
1285 1272 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1286 1273
1287 1274 if ((!*list_offset) || (*list_offset == 0xFFFF))
1288 1275 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1289 1276
1290 1277 /* Shift offset to first ID word */
1291 1278 (*list_offset)++;
1292 1279
1293 1280 /*
1294 1281 * Find the matching SFP ID in the EEPROM
1295 1282 * and program the init sequence
1296 1283 */
1297 1284 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1298 1285
1299 1286 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1300 1287 if (sfp_id == sfp_type) {
1301 1288 (*list_offset)++;
1302 1289 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1303 1290 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1304 1291 DEBUGOUT("SFP+ module not supported\n");
1305 1292 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1306 1293 } else {
1307 1294 break;
1308 1295 }
1309 1296 } else {
1310 1297 (*list_offset) += 2;
1311 1298 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1312 1299 return IXGBE_ERR_PHY;
1313 1300 }
1314 1301 }
1315 1302
1316 1303 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1317 1304 DEBUGOUT("No matching SFP+ module found\n");
1318 1305 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1319 1306 }
1320 1307
1321 1308 return IXGBE_SUCCESS;
1322 1309 }
1323 1310
1324 1311 /**
1325 1312 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1326 1313 * @hw: pointer to hardware structure
1327 1314 * @byte_offset: EEPROM byte offset to read
1328 1315 * @eeprom_data: value read
1329 1316 *
1330 1317 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1331 1318 **/
1332 1319 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
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1333 1320 u8 *eeprom_data)
1334 1321 {
1335 1322 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1336 1323
1337 1324 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1338 1325 IXGBE_I2C_EEPROM_DEV_ADDR,
1339 1326 eeprom_data);
1340 1327 }
1341 1328
1342 1329 /**
1330 + * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1331 + * @hw: pointer to hardware structure
1332 + * @byte_offset: byte offset at address 0xA2
1333 + * @eeprom_data: value read
1334 + *
1335 + * Performs byte read operation to SFP module's SFF-8472 data over I2C
1336 + **/
1337 +static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1338 + u8 *sff8472_data)
1339 +{
1340 + return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1341 + IXGBE_I2C_EEPROM_DEV_ADDR2,
1342 + sff8472_data);
1343 +}
1344 +
1345 +/**
1343 1346 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1344 1347 * @hw: pointer to hardware structure
1345 1348 * @byte_offset: EEPROM byte offset to write
1346 1349 * @eeprom_data: value to write
1347 1350 *
1348 1351 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1349 1352 **/
1350 1353 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1351 1354 u8 eeprom_data)
1352 1355 {
1353 1356 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1354 1357
1355 1358 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1356 1359 IXGBE_I2C_EEPROM_DEV_ADDR,
1357 1360 eeprom_data);
1358 1361 }
1359 1362
1360 1363 /**
1361 1364 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1362 1365 * @hw: pointer to hardware structure
1363 1366 * @byte_offset: byte offset to read
1364 1367 * @data: value read
1365 1368 *
1366 1369 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1367 1370 * a specified device address.
1368 1371 **/
1369 1372 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1370 1373 u8 dev_addr, u8 *data)
1371 1374 {
1372 1375 s32 status = IXGBE_SUCCESS;
1373 1376 u32 max_retry = 10;
1374 1377 u32 retry = 0;
1375 1378 u16 swfw_mask = 0;
1376 1379 bool nack = 1;
1377 1380 *data = 0;
1378 1381
1379 1382 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1380 1383
1381 1384 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1382 1385 swfw_mask = IXGBE_GSSR_PHY1_SM;
1383 1386 else
1384 1387 swfw_mask = IXGBE_GSSR_PHY0_SM;
1385 1388
1386 1389 do {
1387 1390 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1388 1391 != IXGBE_SUCCESS) {
1389 1392 status = IXGBE_ERR_SWFW_SYNC;
1390 1393 goto read_byte_out;
1391 1394 }
1392 1395
1393 1396 ixgbe_i2c_start(hw);
1394 1397
1395 1398 /* Device Address and write indication */
1396 1399 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1397 1400 if (status != IXGBE_SUCCESS)
1398 1401 goto fail;
1399 1402
1400 1403 status = ixgbe_get_i2c_ack(hw);
1401 1404 if (status != IXGBE_SUCCESS)
1402 1405 goto fail;
1403 1406
1404 1407 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1405 1408 if (status != IXGBE_SUCCESS)
1406 1409 goto fail;
1407 1410
1408 1411 status = ixgbe_get_i2c_ack(hw);
1409 1412 if (status != IXGBE_SUCCESS)
1410 1413 goto fail;
1411 1414
1412 1415 ixgbe_i2c_start(hw);
1413 1416
1414 1417 /* Device Address and read indication */
1415 1418 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1416 1419 if (status != IXGBE_SUCCESS)
1417 1420 goto fail;
1418 1421
1419 1422 status = ixgbe_get_i2c_ack(hw);
1420 1423 if (status != IXGBE_SUCCESS)
1421 1424 goto fail;
1422 1425
1423 1426 status = ixgbe_clock_in_i2c_byte(hw, data);
1424 1427 if (status != IXGBE_SUCCESS)
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1425 1428 goto fail;
1426 1429
1427 1430 status = ixgbe_clock_out_i2c_bit(hw, nack);
1428 1431 if (status != IXGBE_SUCCESS)
1429 1432 goto fail;
1430 1433
1431 1434 ixgbe_i2c_stop(hw);
1432 1435 break;
1433 1436
1434 1437 fail:
1438 + ixgbe_i2c_bus_clear(hw);
1435 1439 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1436 1440 msec_delay(100);
1437 - ixgbe_i2c_bus_clear(hw);
1438 1441 retry++;
1439 1442 if (retry < max_retry)
1440 1443 DEBUGOUT("I2C byte read error - Retrying.\n");
1441 1444 else
1442 1445 DEBUGOUT("I2C byte read error.\n");
1443 1446
1444 1447 } while (retry < max_retry);
1445 1448
1446 1449 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1447 1450
1448 1451 read_byte_out:
1449 1452 return status;
1450 1453 }
1451 1454
1452 1455 /**
1453 1456 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1454 1457 * @hw: pointer to hardware structure
1455 1458 * @byte_offset: byte offset to write
1456 1459 * @data: value to write
1457 1460 *
1458 1461 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1459 1462 * a specified device address.
1460 1463 **/
1461 1464 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1462 1465 u8 dev_addr, u8 data)
1463 1466 {
1464 1467 s32 status = IXGBE_SUCCESS;
1465 1468 u32 max_retry = 1;
1466 1469 u32 retry = 0;
1467 1470 u16 swfw_mask = 0;
1468 1471
1469 1472 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1470 1473
1471 1474 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1472 1475 swfw_mask = IXGBE_GSSR_PHY1_SM;
1473 1476 else
1474 1477 swfw_mask = IXGBE_GSSR_PHY0_SM;
1475 1478
1476 1479 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1477 1480 status = IXGBE_ERR_SWFW_SYNC;
1478 1481 goto write_byte_out;
1479 1482 }
1480 1483
1481 1484 do {
1482 1485 ixgbe_i2c_start(hw);
1483 1486
1484 1487 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1485 1488 if (status != IXGBE_SUCCESS)
1486 1489 goto fail;
1487 1490
1488 1491 status = ixgbe_get_i2c_ack(hw);
1489 1492 if (status != IXGBE_SUCCESS)
1490 1493 goto fail;
1491 1494
1492 1495 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1493 1496 if (status != IXGBE_SUCCESS)
1494 1497 goto fail;
1495 1498
1496 1499 status = ixgbe_get_i2c_ack(hw);
1497 1500 if (status != IXGBE_SUCCESS)
1498 1501 goto fail;
1499 1502
1500 1503 status = ixgbe_clock_out_i2c_byte(hw, data);
1501 1504 if (status != IXGBE_SUCCESS)
1502 1505 goto fail;
1503 1506
1504 1507 status = ixgbe_get_i2c_ack(hw);
1505 1508 if (status != IXGBE_SUCCESS)
1506 1509 goto fail;
1507 1510
1508 1511 ixgbe_i2c_stop(hw);
1509 1512 break;
1510 1513
1511 1514 fail:
1512 1515 ixgbe_i2c_bus_clear(hw);
1513 1516 retry++;
1514 1517 if (retry < max_retry)
1515 1518 DEBUGOUT("I2C byte write error - Retrying.\n");
1516 1519 else
1517 1520 DEBUGOUT("I2C byte write error.\n");
1518 1521 } while (retry < max_retry);
1519 1522
1520 1523 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1521 1524
1522 1525 write_byte_out:
1523 1526 return status;
1524 1527 }
1525 1528
1526 1529 /**
1527 1530 * ixgbe_i2c_start - Sets I2C start condition
1528 1531 * @hw: pointer to hardware structure
1529 1532 *
1530 1533 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1531 1534 **/
1532 1535 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1533 1536 {
1534 1537 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1535 1538
1536 1539 DEBUGFUNC("ixgbe_i2c_start");
1537 1540
1538 1541 /* Start condition must begin with data and clock high */
1539 1542 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1540 1543 ixgbe_raise_i2c_clk(hw, &i2cctl);
1541 1544
1542 1545 /* Setup time for start condition (4.7us) */
1543 1546 usec_delay(IXGBE_I2C_T_SU_STA);
1544 1547
1545 1548 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1546 1549
1547 1550 /* Hold time for start condition (4us) */
1548 1551 usec_delay(IXGBE_I2C_T_HD_STA);
1549 1552
1550 1553 ixgbe_lower_i2c_clk(hw, &i2cctl);
1551 1554
1552 1555 /* Minimum low period of clock is 4.7 us */
1553 1556 usec_delay(IXGBE_I2C_T_LOW);
1554 1557
1555 1558 }
1556 1559
1557 1560 /**
1558 1561 * ixgbe_i2c_stop - Sets I2C stop condition
1559 1562 * @hw: pointer to hardware structure
1560 1563 *
1561 1564 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1562 1565 **/
1563 1566 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1564 1567 {
1565 1568 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1566 1569
1567 1570 DEBUGFUNC("ixgbe_i2c_stop");
1568 1571
1569 1572 /* Stop condition must begin with data low and clock high */
1570 1573 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1571 1574 ixgbe_raise_i2c_clk(hw, &i2cctl);
1572 1575
1573 1576 /* Setup time for stop condition (4us) */
1574 1577 usec_delay(IXGBE_I2C_T_SU_STO);
1575 1578
1576 1579 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1577 1580
1578 1581 /* bus free time between stop and start (4.7us)*/
1579 1582 usec_delay(IXGBE_I2C_T_BUF);
1580 1583 }
1581 1584
1582 1585 /**
1583 1586 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1584 1587 * @hw: pointer to hardware structure
1585 1588 * @data: data byte to clock in
1586 1589 *
1587 1590 * Clocks in one byte data via I2C data/clock
1588 1591 **/
1589 1592 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1590 1593 {
1591 1594 s32 i, status = IXGBE_SUCCESS;
1592 1595 bool bit = 0;
1593 1596
1594 1597 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1595 1598
1596 1599 for (i = 7; i >= 0; i--) {
1597 1600 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1598 1601 if (status != IXGBE_SUCCESS)
1599 1602 break;
1600 1603 *data |= bit << i;
1601 1604 }
1602 1605
1603 1606 return status;
1604 1607 }
1605 1608
1606 1609 /**
1607 1610 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1608 1611 * @hw: pointer to hardware structure
1609 1612 * @data: data byte clocked out
1610 1613 *
1611 1614 * Clocks out one byte data via I2C data/clock
1612 1615 **/
1613 1616 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1614 1617 {
1615 1618 s32 status = IXGBE_SUCCESS;
1616 1619 s32 i;
1617 1620 u32 i2cctl;
1618 1621 bool bit = 0;
1619 1622
1620 1623 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1621 1624
1622 1625 for (i = 7; i >= 0; i--) {
1623 1626 bit = (data >> i) & 0x1;
1624 1627 status = ixgbe_clock_out_i2c_bit(hw, bit);
1625 1628
1626 1629 if (status != IXGBE_SUCCESS)
1627 1630 break;
1628 1631 }
1629 1632
1630 1633 /* Release SDA line (set high) */
1631 1634 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1632 1635 i2cctl |= IXGBE_I2C_DATA_OUT;
1633 1636 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1634 1637 IXGBE_WRITE_FLUSH(hw);
1635 1638
1636 1639 return status;
1637 1640 }
1638 1641
1639 1642 /**
1640 1643 * ixgbe_get_i2c_ack - Polls for I2C ACK
1641 1644 * @hw: pointer to hardware structure
1642 1645 *
1643 1646 * Clocks in/out one bit via I2C data/clock
1644 1647 **/
1645 1648 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1646 1649 {
1647 1650 s32 status = IXGBE_SUCCESS;
1648 1651 u32 i = 0;
1649 1652 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1650 1653 u32 timeout = 10;
1651 1654 bool ack = 1;
1652 1655
1653 1656 DEBUGFUNC("ixgbe_get_i2c_ack");
1654 1657
1655 1658 ixgbe_raise_i2c_clk(hw, &i2cctl);
1656 1659
1657 1660
1658 1661 /* Minimum high period of clock is 4us */
1659 1662 usec_delay(IXGBE_I2C_T_HIGH);
1660 1663
1661 1664 /* Poll for ACK. Note that ACK in I2C spec is
1662 1665 * transition from 1 to 0 */
1663 1666 for (i = 0; i < timeout; i++) {
1664 1667 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1665 1668 ack = ixgbe_get_i2c_data(&i2cctl);
1666 1669
1667 1670 usec_delay(1);
1668 1671 if (ack == 0)
1669 1672 break;
1670 1673 }
1671 1674
1672 1675 if (ack == 1) {
1673 1676 DEBUGOUT("I2C ack was not received.\n");
1674 1677 status = IXGBE_ERR_I2C;
1675 1678 }
1676 1679
1677 1680 ixgbe_lower_i2c_clk(hw, &i2cctl);
1678 1681
1679 1682 /* Minimum low period of clock is 4.7 us */
1680 1683 usec_delay(IXGBE_I2C_T_LOW);
1681 1684
1682 1685 return status;
1683 1686 }
1684 1687
1685 1688 /**
1686 1689 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1687 1690 * @hw: pointer to hardware structure
1688 1691 * @data: read data value
1689 1692 *
1690 1693 * Clocks in one bit via I2C data/clock
1691 1694 **/
1692 1695 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1693 1696 {
1694 1697 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1695 1698
1696 1699 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1697 1700
1698 1701 ixgbe_raise_i2c_clk(hw, &i2cctl);
1699 1702
1700 1703 /* Minimum high period of clock is 4us */
1701 1704 usec_delay(IXGBE_I2C_T_HIGH);
1702 1705
1703 1706 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1704 1707 *data = ixgbe_get_i2c_data(&i2cctl);
1705 1708
1706 1709 ixgbe_lower_i2c_clk(hw, &i2cctl);
1707 1710
1708 1711 /* Minimum low period of clock is 4.7 us */
1709 1712 usec_delay(IXGBE_I2C_T_LOW);
1710 1713
1711 1714 return IXGBE_SUCCESS;
1712 1715 }
1713 1716
1714 1717 /**
1715 1718 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1716 1719 * @hw: pointer to hardware structure
1717 1720 * @data: data value to write
1718 1721 *
1719 1722 * Clocks out one bit via I2C data/clock
1720 1723 **/
1721 1724 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1722 1725 {
1723 1726 s32 status;
1724 1727 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1725 1728
1726 1729 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1727 1730
1728 1731 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1729 1732 if (status == IXGBE_SUCCESS) {
1730 1733 ixgbe_raise_i2c_clk(hw, &i2cctl);
1731 1734
1732 1735 /* Minimum high period of clock is 4us */
1733 1736 usec_delay(IXGBE_I2C_T_HIGH);
1734 1737
1735 1738 ixgbe_lower_i2c_clk(hw, &i2cctl);
1736 1739
1737 1740 /* Minimum low period of clock is 4.7 us.
1738 1741 * This also takes care of the data hold time.
1739 1742 */
1740 1743 usec_delay(IXGBE_I2C_T_LOW);
1741 1744 } else {
1742 1745 status = IXGBE_ERR_I2C;
1743 1746 DEBUGOUT1("I2C data was not set to %X\n", data);
1744 1747 }
1745 1748
1746 1749 return status;
1747 1750 }
1748 1751 /**
1749 1752 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1750 1753 * @hw: pointer to hardware structure
1751 1754 * @i2cctl: Current value of I2CCTL register
1752 1755 *
1753 1756 * Raises the I2C clock line '0'->'1'
1754 1757 **/
1755 1758 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1756 1759 {
1757 1760 u32 i = 0;
1758 1761 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1759 1762 u32 i2cctl_r = 0;
1760 1763
1761 1764 DEBUGFUNC("ixgbe_raise_i2c_clk");
1762 1765
1763 1766 for (i = 0; i < timeout; i++) {
1764 1767 *i2cctl |= IXGBE_I2C_CLK_OUT;
1765 1768
1766 1769 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1767 1770 IXGBE_WRITE_FLUSH(hw);
1768 1771 /* SCL rise time (1000ns) */
1769 1772 usec_delay(IXGBE_I2C_T_RISE);
1770 1773
1771 1774 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1772 1775 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1773 1776 break;
1774 1777 }
1775 1778 }
1776 1779
1777 1780 /**
1778 1781 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1779 1782 * @hw: pointer to hardware structure
1780 1783 * @i2cctl: Current value of I2CCTL register
1781 1784 *
1782 1785 * Lowers the I2C clock line '1'->'0'
1783 1786 **/
1784 1787 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1785 1788 {
1786 1789
1787 1790 DEBUGFUNC("ixgbe_lower_i2c_clk");
1788 1791
1789 1792 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1790 1793
1791 1794 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1792 1795 IXGBE_WRITE_FLUSH(hw);
1793 1796
1794 1797 /* SCL fall time (300ns) */
1795 1798 usec_delay(IXGBE_I2C_T_FALL);
1796 1799 }
1797 1800
1798 1801 /**
1799 1802 * ixgbe_set_i2c_data - Sets the I2C data bit
1800 1803 * @hw: pointer to hardware structure
1801 1804 * @i2cctl: Current value of I2CCTL register
1802 1805 * @data: I2C data value (0 or 1) to set
1803 1806 *
1804 1807 * Sets the I2C data bit
1805 1808 **/
1806 1809 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1807 1810 {
1808 1811 s32 status = IXGBE_SUCCESS;
1809 1812
1810 1813 DEBUGFUNC("ixgbe_set_i2c_data");
1811 1814
1812 1815 if (data)
1813 1816 *i2cctl |= IXGBE_I2C_DATA_OUT;
1814 1817 else
1815 1818 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1816 1819
1817 1820 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1818 1821 IXGBE_WRITE_FLUSH(hw);
1819 1822
1820 1823 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1821 1824 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1822 1825
1823 1826 /* Verify data was set correctly */
1824 1827 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1825 1828 if (data != ixgbe_get_i2c_data(i2cctl)) {
1826 1829 status = IXGBE_ERR_I2C;
1827 1830 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1828 1831 }
1829 1832
1830 1833 return status;
1831 1834 }
1832 1835
1833 1836 /**
1834 1837 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1835 1838 * @hw: pointer to hardware structure
1836 1839 * @i2cctl: Current value of I2CCTL register
1837 1840 *
1838 1841 * Returns the I2C data bit value
1839 1842 **/
1840 1843 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1841 1844 {
1842 1845 bool data;
1843 1846
1844 1847 DEBUGFUNC("ixgbe_get_i2c_data");
1845 1848
1846 1849 if (*i2cctl & IXGBE_I2C_DATA_IN)
1847 1850 data = 1;
1848 1851 else
1849 1852 data = 0;
1850 1853
1851 1854 return data;
1852 1855 }
1853 1856
1854 1857 /**
1855 1858 * ixgbe_i2c_bus_clear - Clears the I2C bus
1856 1859 * @hw: pointer to hardware structure
1857 1860 *
1858 1861 * Clears the I2C bus by sending nine clock pulses.
1859 1862 * Used when data line is stuck low.
1860 1863 **/
1861 1864 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1862 1865 {
1863 1866 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1864 1867 u32 i;
1865 1868
1866 1869 DEBUGFUNC("ixgbe_i2c_bus_clear");
1867 1870
1868 1871 ixgbe_i2c_start(hw);
1869 1872
1870 1873 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1871 1874
1872 1875 for (i = 0; i < 9; i++) {
1873 1876 ixgbe_raise_i2c_clk(hw, &i2cctl);
1874 1877
1875 1878 /* Min high period of clock is 4us */
1876 1879 usec_delay(IXGBE_I2C_T_HIGH);
1877 1880
1878 1881 ixgbe_lower_i2c_clk(hw, &i2cctl);
1879 1882
1880 1883 /* Min low period of clock is 4.7us*/
1881 1884 usec_delay(IXGBE_I2C_T_LOW);
1882 1885 }
1883 1886
1884 1887 ixgbe_i2c_start(hw);
1885 1888
1886 1889 /* Put the i2c bus back to default state */
1887 1890 ixgbe_i2c_stop(hw);
1888 1891 }
1889 1892
1890 1893 /**
1891 1894 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1892 1895 * @hw: pointer to hardware structure
1893 1896 *
1894 1897 * Checks if the LASI temp alarm status was triggered due to overtemp
1895 1898 **/
1896 1899 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1897 1900 {
1898 1901 s32 status = IXGBE_SUCCESS;
1899 1902 u16 phy_data = 0;
1900 1903
1901 1904 DEBUGFUNC("ixgbe_tn_check_overtemp");
1902 1905
1903 1906 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1904 1907 goto out;
1905 1908
1906 1909 /* Check that the LASI temp alarm status was triggered */
1907 1910 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1908 1911 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1909 1912
1910 1913 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1911 1914 goto out;
1912 1915
1913 1916 status = IXGBE_ERR_OVERTEMP;
1914 1917 out:
1915 1918 return status;
1916 1919 }
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