1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37 #include "ixgbe_phy.h"
38
39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
50
51 /**
52 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
53 * @hw: pointer to the hardware structure
54 *
55 * Initialize the function pointers.
56 **/
57 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
58 {
59 struct ixgbe_phy_info *phy = &hw->phy;
60
61 DEBUGFUNC("ixgbe_init_phy_ops_generic");
62
63 /* PHY */
64 phy->ops.identify = &ixgbe_identify_phy_generic;
65 phy->ops.reset = &ixgbe_reset_phy_generic;
66 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
67 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
68 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
69 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
70 phy->ops.check_link = NULL;
71 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
72 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
73 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
74 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
75 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
76 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
77 phy->ops.identify_sfp = &ixgbe_identify_module_generic;
78 phy->sfp_type = ixgbe_sfp_type_unknown;
79 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
80 return IXGBE_SUCCESS;
81 }
82
83 /**
84 * ixgbe_identify_phy_generic - Get physical layer module
85 * @hw: pointer to hardware structure
86 *
87 * Determines the physical layer module found on the current adapter.
88 **/
89 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
90 {
91 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
92 u32 phy_addr;
93 u16 ext_ability = 0;
549 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
550 &autoneg_reg);
551
552 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
553 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
554 break;
555 }
556
557 if (time_out == max_time_out) {
558 status = IXGBE_ERR_LINK_SETUP;
559 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
560 }
561
562 return status;
563 }
564
565 /**
566 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
567 * @hw: pointer to hardware structure
568 * @speed: new link speed
569 * @autoneg: TRUE if autonegotiation enabled
570 **/
571 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
572 ixgbe_link_speed speed,
573 bool autoneg,
574 bool autoneg_wait_to_complete)
575 {
576 UNREFERENCED_2PARAMETER(autoneg, autoneg_wait_to_complete);
577
578 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
579
580 /*
581 * Clear autoneg_advertised and set new values based on input link
582 * speed.
583 */
584 hw->phy.autoneg_advertised = 0;
585
586 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
587 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
588
589 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
590 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
591
592 if (speed & IXGBE_LINK_SPEED_100_FULL)
593 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
594
595 /* Setup link based on the new speed settings */
596 hw->phy.ops.setup_link(hw);
958 u8 identifier = 0;
959 u8 comp_codes_1g = 0;
960 u8 comp_codes_10g = 0;
961 u8 oui_bytes[3] = {0, 0, 0};
962 u8 cable_tech = 0;
963 u8 cable_spec = 0;
964 u16 enforce_sfp = 0;
965
966 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
967
968 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
969 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
970 status = IXGBE_ERR_SFP_NOT_PRESENT;
971 goto out;
972 }
973
974 status = hw->phy.ops.read_i2c_eeprom(hw,
975 IXGBE_SFF_IDENTIFIER,
976 &identifier);
977
978 if (status == IXGBE_ERR_SWFW_SYNC ||
979 status == IXGBE_ERR_I2C ||
980 status == IXGBE_ERR_SFP_NOT_PRESENT)
981 goto err_read_i2c_eeprom;
982
983 /* LAN ID is needed for sfp_type determination */
984 hw->mac.ops.set_lan_id(hw);
985
986 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
987 hw->phy.type = ixgbe_phy_sfp_unsupported;
988 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
989 } else {
990 status = hw->phy.ops.read_i2c_eeprom(hw,
991 IXGBE_SFF_1GBE_COMP_CODES,
992 &comp_codes_1g);
993
994 if (status == IXGBE_ERR_SWFW_SYNC ||
995 status == IXGBE_ERR_I2C ||
996 status == IXGBE_ERR_SFP_NOT_PRESENT)
997 goto err_read_i2c_eeprom;
998
999 status = hw->phy.ops.read_i2c_eeprom(hw,
1000 IXGBE_SFF_10GBE_COMP_CODES,
1001 &comp_codes_10g);
1002
1003 if (status == IXGBE_ERR_SWFW_SYNC ||
1004 status == IXGBE_ERR_I2C ||
1005 status == IXGBE_ERR_SFP_NOT_PRESENT)
1006 goto err_read_i2c_eeprom;
1007 status = hw->phy.ops.read_i2c_eeprom(hw,
1008 IXGBE_SFF_CABLE_TECHNOLOGY,
1009 &cable_tech);
1010
1011 if (status == IXGBE_ERR_SWFW_SYNC ||
1012 status == IXGBE_ERR_I2C ||
1013 status == IXGBE_ERR_SFP_NOT_PRESENT)
1014 goto err_read_i2c_eeprom;
1015
1016 /* ID Module
1017 * =========
1018 * 0 SFP_DA_CU
1019 * 1 SFP_SR
1020 * 2 SFP_LR
1021 * 3 SFP_DA_CORE0 - 82599-specific
1022 * 4 SFP_DA_CORE1 - 82599-specific
1023 * 5 SFP_SR/LR_CORE0 - 82599-specific
1024 * 6 SFP_SR/LR_CORE1 - 82599-specific
1025 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1026 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1027 * 9 SFP_1g_cu_CORE0 - 82599-specific
1028 * 10 SFP_1g_cu_CORE1 - 82599-specific
1029 * 11 SFP_1g_sx_CORE0 - 82599-specific
1030 * 12 SFP_1g_sx_CORE1 - 82599-specific
1031 */
1032 if (hw->mac.type == ixgbe_mac_82598EB) {
1033 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1091 }
1092
1093 if (hw->phy.sfp_type != stored_sfp_type)
1094 hw->phy.sfp_setup_needed = TRUE;
1095
1096 /* Determine if the SFP+ PHY is dual speed or not. */
1097 hw->phy.multispeed_fiber = FALSE;
1098 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1099 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1100 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1101 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1102 hw->phy.multispeed_fiber = TRUE;
1103
1104 /* Determine PHY vendor */
1105 if (hw->phy.type != ixgbe_phy_nl) {
1106 hw->phy.id = identifier;
1107 status = hw->phy.ops.read_i2c_eeprom(hw,
1108 IXGBE_SFF_VENDOR_OUI_BYTE0,
1109 &oui_bytes[0]);
1110
1111 if (status == IXGBE_ERR_SWFW_SYNC ||
1112 status == IXGBE_ERR_I2C ||
1113 status == IXGBE_ERR_SFP_NOT_PRESENT)
1114 goto err_read_i2c_eeprom;
1115
1116 status = hw->phy.ops.read_i2c_eeprom(hw,
1117 IXGBE_SFF_VENDOR_OUI_BYTE1,
1118 &oui_bytes[1]);
1119
1120 if (status == IXGBE_ERR_SWFW_SYNC ||
1121 status == IXGBE_ERR_I2C ||
1122 status == IXGBE_ERR_SFP_NOT_PRESENT)
1123 goto err_read_i2c_eeprom;
1124
1125 status = hw->phy.ops.read_i2c_eeprom(hw,
1126 IXGBE_SFF_VENDOR_OUI_BYTE2,
1127 &oui_bytes[2]);
1128
1129 if (status == IXGBE_ERR_SWFW_SYNC ||
1130 status == IXGBE_ERR_I2C ||
1131 status == IXGBE_ERR_SFP_NOT_PRESENT)
1132 goto err_read_i2c_eeprom;
1133
1134 vendor_oui =
1135 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1136 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1137 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1138
1139 switch (vendor_oui) {
1140 case IXGBE_SFF_VENDOR_OUI_TYCO:
1141 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1142 hw->phy.type =
1143 ixgbe_phy_sfp_passive_tyco;
1144 break;
1145 case IXGBE_SFF_VENDOR_OUI_FTL:
1146 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1147 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1148 else
1149 hw->phy.type = ixgbe_phy_sfp_ftl;
1150 break;
1151 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1323
1324 /**
1325 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1326 * @hw: pointer to hardware structure
1327 * @byte_offset: EEPROM byte offset to read
1328 * @eeprom_data: value read
1329 *
1330 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1331 **/
1332 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1333 u8 *eeprom_data)
1334 {
1335 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1336
1337 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1338 IXGBE_I2C_EEPROM_DEV_ADDR,
1339 eeprom_data);
1340 }
1341
1342 /**
1343 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1344 * @hw: pointer to hardware structure
1345 * @byte_offset: EEPROM byte offset to write
1346 * @eeprom_data: value to write
1347 *
1348 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1349 **/
1350 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1351 u8 eeprom_data)
1352 {
1353 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1354
1355 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1356 IXGBE_I2C_EEPROM_DEV_ADDR,
1357 eeprom_data);
1358 }
1359
1360 /**
1361 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1362 * @hw: pointer to hardware structure
1415 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1416 if (status != IXGBE_SUCCESS)
1417 goto fail;
1418
1419 status = ixgbe_get_i2c_ack(hw);
1420 if (status != IXGBE_SUCCESS)
1421 goto fail;
1422
1423 status = ixgbe_clock_in_i2c_byte(hw, data);
1424 if (status != IXGBE_SUCCESS)
1425 goto fail;
1426
1427 status = ixgbe_clock_out_i2c_bit(hw, nack);
1428 if (status != IXGBE_SUCCESS)
1429 goto fail;
1430
1431 ixgbe_i2c_stop(hw);
1432 break;
1433
1434 fail:
1435 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1436 msec_delay(100);
1437 ixgbe_i2c_bus_clear(hw);
1438 retry++;
1439 if (retry < max_retry)
1440 DEBUGOUT("I2C byte read error - Retrying.\n");
1441 else
1442 DEBUGOUT("I2C byte read error.\n");
1443
1444 } while (retry < max_retry);
1445
1446 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1447
1448 read_byte_out:
1449 return status;
1450 }
1451
1452 /**
1453 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1454 * @hw: pointer to hardware structure
1455 * @byte_offset: byte offset to write
1456 * @data: value to write
1457 *
|
1 /******************************************************************************
2
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37 #include "ixgbe_phy.h"
38
39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
51 u8 *sff8472_data);
52
53 /**
54 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
55 * @hw: pointer to the hardware structure
56 *
57 * Initialize the function pointers.
58 **/
59 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
60 {
61 struct ixgbe_phy_info *phy = &hw->phy;
62
63 DEBUGFUNC("ixgbe_init_phy_ops_generic");
64
65 /* PHY */
66 phy->ops.identify = &ixgbe_identify_phy_generic;
67 phy->ops.reset = &ixgbe_reset_phy_generic;
68 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
69 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
70 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
71 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
72 phy->ops.check_link = NULL;
73 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
74 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
75 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
76 phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
77 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
78 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
79 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
80 phy->ops.identify_sfp = &ixgbe_identify_module_generic;
81 phy->sfp_type = ixgbe_sfp_type_unknown;
82 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
83 return IXGBE_SUCCESS;
84 }
85
86 /**
87 * ixgbe_identify_phy_generic - Get physical layer module
88 * @hw: pointer to hardware structure
89 *
90 * Determines the physical layer module found on the current adapter.
91 **/
92 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
93 {
94 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
95 u32 phy_addr;
96 u16 ext_ability = 0;
552 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
553 &autoneg_reg);
554
555 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
556 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
557 break;
558 }
559
560 if (time_out == max_time_out) {
561 status = IXGBE_ERR_LINK_SETUP;
562 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
563 }
564
565 return status;
566 }
567
568 /**
569 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
570 * @hw: pointer to hardware structure
571 * @speed: new link speed
572 **/
573 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
574 ixgbe_link_speed speed,
575 bool autoneg_wait_to_complete)
576 {
577 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
578
579 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
580
581 /*
582 * Clear autoneg_advertised and set new values based on input link
583 * speed.
584 */
585 hw->phy.autoneg_advertised = 0;
586
587 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
588 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
589
590 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
591 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
592
593 if (speed & IXGBE_LINK_SPEED_100_FULL)
594 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
595
596 /* Setup link based on the new speed settings */
597 hw->phy.ops.setup_link(hw);
959 u8 identifier = 0;
960 u8 comp_codes_1g = 0;
961 u8 comp_codes_10g = 0;
962 u8 oui_bytes[3] = {0, 0, 0};
963 u8 cable_tech = 0;
964 u8 cable_spec = 0;
965 u16 enforce_sfp = 0;
966
967 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
968
969 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
970 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
971 status = IXGBE_ERR_SFP_NOT_PRESENT;
972 goto out;
973 }
974
975 status = hw->phy.ops.read_i2c_eeprom(hw,
976 IXGBE_SFF_IDENTIFIER,
977 &identifier);
978
979 if (status != IXGBE_SUCCESS)
980 goto err_read_i2c_eeprom;
981
982 /* LAN ID is needed for sfp_type determination */
983 hw->mac.ops.set_lan_id(hw);
984
985 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
986 hw->phy.type = ixgbe_phy_sfp_unsupported;
987 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
988 } else {
989 status = hw->phy.ops.read_i2c_eeprom(hw,
990 IXGBE_SFF_1GBE_COMP_CODES,
991 &comp_codes_1g);
992
993 if (status != IXGBE_SUCCESS)
994 goto err_read_i2c_eeprom;
995
996 status = hw->phy.ops.read_i2c_eeprom(hw,
997 IXGBE_SFF_10GBE_COMP_CODES,
998 &comp_codes_10g);
999
1000 if (status != IXGBE_SUCCESS)
1001 goto err_read_i2c_eeprom;
1002 status = hw->phy.ops.read_i2c_eeprom(hw,
1003 IXGBE_SFF_CABLE_TECHNOLOGY,
1004 &cable_tech);
1005
1006 if (status != IXGBE_SUCCESS)
1007 goto err_read_i2c_eeprom;
1008
1009 /* ID Module
1010 * =========
1011 * 0 SFP_DA_CU
1012 * 1 SFP_SR
1013 * 2 SFP_LR
1014 * 3 SFP_DA_CORE0 - 82599-specific
1015 * 4 SFP_DA_CORE1 - 82599-specific
1016 * 5 SFP_SR/LR_CORE0 - 82599-specific
1017 * 6 SFP_SR/LR_CORE1 - 82599-specific
1018 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1019 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1020 * 9 SFP_1g_cu_CORE0 - 82599-specific
1021 * 10 SFP_1g_cu_CORE1 - 82599-specific
1022 * 11 SFP_1g_sx_CORE0 - 82599-specific
1023 * 12 SFP_1g_sx_CORE1 - 82599-specific
1024 */
1025 if (hw->mac.type == ixgbe_mac_82598EB) {
1026 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1084 }
1085
1086 if (hw->phy.sfp_type != stored_sfp_type)
1087 hw->phy.sfp_setup_needed = TRUE;
1088
1089 /* Determine if the SFP+ PHY is dual speed or not. */
1090 hw->phy.multispeed_fiber = FALSE;
1091 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1092 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1093 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1094 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1095 hw->phy.multispeed_fiber = TRUE;
1096
1097 /* Determine PHY vendor */
1098 if (hw->phy.type != ixgbe_phy_nl) {
1099 hw->phy.id = identifier;
1100 status = hw->phy.ops.read_i2c_eeprom(hw,
1101 IXGBE_SFF_VENDOR_OUI_BYTE0,
1102 &oui_bytes[0]);
1103
1104 if (status != IXGBE_SUCCESS)
1105 goto err_read_i2c_eeprom;
1106
1107 status = hw->phy.ops.read_i2c_eeprom(hw,
1108 IXGBE_SFF_VENDOR_OUI_BYTE1,
1109 &oui_bytes[1]);
1110
1111 if (status != IXGBE_SUCCESS)
1112 goto err_read_i2c_eeprom;
1113
1114 status = hw->phy.ops.read_i2c_eeprom(hw,
1115 IXGBE_SFF_VENDOR_OUI_BYTE2,
1116 &oui_bytes[2]);
1117
1118 if (status != IXGBE_SUCCESS)
1119 goto err_read_i2c_eeprom;
1120
1121 vendor_oui =
1122 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1123 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1124 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1125
1126 switch (vendor_oui) {
1127 case IXGBE_SFF_VENDOR_OUI_TYCO:
1128 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1129 hw->phy.type =
1130 ixgbe_phy_sfp_passive_tyco;
1131 break;
1132 case IXGBE_SFF_VENDOR_OUI_FTL:
1133 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1134 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1135 else
1136 hw->phy.type = ixgbe_phy_sfp_ftl;
1137 break;
1138 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1310
1311 /**
1312 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1313 * @hw: pointer to hardware structure
1314 * @byte_offset: EEPROM byte offset to read
1315 * @eeprom_data: value read
1316 *
1317 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1318 **/
1319 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1320 u8 *eeprom_data)
1321 {
1322 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1323
1324 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1325 IXGBE_I2C_EEPROM_DEV_ADDR,
1326 eeprom_data);
1327 }
1328
1329 /**
1330 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1331 * @hw: pointer to hardware structure
1332 * @byte_offset: byte offset at address 0xA2
1333 * @eeprom_data: value read
1334 *
1335 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1336 **/
1337 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1338 u8 *sff8472_data)
1339 {
1340 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1341 IXGBE_I2C_EEPROM_DEV_ADDR2,
1342 sff8472_data);
1343 }
1344
1345 /**
1346 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1347 * @hw: pointer to hardware structure
1348 * @byte_offset: EEPROM byte offset to write
1349 * @eeprom_data: value to write
1350 *
1351 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1352 **/
1353 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1354 u8 eeprom_data)
1355 {
1356 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1357
1358 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1359 IXGBE_I2C_EEPROM_DEV_ADDR,
1360 eeprom_data);
1361 }
1362
1363 /**
1364 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1365 * @hw: pointer to hardware structure
1418 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1419 if (status != IXGBE_SUCCESS)
1420 goto fail;
1421
1422 status = ixgbe_get_i2c_ack(hw);
1423 if (status != IXGBE_SUCCESS)
1424 goto fail;
1425
1426 status = ixgbe_clock_in_i2c_byte(hw, data);
1427 if (status != IXGBE_SUCCESS)
1428 goto fail;
1429
1430 status = ixgbe_clock_out_i2c_bit(hw, nack);
1431 if (status != IXGBE_SUCCESS)
1432 goto fail;
1433
1434 ixgbe_i2c_stop(hw);
1435 break;
1436
1437 fail:
1438 ixgbe_i2c_bus_clear(hw);
1439 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1440 msec_delay(100);
1441 retry++;
1442 if (retry < max_retry)
1443 DEBUGOUT("I2C byte read error - Retrying.\n");
1444 else
1445 DEBUGOUT("I2C byte read error.\n");
1446
1447 } while (retry < max_retry);
1448
1449 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1450
1451 read_byte_out:
1452 return status;
1453 }
1454
1455 /**
1456 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1457 * @hw: pointer to hardware structure
1458 * @byte_offset: byte offset to write
1459 * @data: value to write
1460 *
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