1 /******************************************************************************
2
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
19
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_phy.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37 #include "ixgbe_phy.h"
38
39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
50 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
51 u8 *sff8472_data);
52
53 /**
54 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
55 * @hw: pointer to the hardware structure
56 *
57 * Initialize the function pointers.
58 **/
59 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
60 {
61 struct ixgbe_phy_info *phy = &hw->phy;
62
63 DEBUGFUNC("ixgbe_init_phy_ops_generic");
64
65 /* PHY */
66 phy->ops.identify = &ixgbe_identify_phy_generic;
67 phy->ops.reset = &ixgbe_reset_phy_generic;
68 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
69 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
70 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
71 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
72 phy->ops.check_link = NULL;
73 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
74 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
75 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
76 phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
77 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
78 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
79 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
80 phy->ops.identify_sfp = &ixgbe_identify_module_generic;
81 phy->sfp_type = ixgbe_sfp_type_unknown;
82 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
83 return IXGBE_SUCCESS;
84 }
85
86 /**
87 * ixgbe_identify_phy_generic - Get physical layer module
88 * @hw: pointer to hardware structure
89 *
90 * Determines the physical layer module found on the current adapter.
91 **/
92 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
93 {
94 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
95 u32 phy_addr;
96 u16 ext_ability = 0;
97
98 DEBUGFUNC("ixgbe_identify_phy_generic");
99
100 if (hw->phy.type == ixgbe_phy_unknown) {
101 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
102 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
103 hw->phy.addr = phy_addr;
104 (void) ixgbe_get_phy_id(hw);
105 hw->phy.type =
106 ixgbe_get_phy_type_from_id(hw->phy.id);
107
108 if (hw->phy.type == ixgbe_phy_unknown) {
109 hw->phy.ops.read_reg(hw,
110 IXGBE_MDIO_PHY_EXT_ABILITY,
111 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
112 &ext_ability);
113 if (ext_ability &
114 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
115 IXGBE_MDIO_PHY_1000BASET_ABILITY))
116 hw->phy.type =
117 ixgbe_phy_cu_unknown;
118 else
119 hw->phy.type =
120 ixgbe_phy_generic;
121 }
122
123 status = IXGBE_SUCCESS;
124 break;
125 }
126 }
127 /* clear value if nothing found */
128 if (status != IXGBE_SUCCESS)
129 hw->phy.addr = 0;
130 } else {
131 status = IXGBE_SUCCESS;
132 }
133
134 return status;
135 }
136
137 /**
138 * ixgbe_validate_phy_addr - Determines phy address is valid
139 * @hw: pointer to hardware structure
140 *
141 **/
142 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
143 {
144 u16 phy_id = 0;
145 bool valid = FALSE;
146
147 DEBUGFUNC("ixgbe_validate_phy_addr");
148
149 hw->phy.addr = phy_addr;
150 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
151 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
152
153 if (phy_id != 0xFFFF && phy_id != 0x0)
154 valid = TRUE;
155
156 return valid;
157 }
158
159 /**
160 * ixgbe_get_phy_id - Get the phy type
161 * @hw: pointer to hardware structure
162 *
163 **/
164 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
165 {
166 u32 status;
167 u16 phy_id_high = 0;
168 u16 phy_id_low = 0;
169
170 DEBUGFUNC("ixgbe_get_phy_id");
171
172 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
173 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
174 &phy_id_high);
175
176 if (status == IXGBE_SUCCESS) {
177 hw->phy.id = (u32)(phy_id_high << 16);
178 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
179 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
180 &phy_id_low);
181 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
182 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
183 }
184 return status;
185 }
186
187 /**
188 * ixgbe_get_phy_type_from_id - Get the phy type
189 * @hw: pointer to hardware structure
190 *
191 **/
192 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
193 {
194 enum ixgbe_phy_type phy_type;
195
196 DEBUGFUNC("ixgbe_get_phy_type_from_id");
197
198 switch (phy_id) {
199 case TN1010_PHY_ID:
200 phy_type = ixgbe_phy_tn;
201 break;
202 case X540_PHY_ID:
203 phy_type = ixgbe_phy_aq;
204 break;
205 case QT2022_PHY_ID:
206 phy_type = ixgbe_phy_qt;
207 break;
208 case ATH_PHY_ID:
209 phy_type = ixgbe_phy_nl;
210 break;
211 default:
212 phy_type = ixgbe_phy_unknown;
213 break;
214 }
215
216 DEBUGOUT1("phy type found is %d\n", phy_type);
217 return phy_type;
218 }
219
220 /**
221 * ixgbe_reset_phy_generic - Performs a PHY reset
222 * @hw: pointer to hardware structure
223 **/
224 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
225 {
226 u32 i;
227 u16 ctrl = 0;
228 s32 status = IXGBE_SUCCESS;
229
230 DEBUGFUNC("ixgbe_reset_phy_generic");
231
232 if (hw->phy.type == ixgbe_phy_unknown)
233 status = ixgbe_identify_phy_generic(hw);
234
235 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
236 goto out;
237
238 /* Don't reset PHY if it's shut down due to overtemp. */
239 if (!hw->phy.reset_if_overtemp &&
240 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
241 goto out;
242
243 /*
244 * Perform soft PHY reset to the PHY_XS.
245 * This will cause a soft reset to the PHY
246 */
247 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
248 IXGBE_MDIO_PHY_XS_DEV_TYPE,
249 IXGBE_MDIO_PHY_XS_RESET);
250
251 /*
252 * Poll for reset bit to self-clear indicating reset is complete.
253 * Some PHYs could take up to 3 seconds to complete and need about
254 * 1.7 usec delay after the reset is complete.
255 */
256 for (i = 0; i < 30; i++) {
257 msec_delay(100);
258 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
259 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
260 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
261 usec_delay(2);
262 break;
263 }
264 }
265
266 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
267 status = IXGBE_ERR_RESET_FAILED;
268 DEBUGOUT("PHY reset polling failed to complete.\n");
269 }
270
271 out:
272 return status;
273 }
274
275 /**
276 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
277 * @hw: pointer to hardware structure
278 * @reg_addr: 32 bit address of PHY register to read
279 * @phy_data: Pointer to read data from PHY register
280 **/
281 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
282 u32 device_type, u16 *phy_data)
283 {
284 u32 command;
285 u32 i;
286 u32 data;
287 s32 status = IXGBE_SUCCESS;
288 u16 gssr;
289
290 DEBUGFUNC("ixgbe_read_phy_reg_generic");
291
292 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
293 gssr = IXGBE_GSSR_PHY1_SM;
294 else
295 gssr = IXGBE_GSSR_PHY0_SM;
296
297 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
298 status = IXGBE_ERR_SWFW_SYNC;
299
300 if (status == IXGBE_SUCCESS) {
301 /* Setup and write the address cycle command */
302 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
303 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
304 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
305 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
306
307 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
308
309 /*
310 * Check every 10 usec to see if the address cycle completed.
311 * The MDI Command bit will clear when the operation is
312 * complete
313 */
314 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
315 usec_delay(10);
316
317 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
318
319 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
320 break;
321 }
322
323 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
324 DEBUGOUT("PHY address command did not complete.\n");
325 status = IXGBE_ERR_PHY;
326 }
327
328 if (status == IXGBE_SUCCESS) {
329 /*
330 * Address cycle complete, setup and write the read
331 * command
332 */
333 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
334 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
335 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
336 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
337
338 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
339
340 /*
341 * Check every 10 usec to see if the address cycle
342 * completed. The MDI Command bit will clear when the
343 * operation is complete
344 */
345 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
346 usec_delay(10);
347
348 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
349
350 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
351 break;
352 }
353
354 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
355 DEBUGOUT("PHY read command didn't complete\n");
356 status = IXGBE_ERR_PHY;
357 } else {
358 /*
359 * Read operation is complete. Get the data
360 * from MSRWD
361 */
362 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
363 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
364 *phy_data = (u16)(data);
365 }
366 }
367
368 hw->mac.ops.release_swfw_sync(hw, gssr);
369 }
370
371 return status;
372 }
373
374 /**
375 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
376 * @hw: pointer to hardware structure
377 * @reg_addr: 32 bit PHY register to write
378 * @device_type: 5 bit device type
379 * @phy_data: Data to write to the PHY register
380 **/
381 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
382 u32 device_type, u16 phy_data)
383 {
384 u32 command;
385 u32 i;
386 s32 status = IXGBE_SUCCESS;
387 u16 gssr;
388
389 DEBUGFUNC("ixgbe_write_phy_reg_generic");
390
391 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
392 gssr = IXGBE_GSSR_PHY1_SM;
393 else
394 gssr = IXGBE_GSSR_PHY0_SM;
395
396 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
397 status = IXGBE_ERR_SWFW_SYNC;
398
399 if (status == IXGBE_SUCCESS) {
400 /* Put the data in the MDI single read and write data register*/
401 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
402
403 /* Setup and write the address cycle command */
404 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
405 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
406 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
407 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
408
409 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
410
411 /*
412 * Check every 10 usec to see if the address cycle completed.
413 * The MDI Command bit will clear when the operation is
414 * complete
415 */
416 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
417 usec_delay(10);
418
419 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
420
421 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
422 break;
423 }
424
425 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
426 DEBUGOUT("PHY address cmd didn't complete\n");
427 status = IXGBE_ERR_PHY;
428 }
429
430 if (status == IXGBE_SUCCESS) {
431 /*
432 * Address cycle complete, setup and write the write
433 * command
434 */
435 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
436 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
437 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
438 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
439
440 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
441
442 /*
443 * Check every 10 usec to see if the address cycle
444 * completed. The MDI Command bit will clear when the
445 * operation is complete
446 */
447 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
448 usec_delay(10);
449
450 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
451
452 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
453 break;
454 }
455
456 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
457 DEBUGOUT("PHY address cmd didn't complete\n");
458 status = IXGBE_ERR_PHY;
459 }
460 }
461
462 hw->mac.ops.release_swfw_sync(hw, gssr);
463 }
464
465 return status;
466 }
467
468 /**
469 * ixgbe_setup_phy_link_generic - Set and restart autoneg
470 * @hw: pointer to hardware structure
471 *
472 * Restart autonegotiation and PHY and waits for completion.
473 **/
474 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
475 {
476 s32 status;
477 u32 time_out;
478 u32 max_time_out = 10;
479 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
480 bool autoneg = FALSE;
481 ixgbe_link_speed speed;
482
483 DEBUGFUNC("ixgbe_setup_phy_link_generic");
484
485 status =
486 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
487 if (status != IXGBE_SUCCESS)
488 return status;
489
490 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
491 /* Set or unset auto-negotiation 10G advertisement */
492 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
493 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
494 &autoneg_reg);
495
496 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
497 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
498 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
499
500 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
501 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
502 autoneg_reg);
503 }
504
505 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
506 /* Set or unset auto-negotiation 1G advertisement */
507 hw->phy.ops.read_reg(hw,
508 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
509 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
510 &autoneg_reg);
511
512 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
513 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
514 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
515
516 hw->phy.ops.write_reg(hw,
517 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
518 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
519 autoneg_reg);
520 }
521
522 if (speed & IXGBE_LINK_SPEED_100_FULL) {
523 /* Set or unset auto-negotiation 100M advertisement */
524 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
525 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
526 &autoneg_reg);
527
528 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
529 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
530 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
531 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
532
533 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
534 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
535 autoneg_reg);
536 }
537
538 /* Restart PHY autonegotiation and wait for completion */
539 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
540 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
541
542 autoneg_reg |= IXGBE_MII_RESTART;
543
544 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
545 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
546
547 /* Wait for autonegotiation to finish */
548 for (time_out = 0; time_out < max_time_out; time_out++) {
549 usec_delay(10);
550 /* Restart PHY autonegotiation and wait for completion */
551 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
552 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
553 &autoneg_reg);
554
555 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
556 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
557 break;
558 }
559
560 if (time_out == max_time_out) {
561 status = IXGBE_ERR_LINK_SETUP;
562 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
563 }
564
565 return status;
566 }
567
568 /**
569 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
570 * @hw: pointer to hardware structure
571 * @speed: new link speed
572 **/
573 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
574 ixgbe_link_speed speed,
575 bool autoneg_wait_to_complete)
576 {
577 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
578
579 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
580
581 /*
582 * Clear autoneg_advertised and set new values based on input link
583 * speed.
584 */
585 hw->phy.autoneg_advertised = 0;
586
587 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
588 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
589
590 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
591 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
592
593 if (speed & IXGBE_LINK_SPEED_100_FULL)
594 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
595
596 /* Setup link based on the new speed settings */
597 hw->phy.ops.setup_link(hw);
598
599 return IXGBE_SUCCESS;
600 }
601
602 /**
603 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
604 * @hw: pointer to hardware structure
605 * @speed: pointer to link speed
606 * @autoneg: boolean auto-negotiation value
607 *
608 * Determines the link capabilities by reading the AUTOC register.
609 **/
610 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
611 ixgbe_link_speed *speed,
612 bool *autoneg)
613 {
614 s32 status = IXGBE_ERR_LINK_SETUP;
615 u16 speed_ability;
616
617 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
618
619 *speed = 0;
620 *autoneg = TRUE;
621
622 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
623 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
624 &speed_ability);
625
626 if (status == IXGBE_SUCCESS) {
627 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
628 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
629 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
630 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
631 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
632 *speed |= IXGBE_LINK_SPEED_100_FULL;
633 }
634
635 return status;
636 }
637
638 /**
639 * ixgbe_check_phy_link_tnx - Determine link and speed status
640 * @hw: pointer to hardware structure
641 *
642 * Reads the VS1 register to determine if link is up and the current speed for
643 * the PHY.
644 **/
645 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
646 bool *link_up)
647 {
648 s32 status = IXGBE_SUCCESS;
649 u32 time_out;
650 u32 max_time_out = 10;
651 u16 phy_link = 0;
652 u16 phy_speed = 0;
653 u16 phy_data = 0;
654
655 DEBUGFUNC("ixgbe_check_phy_link_tnx");
656
657 /* Initialize speed and link to default case */
658 *link_up = FALSE;
659 *speed = IXGBE_LINK_SPEED_10GB_FULL;
660
661 /*
662 * Check current speed and link status of the PHY register.
663 * This is a vendor specific register and may have to
664 * be changed for other copper PHYs.
665 */
666 for (time_out = 0; time_out < max_time_out; time_out++) {
667 usec_delay(10);
668 status = hw->phy.ops.read_reg(hw,
669 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
670 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
671 &phy_data);
672 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
673 phy_speed = phy_data &
674 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
675 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
676 *link_up = TRUE;
677 if (phy_speed ==
678 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
679 *speed = IXGBE_LINK_SPEED_1GB_FULL;
680 break;
681 }
682 }
683
684 return status;
685 }
686
687 /**
688 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
689 * @hw: pointer to hardware structure
690 *
691 * Restart autonegotiation and PHY and waits for completion.
692 **/
693 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
694 {
695 s32 status;
696 u32 time_out;
697 u32 max_time_out = 10;
698 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
699 bool autoneg = FALSE;
700 ixgbe_link_speed speed;
701
702 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
703
704 status =
705 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
706 if (status != IXGBE_SUCCESS)
707 return status;
708
709 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
710 /* Set or unset auto-negotiation 10G advertisement */
711 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
712 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
713 &autoneg_reg);
714
715 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
716 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
717 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
718
719 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
720 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
721 autoneg_reg);
722 }
723
724 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
725 /* Set or unset auto-negotiation 1G advertisement */
726 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
727 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
728 &autoneg_reg);
729
730 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
731 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
732 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
733
734 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
735 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
736 autoneg_reg);
737 }
738
739 if (speed & IXGBE_LINK_SPEED_100_FULL) {
740 /* Set or unset auto-negotiation 100M advertisement */
741 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
742 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
743 &autoneg_reg);
744
745 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
746 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
747 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
748
749 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
750 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
751 autoneg_reg);
752 }
753
754 /* Restart PHY autonegotiation and wait for completion */
755 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
756 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
757
758 autoneg_reg |= IXGBE_MII_RESTART;
759
760 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
761 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
762
763 /* Wait for autonegotiation to finish */
764 for (time_out = 0; time_out < max_time_out; time_out++) {
765 usec_delay(10);
766 /* Restart PHY autonegotiation and wait for completion */
767 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
768 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
769 &autoneg_reg);
770
771 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
772 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
773 break;
774 }
775
776 if (time_out == max_time_out) {
777 status = IXGBE_ERR_LINK_SETUP;
778 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
779 }
780
781 return status;
782 }
783
784 /**
785 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
786 * @hw: pointer to hardware structure
787 * @firmware_version: pointer to the PHY Firmware Version
788 **/
789 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
790 u16 *firmware_version)
791 {
792 s32 status = IXGBE_SUCCESS;
793
794 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
795
796 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
797 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
798 firmware_version);
799
800 return status;
801 }
802
803 /**
804 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
805 * @hw: pointer to hardware structure
806 * @firmware_version: pointer to the PHY Firmware Version
807 **/
808 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
809 u16 *firmware_version)
810 {
811 s32 status = IXGBE_SUCCESS;
812
813 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
814
815 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
816 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
817 firmware_version);
818
819 return status;
820 }
821
822 /**
823 * ixgbe_reset_phy_nl - Performs a PHY reset
824 * @hw: pointer to hardware structure
825 **/
826 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
827 {
828 u16 phy_offset, control, eword, edata, block_crc;
829 bool end_data = FALSE;
830 u16 list_offset, data_offset;
831 u16 phy_data = 0;
832 s32 ret_val = IXGBE_SUCCESS;
833 u32 i;
834
835 DEBUGFUNC("ixgbe_reset_phy_nl");
836
837 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
838 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
839
840 /* reset the PHY and poll for completion */
841 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
842 IXGBE_MDIO_PHY_XS_DEV_TYPE,
843 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
844
845 for (i = 0; i < 100; i++) {
846 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
847 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
848 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
849 break;
850 msec_delay(10);
851 }
852
853 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
854 DEBUGOUT("PHY reset did not complete.\n");
855 ret_val = IXGBE_ERR_PHY;
856 goto out;
857 }
858
859 /* Get init offsets */
860 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
861 &data_offset);
862 if (ret_val != IXGBE_SUCCESS)
863 goto out;
864
865 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
866 data_offset++;
867 while (!end_data) {
868 /*
869 * Read control word from PHY init contents offset
870 */
871 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
872 control = (eword & IXGBE_CONTROL_MASK_NL) >>
873 IXGBE_CONTROL_SHIFT_NL;
874 edata = eword & IXGBE_DATA_MASK_NL;
875 switch (control) {
876 case IXGBE_DELAY_NL:
877 data_offset++;
878 DEBUGOUT1("DELAY: %d MS\n", edata);
879 msec_delay(edata);
880 break;
881 case IXGBE_DATA_NL:
882 DEBUGOUT("DATA:\n");
883 data_offset++;
884 hw->eeprom.ops.read(hw, data_offset++,
885 &phy_offset);
886 for (i = 0; i < edata; i++) {
887 hw->eeprom.ops.read(hw, data_offset, &eword);
888 hw->phy.ops.write_reg(hw, phy_offset,
889 IXGBE_TWINAX_DEV, eword);
890 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
891 phy_offset);
892 data_offset++;
893 phy_offset++;
894 }
895 break;
896 case IXGBE_CONTROL_NL:
897 data_offset++;
898 DEBUGOUT("CONTROL:\n");
899 if (edata == IXGBE_CONTROL_EOL_NL) {
900 DEBUGOUT("EOL\n");
901 end_data = TRUE;
902 } else if (edata == IXGBE_CONTROL_SOL_NL) {
903 DEBUGOUT("SOL\n");
904 } else {
905 DEBUGOUT("Bad control value\n");
906 ret_val = IXGBE_ERR_PHY;
907 goto out;
908 }
909 break;
910 default:
911 DEBUGOUT("Bad control type\n");
912 ret_val = IXGBE_ERR_PHY;
913 goto out;
914 }
915 }
916
917 out:
918 return ret_val;
919 }
920
921 /**
922 * ixgbe_identify_module_generic - Identifies module type
923 * @hw: pointer to hardware structure
924 *
925 * Determines HW type and calls appropriate function.
926 **/
927 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
928 {
929 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
930
931 DEBUGFUNC("ixgbe_identify_module_generic");
932
933 switch (hw->mac.ops.get_media_type(hw)) {
934 case ixgbe_media_type_fiber:
935 status = ixgbe_identify_sfp_module_generic(hw);
936 break;
937
938
939 default:
940 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
941 status = IXGBE_ERR_SFP_NOT_PRESENT;
942 break;
943 }
944
945 return status;
946 }
947
948 /**
949 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
950 * @hw: pointer to hardware structure
951 *
952 * Searches for and identifies the SFP module and assigns appropriate PHY type.
953 **/
954 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
955 {
956 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
957 u32 vendor_oui = 0;
958 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
959 u8 identifier = 0;
960 u8 comp_codes_1g = 0;
961 u8 comp_codes_10g = 0;
962 u8 oui_bytes[3] = {0, 0, 0};
963 u8 cable_tech = 0;
964 u8 cable_spec = 0;
965 u16 enforce_sfp = 0;
966
967 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
968
969 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
970 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
971 status = IXGBE_ERR_SFP_NOT_PRESENT;
972 goto out;
973 }
974
975 status = hw->phy.ops.read_i2c_eeprom(hw,
976 IXGBE_SFF_IDENTIFIER,
977 &identifier);
978
979 if (status != IXGBE_SUCCESS)
980 goto err_read_i2c_eeprom;
981
982 /* LAN ID is needed for sfp_type determination */
983 hw->mac.ops.set_lan_id(hw);
984
985 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
986 hw->phy.type = ixgbe_phy_sfp_unsupported;
987 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
988 } else {
989 status = hw->phy.ops.read_i2c_eeprom(hw,
990 IXGBE_SFF_1GBE_COMP_CODES,
991 &comp_codes_1g);
992
993 if (status != IXGBE_SUCCESS)
994 goto err_read_i2c_eeprom;
995
996 status = hw->phy.ops.read_i2c_eeprom(hw,
997 IXGBE_SFF_10GBE_COMP_CODES,
998 &comp_codes_10g);
999
1000 if (status != IXGBE_SUCCESS)
1001 goto err_read_i2c_eeprom;
1002 status = hw->phy.ops.read_i2c_eeprom(hw,
1003 IXGBE_SFF_CABLE_TECHNOLOGY,
1004 &cable_tech);
1005
1006 if (status != IXGBE_SUCCESS)
1007 goto err_read_i2c_eeprom;
1008
1009 /* ID Module
1010 * =========
1011 * 0 SFP_DA_CU
1012 * 1 SFP_SR
1013 * 2 SFP_LR
1014 * 3 SFP_DA_CORE0 - 82599-specific
1015 * 4 SFP_DA_CORE1 - 82599-specific
1016 * 5 SFP_SR/LR_CORE0 - 82599-specific
1017 * 6 SFP_SR/LR_CORE1 - 82599-specific
1018 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1019 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1020 * 9 SFP_1g_cu_CORE0 - 82599-specific
1021 * 10 SFP_1g_cu_CORE1 - 82599-specific
1022 * 11 SFP_1g_sx_CORE0 - 82599-specific
1023 * 12 SFP_1g_sx_CORE1 - 82599-specific
1024 */
1025 if (hw->mac.type == ixgbe_mac_82598EB) {
1026 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1027 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1028 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1029 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1030 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1031 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1032 else
1033 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1034 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1035 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1036 if (hw->bus.lan_id == 0)
1037 hw->phy.sfp_type =
1038 ixgbe_sfp_type_da_cu_core0;
1039 else
1040 hw->phy.sfp_type =
1041 ixgbe_sfp_type_da_cu_core1;
1042 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1043 hw->phy.ops.read_i2c_eeprom(
1044 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1045 &cable_spec);
1046 if (cable_spec &
1047 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1048 if (hw->bus.lan_id == 0)
1049 hw->phy.sfp_type =
1050 ixgbe_sfp_type_da_act_lmt_core0;
1051 else
1052 hw->phy.sfp_type =
1053 ixgbe_sfp_type_da_act_lmt_core1;
1054 } else {
1055 hw->phy.sfp_type =
1056 ixgbe_sfp_type_unknown;
1057 }
1058 } else if (comp_codes_10g &
1059 (IXGBE_SFF_10GBASESR_CAPABLE |
1060 IXGBE_SFF_10GBASELR_CAPABLE)) {
1061 if (hw->bus.lan_id == 0)
1062 hw->phy.sfp_type =
1063 ixgbe_sfp_type_srlr_core0;
1064 else
1065 hw->phy.sfp_type =
1066 ixgbe_sfp_type_srlr_core1;
1067 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1068 if (hw->bus.lan_id == 0)
1069 hw->phy.sfp_type =
1070 ixgbe_sfp_type_1g_cu_core0;
1071 else
1072 hw->phy.sfp_type =
1073 ixgbe_sfp_type_1g_cu_core1;
1074 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1075 if (hw->bus.lan_id == 0)
1076 hw->phy.sfp_type =
1077 ixgbe_sfp_type_1g_sx_core0;
1078 else
1079 hw->phy.sfp_type =
1080 ixgbe_sfp_type_1g_sx_core1;
1081 } else {
1082 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1083 }
1084 }
1085
1086 if (hw->phy.sfp_type != stored_sfp_type)
1087 hw->phy.sfp_setup_needed = TRUE;
1088
1089 /* Determine if the SFP+ PHY is dual speed or not. */
1090 hw->phy.multispeed_fiber = FALSE;
1091 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1092 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1093 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1094 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1095 hw->phy.multispeed_fiber = TRUE;
1096
1097 /* Determine PHY vendor */
1098 if (hw->phy.type != ixgbe_phy_nl) {
1099 hw->phy.id = identifier;
1100 status = hw->phy.ops.read_i2c_eeprom(hw,
1101 IXGBE_SFF_VENDOR_OUI_BYTE0,
1102 &oui_bytes[0]);
1103
1104 if (status != IXGBE_SUCCESS)
1105 goto err_read_i2c_eeprom;
1106
1107 status = hw->phy.ops.read_i2c_eeprom(hw,
1108 IXGBE_SFF_VENDOR_OUI_BYTE1,
1109 &oui_bytes[1]);
1110
1111 if (status != IXGBE_SUCCESS)
1112 goto err_read_i2c_eeprom;
1113
1114 status = hw->phy.ops.read_i2c_eeprom(hw,
1115 IXGBE_SFF_VENDOR_OUI_BYTE2,
1116 &oui_bytes[2]);
1117
1118 if (status != IXGBE_SUCCESS)
1119 goto err_read_i2c_eeprom;
1120
1121 vendor_oui =
1122 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1123 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1124 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1125
1126 switch (vendor_oui) {
1127 case IXGBE_SFF_VENDOR_OUI_TYCO:
1128 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1129 hw->phy.type =
1130 ixgbe_phy_sfp_passive_tyco;
1131 break;
1132 case IXGBE_SFF_VENDOR_OUI_FTL:
1133 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1134 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1135 else
1136 hw->phy.type = ixgbe_phy_sfp_ftl;
1137 break;
1138 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1139 hw->phy.type = ixgbe_phy_sfp_avago;
1140 break;
1141 case IXGBE_SFF_VENDOR_OUI_INTEL:
1142 hw->phy.type = ixgbe_phy_sfp_intel;
1143 break;
1144 default:
1145 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1146 hw->phy.type =
1147 ixgbe_phy_sfp_passive_unknown;
1148 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1149 hw->phy.type =
1150 ixgbe_phy_sfp_active_unknown;
1151 else
1152 hw->phy.type = ixgbe_phy_sfp_unknown;
1153 break;
1154 }
1155 }
1156
1157 /* Allow any DA cable vendor */
1158 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1159 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1160 status = IXGBE_SUCCESS;
1161 goto out;
1162 }
1163
1164 /* Verify supported 1G SFP modules */
1165 if (comp_codes_10g == 0 &&
1166 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1167 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1168 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1169 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1170 hw->phy.type = ixgbe_phy_sfp_unsupported;
1171 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1172 goto out;
1173 }
1174
1175 /* Anything else 82598-based is supported */
1176 if (hw->mac.type == ixgbe_mac_82598EB) {
1177 status = IXGBE_SUCCESS;
1178 goto out;
1179 }
1180
1181 (void) ixgbe_get_device_caps(hw, &enforce_sfp);
1182 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1183 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1184 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1185 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
1186 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1187 /* Make sure we're a supported PHY type */
1188 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1189 status = IXGBE_SUCCESS;
1190 } else {
1191 if (hw->allow_unsupported_sfp == TRUE) {
1192 EWARN(hw, "WARNING: Intel (R) Network "
1193 "Connections are quality tested "
1194 "using Intel (R) Ethernet Optics."
1195 " Using untested modules is not "
1196 "supported and may cause unstable"
1197 " operation or damage to the "
1198 "module or the adapter. Intel "
1199 "Corporation is not responsible "
1200 "for any harm caused by using "
1201 "untested modules.\n", status);
1202 status = IXGBE_SUCCESS;
1203 } else {
1204 EWARN(hw, "SFP+ module not supported\n",
1205 status);
1206 hw->phy.type =
1207 ixgbe_phy_sfp_unsupported;
1208 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1209 }
1210 }
1211 } else {
1212 status = IXGBE_SUCCESS;
1213 }
1214 }
1215
1216 out:
1217 return status;
1218
1219 err_read_i2c_eeprom:
1220 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1221 if (hw->phy.type != ixgbe_phy_nl) {
1222 hw->phy.id = 0;
1223 hw->phy.type = ixgbe_phy_unknown;
1224 }
1225 return IXGBE_ERR_SFP_NOT_PRESENT;
1226 }
1227
1228
1229
1230 /**
1231 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1232 * @hw: pointer to hardware structure
1233 * @list_offset: offset to the SFP ID list
1234 * @data_offset: offset to the SFP data block
1235 *
1236 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1237 * so it returns the offsets to the phy init sequence block.
1238 **/
1239 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1240 u16 *list_offset,
1241 u16 *data_offset)
1242 {
1243 u16 sfp_id;
1244 u16 sfp_type = hw->phy.sfp_type;
1245
1246 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1247
1248 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1249 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1250
1251 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1252 return IXGBE_ERR_SFP_NOT_PRESENT;
1253
1254 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1255 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1256 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1257
1258 /*
1259 * Limiting active cables and 1G Phys must be initialized as
1260 * SR modules
1261 */
1262 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1263 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1264 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1265 sfp_type = ixgbe_sfp_type_srlr_core0;
1266 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1267 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1268 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1269 sfp_type = ixgbe_sfp_type_srlr_core1;
1270
1271 /* Read offset to PHY init contents */
1272 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1273
1274 if ((!*list_offset) || (*list_offset == 0xFFFF))
1275 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1276
1277 /* Shift offset to first ID word */
1278 (*list_offset)++;
1279
1280 /*
1281 * Find the matching SFP ID in the EEPROM
1282 * and program the init sequence
1283 */
1284 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1285
1286 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1287 if (sfp_id == sfp_type) {
1288 (*list_offset)++;
1289 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1290 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1291 DEBUGOUT("SFP+ module not supported\n");
1292 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1293 } else {
1294 break;
1295 }
1296 } else {
1297 (*list_offset) += 2;
1298 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1299 return IXGBE_ERR_PHY;
1300 }
1301 }
1302
1303 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1304 DEBUGOUT("No matching SFP+ module found\n");
1305 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1306 }
1307
1308 return IXGBE_SUCCESS;
1309 }
1310
1311 /**
1312 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1313 * @hw: pointer to hardware structure
1314 * @byte_offset: EEPROM byte offset to read
1315 * @eeprom_data: value read
1316 *
1317 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1318 **/
1319 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1320 u8 *eeprom_data)
1321 {
1322 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1323
1324 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1325 IXGBE_I2C_EEPROM_DEV_ADDR,
1326 eeprom_data);
1327 }
1328
1329 /**
1330 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1331 * @hw: pointer to hardware structure
1332 * @byte_offset: byte offset at address 0xA2
1333 * @eeprom_data: value read
1334 *
1335 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1336 **/
1337 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1338 u8 *sff8472_data)
1339 {
1340 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1341 IXGBE_I2C_EEPROM_DEV_ADDR2,
1342 sff8472_data);
1343 }
1344
1345 /**
1346 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1347 * @hw: pointer to hardware structure
1348 * @byte_offset: EEPROM byte offset to write
1349 * @eeprom_data: value to write
1350 *
1351 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1352 **/
1353 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1354 u8 eeprom_data)
1355 {
1356 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1357
1358 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1359 IXGBE_I2C_EEPROM_DEV_ADDR,
1360 eeprom_data);
1361 }
1362
1363 /**
1364 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1365 * @hw: pointer to hardware structure
1366 * @byte_offset: byte offset to read
1367 * @data: value read
1368 *
1369 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1370 * a specified device address.
1371 **/
1372 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1373 u8 dev_addr, u8 *data)
1374 {
1375 s32 status = IXGBE_SUCCESS;
1376 u32 max_retry = 10;
1377 u32 retry = 0;
1378 u16 swfw_mask = 0;
1379 bool nack = 1;
1380 *data = 0;
1381
1382 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1383
1384 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1385 swfw_mask = IXGBE_GSSR_PHY1_SM;
1386 else
1387 swfw_mask = IXGBE_GSSR_PHY0_SM;
1388
1389 do {
1390 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1391 != IXGBE_SUCCESS) {
1392 status = IXGBE_ERR_SWFW_SYNC;
1393 goto read_byte_out;
1394 }
1395
1396 ixgbe_i2c_start(hw);
1397
1398 /* Device Address and write indication */
1399 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1400 if (status != IXGBE_SUCCESS)
1401 goto fail;
1402
1403 status = ixgbe_get_i2c_ack(hw);
1404 if (status != IXGBE_SUCCESS)
1405 goto fail;
1406
1407 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1408 if (status != IXGBE_SUCCESS)
1409 goto fail;
1410
1411 status = ixgbe_get_i2c_ack(hw);
1412 if (status != IXGBE_SUCCESS)
1413 goto fail;
1414
1415 ixgbe_i2c_start(hw);
1416
1417 /* Device Address and read indication */
1418 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1419 if (status != IXGBE_SUCCESS)
1420 goto fail;
1421
1422 status = ixgbe_get_i2c_ack(hw);
1423 if (status != IXGBE_SUCCESS)
1424 goto fail;
1425
1426 status = ixgbe_clock_in_i2c_byte(hw, data);
1427 if (status != IXGBE_SUCCESS)
1428 goto fail;
1429
1430 status = ixgbe_clock_out_i2c_bit(hw, nack);
1431 if (status != IXGBE_SUCCESS)
1432 goto fail;
1433
1434 ixgbe_i2c_stop(hw);
1435 break;
1436
1437 fail:
1438 ixgbe_i2c_bus_clear(hw);
1439 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1440 msec_delay(100);
1441 retry++;
1442 if (retry < max_retry)
1443 DEBUGOUT("I2C byte read error - Retrying.\n");
1444 else
1445 DEBUGOUT("I2C byte read error.\n");
1446
1447 } while (retry < max_retry);
1448
1449 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1450
1451 read_byte_out:
1452 return status;
1453 }
1454
1455 /**
1456 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1457 * @hw: pointer to hardware structure
1458 * @byte_offset: byte offset to write
1459 * @data: value to write
1460 *
1461 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1462 * a specified device address.
1463 **/
1464 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1465 u8 dev_addr, u8 data)
1466 {
1467 s32 status = IXGBE_SUCCESS;
1468 u32 max_retry = 1;
1469 u32 retry = 0;
1470 u16 swfw_mask = 0;
1471
1472 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1473
1474 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1475 swfw_mask = IXGBE_GSSR_PHY1_SM;
1476 else
1477 swfw_mask = IXGBE_GSSR_PHY0_SM;
1478
1479 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1480 status = IXGBE_ERR_SWFW_SYNC;
1481 goto write_byte_out;
1482 }
1483
1484 do {
1485 ixgbe_i2c_start(hw);
1486
1487 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1488 if (status != IXGBE_SUCCESS)
1489 goto fail;
1490
1491 status = ixgbe_get_i2c_ack(hw);
1492 if (status != IXGBE_SUCCESS)
1493 goto fail;
1494
1495 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1496 if (status != IXGBE_SUCCESS)
1497 goto fail;
1498
1499 status = ixgbe_get_i2c_ack(hw);
1500 if (status != IXGBE_SUCCESS)
1501 goto fail;
1502
1503 status = ixgbe_clock_out_i2c_byte(hw, data);
1504 if (status != IXGBE_SUCCESS)
1505 goto fail;
1506
1507 status = ixgbe_get_i2c_ack(hw);
1508 if (status != IXGBE_SUCCESS)
1509 goto fail;
1510
1511 ixgbe_i2c_stop(hw);
1512 break;
1513
1514 fail:
1515 ixgbe_i2c_bus_clear(hw);
1516 retry++;
1517 if (retry < max_retry)
1518 DEBUGOUT("I2C byte write error - Retrying.\n");
1519 else
1520 DEBUGOUT("I2C byte write error.\n");
1521 } while (retry < max_retry);
1522
1523 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1524
1525 write_byte_out:
1526 return status;
1527 }
1528
1529 /**
1530 * ixgbe_i2c_start - Sets I2C start condition
1531 * @hw: pointer to hardware structure
1532 *
1533 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1534 **/
1535 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1536 {
1537 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1538
1539 DEBUGFUNC("ixgbe_i2c_start");
1540
1541 /* Start condition must begin with data and clock high */
1542 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1543 ixgbe_raise_i2c_clk(hw, &i2cctl);
1544
1545 /* Setup time for start condition (4.7us) */
1546 usec_delay(IXGBE_I2C_T_SU_STA);
1547
1548 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1549
1550 /* Hold time for start condition (4us) */
1551 usec_delay(IXGBE_I2C_T_HD_STA);
1552
1553 ixgbe_lower_i2c_clk(hw, &i2cctl);
1554
1555 /* Minimum low period of clock is 4.7 us */
1556 usec_delay(IXGBE_I2C_T_LOW);
1557
1558 }
1559
1560 /**
1561 * ixgbe_i2c_stop - Sets I2C stop condition
1562 * @hw: pointer to hardware structure
1563 *
1564 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1565 **/
1566 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1567 {
1568 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1569
1570 DEBUGFUNC("ixgbe_i2c_stop");
1571
1572 /* Stop condition must begin with data low and clock high */
1573 (void) ixgbe_set_i2c_data(hw, &i2cctl, 0);
1574 ixgbe_raise_i2c_clk(hw, &i2cctl);
1575
1576 /* Setup time for stop condition (4us) */
1577 usec_delay(IXGBE_I2C_T_SU_STO);
1578
1579 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1580
1581 /* bus free time between stop and start (4.7us)*/
1582 usec_delay(IXGBE_I2C_T_BUF);
1583 }
1584
1585 /**
1586 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1587 * @hw: pointer to hardware structure
1588 * @data: data byte to clock in
1589 *
1590 * Clocks in one byte data via I2C data/clock
1591 **/
1592 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1593 {
1594 s32 i, status = IXGBE_SUCCESS;
1595 bool bit = 0;
1596
1597 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1598
1599 for (i = 7; i >= 0; i--) {
1600 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1601 if (status != IXGBE_SUCCESS)
1602 break;
1603 *data |= bit << i;
1604 }
1605
1606 return status;
1607 }
1608
1609 /**
1610 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1611 * @hw: pointer to hardware structure
1612 * @data: data byte clocked out
1613 *
1614 * Clocks out one byte data via I2C data/clock
1615 **/
1616 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1617 {
1618 s32 status = IXGBE_SUCCESS;
1619 s32 i;
1620 u32 i2cctl;
1621 bool bit = 0;
1622
1623 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1624
1625 for (i = 7; i >= 0; i--) {
1626 bit = (data >> i) & 0x1;
1627 status = ixgbe_clock_out_i2c_bit(hw, bit);
1628
1629 if (status != IXGBE_SUCCESS)
1630 break;
1631 }
1632
1633 /* Release SDA line (set high) */
1634 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1635 i2cctl |= IXGBE_I2C_DATA_OUT;
1636 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1637 IXGBE_WRITE_FLUSH(hw);
1638
1639 return status;
1640 }
1641
1642 /**
1643 * ixgbe_get_i2c_ack - Polls for I2C ACK
1644 * @hw: pointer to hardware structure
1645 *
1646 * Clocks in/out one bit via I2C data/clock
1647 **/
1648 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1649 {
1650 s32 status = IXGBE_SUCCESS;
1651 u32 i = 0;
1652 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1653 u32 timeout = 10;
1654 bool ack = 1;
1655
1656 DEBUGFUNC("ixgbe_get_i2c_ack");
1657
1658 ixgbe_raise_i2c_clk(hw, &i2cctl);
1659
1660
1661 /* Minimum high period of clock is 4us */
1662 usec_delay(IXGBE_I2C_T_HIGH);
1663
1664 /* Poll for ACK. Note that ACK in I2C spec is
1665 * transition from 1 to 0 */
1666 for (i = 0; i < timeout; i++) {
1667 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1668 ack = ixgbe_get_i2c_data(&i2cctl);
1669
1670 usec_delay(1);
1671 if (ack == 0)
1672 break;
1673 }
1674
1675 if (ack == 1) {
1676 DEBUGOUT("I2C ack was not received.\n");
1677 status = IXGBE_ERR_I2C;
1678 }
1679
1680 ixgbe_lower_i2c_clk(hw, &i2cctl);
1681
1682 /* Minimum low period of clock is 4.7 us */
1683 usec_delay(IXGBE_I2C_T_LOW);
1684
1685 return status;
1686 }
1687
1688 /**
1689 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1690 * @hw: pointer to hardware structure
1691 * @data: read data value
1692 *
1693 * Clocks in one bit via I2C data/clock
1694 **/
1695 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1696 {
1697 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1698
1699 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1700
1701 ixgbe_raise_i2c_clk(hw, &i2cctl);
1702
1703 /* Minimum high period of clock is 4us */
1704 usec_delay(IXGBE_I2C_T_HIGH);
1705
1706 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1707 *data = ixgbe_get_i2c_data(&i2cctl);
1708
1709 ixgbe_lower_i2c_clk(hw, &i2cctl);
1710
1711 /* Minimum low period of clock is 4.7 us */
1712 usec_delay(IXGBE_I2C_T_LOW);
1713
1714 return IXGBE_SUCCESS;
1715 }
1716
1717 /**
1718 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1719 * @hw: pointer to hardware structure
1720 * @data: data value to write
1721 *
1722 * Clocks out one bit via I2C data/clock
1723 **/
1724 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1725 {
1726 s32 status;
1727 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1728
1729 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1730
1731 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1732 if (status == IXGBE_SUCCESS) {
1733 ixgbe_raise_i2c_clk(hw, &i2cctl);
1734
1735 /* Minimum high period of clock is 4us */
1736 usec_delay(IXGBE_I2C_T_HIGH);
1737
1738 ixgbe_lower_i2c_clk(hw, &i2cctl);
1739
1740 /* Minimum low period of clock is 4.7 us.
1741 * This also takes care of the data hold time.
1742 */
1743 usec_delay(IXGBE_I2C_T_LOW);
1744 } else {
1745 status = IXGBE_ERR_I2C;
1746 DEBUGOUT1("I2C data was not set to %X\n", data);
1747 }
1748
1749 return status;
1750 }
1751 /**
1752 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1753 * @hw: pointer to hardware structure
1754 * @i2cctl: Current value of I2CCTL register
1755 *
1756 * Raises the I2C clock line '0'->'1'
1757 **/
1758 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1759 {
1760 u32 i = 0;
1761 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1762 u32 i2cctl_r = 0;
1763
1764 DEBUGFUNC("ixgbe_raise_i2c_clk");
1765
1766 for (i = 0; i < timeout; i++) {
1767 *i2cctl |= IXGBE_I2C_CLK_OUT;
1768
1769 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1770 IXGBE_WRITE_FLUSH(hw);
1771 /* SCL rise time (1000ns) */
1772 usec_delay(IXGBE_I2C_T_RISE);
1773
1774 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1775 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1776 break;
1777 }
1778 }
1779
1780 /**
1781 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1782 * @hw: pointer to hardware structure
1783 * @i2cctl: Current value of I2CCTL register
1784 *
1785 * Lowers the I2C clock line '1'->'0'
1786 **/
1787 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1788 {
1789
1790 DEBUGFUNC("ixgbe_lower_i2c_clk");
1791
1792 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1793
1794 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1795 IXGBE_WRITE_FLUSH(hw);
1796
1797 /* SCL fall time (300ns) */
1798 usec_delay(IXGBE_I2C_T_FALL);
1799 }
1800
1801 /**
1802 * ixgbe_set_i2c_data - Sets the I2C data bit
1803 * @hw: pointer to hardware structure
1804 * @i2cctl: Current value of I2CCTL register
1805 * @data: I2C data value (0 or 1) to set
1806 *
1807 * Sets the I2C data bit
1808 **/
1809 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1810 {
1811 s32 status = IXGBE_SUCCESS;
1812
1813 DEBUGFUNC("ixgbe_set_i2c_data");
1814
1815 if (data)
1816 *i2cctl |= IXGBE_I2C_DATA_OUT;
1817 else
1818 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1819
1820 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1821 IXGBE_WRITE_FLUSH(hw);
1822
1823 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1824 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1825
1826 /* Verify data was set correctly */
1827 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1828 if (data != ixgbe_get_i2c_data(i2cctl)) {
1829 status = IXGBE_ERR_I2C;
1830 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1831 }
1832
1833 return status;
1834 }
1835
1836 /**
1837 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1838 * @hw: pointer to hardware structure
1839 * @i2cctl: Current value of I2CCTL register
1840 *
1841 * Returns the I2C data bit value
1842 **/
1843 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1844 {
1845 bool data;
1846
1847 DEBUGFUNC("ixgbe_get_i2c_data");
1848
1849 if (*i2cctl & IXGBE_I2C_DATA_IN)
1850 data = 1;
1851 else
1852 data = 0;
1853
1854 return data;
1855 }
1856
1857 /**
1858 * ixgbe_i2c_bus_clear - Clears the I2C bus
1859 * @hw: pointer to hardware structure
1860 *
1861 * Clears the I2C bus by sending nine clock pulses.
1862 * Used when data line is stuck low.
1863 **/
1864 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1865 {
1866 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1867 u32 i;
1868
1869 DEBUGFUNC("ixgbe_i2c_bus_clear");
1870
1871 ixgbe_i2c_start(hw);
1872
1873 (void) ixgbe_set_i2c_data(hw, &i2cctl, 1);
1874
1875 for (i = 0; i < 9; i++) {
1876 ixgbe_raise_i2c_clk(hw, &i2cctl);
1877
1878 /* Min high period of clock is 4us */
1879 usec_delay(IXGBE_I2C_T_HIGH);
1880
1881 ixgbe_lower_i2c_clk(hw, &i2cctl);
1882
1883 /* Min low period of clock is 4.7us*/
1884 usec_delay(IXGBE_I2C_T_LOW);
1885 }
1886
1887 ixgbe_i2c_start(hw);
1888
1889 /* Put the i2c bus back to default state */
1890 ixgbe_i2c_stop(hw);
1891 }
1892
1893 /**
1894 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1895 * @hw: pointer to hardware structure
1896 *
1897 * Checks if the LASI temp alarm status was triggered due to overtemp
1898 **/
1899 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1900 {
1901 s32 status = IXGBE_SUCCESS;
1902 u16 phy_data = 0;
1903
1904 DEBUGFUNC("ixgbe_tn_check_overtemp");
1905
1906 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1907 goto out;
1908
1909 /* Check that the LASI temp alarm status was triggered */
1910 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1911 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1912
1913 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1914 goto out;
1915
1916 status = IXGBE_ERR_OVERTEMP;
1917 out:
1918 return status;
1919 }