1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
130 /* Flow Control */
131 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
132
133 /* Link */
134 mac->ops.get_link_capabilities = NULL;
135 mac->ops.setup_link = NULL;
136 mac->ops.check_link = NULL;
137
138 return IXGBE_SUCCESS;
139 }
140
141 /**
142 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
143 * control
144 * @hw: pointer to hardware structure
145 *
146 * There are several phys that do not support autoneg flow control. This
147 * function check the device id to see if the associated phy supports
148 * autoneg flow control.
149 **/
150 static s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
151 {
152
153 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
154
155 switch (hw->device_id) {
156 case IXGBE_DEV_ID_X540T:
157 case IXGBE_DEV_ID_X540T1:
158 return IXGBE_SUCCESS;
159 case IXGBE_DEV_ID_82599_T3_LOM:
160 return IXGBE_SUCCESS;
161 default:
162 return IXGBE_ERR_FC_NOT_SUPPORTED;
163 }
164 }
165
166 /**
167 * ixgbe_setup_fc - Set up flow control
168 * @hw: pointer to hardware structure
169 *
170 * Called at init time to set up flow control.
171 **/
172 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
173 {
174 s32 ret_val = IXGBE_SUCCESS;
175 u32 reg = 0, reg_bp = 0;
176 u16 reg_cu = 0;
177
178 DEBUGFUNC("ixgbe_setup_fc");
179
180 /*
181 * Validate the requested mode. Strict IEEE mode does not allow
182 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
183 */
184 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
185 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
186 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
187 goto out;
188 }
189
190 /*
191 * 10gig parts do not have a word in the EEPROM to determine the
192 * default flow control setting, so we explicitly set it to full.
193 */
194 if (hw->fc.requested_mode == ixgbe_fc_default)
195 hw->fc.requested_mode = ixgbe_fc_full;
196
197 /*
198 * Set up the 1G and 10G flow control advertisement registers so the
199 * HW will be able to do fc autoneg once the cable is plugged in. If
200 * we link at 10G, the 1G advertisement is harmless and vice versa.
201 */
202 switch (hw->phy.media_type) {
203 case ixgbe_media_type_fiber:
204 case ixgbe_media_type_backplane:
205 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
206 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
207 break;
208 case ixgbe_media_type_copper:
209 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
210 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
211 break;
212 default:
213 break;
214 }
215
216 /*
217 * The possible values of fc.requested_mode are:
218 * 0: Flow control is completely disabled
219 * 1: Rx flow control is enabled (we can receive pause frames,
220 * but not send pause frames).
221 * 2: Tx flow control is enabled (we can send pause frames but
222 * we do not support receiving pause frames).
279 * the MAC will advertise clause 37 flow control.
280 */
281 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
282 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
283
284 /* Disable AN timeout */
285 if (hw->fc.strict_ieee)
286 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
287
288 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
289 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
290 }
291
292 /*
293 * AUTOC restart handles negotiation of 1G and 10G on backplane
294 * and copper. There is no need to set the PCS1GCTL register.
295 *
296 */
297 if (hw->phy.media_type == ixgbe_media_type_backplane) {
298 reg_bp |= IXGBE_AUTOC_AN_RESTART;
299 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
300 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
301 (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
302 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
303 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
304 }
305
306 DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
307 out:
308 return ret_val;
309 }
310
311 /**
312 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
313 * @hw: pointer to hardware structure
314 *
315 * Starts the hardware by filling the bus info structure and media type, clears
316 * all on chip counters, initializes receive address registers, multicast
317 * table, VLAN filter table, calls routine to set up link and flow control
318 * settings, and leaves transmit and receive units disabled and uninitialized
319 **/
662 if (ret_val) {
663 DEBUGOUT("NVM Read Error\n");
664 return ret_val;
665 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
666 DEBUGOUT("NVM Not supported\n");
667 return IXGBE_NOT_IMPLEMENTED;
668 }
669 *pba_num = (u32)(data << 16);
670
671 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
672 if (ret_val) {
673 DEBUGOUT("NVM Read Error\n");
674 return ret_val;
675 }
676 *pba_num |= data;
677
678 return IXGBE_SUCCESS;
679 }
680
681 /**
682 * ixgbe_get_mac_addr_generic - Generic get MAC address
683 * @hw: pointer to hardware structure
684 * @mac_addr: Adapter MAC address
685 *
686 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
687 * A reset of the adapter must be performed prior to calling this function
688 * in order for the MAC address to have been loaded from the EEPROM into RAR0
689 **/
690 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
691 {
692 u32 rar_high;
693 u32 rar_low;
694 u16 i;
695
696 DEBUGFUNC("ixgbe_get_mac_addr_generic");
697
698 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
699 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
700
701 for (i = 0; i < 4; i++)
1252 {
1253 u32 eerd;
1254 s32 status = IXGBE_SUCCESS;
1255 u32 i;
1256
1257 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1258
1259 hw->eeprom.ops.init_params(hw);
1260
1261 if (words == 0) {
1262 status = IXGBE_ERR_INVALID_ARGUMENT;
1263 goto out;
1264 }
1265
1266 if (offset >= hw->eeprom.word_size) {
1267 status = IXGBE_ERR_EEPROM;
1268 goto out;
1269 }
1270
1271 for (i = 0; i < words; i++) {
1272 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) +
1273 IXGBE_EEPROM_RW_REG_START;
1274
1275 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1276 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1277
1278 if (status == IXGBE_SUCCESS) {
1279 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1280 IXGBE_EEPROM_RW_REG_DATA);
1281 } else {
1282 DEBUGOUT("Eeprom read timed out\n");
1283 goto out;
1284 }
1285 }
1286 out:
1287 return status;
1288 }
1289
1290 /**
1291 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1292 * @hw: pointer to hardware structure
2702 ixgbe_link_speed speed;
2703 bool link_up;
2704
2705 DEBUGFUNC("ixgbe_fc_autoneg");
2706
2707 /*
2708 * AN should have completed when the cable was plugged in.
2709 * Look for reasons to bail out. Bail out if:
2710 * - FC autoneg is disabled, or if
2711 * - link is not up.
2712 */
2713 if (hw->fc.disable_fc_autoneg)
2714 goto out;
2715
2716 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2717 if (!link_up)
2718 goto out;
2719
2720 switch (hw->phy.media_type) {
2721 /* Autoneg flow control on fiber adapters */
2722 case ixgbe_media_type_fiber:
2723 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2724 ret_val = ixgbe_fc_autoneg_fiber(hw);
2725 break;
2726
2727 /* Autoneg flow control on backplane adapters */
2728 case ixgbe_media_type_backplane:
2729 ret_val = ixgbe_fc_autoneg_backplane(hw);
2730 break;
2731
2732 /* Autoneg flow control on copper adapters */
2733 case ixgbe_media_type_copper:
2734 if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
2735 ret_val = ixgbe_fc_autoneg_copper(hw);
2736 break;
2737
2738 default:
2739 break;
2740 }
2741
2948 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2949 {
2950 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
2951
2952 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2953
2954 return IXGBE_SUCCESS;
2955 }
2956
2957 /**
2958 * ixgbe_blink_led_start_generic - Blink LED based on index.
2959 * @hw: pointer to hardware structure
2960 * @index: led number to blink
2961 **/
2962 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2963 {
2964 ixgbe_link_speed speed = 0;
2965 bool link_up = 0;
2966 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2967 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2968
2969 DEBUGFUNC("ixgbe_blink_led_start_generic");
2970
2971 /*
2972 * Link must be up to auto-blink the LEDs;
2973 * Force it if link is down.
2974 */
2975 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2976
2977 if (!link_up) {
2978 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2979 autoc_reg |= IXGBE_AUTOC_FLU;
2980 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2981 IXGBE_WRITE_FLUSH(hw);
2982 msec_delay(10);
2983 }
2984
2985 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2986 led_reg |= IXGBE_LED_BLINK(index);
2987 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2988 IXGBE_WRITE_FLUSH(hw);
2989
2990 return IXGBE_SUCCESS;
2991 }
2992
2993 /**
2994 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2995 * @hw: pointer to hardware structure
2996 * @index: led number to stop blinking
2997 **/
2998 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2999 {
3000 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3001 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3002
3003 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3004
3005
3006 autoc_reg &= ~IXGBE_AUTOC_FLU;
3007 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3008 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3009
3010 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3011 led_reg &= ~IXGBE_LED_BLINK(index);
3012 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3013 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3014 IXGBE_WRITE_FLUSH(hw);
3015
3016 return IXGBE_SUCCESS;
3017 }
3018
3019 /**
3020 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3021 * @hw: pointer to hardware structure
3022 * @san_mac_offset: SAN MAC address offset
3023 *
3024 * This function will read the EEPROM location for the SAN MAC address
3025 * pointer, and returns the value at that location. This is used in both
3026 * get and set mac_addr routines.
3027 **/
3028 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3029 u16 *san_mac_offset)
3030 {
3031 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3032
3033 /*
3034 * First read the EEPROM pointer to see if the MAC addresses are
3035 * available.
3036 */
3865 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3866 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
3867 }
3868
3869 for (i = 0; i < hw->mac.max_rx_queues; i++) {
3870 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
3871 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
3872 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
3873 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
3874 }
3875
3876 }
3877
3878 /**
3879 * ixgbe_calculate_checksum - Calculate checksum for buffer
3880 * @buffer: pointer to EEPROM
3881 * @length: size of EEPROM to calculate a checksum for
3882 * Calculates the checksum for some buffer on a specified length. The
3883 * checksum calculated is returned.
3884 **/
3885 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
3886 {
3887 u32 i;
3888 u8 sum = 0;
3889
3890 DEBUGFUNC("ixgbe_calculate_checksum");
3891
3892 if (!buffer)
3893 return 0;
3894
3895 for (i = 0; i < length; i++)
3896 sum += buffer[i];
3897
3898 return (u8) (0 - sum);
3899 }
3900
3901 /**
3902 * ixgbe_host_interface_command - Issue command to manageability block
3903 * @hw: pointer to the HW structure
3904 * @buffer: contains the command to write and where the return status will
3905 * be placed
3906 * @length: length of buffer, must be multiple of 4 bytes
3907 *
3908 * Communicates with the manageability block. On success return IXGBE_SUCCESS
3909 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
3910 **/
3911 static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
3912 u32 length)
3913 {
3914 u32 hicr, i, bi;
3915 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
3916 u8 buf_len, dword_len;
3917
3918 s32 ret_val = IXGBE_SUCCESS;
3919
3920 DEBUGFUNC("ixgbe_host_interface_command");
3921
3922 if (length == 0 || length & 0x3 ||
3923 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
3924 DEBUGOUT("Buffer length failure.\n");
3925 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
3926 goto out;
3927 }
3928
3929 /* Check that the host interface is enabled. */
3930 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
3931 if ((hicr & IXGBE_HICR_EN) == 0) {
|
1 /******************************************************************************
2
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
130 /* Flow Control */
131 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
132
133 /* Link */
134 mac->ops.get_link_capabilities = NULL;
135 mac->ops.setup_link = NULL;
136 mac->ops.check_link = NULL;
137
138 return IXGBE_SUCCESS;
139 }
140
141 /**
142 * ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
143 * control
144 * @hw: pointer to hardware structure
145 *
146 * There are several phys that do not support autoneg flow control. This
147 * function check the device id to see if the associated phy supports
148 * autoneg flow control.
149 **/
150 s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
151 {
152
153 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
154
155 switch (hw->device_id) {
156 case IXGBE_DEV_ID_82599_T3_LOM:
157 case IXGBE_DEV_ID_X540T:
158 return IXGBE_SUCCESS;
159 default:
160 return IXGBE_ERR_FC_NOT_SUPPORTED;
161 }
162 }
163
164 /**
165 * ixgbe_setup_fc - Set up flow control
166 * @hw: pointer to hardware structure
167 *
168 * Called at init time to set up flow control.
169 **/
170 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
171 {
172 s32 ret_val = IXGBE_SUCCESS;
173 u32 reg = 0, reg_bp = 0;
174 u16 reg_cu = 0;
175 bool got_lock = FALSE;
176
177 DEBUGFUNC("ixgbe_setup_fc");
178
179 /*
180 * Validate the requested mode. Strict IEEE mode does not allow
181 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
182 */
183 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
184 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
185 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
186 goto out;
187 }
188
189 /*
190 * 10gig parts do not have a word in the EEPROM to determine the
191 * default flow control setting, so we explicitly set it to full.
192 */
193 if (hw->fc.requested_mode == ixgbe_fc_default)
194 hw->fc.requested_mode = ixgbe_fc_full;
195
196 /*
197 * Set up the 1G and 10G flow control advertisement registers so the
198 * HW will be able to do fc autoneg once the cable is plugged in. If
199 * we link at 10G, the 1G advertisement is harmless and vice versa.
200 */
201 switch (hw->phy.media_type) {
202 case ixgbe_media_type_fiber_fixed:
203 case ixgbe_media_type_fiber:
204 case ixgbe_media_type_backplane:
205 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
206 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
207 break;
208 case ixgbe_media_type_copper:
209 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
210 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
211 break;
212 default:
213 break;
214 }
215
216 /*
217 * The possible values of fc.requested_mode are:
218 * 0: Flow control is completely disabled
219 * 1: Rx flow control is enabled (we can receive pause frames,
220 * but not send pause frames).
221 * 2: Tx flow control is enabled (we can send pause frames but
222 * we do not support receiving pause frames).
279 * the MAC will advertise clause 37 flow control.
280 */
281 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
282 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
283
284 /* Disable AN timeout */
285 if (hw->fc.strict_ieee)
286 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
287
288 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
289 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
290 }
291
292 /*
293 * AUTOC restart handles negotiation of 1G and 10G on backplane
294 * and copper. There is no need to set the PCS1GCTL register.
295 *
296 */
297 if (hw->phy.media_type == ixgbe_media_type_backplane) {
298 reg_bp |= IXGBE_AUTOC_AN_RESTART;
299 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
300 * LESM is on, likewise reset_pipeline requries the lock as
301 * it also writes AUTOC.
302 */
303 if ((hw->mac.type == ixgbe_mac_82599EB) &&
304 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
305 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
306 IXGBE_GSSR_MAC_CSR_SM);
307 if (ret_val != IXGBE_SUCCESS) {
308 ret_val = IXGBE_ERR_SWFW_SYNC;
309 goto out;
310 }
311 got_lock = TRUE;
312 }
313
314 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
315 if (hw->mac.type == ixgbe_mac_82599EB)
316 (void) ixgbe_reset_pipeline_82599(hw);
317
318 if (got_lock)
319 hw->mac.ops.release_swfw_sync(hw,
320 IXGBE_GSSR_MAC_CSR_SM);
321 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
322 (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
323 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
324 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
325 }
326
327 DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
328 out:
329 return ret_val;
330 }
331
332 /**
333 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
334 * @hw: pointer to hardware structure
335 *
336 * Starts the hardware by filling the bus info structure and media type, clears
337 * all on chip counters, initializes receive address registers, multicast
338 * table, VLAN filter table, calls routine to set up link and flow control
339 * settings, and leaves transmit and receive units disabled and uninitialized
340 **/
683 if (ret_val) {
684 DEBUGOUT("NVM Read Error\n");
685 return ret_val;
686 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
687 DEBUGOUT("NVM Not supported\n");
688 return IXGBE_NOT_IMPLEMENTED;
689 }
690 *pba_num = (u32)(data << 16);
691
692 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
693 if (ret_val) {
694 DEBUGOUT("NVM Read Error\n");
695 return ret_val;
696 }
697 *pba_num |= data;
698
699 return IXGBE_SUCCESS;
700 }
701
702 /**
703 * ixgbe_read_pba_raw
704 * @hw: pointer to the HW structure
705 * @eeprom_buf: optional pointer to EEPROM image
706 * @eeprom_buf_size: size of EEPROM image in words
707 * @max_pba_block_size: PBA block size limit
708 * @pba: pointer to output PBA structure
709 *
710 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
711 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
712 *
713 **/
714 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
715 u32 eeprom_buf_size, u16 max_pba_block_size,
716 struct ixgbe_pba *pba)
717 {
718 s32 ret_val;
719 u16 pba_block_size;
720
721 if (pba == NULL)
722 return IXGBE_ERR_PARAM;
723
724 if (eeprom_buf == NULL) {
725 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
726 &pba->word[0]);
727 if (ret_val)
728 return ret_val;
729 } else {
730 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
731 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
732 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
733 } else {
734 return IXGBE_ERR_PARAM;
735 }
736 }
737
738 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
739 if (pba->pba_block == NULL)
740 return IXGBE_ERR_PARAM;
741
742 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
743 eeprom_buf_size,
744 &pba_block_size);
745 if (ret_val)
746 return ret_val;
747
748 if (pba_block_size > max_pba_block_size)
749 return IXGBE_ERR_PARAM;
750
751 if (eeprom_buf == NULL) {
752 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
753 pba_block_size,
754 pba->pba_block);
755 if (ret_val)
756 return ret_val;
757 } else {
758 if (eeprom_buf_size > (u32)(pba->word[1] +
759 pba->pba_block[0])) {
760 (void) memcpy(pba->pba_block,
761 &eeprom_buf[pba->word[1]],
762 pba_block_size * sizeof(u16));
763 } else {
764 return IXGBE_ERR_PARAM;
765 }
766 }
767 }
768
769 return IXGBE_SUCCESS;
770 }
771
772 /**
773 * ixgbe_write_pba_raw
774 * @hw: pointer to the HW structure
775 * @eeprom_buf: optional pointer to EEPROM image
776 * @eeprom_buf_size: size of EEPROM image in words
777 * @pba: pointer to PBA structure
778 *
779 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
780 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
781 *
782 **/
783 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
784 u32 eeprom_buf_size, struct ixgbe_pba *pba)
785 {
786 s32 ret_val;
787
788 if (pba == NULL)
789 return IXGBE_ERR_PARAM;
790
791 if (eeprom_buf == NULL) {
792 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
793 &pba->word[0]);
794 if (ret_val)
795 return ret_val;
796 } else {
797 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
798 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
799 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
800 } else {
801 return IXGBE_ERR_PARAM;
802 }
803 }
804
805 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
806 if (pba->pba_block == NULL)
807 return IXGBE_ERR_PARAM;
808
809 if (eeprom_buf == NULL) {
810 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
811 pba->pba_block[0],
812 pba->pba_block);
813 if (ret_val)
814 return ret_val;
815 } else {
816 if (eeprom_buf_size > (u32)(pba->word[1] +
817 pba->pba_block[0])) {
818 (void) memcpy(&eeprom_buf[pba->word[1]],
819 pba->pba_block,
820 pba->pba_block[0] * sizeof(u16));
821 } else {
822 return IXGBE_ERR_PARAM;
823 }
824 }
825 }
826
827 return IXGBE_SUCCESS;
828 }
829
830 /**
831 * ixgbe_get_pba_block_size
832 * @hw: pointer to the HW structure
833 * @eeprom_buf: optional pointer to EEPROM image
834 * @eeprom_buf_size: size of EEPROM image in words
835 * @pba_data_size: pointer to output variable
836 *
837 * Returns the size of the PBA block in words. Function operates on EEPROM
838 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
839 * EEPROM device.
840 *
841 **/
842 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
843 u32 eeprom_buf_size, u16 *pba_block_size)
844 {
845 s32 ret_val;
846 u16 pba_word[2];
847 u16 length;
848
849 DEBUGFUNC("ixgbe_get_pba_block_size");
850
851 if (eeprom_buf == NULL) {
852 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
853 &pba_word[0]);
854 if (ret_val)
855 return ret_val;
856 } else {
857 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
858 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
859 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
860 } else {
861 return IXGBE_ERR_PARAM;
862 }
863 }
864
865 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
866 if (eeprom_buf == NULL) {
867 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
868 &length);
869 if (ret_val)
870 return ret_val;
871 } else {
872 if (eeprom_buf_size > pba_word[1])
873 length = eeprom_buf[pba_word[1] + 0];
874 else
875 return IXGBE_ERR_PARAM;
876 }
877
878 if (length == 0xFFFF || length == 0)
879 return IXGBE_ERR_PBA_SECTION;
880 } else {
881 /* PBA number in legacy format, there is no PBA Block. */
882 length = 0;
883 }
884
885 if (pba_block_size != NULL)
886 *pba_block_size = length;
887
888 return IXGBE_SUCCESS;
889 }
890
891 /**
892 * ixgbe_get_mac_addr_generic - Generic get MAC address
893 * @hw: pointer to hardware structure
894 * @mac_addr: Adapter MAC address
895 *
896 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
897 * A reset of the adapter must be performed prior to calling this function
898 * in order for the MAC address to have been loaded from the EEPROM into RAR0
899 **/
900 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
901 {
902 u32 rar_high;
903 u32 rar_low;
904 u16 i;
905
906 DEBUGFUNC("ixgbe_get_mac_addr_generic");
907
908 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
909 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
910
911 for (i = 0; i < 4; i++)
1462 {
1463 u32 eerd;
1464 s32 status = IXGBE_SUCCESS;
1465 u32 i;
1466
1467 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1468
1469 hw->eeprom.ops.init_params(hw);
1470
1471 if (words == 0) {
1472 status = IXGBE_ERR_INVALID_ARGUMENT;
1473 goto out;
1474 }
1475
1476 if (offset >= hw->eeprom.word_size) {
1477 status = IXGBE_ERR_EEPROM;
1478 goto out;
1479 }
1480
1481 for (i = 0; i < words; i++) {
1482 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1483 IXGBE_EEPROM_RW_REG_START;
1484
1485 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1486 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1487
1488 if (status == IXGBE_SUCCESS) {
1489 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1490 IXGBE_EEPROM_RW_REG_DATA);
1491 } else {
1492 DEBUGOUT("Eeprom read timed out\n");
1493 goto out;
1494 }
1495 }
1496 out:
1497 return status;
1498 }
1499
1500 /**
1501 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1502 * @hw: pointer to hardware structure
2912 ixgbe_link_speed speed;
2913 bool link_up;
2914
2915 DEBUGFUNC("ixgbe_fc_autoneg");
2916
2917 /*
2918 * AN should have completed when the cable was plugged in.
2919 * Look for reasons to bail out. Bail out if:
2920 * - FC autoneg is disabled, or if
2921 * - link is not up.
2922 */
2923 if (hw->fc.disable_fc_autoneg)
2924 goto out;
2925
2926 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2927 if (!link_up)
2928 goto out;
2929
2930 switch (hw->phy.media_type) {
2931 /* Autoneg flow control on fiber adapters */
2932 case ixgbe_media_type_fiber_fixed:
2933 case ixgbe_media_type_fiber:
2934 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2935 ret_val = ixgbe_fc_autoneg_fiber(hw);
2936 break;
2937
2938 /* Autoneg flow control on backplane adapters */
2939 case ixgbe_media_type_backplane:
2940 ret_val = ixgbe_fc_autoneg_backplane(hw);
2941 break;
2942
2943 /* Autoneg flow control on copper adapters */
2944 case ixgbe_media_type_copper:
2945 if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
2946 ret_val = ixgbe_fc_autoneg_copper(hw);
2947 break;
2948
2949 default:
2950 break;
2951 }
2952
3159 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3160 {
3161 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3162
3163 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
3164
3165 return IXGBE_SUCCESS;
3166 }
3167
3168 /**
3169 * ixgbe_blink_led_start_generic - Blink LED based on index.
3170 * @hw: pointer to hardware structure
3171 * @index: led number to blink
3172 **/
3173 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3174 {
3175 ixgbe_link_speed speed = 0;
3176 bool link_up = 0;
3177 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3178 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3179 s32 ret_val = IXGBE_SUCCESS;
3180
3181 DEBUGFUNC("ixgbe_blink_led_start_generic");
3182
3183 /*
3184 * Link must be up to auto-blink the LEDs;
3185 * Force it if link is down.
3186 */
3187 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3188
3189 if (!link_up) {
3190 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
3191 * LESM is on.
3192 */
3193 bool got_lock = FALSE;
3194 if ((hw->mac.type == ixgbe_mac_82599EB) &&
3195 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3196 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
3197 IXGBE_GSSR_MAC_CSR_SM);
3198 if (ret_val != IXGBE_SUCCESS) {
3199 ret_val = IXGBE_ERR_SWFW_SYNC;
3200 goto out;
3201 }
3202 got_lock = TRUE;
3203 }
3204
3205 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3206 autoc_reg |= IXGBE_AUTOC_FLU;
3207 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3208 IXGBE_WRITE_FLUSH(hw);
3209
3210 if (got_lock)
3211 hw->mac.ops.release_swfw_sync(hw,
3212 IXGBE_GSSR_MAC_CSR_SM);
3213 msec_delay(10);
3214 }
3215
3216 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3217 led_reg |= IXGBE_LED_BLINK(index);
3218 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3219 IXGBE_WRITE_FLUSH(hw);
3220
3221 out:
3222 return ret_val;
3223 }
3224
3225 /**
3226 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3227 * @hw: pointer to hardware structure
3228 * @index: led number to stop blinking
3229 **/
3230 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3231 {
3232 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3233 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3234 s32 ret_val = IXGBE_SUCCESS;
3235 bool got_lock = FALSE;
3236
3237 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3238 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
3239 * LESM is on.
3240 */
3241 if ((hw->mac.type == ixgbe_mac_82599EB) &&
3242 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3243 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
3244 IXGBE_GSSR_MAC_CSR_SM);
3245 if (ret_val != IXGBE_SUCCESS) {
3246 ret_val = IXGBE_ERR_SWFW_SYNC;
3247 goto out;
3248 }
3249 got_lock = TRUE;
3250 }
3251
3252
3253 autoc_reg &= ~IXGBE_AUTOC_FLU;
3254 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3255 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3256
3257 if (hw->mac.type == ixgbe_mac_82599EB)
3258 (void) ixgbe_reset_pipeline_82599(hw);
3259
3260 if (got_lock)
3261 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3262
3263 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3264 led_reg &= ~IXGBE_LED_BLINK(index);
3265 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3266 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3267 IXGBE_WRITE_FLUSH(hw);
3268
3269 out:
3270 return ret_val;
3271 }
3272
3273 /**
3274 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3275 * @hw: pointer to hardware structure
3276 * @san_mac_offset: SAN MAC address offset
3277 *
3278 * This function will read the EEPROM location for the SAN MAC address
3279 * pointer, and returns the value at that location. This is used in both
3280 * get and set mac_addr routines.
3281 **/
3282 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3283 u16 *san_mac_offset)
3284 {
3285 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3286
3287 /*
3288 * First read the EEPROM pointer to see if the MAC addresses are
3289 * available.
3290 */
4119 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4120 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4121 }
4122
4123 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4124 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4125 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4126 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4127 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4128 }
4129
4130 }
4131
4132 /**
4133 * ixgbe_calculate_checksum - Calculate checksum for buffer
4134 * @buffer: pointer to EEPROM
4135 * @length: size of EEPROM to calculate a checksum for
4136 * Calculates the checksum for some buffer on a specified length. The
4137 * checksum calculated is returned.
4138 **/
4139 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4140 {
4141 u32 i;
4142 u8 sum = 0;
4143
4144 DEBUGFUNC("ixgbe_calculate_checksum");
4145
4146 if (!buffer)
4147 return 0;
4148
4149 for (i = 0; i < length; i++)
4150 sum += buffer[i];
4151
4152 return (u8) (0 - sum);
4153 }
4154
4155 /**
4156 * ixgbe_host_interface_command - Issue command to manageability block
4157 * @hw: pointer to the HW structure
4158 * @buffer: contains the command to write and where the return status will
4159 * be placed
4160 * @length: length of buffer, must be multiple of 4 bytes
4161 *
4162 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4163 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4164 **/
4165 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4166 u32 length)
4167 {
4168 u32 hicr, i, bi;
4169 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4170 u8 buf_len, dword_len;
4171
4172 s32 ret_val = IXGBE_SUCCESS;
4173
4174 DEBUGFUNC("ixgbe_host_interface_command");
4175
4176 if (length == 0 || length & 0x3 ||
4177 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4178 DEBUGOUT("Buffer length failure.\n");
4179 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4180 goto out;
4181 }
4182
4183 /* Check that the host interface is enabled. */
4184 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4185 if ((hicr & IXGBE_HICR_EN) == 0) {
|