1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
55 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw);
56 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);
57 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);
58 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
59 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num);
60 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);
61
62 s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
63 s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
64 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
65 u16 *phy_data);
66 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
67 u16 phy_data);
68
69 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
70 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
71 ixgbe_link_speed *speed,
72 bool *link_up);
73 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,
74 ixgbe_link_speed speed,
75 bool autoneg,
76 bool autoneg_wait_to_complete);
77 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw);
78 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw);
79 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw);
80 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
81 bool autoneg, bool autoneg_wait_to_complete);
82 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
83 bool *link_up, bool link_up_wait_to_complete);
84 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
85 bool *autoneg);
86 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
87 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
88 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);
89 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);
90
91 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);
92 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);
93 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
94 u16 words, u16 *data);
95 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
96 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
97 u16 words, u16 *data);
98
99 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
100 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);
101
142 union ixgbe_atr_hash_dword input,
143 union ixgbe_atr_hash_dword common,
144 u8 queue);
145 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
146 union ixgbe_atr_input *input_mask);
147 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
148 union ixgbe_atr_input *input,
149 u16 soft_id, u8 queue);
150 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
151 union ixgbe_atr_input *input,
152 u16 soft_id);
153 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
154 union ixgbe_atr_input *input,
155 union ixgbe_atr_input *mask,
156 u16 soft_id,
157 u8 queue);
158 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
159 union ixgbe_atr_input *mask);
160 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
161 union ixgbe_atr_hash_dword common);
162 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
163 u8 *data);
164 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
165 u8 data);
166 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);
167 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
168 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
169 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);
170 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
171 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
172 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
173 u16 *wwpn_prefix);
174 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);
175
176 #endif /* _IXGBE_API_H_ */
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1 /******************************************************************************
2
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
55 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw);
56 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw);
57 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw);
58 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw);
59 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num);
60 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);
61
62 s32 ixgbe_identify_phy(struct ixgbe_hw *hw);
63 s32 ixgbe_reset_phy(struct ixgbe_hw *hw);
64 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
65 u16 *phy_data);
66 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
67 u16 phy_data);
68
69 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw);
70 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw,
71 ixgbe_link_speed *speed,
72 bool *link_up);
73 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw,
74 ixgbe_link_speed speed,
75 bool autoneg_wait_to_complete);
76 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw);
77 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw);
78 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw);
79 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
80 bool autoneg_wait_to_complete);
81 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
82 bool *link_up, bool link_up_wait_to_complete);
83 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
84 bool *autoneg);
85 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index);
86 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index);
87 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index);
88 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index);
89
90 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw);
91 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data);
92 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
93 u16 words, u16 *data);
94 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data);
95 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
96 u16 words, u16 *data);
97
98 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val);
99 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw);
100
141 union ixgbe_atr_hash_dword input,
142 union ixgbe_atr_hash_dword common,
143 u8 queue);
144 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
145 union ixgbe_atr_input *input_mask);
146 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
147 union ixgbe_atr_input *input,
148 u16 soft_id, u8 queue);
149 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
150 union ixgbe_atr_input *input,
151 u16 soft_id);
152 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
153 union ixgbe_atr_input *input,
154 union ixgbe_atr_input *mask,
155 u16 soft_id,
156 u8 queue);
157 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
158 union ixgbe_atr_input *mask);
159 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
160 union ixgbe_atr_hash_dword common);
161 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
162 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
163 u8 *data);
164 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
165 u8 data);
166 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);
167 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
168 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);
169 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);
170 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
171 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);
172 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
173 u16 *wwpn_prefix);
174 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);
175
176 #endif /* _IXGBE_API_H_ */
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