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Import some changes from FreeBSD (details later, this is quick-n-dirty for now).
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--- old/usr/src/uts/common/io/ixgbe/ixgbe_api.c
+++ new/usr/src/uts/common/io/ixgbe/ixgbe_api.c
1 1 /******************************************************************************
2 2
3 - Copyright (c) 2001-2012, Intel Corporation
3 + Copyright (c) 2001-2013, Intel Corporation
4 4 All rights reserved.
5 5
6 6 Redistribution and use in source and binary forms, with or without
7 7 modification, are permitted provided that the following conditions are met:
8 8
9 9 1. Redistributions of source code must retain the above copyright notice,
10 10 this list of conditions and the following disclaimer.
11 11
12 12 2. Redistributions in binary form must reproduce the above copyright
13 13 notice, this list of conditions and the following disclaimer in the
14 14 documentation and/or other materials provided with the distribution.
15 15
16 16 3. Neither the name of the Intel Corporation nor the names of its
17 17 contributors may be used to endorse or promote products derived from
18 18 this software without specific prior written permission.
19 19
20 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 30 POSSIBILITY OF SUCH DAMAGE.
31 31
32 32 ******************************************************************************/
33 33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_api.c,v 1.13 2012/07/05 20:51:44 jfv Exp $*/
34 34
35 35 #include "ixgbe_api.h"
36 36 #include "ixgbe_common.h"
37 37
38 38 /**
39 39 * ixgbe_init_shared_code - Initialize the shared code
40 40 * @hw: pointer to hardware structure
41 41 *
42 42 * This will assign function pointers and assign the MAC type and PHY code.
43 43 * Does not touch the hardware. This function must be called prior to any
44 44 * other function in the shared code. The ixgbe_hw structure should be
45 45 * memset to 0 prior to calling this function. The following fields in
46 46 * hw structure should be filled in prior to calling this function:
47 47 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
48 48 * subsystem_vendor_id, and revision_id
49 49 **/
50 50 s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
51 51 {
52 52 s32 status;
53 53
54 54 DEBUGFUNC("ixgbe_init_shared_code");
55 55
56 56 /*
57 57 * Set the mac type
58 58 */
59 59 status = ixgbe_set_mac_type(hw);
60 60 if (status != IXGBE_SUCCESS)
61 61 return (status);
62 62
63 63 switch (hw->mac.type) {
64 64 case ixgbe_mac_82598EB:
65 65 status = ixgbe_init_ops_82598(hw);
66 66 break;
67 67 case ixgbe_mac_82599EB:
68 68 status = ixgbe_init_ops_82599(hw);
69 69 break;
70 70 case ixgbe_mac_X540:
71 71 status = ixgbe_init_ops_X540(hw);
72 72 break;
73 73 default:
74 74 status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
75 75 break;
76 76 }
77 77
78 78 return status;
79 79 }
80 80
81 81 /**
82 82 * ixgbe_set_mac_type - Sets MAC type
83 83 * @hw: pointer to the HW structure
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84 84 *
85 85 * This function sets the mac type of the adapter based on the
86 86 * vendor ID and device ID stored in the hw structure.
87 87 **/
88 88 s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)
89 89 {
90 90 s32 ret_val = IXGBE_SUCCESS;
91 91
92 92 DEBUGFUNC("ixgbe_set_mac_type\n");
93 93
94 - if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
95 - switch (hw->device_id) {
96 - case IXGBE_DEV_ID_82598:
97 - case IXGBE_DEV_ID_82598_BX:
98 - case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
99 - case IXGBE_DEV_ID_82598AF_DUAL_PORT:
100 - case IXGBE_DEV_ID_82598AT:
101 - case IXGBE_DEV_ID_82598AT2:
102 - case IXGBE_DEV_ID_82598EB_CX4:
103 - case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
104 - case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
105 - case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
106 - case IXGBE_DEV_ID_82598EB_XF_LR:
107 - case IXGBE_DEV_ID_82598EB_SFP_LOM:
108 - hw->mac.type = ixgbe_mac_82598EB;
109 - break;
110 - case IXGBE_DEV_ID_82599_KX4:
111 - case IXGBE_DEV_ID_82599_KX4_MEZZ:
112 - case IXGBE_DEV_ID_82599_XAUI_LOM:
113 - case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
114 - case IXGBE_DEV_ID_82599_KR:
115 - case IXGBE_DEV_ID_82599_SFP:
116 - case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
117 - case IXGBE_DEV_ID_82599_SFP_FCOE:
118 - case IXGBE_DEV_ID_82599_SFP_EM:
119 - case IXGBE_DEV_ID_82599_SFP_SF2:
120 - case IXGBE_DEV_ID_82599EN_SFP:
121 - case IXGBE_DEV_ID_82599_CX4:
122 - case IXGBE_DEV_ID_82599_T3_LOM:
123 - hw->mac.type = ixgbe_mac_82599EB;
124 - break;
125 - case IXGBE_DEV_ID_82599_VF:
126 - hw->mac.type = ixgbe_mac_82599_vf;
127 - break;
128 - case IXGBE_DEV_ID_X540_VF:
129 - hw->mac.type = ixgbe_mac_X540_vf;
130 - break;
131 - case IXGBE_DEV_ID_X540T:
132 - case IXGBE_DEV_ID_X540T1:
133 - hw->mac.type = ixgbe_mac_X540;
134 - break;
135 - default:
136 - ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
137 - break;
138 - }
139 - } else {
94 + switch (hw->device_id) {
95 + case IXGBE_DEV_ID_82598:
96 + case IXGBE_DEV_ID_82598_BX:
97 + case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
98 + case IXGBE_DEV_ID_82598AF_DUAL_PORT:
99 + case IXGBE_DEV_ID_82598AT:
100 + case IXGBE_DEV_ID_82598AT2:
101 + case IXGBE_DEV_ID_82598EB_CX4:
102 + case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
103 + case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
104 + case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
105 + case IXGBE_DEV_ID_82598EB_XF_LR:
106 + case IXGBE_DEV_ID_82598EB_SFP_LOM:
107 + hw->mac.type = ixgbe_mac_82598EB;
108 + break;
109 + case IXGBE_DEV_ID_82599_KX4:
110 + case IXGBE_DEV_ID_82599_KX4_MEZZ:
111 + case IXGBE_DEV_ID_82599_XAUI_LOM:
112 + case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
113 + case IXGBE_DEV_ID_82599_KR:
114 + case IXGBE_DEV_ID_82599_SFP:
115 + case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
116 + case IXGBE_DEV_ID_82599_SFP_FCOE:
117 + case IXGBE_DEV_ID_82599_SFP_EM:
118 + case IXGBE_DEV_ID_82599_SFP_SF2:
119 + case IXGBE_DEV_ID_82599_SFP_SF_QP:
120 + case IXGBE_DEV_ID_82599EN_SFP:
121 + case IXGBE_DEV_ID_82599_CX4:
122 + case IXGBE_DEV_ID_82599_BYPASS:
123 + case IXGBE_DEV_ID_82599_T3_LOM:
124 + hw->mac.type = ixgbe_mac_82599EB;
125 + break;
126 + case IXGBE_DEV_ID_82599_VF:
127 + case IXGBE_DEV_ID_82599_VF_HV:
128 + hw->mac.type = ixgbe_mac_82599_vf;
129 + break;
130 + case IXGBE_DEV_ID_X540_VF:
131 + case IXGBE_DEV_ID_X540_VF_HV:
132 + hw->mac.type = ixgbe_mac_X540_vf;
133 + break;
134 + case IXGBE_DEV_ID_X540T:
135 + case IXGBE_DEV_ID_X540_BYPASS:
136 + hw->mac.type = ixgbe_mac_X540;
137 + break;
138 + default:
140 139 ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
140 + break;
141 141 }
142 142
143 143 DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
144 144 hw->mac.type, ret_val);
145 145 return ret_val;
146 146 }
147 147
148 148 /**
149 149 * ixgbe_init_hw - Initialize the hardware
150 150 * @hw: pointer to hardware structure
151 151 *
152 152 * Initialize the hardware by resetting and then starting the hardware
153 153 **/
154 154 s32 ixgbe_init_hw(struct ixgbe_hw *hw)
155 155 {
156 156 return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw),
157 157 IXGBE_NOT_IMPLEMENTED);
158 158 }
159 159
160 160 /**
161 161 * ixgbe_reset_hw - Performs a hardware reset
162 162 * @hw: pointer to hardware structure
163 163 *
164 164 * Resets the hardware by resetting the transmit and receive units, masks and
165 165 * clears all interrupts, performs a PHY reset, and performs a MAC reset
166 166 **/
167 167 s32 ixgbe_reset_hw(struct ixgbe_hw *hw)
168 168 {
169 169 return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw),
170 170 IXGBE_NOT_IMPLEMENTED);
171 171 }
172 172
173 173 /**
174 174 * ixgbe_start_hw - Prepares hardware for Rx/Tx
175 175 * @hw: pointer to hardware structure
176 176 *
177 177 * Starts the hardware by filling the bus info structure and media type,
178 178 * clears all on chip counters, initializes receive address registers,
179 179 * multicast table, VLAN filter table, calls routine to setup link and
180 180 * flow control settings, and leaves transmit and receive units disabled
181 181 * and uninitialized.
182 182 **/
183 183 s32 ixgbe_start_hw(struct ixgbe_hw *hw)
184 184 {
185 185 return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw),
186 186 IXGBE_NOT_IMPLEMENTED);
187 187 }
188 188
189 189 /**
190 190 * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering,
191 191 * which is disabled by default in ixgbe_start_hw();
192 192 *
193 193 * @hw: pointer to hardware structure
194 194 *
195 195 * Enable relaxed ordering;
196 196 **/
197 197 void ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw)
198 198 {
199 199 if (hw->mac.ops.enable_relaxed_ordering)
200 200 hw->mac.ops.enable_relaxed_ordering(hw);
201 201 }
202 202
203 203 /**
204 204 * ixgbe_clear_hw_cntrs - Clear hardware counters
205 205 * @hw: pointer to hardware structure
206 206 *
207 207 * Clears all hardware statistics counters by reading them from the hardware
208 208 * Statistics counters are clear on read.
209 209 **/
210 210 s32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw)
211 211 {
212 212 return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw),
213 213 IXGBE_NOT_IMPLEMENTED);
214 214 }
215 215
216 216 /**
217 217 * ixgbe_get_media_type - Get media type
218 218 * @hw: pointer to hardware structure
219 219 *
220 220 * Returns the media type (fiber, copper, backplane)
221 221 **/
222 222 enum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw)
223 223 {
224 224 return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw),
225 225 ixgbe_media_type_unknown);
226 226 }
227 227
228 228 /**
229 229 * ixgbe_get_mac_addr - Get MAC address
230 230 * @hw: pointer to hardware structure
231 231 * @mac_addr: Adapter MAC address
232 232 *
233 233 * Reads the adapter's MAC address from the first Receive Address Register
234 234 * (RAR0) A reset of the adapter must have been performed prior to calling
235 235 * this function in order for the MAC address to have been loaded from the
236 236 * EEPROM into RAR0
237 237 **/
238 238 s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)
239 239 {
240 240 return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr,
241 241 (hw, mac_addr), IXGBE_NOT_IMPLEMENTED);
242 242 }
243 243
244 244 /**
245 245 * ixgbe_get_san_mac_addr - Get SAN MAC address
246 246 * @hw: pointer to hardware structure
247 247 * @san_mac_addr: SAN MAC address
248 248 *
249 249 * Reads the SAN MAC address from the EEPROM, if it's available. This is
250 250 * per-port, so set_lan_id() must be called before reading the addresses.
251 251 **/
252 252 s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
253 253 {
254 254 return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr,
255 255 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
256 256 }
257 257
258 258 /**
259 259 * ixgbe_set_san_mac_addr - Write a SAN MAC address
260 260 * @hw: pointer to hardware structure
261 261 * @san_mac_addr: SAN MAC address
262 262 *
263 263 * Writes A SAN MAC address to the EEPROM.
264 264 **/
265 265 s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)
266 266 {
267 267 return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr,
268 268 (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED);
269 269 }
270 270
271 271 /**
272 272 * ixgbe_get_device_caps - Get additional device capabilities
273 273 * @hw: pointer to hardware structure
274 274 * @device_caps: the EEPROM word for device capabilities
275 275 *
276 276 * Reads the extra device capabilities from the EEPROM
277 277 **/
278 278 s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps)
279 279 {
280 280 return ixgbe_call_func(hw, hw->mac.ops.get_device_caps,
281 281 (hw, device_caps), IXGBE_NOT_IMPLEMENTED);
282 282 }
283 283
284 284 /**
285 285 * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM
286 286 * @hw: pointer to hardware structure
287 287 * @wwnn_prefix: the alternative WWNN prefix
288 288 * @wwpn_prefix: the alternative WWPN prefix
289 289 *
290 290 * This function will read the EEPROM from the alternative SAN MAC address
291 291 * block to check the support for the alternative WWNN/WWPN prefix support.
292 292 **/
293 293 s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,
294 294 u16 *wwpn_prefix)
295 295 {
296 296 return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix,
297 297 (hw, wwnn_prefix, wwpn_prefix),
298 298 IXGBE_NOT_IMPLEMENTED);
299 299 }
300 300
301 301 /**
302 302 * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM
303 303 * @hw: pointer to hardware structure
304 304 * @bs: the fcoe boot status
305 305 *
306 306 * This function will read the FCOE boot status from the iSCSI FCOE block
307 307 **/
308 308 s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs)
309 309 {
310 310 return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status,
311 311 (hw, bs),
312 312 IXGBE_NOT_IMPLEMENTED);
313 313 }
314 314
315 315 /**
316 316 * ixgbe_get_bus_info - Set PCI bus info
317 317 * @hw: pointer to hardware structure
318 318 *
319 319 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
320 320 **/
321 321 s32 ixgbe_get_bus_info(struct ixgbe_hw *hw)
322 322 {
323 323 return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw),
324 324 IXGBE_NOT_IMPLEMENTED);
325 325 }
326 326
327 327 /**
328 328 * ixgbe_get_num_of_tx_queues - Get Tx queues
329 329 * @hw: pointer to hardware structure
330 330 *
331 331 * Returns the number of transmit queues for the given adapter.
332 332 **/
333 333 u32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw)
334 334 {
335 335 return hw->mac.max_tx_queues;
336 336 }
337 337
338 338 /**
339 339 * ixgbe_get_num_of_rx_queues - Get Rx queues
340 340 * @hw: pointer to hardware structure
341 341 *
342 342 * Returns the number of receive queues for the given adapter.
343 343 **/
344 344 u32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw)
345 345 {
346 346 return hw->mac.max_rx_queues;
347 347 }
348 348
349 349 /**
350 350 * ixgbe_stop_adapter - Disable Rx/Tx units
351 351 * @hw: pointer to hardware structure
352 352 *
353 353 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
354 354 * disables transmit and receive units. The adapter_stopped flag is used by
355 355 * the shared code and drivers to determine if the adapter is in a stopped
356 356 * state and should not touch the hardware.
357 357 **/
358 358 s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)
359 359 {
360 360 return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw),
361 361 IXGBE_NOT_IMPLEMENTED);
362 362 }
363 363
364 364 /**
365 365 * ixgbe_read_pba_string - Reads part number string from EEPROM
366 366 * @hw: pointer to hardware structure
367 367 * @pba_num: stores the part number string from the EEPROM
368 368 * @pba_num_size: part number string buffer length
369 369 *
370 370 * Reads the part number string from the EEPROM.
371 371 **/
372 372 s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)
373 373 {
374 374 return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);
375 375 }
376 376
377 377 /**
378 378 * ixgbe_read_pba_num - Reads part number from EEPROM
379 379 * @hw: pointer to hardware structure
380 380 * @pba_num: stores the part number from the EEPROM
381 381 *
382 382 * Reads the part number from the EEPROM.
383 383 **/
384 384 s32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num)
385 385 {
386 386 return ixgbe_read_pba_num_generic(hw, pba_num);
387 387 }
388 388
389 389 /**
390 390 * ixgbe_identify_phy - Get PHY type
391 391 * @hw: pointer to hardware structure
392 392 *
393 393 * Determines the physical layer module found on the current adapter.
394 394 **/
395 395 s32 ixgbe_identify_phy(struct ixgbe_hw *hw)
396 396 {
397 397 s32 status = IXGBE_SUCCESS;
398 398
399 399 if (hw->phy.type == ixgbe_phy_unknown) {
400 400 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw),
401 401 IXGBE_NOT_IMPLEMENTED);
402 402 }
403 403
404 404 return status;
405 405 }
406 406
407 407 /**
408 408 * ixgbe_reset_phy - Perform a PHY reset
409 409 * @hw: pointer to hardware structure
410 410 **/
411 411 s32 ixgbe_reset_phy(struct ixgbe_hw *hw)
412 412 {
413 413 s32 status = IXGBE_SUCCESS;
414 414
415 415 if (hw->phy.type == ixgbe_phy_unknown) {
416 416 if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS)
417 417 status = IXGBE_ERR_PHY;
418 418 }
419 419
420 420 if (status == IXGBE_SUCCESS) {
421 421 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw),
422 422 IXGBE_NOT_IMPLEMENTED);
423 423 }
424 424 return status;
425 425 }
426 426
427 427 /**
428 428 * ixgbe_get_phy_firmware_version -
429 429 * @hw: pointer to hardware structure
430 430 * @firmware_version: pointer to firmware version
431 431 **/
432 432 s32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version)
433 433 {
434 434 s32 status = IXGBE_SUCCESS;
435 435
436 436 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version,
437 437 (hw, firmware_version),
438 438 IXGBE_NOT_IMPLEMENTED);
439 439 return status;
440 440 }
441 441
442 442 /**
443 443 * ixgbe_read_phy_reg - Read PHY register
444 444 * @hw: pointer to hardware structure
445 445 * @reg_addr: 32 bit address of PHY register to read
446 446 * @phy_data: Pointer to read data from PHY register
447 447 *
448 448 * Reads a value from a specified PHY register
449 449 **/
450 450 s32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
451 451 u16 *phy_data)
452 452 {
453 453 s32 status;
454 454
455 455 if (hw->phy.id == 0)
456 456 status = ixgbe_identify_phy(hw);
457 457 else
458 458 status = IXGBE_SUCCESS;
459 459
460 460 if (status == IXGBE_SUCCESS) {
461 461 status = ixgbe_call_func(hw, hw->phy.ops.read_reg,
462 462 (hw, reg_addr, device_type, phy_data),
463 463 IXGBE_NOT_IMPLEMENTED);
464 464 }
465 465 return (status);
466 466 }
467 467
468 468 /**
469 469 * ixgbe_write_phy_reg - Write PHY register
470 470 * @hw: pointer to hardware structure
471 471 * @reg_addr: 32 bit PHY register to write
472 472 * @phy_data: Data to write to the PHY register
473 473 *
474 474 * Writes a value to specified PHY register
475 475 **/
476 476 s32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
477 477 u16 phy_data)
478 478 {
479 479 s32 status;
480 480
481 481 if (hw->phy.id == 0)
482 482 status = ixgbe_identify_phy(hw);
483 483 else
484 484 status = IXGBE_SUCCESS;
485 485
486 486 if (status == IXGBE_SUCCESS) {
487 487 status = ixgbe_call_func(hw, hw->phy.ops.write_reg,
488 488 (hw, reg_addr, device_type, phy_data),
489 489 IXGBE_NOT_IMPLEMENTED);
490 490 }
491 491
492 492 return status;
493 493 }
494 494
495 495 /**
496 496 * ixgbe_setup_phy_link - Restart PHY autoneg
497 497 * @hw: pointer to hardware structure
498 498 *
499 499 * Restart autonegotiation and PHY and waits for completion.
500 500 **/
501 501 s32 ixgbe_setup_phy_link(struct ixgbe_hw *hw)
502 502 {
503 503 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw),
504 504 IXGBE_NOT_IMPLEMENTED);
505 505 }
506 506
507 507 /**
508 508 * ixgbe_check_phy_link - Determine link and speed status
509 509 * @hw: pointer to hardware structure
510 510 *
511 511 * Reads a PHY register to determine if link is up and the current speed for
512 512 * the PHY.
513 513 **/
514 514 s32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
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515 515 bool *link_up)
516 516 {
517 517 return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed,
518 518 link_up), IXGBE_NOT_IMPLEMENTED);
519 519 }
520 520
521 521 /**
522 522 * ixgbe_setup_phy_link_speed - Set auto advertise
523 523 * @hw: pointer to hardware structure
524 524 * @speed: new link speed
525 - * @autoneg: TRUE if autonegotiation enabled
526 525 *
527 526 * Sets the auto advertised capabilities
528 527 **/
529 528 s32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed,
530 - bool autoneg,
531 529 bool autoneg_wait_to_complete)
532 530 {
533 531 return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed,
534 - autoneg, autoneg_wait_to_complete),
532 + autoneg_wait_to_complete),
535 533 IXGBE_NOT_IMPLEMENTED);
536 534 }
537 535
538 536 /**
539 537 * ixgbe_check_link - Get link and speed status
540 538 * @hw: pointer to hardware structure
541 539 *
542 540 * Reads the links register to determine if link is up and the current speed
543 541 **/
544 542 s32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
545 543 bool *link_up, bool link_up_wait_to_complete)
546 544 {
547 545 return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed,
548 546 link_up, link_up_wait_to_complete),
549 547 IXGBE_NOT_IMPLEMENTED);
550 548 }
551 549
552 550 /**
553 551 * ixgbe_disable_tx_laser - Disable Tx laser
554 552 * @hw: pointer to hardware structure
555 553 *
556 554 * If the driver needs to disable the laser on SFI optics.
557 555 **/
558 556 void ixgbe_disable_tx_laser(struct ixgbe_hw *hw)
559 557 {
560 558 if (hw->mac.ops.disable_tx_laser)
561 559 hw->mac.ops.disable_tx_laser(hw);
562 560 }
563 561
564 562 /**
565 563 * ixgbe_enable_tx_laser - Enable Tx laser
566 564 * @hw: pointer to hardware structure
567 565 *
568 566 * If the driver needs to enable the laser on SFI optics.
569 567 **/
570 568 void ixgbe_enable_tx_laser(struct ixgbe_hw *hw)
571 569 {
572 570 if (hw->mac.ops.enable_tx_laser)
573 571 hw->mac.ops.enable_tx_laser(hw);
574 572 }
575 573
576 574 /**
577 575 * ixgbe_flap_tx_laser - flap Tx laser to start autotry process
578 576 * @hw: pointer to hardware structure
579 577 *
580 578 * When the driver changes the link speeds that it can support then
581 579 * flap the tx laser to alert the link partner to start autotry
582 580 * process on its end.
583 581 **/
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584 582 void ixgbe_flap_tx_laser(struct ixgbe_hw *hw)
585 583 {
586 584 if (hw->mac.ops.flap_tx_laser)
587 585 hw->mac.ops.flap_tx_laser(hw);
588 586 }
589 587
590 588 /**
591 589 * ixgbe_setup_link - Set link speed
592 590 * @hw: pointer to hardware structure
593 591 * @speed: new link speed
594 - * @autoneg: TRUE if autonegotiation enabled
595 592 *
596 593 * Configures link settings. Restarts the link.
597 594 * Performs autonegotiation if needed.
598 595 **/
599 596 s32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed,
600 - bool autoneg,
601 597 bool autoneg_wait_to_complete)
602 598 {
603 599 return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed,
604 - autoneg, autoneg_wait_to_complete),
600 + autoneg_wait_to_complete),
605 601 IXGBE_NOT_IMPLEMENTED);
606 602 }
607 603
608 604 /**
609 605 * ixgbe_get_link_capabilities - Returns link capabilities
610 606 * @hw: pointer to hardware structure
611 607 *
612 608 * Determines the link capabilities of the current configuration.
613 609 **/
614 610 s32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
615 611 bool *autoneg)
616 612 {
617 613 return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw,
618 614 speed, autoneg), IXGBE_NOT_IMPLEMENTED);
619 615 }
620 616
621 617 /**
622 618 * ixgbe_led_on - Turn on LEDs
623 619 * @hw: pointer to hardware structure
624 620 * @index: led number to turn on
625 621 *
626 622 * Turns on the software controllable LEDs.
627 623 **/
628 624 s32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index)
629 625 {
630 626 return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index),
631 627 IXGBE_NOT_IMPLEMENTED);
632 628 }
633 629
634 630 /**
635 631 * ixgbe_led_off - Turn off LEDs
636 632 * @hw: pointer to hardware structure
637 633 * @index: led number to turn off
638 634 *
639 635 * Turns off the software controllable LEDs.
640 636 **/
641 637 s32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index)
642 638 {
643 639 return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index),
644 640 IXGBE_NOT_IMPLEMENTED);
645 641 }
646 642
647 643 /**
648 644 * ixgbe_blink_led_start - Blink LEDs
649 645 * @hw: pointer to hardware structure
650 646 * @index: led number to blink
651 647 *
652 648 * Blink LED based on index.
653 649 **/
654 650 s32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index)
655 651 {
656 652 return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index),
657 653 IXGBE_NOT_IMPLEMENTED);
658 654 }
659 655
660 656 /**
661 657 * ixgbe_blink_led_stop - Stop blinking LEDs
662 658 * @hw: pointer to hardware structure
663 659 *
664 660 * Stop blinking LED based on index.
665 661 **/
666 662 s32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index)
667 663 {
668 664 return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index),
669 665 IXGBE_NOT_IMPLEMENTED);
670 666 }
671 667
672 668 /**
673 669 * ixgbe_init_eeprom_params - Initialize EEPROM parameters
674 670 * @hw: pointer to hardware structure
675 671 *
676 672 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
677 673 * ixgbe_hw struct in order to set up EEPROM access.
678 674 **/
679 675 s32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw)
680 676 {
681 677 return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw),
682 678 IXGBE_NOT_IMPLEMENTED);
683 679 }
684 680
685 681
686 682 /**
687 683 * ixgbe_write_eeprom - Write word to EEPROM
688 684 * @hw: pointer to hardware structure
689 685 * @offset: offset within the EEPROM to be written to
690 686 * @data: 16 bit word to be written to the EEPROM
691 687 *
692 688 * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not
693 689 * called after this function, the EEPROM will most likely contain an
694 690 * invalid checksum.
695 691 **/
696 692 s32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data)
697 693 {
698 694 return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data),
699 695 IXGBE_NOT_IMPLEMENTED);
700 696 }
701 697
702 698 /**
703 699 * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM
704 700 * @hw: pointer to hardware structure
705 701 * @offset: offset within the EEPROM to be written to
706 702 * @data: 16 bit word(s) to be written to the EEPROM
707 703 * @words: number of words
708 704 *
709 705 * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not
710 706 * called after this function, the EEPROM will most likely contain an
711 707 * invalid checksum.
712 708 **/
713 709 s32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words,
714 710 u16 *data)
715 711 {
716 712 return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer,
717 713 (hw, offset, words, data),
718 714 IXGBE_NOT_IMPLEMENTED);
719 715 }
720 716
721 717 /**
722 718 * ixgbe_read_eeprom - Read word from EEPROM
723 719 * @hw: pointer to hardware structure
724 720 * @offset: offset within the EEPROM to be read
725 721 * @data: read 16 bit value from EEPROM
726 722 *
727 723 * Reads 16 bit value from EEPROM
728 724 **/
729 725 s32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data)
730 726 {
731 727 return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data),
732 728 IXGBE_NOT_IMPLEMENTED);
733 729 }
734 730
735 731 /**
736 732 * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM
737 733 * @hw: pointer to hardware structure
738 734 * @offset: offset within the EEPROM to be read
739 735 * @data: read 16 bit word(s) from EEPROM
740 736 * @words: number of words
741 737 *
742 738 * Reads 16 bit word(s) from EEPROM
743 739 **/
744 740 s32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset,
745 741 u16 words, u16 *data)
746 742 {
747 743 return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer,
748 744 (hw, offset, words, data),
749 745 IXGBE_NOT_IMPLEMENTED);
750 746 }
751 747
752 748 /**
753 749 * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum
754 750 * @hw: pointer to hardware structure
755 751 * @checksum_val: calculated checksum
756 752 *
757 753 * Performs checksum calculation and validates the EEPROM checksum
758 754 **/
759 755 s32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val)
760 756 {
761 757 return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum,
762 758 (hw, checksum_val), IXGBE_NOT_IMPLEMENTED);
763 759 }
764 760
765 761 /**
766 762 * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum
767 763 * @hw: pointer to hardware structure
768 764 **/
769 765 s32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw)
770 766 {
771 767 return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw),
772 768 IXGBE_NOT_IMPLEMENTED);
773 769 }
774 770
775 771 /**
776 772 * ixgbe_insert_mac_addr - Find a RAR for this mac address
777 773 * @hw: pointer to hardware structure
778 774 * @addr: Address to put into receive address register
779 775 * @vmdq: VMDq pool to assign
780 776 *
781 777 * Puts an ethernet address into a receive address register, or
782 778 * finds the rar that it is aleady in; adds to the pool list
783 779 **/
784 780 s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
785 781 {
786 782 return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr,
787 783 (hw, addr, vmdq),
788 784 IXGBE_NOT_IMPLEMENTED);
789 785 }
790 786
791 787 /**
792 788 * ixgbe_set_rar - Set Rx address register
793 789 * @hw: pointer to hardware structure
794 790 * @index: Receive address register to write
795 791 * @addr: Address to put into receive address register
796 792 * @vmdq: VMDq "set"
797 793 * @enable_addr: set flag that address is active
798 794 *
799 795 * Puts an ethernet address into a receive address register.
800 796 **/
801 797 s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
802 798 u32 enable_addr)
803 799 {
804 800 return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq,
805 801 enable_addr), IXGBE_NOT_IMPLEMENTED);
806 802 }
807 803
808 804 /**
809 805 * ixgbe_clear_rar - Clear Rx address register
810 806 * @hw: pointer to hardware structure
811 807 * @index: Receive address register to write
812 808 *
813 809 * Puts an ethernet address into a receive address register.
814 810 **/
815 811 s32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index)
816 812 {
817 813 return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index),
818 814 IXGBE_NOT_IMPLEMENTED);
819 815 }
820 816
821 817 /**
822 818 * ixgbe_set_vmdq - Associate a VMDq index with a receive address
823 819 * @hw: pointer to hardware structure
824 820 * @rar: receive address register index to associate with VMDq index
825 821 * @vmdq: VMDq set or pool index
826 822 **/
827 823 s32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
828 824 {
829 825 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq),
830 826 IXGBE_NOT_IMPLEMENTED);
831 827
832 828 }
833 829
834 830 /**
835 831 * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address
836 832 * @hw: pointer to hardware structure
837 833 * @vmdq: VMDq default pool index
838 834 **/
839 835 s32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq)
840 836 {
841 837 return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac,
842 838 (hw, vmdq), IXGBE_NOT_IMPLEMENTED);
843 839 }
844 840
845 841 /**
846 842 * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address
847 843 * @hw: pointer to hardware structure
848 844 * @rar: receive address register index to disassociate with VMDq index
849 845 * @vmdq: VMDq set or pool index
850 846 **/
851 847 s32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
852 848 {
853 849 return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq),
854 850 IXGBE_NOT_IMPLEMENTED);
855 851 }
856 852
857 853 /**
858 854 * ixgbe_init_rx_addrs - Initializes receive address filters.
859 855 * @hw: pointer to hardware structure
860 856 *
861 857 * Places the MAC address in receive address register 0 and clears the rest
862 858 * of the receive address registers. Clears the multicast table. Assumes
863 859 * the receiver is in reset when the routine is called.
864 860 **/
865 861 s32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw)
866 862 {
867 863 return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw),
868 864 IXGBE_NOT_IMPLEMENTED);
869 865 }
870 866
871 867 /**
872 868 * ixgbe_get_num_rx_addrs - Returns the number of RAR entries.
873 869 * @hw: pointer to hardware structure
874 870 **/
875 871 u32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw)
876 872 {
877 873 return hw->mac.num_rar_entries;
878 874 }
879 875
880 876 /**
881 877 * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses
882 878 * @hw: pointer to hardware structure
883 879 * @addr_list: the list of new multicast addresses
884 880 * @addr_count: number of addresses
885 881 * @func: iterator function to walk the multicast address list
886 882 *
887 883 * The given list replaces any existing list. Clears the secondary addrs from
888 884 * receive address registers. Uses unused receive address registers for the
889 885 * first secondary addresses, and falls back to promiscuous mode as needed.
890 886 **/
891 887 s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,
892 888 u32 addr_count, ixgbe_mc_addr_itr func)
893 889 {
894 890 return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw,
895 891 addr_list, addr_count, func),
896 892 IXGBE_NOT_IMPLEMENTED);
897 893 }
898 894
899 895 /**
900 896 * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses
901 897 * @hw: pointer to hardware structure
902 898 * @mc_addr_list: the list of new multicast addresses
903 899 * @mc_addr_count: number of addresses
904 900 * @func: iterator function to walk the multicast address list
905 901 *
906 902 * The given list replaces any existing list. Clears the MC addrs from receive
907 903 * address registers and the multicast table. Uses unused receive address
908 904 * registers for the first multicast addresses, and hashes the rest into the
909 905 * multicast table.
910 906 **/
911 907 s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,
912 908 u32 mc_addr_count, ixgbe_mc_addr_itr func,
913 909 bool clear)
914 910 {
915 911 return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw,
916 912 mc_addr_list, mc_addr_count, func, clear),
917 913 IXGBE_NOT_IMPLEMENTED);
918 914 }
919 915
920 916 /**
921 917 * ixgbe_enable_mc - Enable multicast address in RAR
922 918 * @hw: pointer to hardware structure
923 919 *
924 920 * Enables multicast address in RAR and the use of the multicast hash table.
925 921 **/
926 922 s32 ixgbe_enable_mc(struct ixgbe_hw *hw)
927 923 {
928 924 return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw),
929 925 IXGBE_NOT_IMPLEMENTED);
930 926 }
931 927
932 928 /**
933 929 * ixgbe_disable_mc - Disable multicast address in RAR
934 930 * @hw: pointer to hardware structure
935 931 *
936 932 * Disables multicast address in RAR and the use of the multicast hash table.
937 933 **/
938 934 s32 ixgbe_disable_mc(struct ixgbe_hw *hw)
939 935 {
940 936 return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw),
941 937 IXGBE_NOT_IMPLEMENTED);
942 938 }
943 939
944 940 /**
945 941 * ixgbe_clear_vfta - Clear VLAN filter table
946 942 * @hw: pointer to hardware structure
947 943 *
948 944 * Clears the VLAN filer table, and the VMDq index associated with the filter
949 945 **/
950 946 s32 ixgbe_clear_vfta(struct ixgbe_hw *hw)
951 947 {
952 948 return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw),
953 949 IXGBE_NOT_IMPLEMENTED);
954 950 }
955 951
956 952 /**
957 953 * ixgbe_set_vfta - Set VLAN filter table
958 954 * @hw: pointer to hardware structure
959 955 * @vlan: VLAN id to write to VLAN filter
960 956 * @vind: VMDq output index that maps queue to VLAN id in VFTA
961 957 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
962 958 *
963 959 * Turn on/off specified VLAN in the VLAN filter table.
964 960 **/
965 961 s32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
966 962 {
967 963 return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind,
968 964 vlan_on), IXGBE_NOT_IMPLEMENTED);
969 965 }
970 966
971 967 /**
972 968 * ixgbe_set_vlvf - Set VLAN Pool Filter
973 969 * @hw: pointer to hardware structure
974 970 * @vlan: VLAN id to write to VLAN filter
975 971 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
976 972 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
977 973 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
978 974 * should be changed
979 975 *
980 976 * Turn on/off specified bit in VLVF table.
981 977 **/
982 978 s32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on,
983 979 bool *vfta_changed)
984 980 {
985 981 return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind,
986 982 vlan_on, vfta_changed), IXGBE_NOT_IMPLEMENTED);
987 983 }
988 984
989 985 /**
990 986 * ixgbe_fc_enable - Enable flow control
991 987 * @hw: pointer to hardware structure
992 988 *
993 989 * Configures the flow control settings based on SW configuration.
994 990 **/
995 991 s32 ixgbe_fc_enable(struct ixgbe_hw *hw)
996 992 {
997 993 return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw),
998 994 IXGBE_NOT_IMPLEMENTED);
999 995 }
1000 996
1001 997 /**
1002 998 * ixgbe_set_fw_drv_ver - Try to send the driver version number FW
1003 999 * @hw: pointer to hardware structure
1004 1000 * @maj: driver major number to be sent to firmware
1005 1001 * @min: driver minor number to be sent to firmware
1006 1002 * @build: driver build number to be sent to firmware
1007 1003 * @ver: driver version number to be sent to firmware
1008 1004 **/
1009 1005 s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
1010 1006 u8 ver)
1011 1007 {
1012 1008 return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min,
1013 1009 build, ver), IXGBE_NOT_IMPLEMENTED);
1014 1010 }
1015 1011
1016 1012
1017 1013 /**
1018 1014 * ixgbe_read_analog_reg8 - Reads 8 bit analog register
1019 1015 * @hw: pointer to hardware structure
1020 1016 * @reg: analog register to read
1021 1017 * @val: read value
1022 1018 *
1023 1019 * Performs write operation to analog register specified.
1024 1020 **/
1025 1021 s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)
1026 1022 {
1027 1023 return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg,
1028 1024 val), IXGBE_NOT_IMPLEMENTED);
1029 1025 }
1030 1026
1031 1027 /**
1032 1028 * ixgbe_write_analog_reg8 - Writes 8 bit analog register
1033 1029 * @hw: pointer to hardware structure
1034 1030 * @reg: analog register to write
1035 1031 * @val: value to write
1036 1032 *
1037 1033 * Performs write operation to Atlas analog register specified.
1038 1034 **/
1039 1035 s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)
1040 1036 {
1041 1037 return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg,
1042 1038 val), IXGBE_NOT_IMPLEMENTED);
1043 1039 }
1044 1040
1045 1041 /**
1046 1042 * ixgbe_init_uta_tables - Initializes Unicast Table Arrays.
1047 1043 * @hw: pointer to hardware structure
1048 1044 *
1049 1045 * Initializes the Unicast Table Arrays to zero on device load. This
1050 1046 * is part of the Rx init addr execution path.
1051 1047 **/
1052 1048 s32 ixgbe_init_uta_tables(struct ixgbe_hw *hw)
1053 1049 {
1054 1050 return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw),
1055 1051 IXGBE_NOT_IMPLEMENTED);
1056 1052 }
1057 1053
1058 1054 /**
1059 1055 * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address
1060 1056 * @hw: pointer to hardware structure
1061 1057 * @byte_offset: byte offset to read
1062 1058 * @data: value read
1063 1059 *
1064 1060 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1065 1061 **/
1066 1062 s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1067 1063 u8 *data)
1068 1064 {
1069 1065 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset,
1070 1066 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1071 1067 }
1072 1068
1073 1069 /**
1074 1070 * ixgbe_write_i2c_byte - Writes 8 bit word over I2C
1075 1071 * @hw: pointer to hardware structure
1076 1072 * @byte_offset: byte offset to write
1077 1073 * @data: value to write
1078 1074 *
1079 1075 * Performs byte write operation to SFP module's EEPROM over I2C interface
1080 1076 * at a specified device address.
1081 1077 **/
1082 1078 s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
1083 1079 u8 data)
1084 1080 {
1085 1081 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset,
1086 1082 dev_addr, data), IXGBE_NOT_IMPLEMENTED);
1087 1083 }
1088 1084
1089 1085 /**
1090 1086 * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1091 1087 * @hw: pointer to hardware structure
1092 1088 * @byte_offset: EEPROM byte offset to write
1093 1089 * @eeprom_data: value to write
1094 1090 *
1095 1091 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1096 1092 **/
1097 1093 s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw,
1098 1094 u8 byte_offset, u8 eeprom_data)
1099 1095 {
1100 1096 return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom,
1101 1097 (hw, byte_offset, eeprom_data),
1102 1098 IXGBE_NOT_IMPLEMENTED);
1103 1099 }
1104 1100
1105 1101 /**
1106 1102 * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1107 1103 * @hw: pointer to hardware structure
1108 1104 * @byte_offset: EEPROM byte offset to read
1109 1105 * @eeprom_data: value read
1110 1106 *
1111 1107 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1112 1108 **/
1113 1109 s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)
1114 1110 {
1115 1111 return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom,
1116 1112 (hw, byte_offset, eeprom_data),
1117 1113 IXGBE_NOT_IMPLEMENTED);
1118 1114 }
1119 1115
1120 1116 /**
1121 1117 * ixgbe_get_supported_physical_layer - Returns physical layer type
1122 1118 * @hw: pointer to hardware structure
1123 1119 *
1124 1120 * Determines physical layer capabilities of the current configuration.
1125 1121 **/
1126 1122 u32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw)
1127 1123 {
1128 1124 return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer,
1129 1125 (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN);
1130 1126 }
1131 1127
1132 1128 /**
1133 1129 * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics
1134 1130 * @hw: pointer to hardware structure
1135 1131 * @regval: bitfield to write to the Rx DMA register
1136 1132 *
1137 1133 * Enables the Rx DMA unit of the device.
1138 1134 **/
1139 1135 s32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval)
1140 1136 {
1141 1137 return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma,
1142 1138 (hw, regval), IXGBE_NOT_IMPLEMENTED);
1143 1139 }
1144 1140
1145 1141 /**
1146 1142 * ixgbe_disable_sec_rx_path - Stops the receive data path
1147 1143 * @hw: pointer to hardware structure
1148 1144 *
1149 1145 * Stops the receive data path.
1150 1146 **/
1151 1147 s32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw)
1152 1148 {
1153 1149 return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path,
1154 1150 (hw), IXGBE_NOT_IMPLEMENTED);
1155 1151 }
1156 1152
1157 1153 /**
1158 1154 * ixgbe_enable_sec_rx_path - Enables the receive data path
1159 1155 * @hw: pointer to hardware structure
1160 1156 *
1161 1157 * Enables the receive data path.
1162 1158 **/
1163 1159 s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)
1164 1160 {
1165 1161 return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path,
1166 1162 (hw), IXGBE_NOT_IMPLEMENTED);
1167 1163 }
1168 1164
1169 1165 /**
1170 1166 * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore
1171 1167 * @hw: pointer to hardware structure
1172 1168 * @mask: Mask to specify which semaphore to acquire
1173 1169 *
1174 1170 * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified
1175 1171 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1176 1172 **/
1177 1173 s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
1178 1174 {
1179 1175 return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,
1180 1176 (hw, mask), IXGBE_NOT_IMPLEMENTED);
1181 1177 }
1182 1178
1183 1179 /**
1184 1180 * ixgbe_release_swfw_semaphore - Release SWFW semaphore
1185 1181 * @hw: pointer to hardware structure
1186 1182 * @mask: Mask to specify which semaphore to release
1187 1183 *
1188 1184 * Releases the SWFW semaphore through SW_FW_SYNC register for the specified
1189 1185 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1190 1186 **/
1191 1187 void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)
1192 1188 {
1193 1189 if (hw->mac.ops.release_swfw_sync)
1194 1190 hw->mac.ops.release_swfw_sync(hw, mask);
1195 1191 }
1196 1192
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