1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c,v 1.8 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_type.h"
36 #include "ixgbe_82599.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
40
41 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
43 bool autoneg,
44 bool autoneg_wait_to_complete);
45 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
46 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
47 u16 offset, u16 *data);
48 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
49 u16 words, u16 *data);
50
51 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
52 {
53 struct ixgbe_mac_info *mac = &hw->mac;
54
55 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
56
57 /* enable the laser control functions for SFP+ fiber */
58 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
59 mac->ops.disable_tx_laser =
60 &ixgbe_disable_tx_laser_multispeed_fiber;
61 mac->ops.enable_tx_laser =
62 &ixgbe_enable_tx_laser_multispeed_fiber;
63 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
64
65 } else {
66 mac->ops.disable_tx_laser = NULL;
67 mac->ops.enable_tx_laser = NULL;
68 mac->ops.flap_tx_laser = NULL;
69 }
70
71 if (hw->phy.multispeed_fiber) {
72 /* Set up dual speed SFP+ support */
73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
74 } else {
75 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
76 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
77 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
78 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
118 }
119
120 /* Set necessary function pointers based on phy type */
121 switch (hw->phy.type) {
122 case ixgbe_phy_tn:
123 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
124 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
125 phy->ops.get_firmware_version =
126 &ixgbe_get_phy_firmware_version_tnx;
127 break;
128 default:
129 break;
130 }
131 init_phy_ops_out:
132 return ret_val;
133 }
134
135 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
136 {
137 s32 ret_val = IXGBE_SUCCESS;
138 u32 reg_anlp1 = 0;
139 u32 i = 0;
140 u16 list_offset, data_offset, data_value;
141
142 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
143
144 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
145 ixgbe_init_mac_link_ops_82599(hw);
146
147 hw->phy.ops.reset = NULL;
148
149 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
150 &data_offset);
151 if (ret_val != IXGBE_SUCCESS)
152 goto setup_sfp_out;
153
154 /* PHY config will finish before releasing the semaphore */
155 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
156 IXGBE_GSSR_MAC_CSR_SM);
157 if (ret_val != IXGBE_SUCCESS) {
158 ret_val = IXGBE_ERR_SWFW_SYNC;
159 goto setup_sfp_out;
160 }
161
162 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
163 while (data_value != 0xffff) {
164 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
165 IXGBE_WRITE_FLUSH(hw);
166 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
167 }
168
169 /* Release the semaphore */
170 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
171 /* Delay obtaining semaphore again to allow FW access */
172 msec_delay(hw->eeprom.semaphore_delay);
173
174 /* Now restart DSP by setting Restart_AN and clearing LMS */
175 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
176 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
177 IXGBE_AUTOC_AN_RESTART));
178
179 /* Wait for AN to leave state 0 */
180 for (i = 0; i < 10; i++) {
181 msec_delay(4);
182 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
183 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
184 break;
185 }
186 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
187 DEBUGOUT("sfp module setup not complete\n");
188 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
189 goto setup_sfp_out;
190 }
191
192 /* Restart DSP by setting Restart_AN and return to SFI mode */
193 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
194 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
195 IXGBE_AUTOC_AN_RESTART));
196 }
197
198 setup_sfp_out:
199 return ret_val;
200 }
201
202 /**
203 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
204 * @hw: pointer to hardware structure
205 *
206 * Initialize the function pointers and assign the MAC type for 82599.
207 * Does not touch the hardware.
208 **/
209
210 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
211 {
212 struct ixgbe_mac_info *mac = &hw->mac;
213 struct ixgbe_phy_info *phy = &hw->phy;
214 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
215 s32 ret_val;
216
217 DEBUGFUNC("ixgbe_init_ops_82599");
218
219 ret_val = ixgbe_init_phy_ops_generic(hw);
220 ret_val = ixgbe_init_ops_generic(hw);
221
222 /* PHY */
223 phy->ops.identify = &ixgbe_identify_phy_82599;
224 phy->ops.init = &ixgbe_init_phy_ops_82599;
225
226 /* MAC */
227 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
228 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
229 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
230 mac->ops.get_supported_physical_layer =
231 &ixgbe_get_supported_physical_layer_82599;
232 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
233 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
234 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
235 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
236 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
237 mac->ops.start_hw = &ixgbe_start_hw_82599;
238 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
239 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
272 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
273 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
274
275 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
276
277 /* EEPROM */
278 eeprom->ops.read = &ixgbe_read_eeprom_82599;
279 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
280
281 /* Manageability interface */
282 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
283
284
285 return ret_val;
286 }
287
288 /**
289 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
290 * @hw: pointer to hardware structure
291 * @speed: pointer to link speed
292 * @negotiation: TRUE when autoneg or autotry is enabled
293 *
294 * Determines the link capabilities by reading the AUTOC register.
295 **/
296 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
297 ixgbe_link_speed *speed,
298 bool *negotiation)
299 {
300 s32 status = IXGBE_SUCCESS;
301 u32 autoc = 0;
302
303 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
304
305
306 /* Check if 1G SFP module. */
307 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
308 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
309 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
310 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
311 *speed = IXGBE_LINK_SPEED_1GB_FULL;
312 *negotiation = TRUE;
313 goto out;
314 }
315
316 /*
317 * Determine link capabilities based on the stored value of AUTOC,
318 * which represents EEPROM defaults. If AUTOC value has not
319 * been stored, use the current register values.
320 */
321 if (hw->mac.orig_link_settings_stored)
322 autoc = hw->mac.orig_autoc;
323 else
324 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
325
326 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
327 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
328 *speed = IXGBE_LINK_SPEED_1GB_FULL;
329 *negotiation = FALSE;
330 break;
331
332 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
333 *speed = IXGBE_LINK_SPEED_10GB_FULL;
334 *negotiation = FALSE;
335 break;
336
337 case IXGBE_AUTOC_LMS_1G_AN:
338 *speed = IXGBE_LINK_SPEED_1GB_FULL;
339 *negotiation = TRUE;
340 break;
341
342 case IXGBE_AUTOC_LMS_10G_SERIAL:
343 *speed = IXGBE_LINK_SPEED_10GB_FULL;
344 *negotiation = FALSE;
345 break;
346
347 case IXGBE_AUTOC_LMS_KX4_KX_KR:
348 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
349 *speed = IXGBE_LINK_SPEED_UNKNOWN;
350 if (autoc & IXGBE_AUTOC_KR_SUPP)
351 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
352 if (autoc & IXGBE_AUTOC_KX4_SUPP)
353 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
354 if (autoc & IXGBE_AUTOC_KX_SUPP)
355 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
356 *negotiation = TRUE;
357 break;
358
359 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
360 *speed = IXGBE_LINK_SPEED_100_FULL;
361 if (autoc & IXGBE_AUTOC_KR_SUPP)
362 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
363 if (autoc & IXGBE_AUTOC_KX4_SUPP)
364 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
365 if (autoc & IXGBE_AUTOC_KX_SUPP)
366 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
367 *negotiation = TRUE;
368 break;
369
370 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
371 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
372 *negotiation = FALSE;
373 break;
374
375 default:
376 status = IXGBE_ERR_LINK_SETUP;
377 goto out;
378 }
379
380 if (hw->phy.multispeed_fiber) {
381 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
382 IXGBE_LINK_SPEED_1GB_FULL;
383 *negotiation = TRUE;
384 }
385
386 out:
387 return status;
388 }
389
390 /**
391 * ixgbe_get_media_type_82599 - Get media type
392 * @hw: pointer to hardware structure
393 *
394 * Returns the media type (fiber, copper, backplane)
395 **/
396 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
397 {
398 enum ixgbe_media_type media_type;
399
400 DEBUGFUNC("ixgbe_get_media_type_82599");
401
402 /* Detect if there is a copper PHY attached. */
403 switch (hw->phy.type) {
406 media_type = ixgbe_media_type_copper;
407 goto out;
408 default:
409 break;
410 }
411
412 switch (hw->device_id) {
413 case IXGBE_DEV_ID_82599_KX4:
414 case IXGBE_DEV_ID_82599_KX4_MEZZ:
415 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
416 case IXGBE_DEV_ID_82599_KR:
417 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
418 case IXGBE_DEV_ID_82599_XAUI_LOM:
419 /* Default device ID is mezzanine card KX/KX4 */
420 media_type = ixgbe_media_type_backplane;
421 break;
422 case IXGBE_DEV_ID_82599_SFP:
423 case IXGBE_DEV_ID_82599_SFP_FCOE:
424 case IXGBE_DEV_ID_82599_SFP_EM:
425 case IXGBE_DEV_ID_82599_SFP_SF2:
426 case IXGBE_DEV_ID_82599EN_SFP:
427 media_type = ixgbe_media_type_fiber;
428 break;
429 case IXGBE_DEV_ID_82599_CX4:
430 media_type = ixgbe_media_type_cx4;
431 break;
432 case IXGBE_DEV_ID_82599_T3_LOM:
433 media_type = ixgbe_media_type_copper;
434 break;
435 default:
436 media_type = ixgbe_media_type_unknown;
437 break;
438 }
439 out:
440 return media_type;
441 }
442
443 /**
444 * ixgbe_start_mac_link_82599 - Setup MAC link settings
445 * @hw: pointer to hardware structure
446 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
447 *
448 * Configures link settings based on values in the ixgbe_hw struct.
449 * Restarts the link. Performs autonegotiation if needed.
450 **/
451 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
452 bool autoneg_wait_to_complete)
453 {
454 u32 autoc_reg;
455 u32 links_reg;
456 u32 i;
457 s32 status = IXGBE_SUCCESS;
458
459 DEBUGFUNC("ixgbe_start_mac_link_82599");
460
461
462 /* Restart link */
463 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
464 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
465 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
466
467 /* Only poll for autoneg to complete if specified to do so */
468 if (autoneg_wait_to_complete) {
469 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
470 IXGBE_AUTOC_LMS_KX4_KX_KR ||
471 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
472 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
473 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
474 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
475 links_reg = 0; /* Just in case Autoneg time = 0 */
476 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
477 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
478 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
479 break;
480 msec_delay(100);
481 }
482 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
483 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
484 DEBUGOUT("Autoneg did not complete.\n");
485 }
486 }
487 }
488
489 /* Add delay to filter out noises during initial link setup */
490 msec_delay(50);
491
492 return status;
493 }
494
495 /**
496 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
497 * @hw: pointer to hardware structure
498 *
499 * The base drivers may require better control over SFP+ module
500 * PHY states. This includes selectively shutting down the Tx
501 * laser on the PHY, effectively halting physical link.
502 **/
503 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
504 {
505 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
506
507 /* Disable tx laser; allow 100us to go dark per spec */
508 esdp_reg |= IXGBE_ESDP_SDP3;
509 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
510 IXGBE_WRITE_FLUSH(hw);
511 usec_delay(100);
537 * When the driver changes the link speeds that it can support,
538 * it sets autotry_restart to TRUE to indicate that we need to
539 * initiate a new autotry session with the link partner. To do
540 * so, we set the speed then disable and re-enable the tx laser, to
541 * alert the link partner that it also needs to restart autotry on its
542 * end. This is consistent with TRUE clause 37 autoneg, which also
543 * involves a loss of signal.
544 **/
545 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
546 {
547 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
548
549 if (hw->mac.autotry_restart) {
550 ixgbe_disable_tx_laser_multispeed_fiber(hw);
551 ixgbe_enable_tx_laser_multispeed_fiber(hw);
552 hw->mac.autotry_restart = FALSE;
553 }
554 }
555
556 /**
557 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
558 * @hw: pointer to hardware structure
559 * @speed: new link speed
560 * @autoneg: TRUE if autonegotiation enabled
561 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
562 *
563 * Set the link speed in the AUTOC register and restarts link.
564 **/
565 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
566 ixgbe_link_speed speed, bool autoneg,
567 bool autoneg_wait_to_complete)
568 {
569 s32 status = IXGBE_SUCCESS;
570 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
571 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
572 u32 speedcnt = 0;
573 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
574 u32 i = 0;
575 bool link_up = FALSE;
576 bool negotiation;
577
578 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
579
580 /* Mask off requested but non-supported speeds */
581 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
582 if (status != IXGBE_SUCCESS)
583 return status;
584
585 speed &= link_speed;
586
587 /*
588 * Try each speed one by one, highest priority first. We do this in
589 * software because 10gb fiber doesn't support speed autonegotiation.
590 */
591 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
592 speedcnt++;
593 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
594
595 /* If we already have link at this speed, just jump out */
596 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
597 if (status != IXGBE_SUCCESS)
598 return status;
599
600 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
601 goto out;
602
603 /* Set the module link speed */
604 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
605 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
606 IXGBE_WRITE_FLUSH(hw);
607
608 /* Allow module to change analog characteristics (1G->10G) */
609 msec_delay(40);
610
611 status = ixgbe_setup_mac_link_82599(hw,
612 IXGBE_LINK_SPEED_10GB_FULL,
613 autoneg,
614 autoneg_wait_to_complete);
615 if (status != IXGBE_SUCCESS)
616 return status;
617
618 /* Flap the tx laser if it has not already been done */
619 ixgbe_flap_tx_laser(hw);
620
621 /*
622 * Wait for the controller to acquire link. Per IEEE 802.3ap,
623 * Section 73.10.2, we may have to wait up to 500ms if KR is
624 * attempted. 82599 uses the same timing for 10g SFI.
625 */
626 for (i = 0; i < 5; i++) {
627 /* Wait for the link partner to also set speed */
628 msec_delay(100);
629
630 /* If we have link, just jump out */
631 status = ixgbe_check_link(hw, &link_speed,
632 &link_up, FALSE);
633 if (status != IXGBE_SUCCESS)
635
636 if (link_up)
637 goto out;
638 }
639 }
640
641 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
642 speedcnt++;
643 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
644 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
645
646 /* If we already have link at this speed, just jump out */
647 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
648 if (status != IXGBE_SUCCESS)
649 return status;
650
651 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
652 goto out;
653
654 /* Set the module link speed */
655 esdp_reg &= ~IXGBE_ESDP_SDP5;
656 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
657 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
658 IXGBE_WRITE_FLUSH(hw);
659
660 /* Allow module to change analog characteristics (10G->1G) */
661 msec_delay(40);
662
663 status = ixgbe_setup_mac_link_82599(hw,
664 IXGBE_LINK_SPEED_1GB_FULL,
665 autoneg,
666 autoneg_wait_to_complete);
667 if (status != IXGBE_SUCCESS)
668 return status;
669
670 /* Flap the tx laser if it has not already been done */
671 ixgbe_flap_tx_laser(hw);
672
673 /* Wait for the link partner to also set speed */
674 msec_delay(100);
675
676 /* If we have link, just jump out */
677 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
678 if (status != IXGBE_SUCCESS)
679 return status;
680
681 if (link_up)
682 goto out;
683 }
684
685 /*
686 * We didn't get link. Configure back to the highest speed we tried,
687 * (if there was more than one). We call ourselves back with just the
688 * single highest speed that the user requested.
689 */
690 if (speedcnt > 1)
691 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
692 highest_link_speed, autoneg, autoneg_wait_to_complete);
693
694 out:
695 /* Set autoneg_advertised value based on input link speed */
696 hw->phy.autoneg_advertised = 0;
697
698 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
699 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
700
701 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
702 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
703
704 return status;
705 }
706
707 /**
708 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
709 * @hw: pointer to hardware structure
710 * @speed: new link speed
711 * @autoneg: TRUE if autonegotiation enabled
712 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
713 *
714 * Implements the Intel SmartSpeed algorithm.
715 **/
716 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
717 ixgbe_link_speed speed, bool autoneg,
718 bool autoneg_wait_to_complete)
719 {
720 s32 status = IXGBE_SUCCESS;
721 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
722 s32 i, j;
723 bool link_up = FALSE;
724 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
725
726 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
727
728 /* Set autoneg_advertised value based on input link speed */
729 hw->phy.autoneg_advertised = 0;
730
731 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
732 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
733
734 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
735 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
736
737 if (speed & IXGBE_LINK_SPEED_100_FULL)
738 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
739
740 /*
741 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
742 * autoneg advertisement if link is unable to be established at the
743 * highest negotiated rate. This can sometimes happen due to integrity
744 * issues with the physical media connection.
745 */
746
747 /* First, try to get link with full advertisement */
748 hw->phy.smart_speed_active = FALSE;
749 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
750 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
751 autoneg_wait_to_complete);
752 if (status != IXGBE_SUCCESS)
753 goto out;
754
755 /*
756 * Wait for the controller to acquire link. Per IEEE 802.3ap,
757 * Section 73.10.2, we may have to wait up to 500ms if KR is
758 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
759 * Table 9 in the AN MAS.
760 */
761 for (i = 0; i < 5; i++) {
762 msec_delay(100);
763
764 /* If we have link, just jump out */
765 status = ixgbe_check_link(hw, &link_speed, &link_up,
766 FALSE);
767 if (status != IXGBE_SUCCESS)
768 goto out;
769
770 if (link_up)
771 goto out;
772 }
773 }
774
775 /*
776 * We didn't get link. If we advertised KR plus one of KX4/KX
777 * (or BX4/BX), then disable KR and try again.
778 */
779 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
780 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
781 goto out;
782
783 /* Turn SmartSpeed on to disable KR support */
784 hw->phy.smart_speed_active = TRUE;
785 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
786 autoneg_wait_to_complete);
787 if (status != IXGBE_SUCCESS)
788 goto out;
789
790 /*
791 * Wait for the controller to acquire link. 600ms will allow for
792 * the AN link_fail_inhibit_timer as well for multiple cycles of
793 * parallel detect, both 10g and 1g. This allows for the maximum
794 * connect attempts as defined in the AN MAS table 73-7.
795 */
796 for (i = 0; i < 6; i++) {
797 msec_delay(100);
798
799 /* If we have link, just jump out */
800 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
801 if (status != IXGBE_SUCCESS)
802 goto out;
803
804 if (link_up)
805 goto out;
806 }
807
808 /* We didn't get link. Turn SmartSpeed back off. */
809 hw->phy.smart_speed_active = FALSE;
810 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
811 autoneg_wait_to_complete);
812
813 out:
814 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
815 DEBUGOUT("Smartspeed has downgraded the link speed "
816 "from the maximum advertised\n");
817 return status;
818 }
819
820 /**
821 * ixgbe_setup_mac_link_82599 - Set MAC link speed
822 * @hw: pointer to hardware structure
823 * @speed: new link speed
824 * @autoneg: TRUE if autonegotiation enabled
825 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
826 *
827 * Set the link speed in the AUTOC register and restarts link.
828 **/
829 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
830 ixgbe_link_speed speed, bool autoneg,
831 bool autoneg_wait_to_complete)
832 {
833 s32 status = IXGBE_SUCCESS;
834 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
835 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
836 u32 start_autoc = autoc;
837 u32 orig_autoc = 0;
838 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
839 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
840 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
841 u32 links_reg;
842 u32 i;
843 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
844
845 DEBUGFUNC("ixgbe_setup_mac_link_82599");
846
847 /* Check to see if speed passed in is supported. */
848 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
849 if (status != IXGBE_SUCCESS)
850 goto out;
851
852 speed &= link_capabilities;
853
854 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
855 status = IXGBE_ERR_LINK_SETUP;
856 goto out;
857 }
858
859 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
860 if (hw->mac.orig_link_settings_stored)
861 orig_autoc = hw->mac.orig_autoc;
862 else
863 orig_autoc = autoc;
864
865 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
866 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
867 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
868 /* Set KX4/KX/KR support according to speed requested */
869 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
870 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
871 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
872 autoc |= IXGBE_AUTOC_KX4_SUPP;
873 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
874 (hw->phy.smart_speed_active == FALSE))
875 autoc |= IXGBE_AUTOC_KR_SUPP;
876 }
877 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
878 autoc |= IXGBE_AUTOC_KX_SUPP;
879 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
880 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
881 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
882 /* Switch from 1G SFI to 10G SFI if requested */
883 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
884 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
885 autoc &= ~IXGBE_AUTOC_LMS_MASK;
886 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
887 }
888 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
889 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
890 /* Switch from 10G SFI to 1G SFI if requested */
891 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
892 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
893 autoc &= ~IXGBE_AUTOC_LMS_MASK;
894 if (autoneg)
895 autoc |= IXGBE_AUTOC_LMS_1G_AN;
896 else
897 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
898 }
899 }
900
901 if (autoc != start_autoc) {
902 /* Restart link */
903 autoc |= IXGBE_AUTOC_AN_RESTART;
904 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
905
906 /* Only poll for autoneg to complete if specified to do so */
907 if (autoneg_wait_to_complete) {
908 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
909 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
910 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
911 links_reg = 0; /*Just in case Autoneg time=0*/
912 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
913 links_reg =
914 IXGBE_READ_REG(hw, IXGBE_LINKS);
915 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
916 break;
917 msec_delay(100);
918 }
919 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
920 status =
921 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
922 DEBUGOUT("Autoneg did not complete.\n");
923 }
924 }
925 }
926
927 /* Add delay to filter out noises during initial link setup */
928 msec_delay(50);
929 }
930
931 out:
932 return status;
933 }
934
935 /**
936 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
937 * @hw: pointer to hardware structure
938 * @speed: new link speed
939 * @autoneg: TRUE if autonegotiation enabled
940 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
941 *
942 * Restarts link on PHY and MAC based on settings passed in.
943 **/
944 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
945 ixgbe_link_speed speed,
946 bool autoneg,
947 bool autoneg_wait_to_complete)
948 {
949 s32 status;
950
951 DEBUGFUNC("ixgbe_setup_copper_link_82599");
952
953 /* Setup the PHY according to input speed */
954 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
955 autoneg_wait_to_complete);
956 if (status == IXGBE_SUCCESS) {
957 /* Set up MAC */
958 status =
959 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
960 }
961
962 return status;
963 }
964
965 /**
966 * ixgbe_reset_hw_82599 - Perform hardware reset
967 * @hw: pointer to hardware structure
968 *
969 * Resets the hardware by resetting the transmit and receive units, masks
970 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
971 * reset.
972 **/
973 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
974 {
975 ixgbe_link_speed link_speed;
976 s32 status;
977 u32 ctrl, i, autoc, autoc2;
978 bool link_up = FALSE;
979
980 DEBUGFUNC("ixgbe_reset_hw_82599");
1041
1042 msec_delay(50);
1043
1044 /*
1045 * Double resets are required for recovery from certain error
1046 * conditions. Between resets, it is necessary to stall to allow time
1047 * for any pending HW events to complete.
1048 */
1049 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1050 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1051 goto mac_reset_top;
1052 }
1053
1054 /*
1055 * Store the original AUTOC/AUTOC2 values if they have not been
1056 * stored off yet. Otherwise restore the stored original
1057 * values since the reset operation sets back to defaults.
1058 */
1059 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1060 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1061 if (hw->mac.orig_link_settings_stored == FALSE) {
1062 hw->mac.orig_autoc = autoc;
1063 hw->mac.orig_autoc2 = autoc2;
1064 hw->mac.orig_link_settings_stored = TRUE;
1065 } else {
1066 if (autoc != hw->mac.orig_autoc)
1067 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
1068 IXGBE_AUTOC_AN_RESTART));
1069
1070 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1071 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1072 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1073 autoc2 |= (hw->mac.orig_autoc2 &
1074 IXGBE_AUTOC2_UPPER_MASK);
1075 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1076 }
1077 }
1078
1079 /* Store the permanent mac address */
1080 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1081
1082 /*
1083 * Store MAC address from RAR0, clear receive address registers, and
1084 * clear the multicast table. Also reset num_rar_entries to 128,
1085 * since we modify this value when programming the SAN MAC address.
1086 */
1087 hw->mac.num_rar_entries = 128;
1088 hw->mac.ops.init_rx_addrs(hw);
1089
1153 IXGBE_WRITE_FLUSH(hw);
1154 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1155 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1156 ~IXGBE_FDIRCMD_CLEARHT));
1157 IXGBE_WRITE_FLUSH(hw);
1158 /*
1159 * Clear FDIR Hash register to clear any leftover hashes
1160 * waiting to be programmed.
1161 */
1162 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1163 IXGBE_WRITE_FLUSH(hw);
1164
1165 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1166 IXGBE_WRITE_FLUSH(hw);
1167
1168 /* Poll init-done after we write FDIRCTRL register */
1169 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1170 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1171 IXGBE_FDIRCTRL_INIT_DONE)
1172 break;
1173 usec_delay(10);
1174 }
1175 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1176 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1177 return IXGBE_ERR_FDIR_REINIT_FAILED;
1178 }
1179
1180 /* Clear FDIR statistics registers (read to clear) */
1181 (void) IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1182 (void) IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1183 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1184 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1185 (void) IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1186
1187 return IXGBE_SUCCESS;
1188 }
1189
1190 /**
1191 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1192 * @hw: pointer to hardware structure
1193 * @fdirctrl: value to write to flow director control register
2088
2089 hw->mac.ops.disable_sec_rx_path(hw);
2090
2091 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2092
2093 hw->mac.ops.enable_sec_rx_path(hw);
2094
2095 return IXGBE_SUCCESS;
2096 }
2097
2098 /**
2099 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2100 * @hw: pointer to hardware structure
2101 *
2102 * Verifies that installed the firmware version is 0.6 or higher
2103 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2104 *
2105 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2106 * if the FW version is not supported.
2107 **/
2108 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2109 {
2110 s32 status = IXGBE_ERR_EEPROM_VERSION;
2111 u16 fw_offset, fw_ptp_cfg_offset;
2112 u16 fw_version = 0;
2113
2114 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2115
2116 /* firmware check is only necessary for SFI devices */
2117 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2118 status = IXGBE_SUCCESS;
2119 goto fw_version_out;
2120 }
2121
2122 /* get the offset to the Firmware Module block */
2123 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2124
2125 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2126 goto fw_version_out;
2127
2128 /* get the offset to the Pass Through Patch Configuration block */
2237 u16 offset, u16 *data)
2238 {
2239 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2240 s32 ret_val = IXGBE_ERR_CONFIG;
2241
2242 DEBUGFUNC("ixgbe_read_eeprom_82599");
2243
2244 /*
2245 * If EEPROM is detected and can be addressed using 14 bits,
2246 * use EERD otherwise use bit bang
2247 */
2248 if ((eeprom->type == ixgbe_eeprom_spi) &&
2249 (offset <= IXGBE_EERD_MAX_ADDR))
2250 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2251 else
2252 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2253
2254 return ret_val;
2255 }
2256
2257
|
1 /******************************************************************************
2
3 Copyright (c) 2001-2013, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD: src/sys/dev/ixgbe/ixgbe_82599.c,v 1.8 2012/07/05 20:51:44 jfv Exp $*/
34
35 #include "ixgbe_type.h"
36 #include "ixgbe_82599.h"
37 #include "ixgbe_api.h"
38 #include "ixgbe_common.h"
39 #include "ixgbe_phy.h"
40
41 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
43 bool autoneg_wait_to_complete);
44 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
45 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
46 u16 offset, u16 *data);
47 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
48 u16 words, u16 *data);
49
50 static bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
51 {
52 u32 fwsm, manc, factps;
53
54 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
55 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
56 return FALSE;
57
58 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
59 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
60 return FALSE;
61
62 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
63 if (factps & IXGBE_FACTPS_MNGCG)
64 return FALSE;
65
66 return TRUE;
67 }
68
69 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
70 {
71 struct ixgbe_mac_info *mac = &hw->mac;
72
73 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
74
75 /*
76 * enable the laser control functions for SFP+ fiber
77 * and MNG not enabled
78 */
79 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
80 !(ixgbe_mng_enabled(hw))) {
81 mac->ops.disable_tx_laser =
82 &ixgbe_disable_tx_laser_multispeed_fiber;
83 mac->ops.enable_tx_laser =
84 &ixgbe_enable_tx_laser_multispeed_fiber;
85 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
86
87 } else {
88 mac->ops.disable_tx_laser = NULL;
89 mac->ops.enable_tx_laser = NULL;
90 mac->ops.flap_tx_laser = NULL;
91 }
92
93 if (hw->phy.multispeed_fiber) {
94 /* Set up dual speed SFP+ support */
95 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
96 } else {
97 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
98 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
99 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
100 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
140 }
141
142 /* Set necessary function pointers based on phy type */
143 switch (hw->phy.type) {
144 case ixgbe_phy_tn:
145 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
146 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
147 phy->ops.get_firmware_version =
148 &ixgbe_get_phy_firmware_version_tnx;
149 break;
150 default:
151 break;
152 }
153 init_phy_ops_out:
154 return ret_val;
155 }
156
157 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
158 {
159 s32 ret_val = IXGBE_SUCCESS;
160 u16 list_offset, data_offset, data_value;
161 bool got_lock = FALSE;
162
163 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
164
165 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
166 ixgbe_init_mac_link_ops_82599(hw);
167
168 hw->phy.ops.reset = NULL;
169
170 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
171 &data_offset);
172 if (ret_val != IXGBE_SUCCESS)
173 goto setup_sfp_out;
174
175 /* PHY config will finish before releasing the semaphore */
176 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
177 IXGBE_GSSR_MAC_CSR_SM);
178 if (ret_val != IXGBE_SUCCESS) {
179 ret_val = IXGBE_ERR_SWFW_SYNC;
180 goto setup_sfp_out;
181 }
182
183 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
184 while (data_value != 0xffff) {
185 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
186 IXGBE_WRITE_FLUSH(hw);
187 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
188 }
189
190 /* Release the semaphore */
191 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
192 /* Delay obtaining semaphore again to allow FW access */
193 msec_delay(hw->eeprom.semaphore_delay);
194
195 /* Need SW/FW semaphore around AUTOC writes if LESM on,
196 * likewise reset_pipeline requires lock as it also writes
197 * AUTOC.
198 */
199 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
200 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
201 IXGBE_GSSR_MAC_CSR_SM);
202 if (ret_val != IXGBE_SUCCESS) {
203 ret_val = IXGBE_ERR_SWFW_SYNC;
204 goto setup_sfp_out;
205 }
206
207 got_lock = TRUE;
208 }
209
210 /* Restart DSP and set SFI mode */
211 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((hw->mac.orig_autoc) |
212 IXGBE_AUTOC_LMS_10G_SERIAL));
213 hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
214 ret_val = ixgbe_reset_pipeline_82599(hw);
215
216 if (got_lock) {
217 hw->mac.ops.release_swfw_sync(hw,
218 IXGBE_GSSR_MAC_CSR_SM);
219 got_lock = FALSE;
220 }
221
222 if (ret_val) {
223 DEBUGOUT("sfp module setup not complete\n");
224 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
225 goto setup_sfp_out;
226 }
227
228 }
229
230 setup_sfp_out:
231 return ret_val;
232 }
233
234 /**
235 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
236 * @hw: pointer to hardware structure
237 *
238 * Initialize the function pointers and assign the MAC type for 82599.
239 * Does not touch the hardware.
240 **/
241
242 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
243 {
244 struct ixgbe_mac_info *mac = &hw->mac;
245 struct ixgbe_phy_info *phy = &hw->phy;
246 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
247 s32 ret_val;
248
249 DEBUGFUNC("ixgbe_init_ops_82599");
250
251 (void) ixgbe_init_phy_ops_generic(hw);
252 ret_val = ixgbe_init_ops_generic(hw);
253
254 /* PHY */
255 phy->ops.identify = &ixgbe_identify_phy_82599;
256 phy->ops.init = &ixgbe_init_phy_ops_82599;
257
258 /* MAC */
259 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
260 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
261 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
262 mac->ops.get_supported_physical_layer =
263 &ixgbe_get_supported_physical_layer_82599;
264 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
265 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
266 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
267 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
268 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
269 mac->ops.start_hw = &ixgbe_start_hw_82599;
270 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
271 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
304 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
305 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
306
307 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
308
309 /* EEPROM */
310 eeprom->ops.read = &ixgbe_read_eeprom_82599;
311 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
312
313 /* Manageability interface */
314 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
315
316
317 return ret_val;
318 }
319
320 /**
321 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
322 * @hw: pointer to hardware structure
323 * @speed: pointer to link speed
324 * @autoneg: TRUE when autoneg or autotry is enabled
325 *
326 * Determines the link capabilities by reading the AUTOC register.
327 **/
328 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
329 ixgbe_link_speed *speed,
330 bool *autoneg)
331 {
332 s32 status = IXGBE_SUCCESS;
333 u32 autoc = 0;
334
335 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
336
337
338 /* Check if 1G SFP module. */
339 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
340 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
341 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
342 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
343 *speed = IXGBE_LINK_SPEED_1GB_FULL;
344 *autoneg = TRUE;
345 goto out;
346 }
347
348 /*
349 * Determine link capabilities based on the stored value of AUTOC,
350 * which represents EEPROM defaults. If AUTOC value has not
351 * been stored, use the current register values.
352 */
353 if (hw->mac.orig_link_settings_stored)
354 autoc = hw->mac.orig_autoc;
355 else
356 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
357
358 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
359 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
360 *speed = IXGBE_LINK_SPEED_1GB_FULL;
361 *autoneg = FALSE;
362 break;
363
364 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
365 *speed = IXGBE_LINK_SPEED_10GB_FULL;
366 *autoneg = FALSE;
367 break;
368
369 case IXGBE_AUTOC_LMS_1G_AN:
370 *speed = IXGBE_LINK_SPEED_1GB_FULL;
371 *autoneg = TRUE;
372 break;
373
374 case IXGBE_AUTOC_LMS_10G_SERIAL:
375 *speed = IXGBE_LINK_SPEED_10GB_FULL;
376 *autoneg = FALSE;
377 break;
378
379 case IXGBE_AUTOC_LMS_KX4_KX_KR:
380 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
381 *speed = IXGBE_LINK_SPEED_UNKNOWN;
382 if (autoc & IXGBE_AUTOC_KR_SUPP)
383 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
384 if (autoc & IXGBE_AUTOC_KX4_SUPP)
385 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
386 if (autoc & IXGBE_AUTOC_KX_SUPP)
387 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
388 *autoneg = TRUE;
389 break;
390
391 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
392 *speed = IXGBE_LINK_SPEED_100_FULL;
393 if (autoc & IXGBE_AUTOC_KR_SUPP)
394 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
395 if (autoc & IXGBE_AUTOC_KX4_SUPP)
396 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
397 if (autoc & IXGBE_AUTOC_KX_SUPP)
398 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
399 *autoneg = TRUE;
400 break;
401
402 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
403 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
404 *autoneg = FALSE;
405 break;
406
407 default:
408 status = IXGBE_ERR_LINK_SETUP;
409 goto out;
410 }
411
412 if (hw->phy.multispeed_fiber) {
413 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
414 IXGBE_LINK_SPEED_1GB_FULL;
415 *autoneg = TRUE;
416 }
417
418 out:
419 return status;
420 }
421
422 /**
423 * ixgbe_get_media_type_82599 - Get media type
424 * @hw: pointer to hardware structure
425 *
426 * Returns the media type (fiber, copper, backplane)
427 **/
428 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
429 {
430 enum ixgbe_media_type media_type;
431
432 DEBUGFUNC("ixgbe_get_media_type_82599");
433
434 /* Detect if there is a copper PHY attached. */
435 switch (hw->phy.type) {
438 media_type = ixgbe_media_type_copper;
439 goto out;
440 default:
441 break;
442 }
443
444 switch (hw->device_id) {
445 case IXGBE_DEV_ID_82599_KX4:
446 case IXGBE_DEV_ID_82599_KX4_MEZZ:
447 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
448 case IXGBE_DEV_ID_82599_KR:
449 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
450 case IXGBE_DEV_ID_82599_XAUI_LOM:
451 /* Default device ID is mezzanine card KX/KX4 */
452 media_type = ixgbe_media_type_backplane;
453 break;
454 case IXGBE_DEV_ID_82599_SFP:
455 case IXGBE_DEV_ID_82599_SFP_FCOE:
456 case IXGBE_DEV_ID_82599_SFP_EM:
457 case IXGBE_DEV_ID_82599_SFP_SF2:
458 case IXGBE_DEV_ID_82599_SFP_SF_QP:
459 case IXGBE_DEV_ID_82599EN_SFP:
460 media_type = ixgbe_media_type_fiber;
461 break;
462 case IXGBE_DEV_ID_82599_CX4:
463 media_type = ixgbe_media_type_cx4;
464 break;
465 case IXGBE_DEV_ID_82599_T3_LOM:
466 media_type = ixgbe_media_type_copper;
467 break;
468 case IXGBE_DEV_ID_82599_BYPASS:
469 media_type = ixgbe_media_type_fiber_fixed;
470 hw->phy.multispeed_fiber = TRUE;
471 break;
472 default:
473 media_type = ixgbe_media_type_unknown;
474 break;
475 }
476 out:
477 return media_type;
478 }
479
480 /**
481 * ixgbe_start_mac_link_82599 - Setup MAC link settings
482 * @hw: pointer to hardware structure
483 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
484 *
485 * Configures link settings based on values in the ixgbe_hw struct.
486 * Restarts the link. Performs autonegotiation if needed.
487 **/
488 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
489 bool autoneg_wait_to_complete)
490 {
491 u32 autoc_reg;
492 u32 links_reg;
493 u32 i;
494 s32 status = IXGBE_SUCCESS;
495 bool got_lock = FALSE;
496
497 DEBUGFUNC("ixgbe_start_mac_link_82599");
498
499
500 /* reset_pipeline requires us to hold this lock as it writes to
501 * AUTOC.
502 */
503 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
504 status = hw->mac.ops.acquire_swfw_sync(hw,
505 IXGBE_GSSR_MAC_CSR_SM);
506 if (status != IXGBE_SUCCESS)
507 goto out;
508
509 got_lock = TRUE;
510 }
511
512 /* Restart link */
513 (void) ixgbe_reset_pipeline_82599(hw);
514
515 if (got_lock)
516 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
517
518 /* Only poll for autoneg to complete if specified to do so */
519 if (autoneg_wait_to_complete) {
520 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
521 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
522 IXGBE_AUTOC_LMS_KX4_KX_KR ||
523 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
524 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
525 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
526 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
527 links_reg = 0; /* Just in case Autoneg time = 0 */
528 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
529 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
530 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
531 break;
532 msec_delay(100);
533 }
534 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
535 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
536 DEBUGOUT("Autoneg did not complete.\n");
537 }
538 }
539 }
540
541 /* Add delay to filter out noises during initial link setup */
542 msec_delay(50);
543
544 out:
545 return status;
546 }
547
548 /**
549 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
550 * @hw: pointer to hardware structure
551 *
552 * The base drivers may require better control over SFP+ module
553 * PHY states. This includes selectively shutting down the Tx
554 * laser on the PHY, effectively halting physical link.
555 **/
556 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
557 {
558 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
559
560 /* Disable tx laser; allow 100us to go dark per spec */
561 esdp_reg |= IXGBE_ESDP_SDP3;
562 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
563 IXGBE_WRITE_FLUSH(hw);
564 usec_delay(100);
590 * When the driver changes the link speeds that it can support,
591 * it sets autotry_restart to TRUE to indicate that we need to
592 * initiate a new autotry session with the link partner. To do
593 * so, we set the speed then disable and re-enable the tx laser, to
594 * alert the link partner that it also needs to restart autotry on its
595 * end. This is consistent with TRUE clause 37 autoneg, which also
596 * involves a loss of signal.
597 **/
598 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
599 {
600 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
601
602 if (hw->mac.autotry_restart) {
603 ixgbe_disable_tx_laser_multispeed_fiber(hw);
604 ixgbe_enable_tx_laser_multispeed_fiber(hw);
605 hw->mac.autotry_restart = FALSE;
606 }
607 }
608
609 /**
610 * ixgbe_set_fiber_fixed_speed - Set module link speed for fixed fiber
611 * @hw: pointer to hardware structure
612 * @speed: link speed to set
613 *
614 * We set the module speed differently for fixed fiber. For other
615 * multi-speed devices we don't have an error value so here if we
616 * detect an error we just log it and exit.
617 */
618 static void ixgbe_set_fiber_fixed_speed(struct ixgbe_hw *hw,
619 ixgbe_link_speed speed)
620 {
621 s32 status;
622 u8 rs, eeprom_data;
623
624 switch (speed) {
625 case IXGBE_LINK_SPEED_10GB_FULL:
626 /* one bit mask same as setting on */
627 rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
628 break;
629 case IXGBE_LINK_SPEED_1GB_FULL:
630 rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
631 break;
632 default:
633 DEBUGOUT("Invalid fixed module speed\n");
634 return;
635 }
636
637 /* Set RS0 */
638 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
639 IXGBE_I2C_EEPROM_DEV_ADDR2,
640 &eeprom_data);
641 if (status) {
642 DEBUGOUT("Failed to read Rx Rate Select RS0\n");
643 goto out;
644 }
645
646 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
647
648 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
649 IXGBE_I2C_EEPROM_DEV_ADDR2,
650 eeprom_data);
651 if (status) {
652 DEBUGOUT("Failed to write Rx Rate Select RS0\n");
653 goto out;
654 }
655
656 /* Set RS1 */
657 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
658 IXGBE_I2C_EEPROM_DEV_ADDR2,
659 &eeprom_data);
660 if (status) {
661 DEBUGOUT("Failed to read Rx Rate Select RS1\n");
662 goto out;
663 }
664
665 eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
666
667 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
668 IXGBE_I2C_EEPROM_DEV_ADDR2,
669 eeprom_data);
670 if (status) {
671 DEBUGOUT("Failed to write Rx Rate Select RS1\n");
672 goto out;
673 }
674 out:
675 return;
676 }
677
678 /**
679 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
680 * @hw: pointer to hardware structure
681 * @speed: new link speed
682 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
683 *
684 * Set the link speed in the AUTOC register and restarts link.
685 **/
686 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
687 ixgbe_link_speed speed,
688 bool autoneg_wait_to_complete)
689 {
690 s32 status = IXGBE_SUCCESS;
691 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
692 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
693 u32 speedcnt = 0;
694 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
695 u32 i = 0;
696 bool autoneg, link_up = FALSE;
697
698 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
699
700 /* Mask off requested but non-supported speeds */
701 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
702 if (status != IXGBE_SUCCESS)
703 return status;
704
705 speed &= link_speed;
706
707 /*
708 * Try each speed one by one, highest priority first. We do this in
709 * software because 10gb fiber doesn't support speed autonegotiation.
710 */
711 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
712 speedcnt++;
713 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
714
715 /* If we already have link at this speed, just jump out */
716 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
717 if (status != IXGBE_SUCCESS)
718 return status;
719
720 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
721 goto out;
722
723 /* Set the module link speed */
724 if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
725 ixgbe_set_fiber_fixed_speed(hw,
726 IXGBE_LINK_SPEED_10GB_FULL);
727 } else {
728 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
729 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
730 IXGBE_WRITE_FLUSH(hw);
731 }
732
733 /* Allow module to change analog characteristics (1G->10G) */
734 msec_delay(40);
735
736 status = ixgbe_setup_mac_link_82599(hw,
737 IXGBE_LINK_SPEED_10GB_FULL,
738 autoneg_wait_to_complete);
739 if (status != IXGBE_SUCCESS)
740 return status;
741
742 /* Flap the tx laser if it has not already been done */
743 ixgbe_flap_tx_laser(hw);
744
745 /*
746 * Wait for the controller to acquire link. Per IEEE 802.3ap,
747 * Section 73.10.2, we may have to wait up to 500ms if KR is
748 * attempted. 82599 uses the same timing for 10g SFI.
749 */
750 for (i = 0; i < 5; i++) {
751 /* Wait for the link partner to also set speed */
752 msec_delay(100);
753
754 /* If we have link, just jump out */
755 status = ixgbe_check_link(hw, &link_speed,
756 &link_up, FALSE);
757 if (status != IXGBE_SUCCESS)
759
760 if (link_up)
761 goto out;
762 }
763 }
764
765 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
766 speedcnt++;
767 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
768 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
769
770 /* If we already have link at this speed, just jump out */
771 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
772 if (status != IXGBE_SUCCESS)
773 return status;
774
775 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
776 goto out;
777
778 /* Set the module link speed */
779 if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
780 ixgbe_set_fiber_fixed_speed(hw,
781 IXGBE_LINK_SPEED_1GB_FULL);
782 } else {
783 esdp_reg &= ~IXGBE_ESDP_SDP5;
784 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
785 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
786 IXGBE_WRITE_FLUSH(hw);
787 }
788
789 /* Allow module to change analog characteristics (10G->1G) */
790 msec_delay(40);
791
792 status = ixgbe_setup_mac_link_82599(hw,
793 IXGBE_LINK_SPEED_1GB_FULL,
794 autoneg_wait_to_complete);
795 if (status != IXGBE_SUCCESS)
796 return status;
797
798 /* Flap the tx laser if it has not already been done */
799 ixgbe_flap_tx_laser(hw);
800
801 /* Wait for the link partner to also set speed */
802 msec_delay(100);
803
804 /* If we have link, just jump out */
805 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
806 if (status != IXGBE_SUCCESS)
807 return status;
808
809 if (link_up)
810 goto out;
811 }
812
813 /*
814 * We didn't get link. Configure back to the highest speed we tried,
815 * (if there was more than one). We call ourselves back with just the
816 * single highest speed that the user requested.
817 */
818 if (speedcnt > 1)
819 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
820 highest_link_speed, autoneg_wait_to_complete);
821
822 out:
823 /* Set autoneg_advertised value based on input link speed */
824 hw->phy.autoneg_advertised = 0;
825
826 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
827 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
828
829 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
830 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
831
832 return status;
833 }
834
835 /**
836 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
837 * @hw: pointer to hardware structure
838 * @speed: new link speed
839 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
840 *
841 * Implements the Intel SmartSpeed algorithm.
842 **/
843 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
844 ixgbe_link_speed speed,
845 bool autoneg_wait_to_complete)
846 {
847 s32 status = IXGBE_SUCCESS;
848 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
849 s32 i, j;
850 bool link_up = FALSE;
851 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
852
853 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
854
855 /* Set autoneg_advertised value based on input link speed */
856 hw->phy.autoneg_advertised = 0;
857
858 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
859 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
860
861 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
862 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
863
864 if (speed & IXGBE_LINK_SPEED_100_FULL)
865 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
866
867 /*
868 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
869 * autoneg advertisement if link is unable to be established at the
870 * highest negotiated rate. This can sometimes happen due to integrity
871 * issues with the physical media connection.
872 */
873
874 /* First, try to get link with full advertisement */
875 hw->phy.smart_speed_active = FALSE;
876 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
877 status = ixgbe_setup_mac_link_82599(hw, speed,
878 autoneg_wait_to_complete);
879 if (status != IXGBE_SUCCESS)
880 goto out;
881
882 /*
883 * Wait for the controller to acquire link. Per IEEE 802.3ap,
884 * Section 73.10.2, we may have to wait up to 500ms if KR is
885 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
886 * Table 9 in the AN MAS.
887 */
888 for (i = 0; i < 5; i++) {
889 msec_delay(100);
890
891 /* If we have link, just jump out */
892 status = ixgbe_check_link(hw, &link_speed, &link_up,
893 FALSE);
894 if (status != IXGBE_SUCCESS)
895 goto out;
896
897 if (link_up)
898 goto out;
899 }
900 }
901
902 /*
903 * We didn't get link. If we advertised KR plus one of KX4/KX
904 * (or BX4/BX), then disable KR and try again.
905 */
906 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
907 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
908 goto out;
909
910 /* Turn SmartSpeed on to disable KR support */
911 hw->phy.smart_speed_active = TRUE;
912 status = ixgbe_setup_mac_link_82599(hw, speed,
913 autoneg_wait_to_complete);
914 if (status != IXGBE_SUCCESS)
915 goto out;
916
917 /*
918 * Wait for the controller to acquire link. 600ms will allow for
919 * the AN link_fail_inhibit_timer as well for multiple cycles of
920 * parallel detect, both 10g and 1g. This allows for the maximum
921 * connect attempts as defined in the AN MAS table 73-7.
922 */
923 for (i = 0; i < 6; i++) {
924 msec_delay(100);
925
926 /* If we have link, just jump out */
927 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
928 if (status != IXGBE_SUCCESS)
929 goto out;
930
931 if (link_up)
932 goto out;
933 }
934
935 /* We didn't get link. Turn SmartSpeed back off. */
936 hw->phy.smart_speed_active = FALSE;
937 status = ixgbe_setup_mac_link_82599(hw, speed,
938 autoneg_wait_to_complete);
939
940 out:
941 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
942 DEBUGOUT("Smartspeed has downgraded the link speed "
943 "from the maximum advertised\n");
944 return status;
945 }
946
947 /**
948 * ixgbe_setup_mac_link_82599 - Set MAC link speed
949 * @hw: pointer to hardware structure
950 * @speed: new link speed
951 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
952 *
953 * Set the link speed in the AUTOC register and restarts link.
954 **/
955 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
956 ixgbe_link_speed speed,
957 bool autoneg_wait_to_complete)
958 {
959 bool autoneg = FALSE;
960 s32 status = IXGBE_SUCCESS;
961 u32 autoc, pma_pmd_1g, link_mode, start_autoc;
962 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
963 u32 orig_autoc = 0;
964 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
965 u32 links_reg;
966 u32 i;
967 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
968 bool got_lock = FALSE;
969
970 DEBUGFUNC("ixgbe_setup_mac_link_82599");
971
972 /* Check to see if speed passed in is supported. */
973 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
974 if (status)
975 goto out;
976
977 speed &= link_capabilities;
978
979 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
980 status = IXGBE_ERR_LINK_SETUP;
981 goto out;
982 }
983
984 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
985 if (hw->mac.orig_link_settings_stored)
986 autoc = hw->mac.orig_autoc;
987 else
988 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
989
990 orig_autoc = autoc;
991 start_autoc = hw->mac.cached_autoc;
992 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
993 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
994
995 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
996 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
997 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
998 /* Set KX4/KX/KR support according to speed requested */
999 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
1000 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1001 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
1002 autoc |= IXGBE_AUTOC_KX4_SUPP;
1003 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
1004 (hw->phy.smart_speed_active == FALSE))
1005 autoc |= IXGBE_AUTOC_KR_SUPP;
1006 }
1007 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1008 autoc |= IXGBE_AUTOC_KX_SUPP;
1009 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
1010 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
1011 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
1012 /* Switch from 1G SFI to 10G SFI if requested */
1013 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
1014 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
1015 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1016 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
1017 }
1018 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
1019 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
1020 /* Switch from 10G SFI to 1G SFI if requested */
1021 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1022 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
1023 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1024 if (autoneg)
1025 autoc |= IXGBE_AUTOC_LMS_1G_AN;
1026 else
1027 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1028 }
1029 }
1030
1031 if (autoc != start_autoc) {
1032 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
1033 * likewise reset_pipeline requires us to hold this lock as
1034 * it also writes to AUTOC.
1035 */
1036 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1037 status = hw->mac.ops.acquire_swfw_sync(hw,
1038 IXGBE_GSSR_MAC_CSR_SM);
1039 if (status != IXGBE_SUCCESS) {
1040 status = IXGBE_ERR_SWFW_SYNC;
1041 goto out;
1042 }
1043
1044 got_lock = TRUE;
1045 }
1046
1047 /* Restart link */
1048 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
1049 hw->mac.cached_autoc = autoc;
1050 (void) ixgbe_reset_pipeline_82599(hw);
1051
1052 if (got_lock) {
1053 hw->mac.ops.release_swfw_sync(hw,
1054 IXGBE_GSSR_MAC_CSR_SM);
1055 got_lock = FALSE;
1056 }
1057
1058 /* Only poll for autoneg to complete if specified to do so */
1059 if (autoneg_wait_to_complete) {
1060 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1061 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1062 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1063 links_reg = 0; /*Just in case Autoneg time=0*/
1064 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1065 links_reg =
1066 IXGBE_READ_REG(hw, IXGBE_LINKS);
1067 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1068 break;
1069 msec_delay(100);
1070 }
1071 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1072 status =
1073 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1074 DEBUGOUT("Autoneg did not complete.\n");
1075 }
1076 }
1077 }
1078
1079 /* Add delay to filter out noises during initial link setup */
1080 msec_delay(50);
1081 }
1082
1083 out:
1084 return status;
1085 }
1086
1087 /**
1088 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1089 * @hw: pointer to hardware structure
1090 * @speed: new link speed
1091 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
1092 *
1093 * Restarts link on PHY and MAC based on settings passed in.
1094 **/
1095 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1096 ixgbe_link_speed speed,
1097 bool autoneg_wait_to_complete)
1098 {
1099 s32 status;
1100
1101 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1102
1103 /* Setup the PHY according to input speed */
1104 status = hw->phy.ops.setup_link_speed(hw, speed,
1105 autoneg_wait_to_complete);
1106 /* Set up MAC */
1107 (void) ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1108
1109 return status;
1110 }
1111
1112 /**
1113 * ixgbe_reset_hw_82599 - Perform hardware reset
1114 * @hw: pointer to hardware structure
1115 *
1116 * Resets the hardware by resetting the transmit and receive units, masks
1117 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1118 * reset.
1119 **/
1120 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1121 {
1122 ixgbe_link_speed link_speed;
1123 s32 status;
1124 u32 ctrl, i, autoc, autoc2;
1125 bool link_up = FALSE;
1126
1127 DEBUGFUNC("ixgbe_reset_hw_82599");
1188
1189 msec_delay(50);
1190
1191 /*
1192 * Double resets are required for recovery from certain error
1193 * conditions. Between resets, it is necessary to stall to allow time
1194 * for any pending HW events to complete.
1195 */
1196 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1197 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1198 goto mac_reset_top;
1199 }
1200
1201 /*
1202 * Store the original AUTOC/AUTOC2 values if they have not been
1203 * stored off yet. Otherwise restore the stored original
1204 * values since the reset operation sets back to defaults.
1205 */
1206 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1207 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1208
1209 /* Enable link if disabled in NVM */
1210 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1211 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1212 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1213 IXGBE_WRITE_FLUSH(hw);
1214 }
1215
1216 if (hw->mac.orig_link_settings_stored == FALSE) {
1217 hw->mac.orig_autoc = autoc;
1218 hw->mac.orig_autoc2 = autoc2;
1219 hw->mac.cached_autoc = autoc;
1220 hw->mac.orig_link_settings_stored = TRUE;
1221 } else {
1222 if (autoc != hw->mac.orig_autoc) {
1223 /* Need SW/FW semaphore around AUTOC writes if LESM is
1224 * on, likewise reset_pipeline requires us to hold
1225 * this lock as it also writes to AUTOC.
1226 */
1227 bool got_lock = FALSE;
1228 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1229 status = hw->mac.ops.acquire_swfw_sync(hw,
1230 IXGBE_GSSR_MAC_CSR_SM);
1231 if (status != IXGBE_SUCCESS) {
1232 status = IXGBE_ERR_SWFW_SYNC;
1233 goto reset_hw_out;
1234 }
1235
1236 got_lock = TRUE;
1237 }
1238
1239 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1240 hw->mac.cached_autoc = hw->mac.orig_autoc;
1241 (void) ixgbe_reset_pipeline_82599(hw);
1242
1243 if (got_lock)
1244 hw->mac.ops.release_swfw_sync(hw,
1245 IXGBE_GSSR_MAC_CSR_SM);
1246 }
1247
1248 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1249 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1250 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1251 autoc2 |= (hw->mac.orig_autoc2 &
1252 IXGBE_AUTOC2_UPPER_MASK);
1253 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1254 }
1255 }
1256
1257 /* Store the permanent mac address */
1258 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1259
1260 /*
1261 * Store MAC address from RAR0, clear receive address registers, and
1262 * clear the multicast table. Also reset num_rar_entries to 128,
1263 * since we modify this value when programming the SAN MAC address.
1264 */
1265 hw->mac.num_rar_entries = 128;
1266 hw->mac.ops.init_rx_addrs(hw);
1267
1331 IXGBE_WRITE_FLUSH(hw);
1332 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1333 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1334 ~IXGBE_FDIRCMD_CLEARHT));
1335 IXGBE_WRITE_FLUSH(hw);
1336 /*
1337 * Clear FDIR Hash register to clear any leftover hashes
1338 * waiting to be programmed.
1339 */
1340 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1341 IXGBE_WRITE_FLUSH(hw);
1342
1343 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1344 IXGBE_WRITE_FLUSH(hw);
1345
1346 /* Poll init-done after we write FDIRCTRL register */
1347 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1348 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1349 IXGBE_FDIRCTRL_INIT_DONE)
1350 break;
1351 msec_delay(1);
1352 }
1353 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1354 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1355 return IXGBE_ERR_FDIR_REINIT_FAILED;
1356 }
1357
1358 /* Clear FDIR statistics registers (read to clear) */
1359 (void) IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1360 (void) IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1361 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1362 (void) IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1363 (void) IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1364
1365 return IXGBE_SUCCESS;
1366 }
1367
1368 /**
1369 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1370 * @hw: pointer to hardware structure
1371 * @fdirctrl: value to write to flow director control register
2266
2267 hw->mac.ops.disable_sec_rx_path(hw);
2268
2269 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2270
2271 hw->mac.ops.enable_sec_rx_path(hw);
2272
2273 return IXGBE_SUCCESS;
2274 }
2275
2276 /**
2277 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2278 * @hw: pointer to hardware structure
2279 *
2280 * Verifies that installed the firmware version is 0.6 or higher
2281 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2282 *
2283 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2284 * if the FW version is not supported.
2285 **/
2286 s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2287 {
2288 s32 status = IXGBE_ERR_EEPROM_VERSION;
2289 u16 fw_offset, fw_ptp_cfg_offset;
2290 u16 fw_version = 0;
2291
2292 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2293
2294 /* firmware check is only necessary for SFI devices */
2295 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2296 status = IXGBE_SUCCESS;
2297 goto fw_version_out;
2298 }
2299
2300 /* get the offset to the Firmware Module block */
2301 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2302
2303 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2304 goto fw_version_out;
2305
2306 /* get the offset to the Pass Through Patch Configuration block */
2415 u16 offset, u16 *data)
2416 {
2417 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2418 s32 ret_val = IXGBE_ERR_CONFIG;
2419
2420 DEBUGFUNC("ixgbe_read_eeprom_82599");
2421
2422 /*
2423 * If EEPROM is detected and can be addressed using 14 bits,
2424 * use EERD otherwise use bit bang
2425 */
2426 if ((eeprom->type == ixgbe_eeprom_spi) &&
2427 (offset <= IXGBE_EERD_MAX_ADDR))
2428 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2429 else
2430 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2431
2432 return ret_val;
2433 }
2434
2435 /**
2436 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2437 *
2438 * @hw: pointer to hardware structure
2439 *
2440 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2441 * full pipeline reset
2442 **/
2443 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2444 {
2445 s32 ret_val;
2446 u32 anlp1_reg = 0;
2447 u32 i, autoc_reg, autoc2_reg;
2448
2449 /* Enable link if disabled in NVM */
2450 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2451 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2452 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2453 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2454 IXGBE_WRITE_FLUSH(hw);
2455 }
2456
2457 autoc_reg = hw->mac.cached_autoc;
2458 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2459 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2460 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2461 /* Wait for AN to leave state 0 */
2462 for (i = 0; i < 10; i++) {
2463 msec_delay(4);
2464 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2465 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2466 break;
2467 }
2468
2469 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2470 DEBUGOUT("auto negotiation not completed\n");
2471 ret_val = IXGBE_ERR_RESET_FAILED;
2472 goto reset_pipeline_out;
2473 }
2474
2475 ret_val = IXGBE_SUCCESS;
2476
2477 reset_pipeline_out:
2478 /* Write AUTOC register with original LMS field and Restart_AN */
2479 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2480 IXGBE_WRITE_FLUSH(hw);
2481
2482 return ret_val;
2483 }
2484
2485
2486
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